1. Documentation conventions
1.1 General information
The STM32G0x1 devices have an Arm ®(a) Cortex ® -M0+ core.
1.2 List of abbreviations for registers
The following abbreviations (b) are used in register descriptions:
| read/write (rw) | Software can read and write to this bit. |
| read-only (r) | Software can only read this bit. |
| write-only (w) | Software can only write to this bit. Reading this bit returns the reset value. |
| read/clear write0 (rc_w0) | Software can read as well as clear this bit by writing 0. Writing 1 has no effect on the bit value. |
| read/clear write1 (rc_w1) | Software can read as well as clear this bit by writing 1. Writing 0 has no effect on the bit value. |
| read/clear write (rc_w) | Software can read as well as clear this bit by writing to the register. The value written to this bit is not important. |
| read/clear by read (rc_r) | Software can read this bit. Reading this bit automatically clears it to 0. Writing this bit has no effect on the bit value. |
| read/set by read (rs_r) | Software can read this bit. Reading this bit automatically sets it to 1. Writing this bit has no effect on the bit value. |
| read/set (rs) | Software can read as well as set this bit. Writing 0 has no effect on the bit value. |
| read/write once (rwo) | Software can only write once to this bit and can also read it at any time. Only a reset can return the bit to its reset value. |
| toggle (t) | The software can toggle this bit by writing 1. Writing 0 has no effect. |
| read-only write trigger (rt_w1) | Software can read this bit. Writing 1 triggers an event but has no effect on the bit value. |
| Reserved (Res.) | Reserved bit, must be kept at reset value. |
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of them may not be used in the current document.
1.3 Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
- • Word : data of 32-bit length.
- • Half-word : data of 16-bit length.
- • Byte : data of 8-bit length.
- • SWD-DP (SWD DEBUG PORT) : SWD-DP provides a 2-pin (clock and data) interface based on the Serial Wire Debug (SWD) protocol. Please refer to the Cortex ® -M0+ technical reference manual.
- • IAP (in-application programming) : IAP is the ability to re-program the flash memory of a microcontroller while the user program is running.
- • ICP (in-circuit programming) : ICP is the ability to program the flash memory of a microcontroller using the SWD protocol or the bootloader while the device is mounted on the user application board.
- • Option bytes : device configuration bits stored in the flash memory.
- • OBL : option byte loader.
- • AHB : advanced high-performance bus.
- • APB : advanced peripheral bus.
1.4 Availability of peripherals
For availability of peripherals and their number across all devices, refer to the particular device datasheet.
The following table shows per-device availability of peripherals that are not common to all STM32G0x1 devices. The “X” means that the peripheral is available, “-” not available.
Table 1. Peripherals versus devices
| Feature | STM32G031 | STM32G041 | STM32G051 | STM32G061 | STM32G071 | STM32G081 | STM32G0B1 | STM32G0C1 |
|---|---|---|---|---|---|---|---|---|
| CRS | - | - | - | - | - | - | X | X |
| RNG | - | X | - | X | - | X | - | X |
| AES | - | X | - | X | - | X | - | X |
| DAC | - | - | X | X | X | X | X | X |
| COMP1, COMP2 | - | - | X | X | X | X | X | X |
| COMP3 | - | - | - | - | - | - | X | X |
| TIM4 | - | - | - | - | - | - | X | X |
| TIM6 and TIM7 | - | - | X | X | X | X | X | X |
| TIM15 | - | - | X | X | X | X | X | X |
| I2C2 | X (1) | X (1) | X (1) | X (1) | X (1) | X (1) | X (2) | X (2) |
| I2C3 | - | - | - | - | - | - | X (1) | X (1) |
| SPI3 | - | - | - | - | - | - | X | X |
| I2S2 | - | - | - | - | - | - | X | X |
Table 1. Peripherals versus devices (continued)
| Feature | STM32G0 31 | STM32G0 41 | STM32G0 51 | STM32G0 61 | STM32G0 71 | STM32G0 81 | STM32G0 B1 | STM32G0 C1 |
|---|---|---|---|---|---|---|---|---|
| USART2 | X (1) | X (1) | X (1) | X (1) | X (2) | X (2) | X (2) | X (2) |
| USART3 | - | - | - | - | X (1) | X (1) | X (2) | X (2) |
| USART4 | - | - | - | - | X (1) | X (1) | X (1) | X (1) |
| USART5, USART6 | - | - | - | - | - | - | X (1) | X (1) |
| LPUART2 | - | - | - | - | - | - | X | X |
| USB | - | - | - | - | - | - | X | X |
| UCPD1, UCPD2 | - | - | - | - | X | X | X | X |
| FDCAN1, FDCAN2 | - | - | - | - | - | - | X | X |
| CEC | - | - | - | - | X | X | X | X |
| DMA2 | - | - | - | - | - | - | X | X |
| MCO2 | - | - | - | - | - | - | X | X |
| HSI48 RC | - | - | - | - | - | - | X | X |
| CRS | - | - | - | - | - | - | X | X |
| GPIO port E | - | - | - | - | - | - | X | X |
| Switchable I/O clamping diode | X | X | X | X | - | - | X | X |
| V DDIO2 monitor | - | - | - | - | - | - | X | X |
1. Basic configuration
2. Full configuration