RM0444-STM32G0x1

This reference manual complements the datasheets of the STM32G0x1 microcontrollers, providing information required for application and in particular for software development. It pertains to the superset of feature sets available on STM32G0x1 microcontrollers.

The devices include ST state-of-the-art patented technology.

For feature set, ordering information, and mechanical and electrical characteristics of a particular STM32G0x1 device, refer to its corresponding datasheet.

For information on the Arm ® Cortex ® -M0+ core, refer to the Cortex ® -M0+ technical reference manual.

a. Available on STMicroelectronics website www.st.com

Contents

1Documentation conventions . . . . .55
1.1General information . . . . .55
1.2List of abbreviations for registers . . . . .55
1.3Glossary . . . . .56
1.4Availability of peripherals . . . . .56
2Memory and bus architecture . . . . .58
2.1System architecture . . . . .58
2.2Memory organization . . . . .60
2.2.1Introduction . . . . .60
2.2.2Memory map and register boundary addresses . . . . .61
2.3Embedded SRAM . . . . .66
2.4Flash memory overview . . . . .67
2.5Boot configuration . . . . .68
2.5.1Physical remap . . . . .69
2.5.2Embedded bootloader . . . . .69
2.5.3Forcing boot from main flash memory . . . . .69
2.5.4Empty check . . . . .69
3Embedded flash memory (FLASH) . . . . .70
3.1FLASH Introduction . . . . .70
3.2FLASH main features . . . . .70
3.3FLASH functional description . . . . .71
3.3.1FLASH organization . . . . .71
3.3.2FLASH dual-bank capability . . . . .73
3.3.3FLASH error code correction (ECC) . . . . .74
3.3.4FLASH read access latency . . . . .75
3.3.5FLASH memory acceleration . . . . .76
3.3.6FLASH program and erase operations . . . . .77
3.3.7FLASH main memory erase sequences . . . . .77
3.3.8FLASH main memory programming sequences . . . . .79
3.3.9Read-while-write (RWW) function . . . . .82
3.4FLASH option bytes . . . . .82
3.4.1FLASH option byte description . . . . .82
3.4.2FLASH option byte programming . . . . .84
3.5FLASH memory protection . . . . .85
3.5.1FLASH read protection (RDP) . . . . .86
3.5.2FLASH proprietary code readout protection (PCROP) . . . . .88
3.5.3FLASH write protection (WRP) . . . . .90
3.5.4Securable memory area . . . . .91
3.5.5Disabling core debug access . . . . .92
3.5.6Forcing boot from main flash memory . . . . .92
3.6FLASH interrupts . . . . .93
3.7FLASH registers . . . . .94
3.7.1FLASH access control register (FLASH_ACR) . . . . .94
3.7.2FLASH key register (FLASH_KEYR) . . . . .95
3.7.3FLASH option key register (FLASH_OPTKEYR) . . . . .95
3.7.4FLASH status register (FLASH_SR) . . . . .96
3.7.5FLASH control register (FLASH_CR) . . . . .98
3.7.6FLASH ECC register (FLASH_ECCR) . . . . .100
3.7.7FLASH ECC register 2 (FLASH_ECCR2) . . . . .101
3.7.8FLASH option register (FLASH_OPTR) . . . . .102
3.7.9FLASH PCROP area A start address register
(FLASH_PCROP1ASR) . . . . .		104
3.7.10FLASH PCROP area A end address register
(FLASH_PCROP1AER) . . . . .		105
3.7.11FLASH WRP area A address register (FLASH_WRP1AR) . . . . .105
3.7.12FLASH WRP area B address register (FLASH_WRP1BR) . . . . .106
3.7.13FLASH PCROP area B start address register
(FLASH_PCROP1BSR) . . . . .		107
3.7.14FLASH PCROP area B end address register
(FLASH_PCROP1BER) . . . . .		107
3.7.15FLASH PCROP2 area A start address register
(FLASH_PCROP2ASR) . . . . .		108
3.7.16FLASH PCROP2 area A end address register
(FLASH_PCROP2AER) . . . . .		108
3.7.17FLASH WRP2 area A address register (FLASH_WRP2AR) . . . . .109
3.7.18FLASH WRP2 area B address register (FLASH_WRP2BR) . . . . .109
3.7.19FLASH PCROP2 area B start address register
(FLASH_PCROP2BSR) . . . . .		110
3.7.20FLASH PCROP2 area B end address register
(FLASH_PCROP2BER) . . . . .		110
4.4.13Power Port C pull-down control register (PWR_PDCRC)148
4.4.14Power Port D pull-up control register (PWR_PUCRD)149
4.4.15Power Port D pull-down control register (PWR_PDCRD)149
4.4.16Power Port E pull-up control register (PWR_PUCRE)150
4.4.17Power Port E pull-down control register (PWR_PDCRE)150
4.4.18Power Port F pull-up control register (PWR_PUCRF)151
4.4.19Power Port F pull-down control register (PWR_PDCRF)151
4.4.20PWR register map153
5Reset and clock control (RCC)155
5.1Reset155
5.1.1Power reset155
5.1.2System reset155
5.1.3RTC domain reset157
5.2Clocks158
5.2.1HSE clock162
5.2.2HSI16 clock163
5.2.3HSI48 clock164
5.2.4PLL164
5.2.5LSE clock165
5.2.6LSI clock165
5.2.7System clock (SYSCLK) selection166
5.2.8Clock source frequency versus voltage scaling166
5.2.9Clock security system (CSS)166
5.2.10Clock security system for LSE clock (LSECSS)167
5.2.11ADC clock167
5.2.12RTC clock168
5.2.13Timer clock168
5.2.14Watchdog clock168
5.2.15Clock-out capability169
5.2.16Internal/external clock measurement with TIM14/TIM16/TIM17169
5.2.17Peripheral clock enable registers172
5.3Low-power modes172
5.4RCC registers174
5.4.1Clock control register (RCC_CR)174
5.4.2Internal clock source calibration register (RCC_ICSCR)176
5.4.3Clock configuration register (RCC_CFGR)176
5.4.4PLL configuration register (RCC_PLLCFGR) . . . . .179
5.4.5RCC clock recovery RC register (RCC_CRRCR) . . . . .182
5.4.6Clock interrupt enable register (RCC_CIER) . . . . .182
5.4.7Clock interrupt flag register (RCC_CIFR) . . . . .183
5.4.8Clock interrupt clear register (RCC_CICR) . . . . .185
5.4.9I/O port reset register (RCC_IOPRSTR) . . . . .186
5.4.10AHB peripheral reset register (RCC_AHBRSTR) . . . . .187
5.4.11APB peripheral reset register 1 (RCC_APBSTR1) . . . . .188
5.4.12APB peripheral reset register 2 (RCC_APBSTR2) . . . . .191
5.4.13I/O port clock enable register (RCC_IOPENR) . . . . .192
5.4.14AHB peripheral clock enable register (RCC_AHBENR) . . . . .193
5.4.15APB peripheral clock enable register 1 (RCC_APBENR1) . . . . .194
5.4.16APB peripheral clock enable register 2(RCC_APBENR2) . . . . .198
5.4.17I/O port in Sleep mode clock enable register (RCC_IOPSMENR) . . . . .199
5.4.18AHB peripheral clock enable in Sleep/Stop mode register
(RCC_AHBSMENR) . . . . .		200
5.4.19APB peripheral clock enable in Sleep/Stop mode register 1
(RCC_APBSMENR1) . . . . .		201
5.4.20APB peripheral clock enable in Sleep/Stop mode register 2
(RCC_APBSMENR2) . . . . .		205
5.4.21Peripherals independent clock configuration register (RCC_CCIPR) . . . . .206
5.4.22Peripherals independent clock configuration register 2
(RCC_CCIPR2) . . . . .		208
5.4.23RTC domain control register (RCC_BDCR) . . . . .209
5.4.24Control/status register (RCC_CSR) . . . . .211
5.4.25RCC register map . . . . .213
6Clock recovery system (CRS) . . . . .217
6.1CRS introduction . . . . .217
6.2CRS main features . . . . .217
6.3CRS implementation . . . . .217
6.4CRS functional description . . . . .218
6.4.1CRS block diagram . . . . .218
6.4.2CRS internal signals . . . . .218
6.4.3Synchronization input . . . . .219
6.4.4Frequency error measurement . . . . .219
6.4.5Frequency error evaluation and automatic trimming . . . . .220
6.4.6CRS initialization and configuration . . . . .221
6.5CRS in low-power modes . . . . .222
6.6CRS interrupts . . . . .222
6.7CRS registers . . . . .222
6.7.1CRS control register (CRS_CR) . . . . .222
6.7.2CRS configuration register (CRS_CFGR) . . . . .223
6.7.3CRS interrupt and status register (CRS_ISR) . . . . .224
6.7.4CRS interrupt flag clear register (CRS_ICR) . . . . .226
6.7.5CRS register map . . . . .227
7General-purpose I/Os (GPIO) . . . . .228
7.1Introduction . . . . .228
7.2GPIO main features . . . . .228
7.3GPIO functional description . . . . .228
7.3.1General-purpose I/O (GPIO) . . . . .230
7.3.2I/O pin alternate function multiplexer and mapping . . . . .230
7.3.3I/O port control registers . . . . .232
7.3.4I/O port state in low-power modes . . . . .232
7.3.5I/O port data registers . . . . .232
7.3.6I/O data bitwise handling . . . . .232
7.3.7GPIO locking mechanism . . . . .233
7.3.8I/O alternate function input/output . . . . .233
7.3.9External interrupt/wake-up lines . . . . .233
7.3.10Input configuration . . . . .233
7.3.11Output configuration . . . . .234
7.3.12Alternate function configuration . . . . .235
7.3.13Analog configuration . . . . .236
7.3.14Using the HSE or LSE oscillator pins as GPIOs . . . . .237
7.3.15Using the GPIO pins in the RTC domain . . . . .237
7.3.16USB PD / Dead battery support . . . . .237
7.3.17Reset pin (PF2-NRST) in GPIO mode . . . . .237
7.4GPIO in low-power modes . . . . .238
7.5GPIO registers . . . . .238
7.5.1GPIO port mode register (GPIOx_MODER)
(x = A to F) . . . . .		238
7.5.2GPIO port output type register (GPIOx_OTYPER)
(x = A to F) . . . . .		239
7.5.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to F) . . . . .		239
7.5.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to F) . . . . .		240
7.5.5GPIO port input data register (GPIOx_IDR)
(x = A to F) . . . . .		240
7.5.6GPIO port output data register (GPIOx_ODR)
(x = A to F) . . . . .		241
7.5.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to F) . . . . .		241
7.5.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to F) . . . . .		241
7.5.9GPIO port alternate function low register (GPIOx_AFRL)
(x = A to F) . . . . .		242
7.5.10GPIO port alternate function high register (GPIOx_AFRH)
(x = A to F) . . . . .		243
7.5.11GPIO port bit reset register (GPIOx_BRR) (x = A to F) . . . . .243
7.5.12GPIO register map . . . . .245
8System configuration controller (SYSCFG) . . . . .246
8.1SYSCFG registers . . . . .246
8.1.1SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .246
8.1.2SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .249
8.1.3SYSCFG interrupt line 0 status register (SYSCFG_ITLINE0) . . . . .251
8.1.4SYSCFG interrupt line 1 status register (SYSCFG_ITLINE1) . . . . .252
8.1.5SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2) . . . . .252
8.1.6SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3) . . . . .252
8.1.7SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4) . . . . .253
8.1.8SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5) . . . . .254
8.1.9SYSCFG interrupt line 6 status register (SYSCFG_ITLINE6) . . . . .254
8.1.10SYSCFG interrupt line 7 status register (SYSCFG_ITLINE7) . . . . .254
8.1.11SYSCFG interrupt line 8 status register (SYSCFG_ITLINE8) . . . . .255
8.1.12SYSCFG interrupt line 9 status register (SYSCFG_ITLINE9) . . . . .255
8.1.13SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10) . . . . .256
8.1.14SYSCFG interrupt line 11 status register (SYSCFG_ITLINE11) . . . . .256
8.1.15SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12) . . . . .257
8.1.16SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13) . . . . .257
8.1.17SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14) . . . . .258
8.1.18SYSCFG interrupt line 15 status register (SYSCFG_ITLINE15) . . . . .258
8.1.19SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16) . . . . .258
8.1.20SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17) . . . . .259
8.1.21SYSCFG interrupt line 18 status register (SYSCFG_ITLINE18) . . . . .259
8.1.22SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19) . . . . .260
8.1.23SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20) . . . . .260
8.1.24SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21) . . . . .260
8.1.25SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22) . . . . .261
8.1.26SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23) . . . . .261
8.1.27SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24) . . . . .262
8.1.28SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25) . . . . .262
8.1.29SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26) . . . . .262
8.1.30SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27) . . . . .263
8.1.31SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28) . . . . .263
8.1.32SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29) . . . . .264
8.1.33SYSCFG interrupt line 30 status register (SYSCFG_ITLINE30) . . . . .264
8.1.34SYSCFG interrupt line 31 status register (SYSCFG_ITLINE31) . . . . .264
8.1.35SYSCFG register map . . . . .265
9Interconnect matrix . . . . .268
9.1Introduction . . . . .268
9.2Connection summary . . . . .268
9.3Interconnection details . . . . .269
9.3.1From TIM1, TIM2, TIM3, TIM4, TIM15, TIM16, and TIM17,
to TIM1, TIM2, TIM3, TIM4, and TIM15 . . . . .		269
9.3.2From TIM1, TIM2, TIM3, TIM4, TIM6, TIM15, and EXTI, to ADC . . . . .270
9.3.3From ADC to TIM1 . . . . .270
9.3.4From TIM1, TIM2, TIM3, TIM4, TIM6, TIM7, TIM15, LPTIM1, LPTIM2,
and EXTI, to DAC . . . . .		271
9.3.5From HSE, LSE, LSI, MCO, MCO2, RTC and TAMP, to TIM2, TIM14,
TIM16, and TIM17 . . . . .		271
9.3.6From RTC, TAMP, COMP1, COMP2, and COMP3 to LPTIM1
and LPTIM2 . . . . .		272
9.3.7From TIM1, TIM2, TIM3, TIM4, and TIM15, to COMP1, COMP2,
and COMP3 . . . . .		272
9.3.8From internal analog sources to ADC . . . . .272
9.3.9From COMP1, COMP2, and COMP3 to TIM1, TIM2, TIM3, TIM4, TIM15,
TIM16, and TIM17 . . . . .		273
9.3.10From system errors to TIM1, TIM2, TIM3, TIM4, TIM15, TIM16,
and TIM17 . . . . .		273
11.4.3DMAMUX channels . . . . .301
11.4.4DMAMUX request line multiplexer . . . . .301
11.4.5DMAMUX request generator . . . . .304
11.5DMAMUX interrupts . . . . .305
11.6DMAMUX registers . . . . .306
11.6.1DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR) . . . . .306
11.6.2DMAMUX request line multiplexer interrupt channel status register (DMAMUX_CSR) . . . . .307
11.6.3DMAMUX request line multiplexer interrupt clear flag register (DMAMUX_CFR) . . . . .307
11.6.4DMAMUX request generator channel x configuration register (DMAMUX_RGxCR) . . . . .308
11.6.5DMAMUX request generator interrupt status register (DMAMUX_RGSR) . . . . .309
11.6.6DMAMUX request generator interrupt clear flag register (DMAMUX_RGCFR) . . . . .309
11.6.7DMAMUX register map . . . . .310
12Nested vectored interrupt controller (NVIC) . . . . .312
12.1Main features . . . . .312
12.2SysTick calibration value register . . . . .312
12.3Interrupt and exception vectors . . . . .312
13Extended interrupt and event controller (EXTI) . . . . .315
13.1EXTI main features . . . . .315
13.2EXTI block diagram . . . . .315
13.2.1EXTI connections between peripherals and CPU . . . . .317
13.3EXTI functional description . . . . .317
13.3.1EXTI configurable event input wake-up . . . . .318
13.3.2EXTI direct event input wake-up . . . . .319
13.3.3EXTI mux . . . . .319
13.4EXTI functional behavior . . . . .321
13.5EXTI registers . . . . .322
13.5.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .322
13.5.2EXTI falling trigger selection register 1 (EXTI_FTSR1) . . . . .323
13.5.3EXTI software interrupt event register 1 (EXTI_SWIER1) . . . . .323
13.5.4EXTI rising edge pending register 1 (EXTI_RPR1) . . . . .324
13.5.5EXTI falling edge pending register 1 (EXTI_FPR1) . . . . .325
13.5.6EXTI rising trigger selection register 2 (EXTI_RTSR2) . . . . .325
13.5.7EXTI falling trigger selection register 2 (EXTI_FTSR2) . . . . .326
13.5.8EXTI software interrupt event register 2 (EXTI_SWIER2) . . . . .326
13.5.9EXTI rising edge pending register 2 (EXTI_RPR2) . . . . .327
13.5.10EXTI falling edge pending register 2 (EXTI_FPR2) . . . . .327
13.5.11EXTI external interrupt selection register (EXTI_EXTICRx) . . . . .328
13.5.12EXTI CPU wake-up with interrupt mask register (EXTI_IMR1) . . . . .329
13.5.13EXTI CPU wake-up with event mask register (EXTI_EMR1) . . . . .330
13.5.14EXTI CPU wake-up with interrupt mask register (EXTI_IMR2) . . . . .330
13.5.15EXTI CPU wake-up with event mask register (EXTI_EMR2) . . . . .331
13.5.16EXTI register map . . . . .332
14Cyclic redundancy check calculation unit (CRC) . . . . .334
14.1Introduction . . . . .334
14.2CRC main features . . . . .334
14.3CRC functional description . . . . .335
14.3.1CRC block diagram . . . . .335
14.3.2CRC internal signals . . . . .335
14.3.3CRC operation . . . . .335
14.4CRC registers . . . . .337
14.4.1CRC data register (CRC_DR) . . . . .337
14.4.2CRC independent data register (CRC_IDR) . . . . .337
14.4.3CRC control register (CRC_CR) . . . . .338
14.4.4CRC initial value (CRC_INIT) . . . . .339
14.4.5CRC polynomial (CRC_POL) . . . . .339
14.4.6CRC register map . . . . .340
15Analog-to-digital converter (ADC) . . . . .341
15.1Introduction . . . . .341
15.2ADC main features . . . . .342
15.3ADC functional description . . . . .343
15.3.1ADC pins and internal signals . . . . .343
15.3.2ADC voltage regulator (ADVREGEN) . . . . .344
15.3.3Calibration (ADCAL) . . . . .345
15.3.4ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .347
15.3.5ADC clock (CKMODE, PRESC[3:0])349
15.3.6ADC connectivity351
15.3.7Configuring the ADC352
15.3.8Channel selection (CHSEL, SCANDIR, CHSELRMOD)352
15.3.9Programmable sampling time (SMPx[2:0])353
15.3.10Single conversion mode (CONT = 0)354
15.3.11Continuous conversion mode (CONT = 1)354
15.3.12Starting conversions (ADSTART)355
15.3.13Timings356
15.3.14Stopping an ongoing conversion (ADSTP)357
15.4Conversion on external trigger and trigger polarity (EXTSEL, EXTEN)357
15.4.1Discontinuous mode (DISCEN)358
15.4.2Programmable resolution (RES) - Fast conversion mode358
15.4.3End of conversion, end of sampling phase (EOC, EOSMP flags)359
15.4.4End of conversion sequence (EOS flag)359
15.4.5Example timing diagrams (single/continuous modes
hardware/software triggers)		360
15.4.6Low frequency trigger mode362
15.5Data management362
15.5.1Data register and data alignment (ADC_DR, ALIGN)362
15.5.2ADC overrun (OVR, OVRMOD)362
15.5.3Managing a sequence of data converted without using the DMA364
15.5.4Managing converted data without using the DMA without overrun364
15.5.5Managing converted data using the DMA364
15.6Low-power features365
15.6.1Wait mode conversion365
15.6.2Auto-off mode (AUTOFF)366
15.7Analog window watchdogs367
15.7.1Description of analog watchdog 1368
15.7.2Description of analog watchdog 2 and 3369
15.7.3ADC_AWDx_OUT output signal generation369
15.7.4Analog watchdog threshold control371
15.8Oversampler372
15.8.1ADC operating modes supported when oversampling373
15.8.2Analog watchdog374
15.8.3Triggered mode374
15.9Temperature sensor and internal reference voltage374
15.10Battery voltage monitoring . . . . .377
15.11ADC interrupts . . . . .378
15.12ADC registers . . . . .379
15.12.1ADC interrupt and status register (ADC_ISR) . . . . .379
15.12.2ADC interrupt enable register (ADC_IER) . . . . .380
15.12.3ADC control register (ADC_CR) . . . . .382
15.12.4ADC configuration register 1 (ADC_CFGR1) . . . . .384
15.12.5ADC configuration register 2 (ADC_CFGR2) . . . . .387
15.12.6ADC sampling time register (ADC_SMPR) . . . . .389
15.12.7ADC watchdog threshold register (ADC_AWD1TR) . . . . .390
15.12.8ADC watchdog threshold register (ADC_AWD2TR) . . . . .390
15.12.9ADC channel selection register (ADC_CHSELR) . . . . .390
15.12.10ADC channel selection register [alternate] (ADC_CHSELR) . . . . .391
15.12.11ADC watchdog threshold register (ADC_AWD3TR) . . . . .393
15.12.12ADC data register (ADC_DR) . . . . .394
15.12.13ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . .394
15.12.14ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR) . . . . .395
15.12.15ADC calibration factor (ADC_CALFACT) . . . . .395
15.12.16ADC common configuration register (ADC_CCR) . . . . .396
15.13ADC register map . . . . .397
16Digital-to-analog converter (DAC) . . . . .400
16.1Introduction . . . . .400
16.2DAC main features . . . . .400
16.3DAC implementation . . . . .401
16.4DAC functional description . . . . .402
16.4.1DAC block diagram . . . . .402
16.4.2DAC pins and internal signals . . . . .403
16.4.3DAC channel enable . . . . .404
16.4.4DAC data format . . . . .404
16.4.5DAC conversion . . . . .406
16.4.6DAC output voltage . . . . .406
16.4.7DAC trigger selection . . . . .406
16.4.8DMA requests . . . . .407
16.4.9Noise generation . . . . .407
16.4.10Triangle-wave generation . . . . .409
16.4.11DAC channel modes . . . . .410
16.4.12DAC channel buffer calibration . . . . .413
16.4.13DAC channel conversion modes . . . . .414
16.4.14Dual DAC channel conversion modes (if dual channels are available) . . . . .415
16.5DAC in low-power modes . . . . .419
16.6DAC interrupts . . . . .420
16.7DAC registers . . . . .420
16.7.1DAC control register (DAC_CR) . . . . .420
16.7.2DAC software trigger register (DAC_SWTRGR) . . . . .423
16.7.3DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . .424
16.7.4DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . .424
16.7.5DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . .425
16.7.6DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . .425
16.7.7DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . .426
16.7.8DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . .426
16.7.9Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . .427
16.7.10Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . .427
16.7.11Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . .428
16.7.12DAC channel1 data output register (DAC_DOR1) . . . . .428
16.7.13DAC channel2 data output register (DAC_DOR2) . . . . .429
16.7.14DAC status register (DAC_SR) . . . . .429
16.7.15DAC calibration control register (DAC_CCR) . . . . .431
16.7.16DAC mode control register (DAC_MCR) . . . . .431
16.7.17DAC channel1 sample and hold sample time register (DAC_SHSR1) . . . . .433
16.7.18DAC channel2 sample and hold sample time register (DAC_SHSR2) . . . . .433
16.7.19DAC sample and hold time register (DAC_SHHR) . . . . .433
16.7.20DAC sample and hold refresh time register (DAC_SHRR) . . . . .434
16.7.21DAC register map . . . . .435
17Voltage reference buffer (VREFBUF) . . . . .437
17.1Introduction . . . . .437
17.2VREFBUF functional description . . . . .437
17.3VREFBUF registers . . . . .438
17.3.1VREFBUF control and status register (VREFBUF_CSR) . . . . .438
17.3.2VREFBUF calibration control register (VREFBUF_CCR) . . . . .438
17.3.3VREFBUF register map . . . . .439
18Comparator (COMP) . . . . .440
18.1Introduction . . . . .440
18.2COMP main features . . . . .440
18.3COMP functional description . . . . .441
18.3.1COMP block diagram . . . . .441
18.3.2COMP pins and internal signals . . . . .441
18.3.3COMP reset and clocks . . . . .443
18.3.4Comparator LOCK mechanism . . . . .443
18.3.5Window comparator . . . . .444
18.3.6Hysteresis . . . . .444
18.3.7Comparator output blanking function . . . . .445
18.3.8COMP power and speed modes . . . . .445
18.4COMP low-power modes . . . . .446
18.5COMP interrupts . . . . .446
18.6COMP registers . . . . .446
18.6.1Comparator 1 control and status register (COMP1_CSR) . . . . .446
18.6.2Comparator 2 control and status register (COMP2_CSR) . . . . .448
18.6.3Comparator 3 control and status register (COMP3_CSR) . . . . .450
18.6.4COMP register map . . . . .453
19True random number generator (RNG) . . . . .454
19.1Introduction . . . . .454
19.2RNG main features . . . . .454
19.3RNG functional description . . . . .455
19.3.1RNG block diagram . . . . .455
19.3.2RNG internal signals . . . . .455
19.3.3Random number generation . . . . .456
19.3.4RNG initialization . . . . .458
19.3.5RNG operation . . . . .459
19.3.6RNG clocking . . . . .460
19.3.7Error management . . . . .460
19.3.8RNG low-power use . . . . .461
19.4RNG interrupts . . . . .461
19.5RNG processing time . . . . .461
19.6RNG entropy source validation . . . . .462
19.6.1Introduction . . . . .462
19.6.2Validation conditions . . . . .462
19.6.3Data collection . . . . .462
19.7RNG registers . . . . .463
19.7.1RNG control register (RNG_CR) . . . . .463
19.7.2RNG status register (RNG_SR) . . . . .464
19.7.3RNG data register (RNG_DR) . . . . .465
19.7.4RNG register map . . . . .465
20AES hardware accelerator (AES) . . . . .466
20.1Introduction . . . . .466
20.2AES main features . . . . .466
20.3AES implementation . . . . .466
20.4AES functional description . . . . .467
20.4.1AES block diagram . . . . .467
20.4.2AES internal signals . . . . .467
20.4.3AES cryptographic core . . . . .467
20.4.4AES procedure to perform a cipher operation . . . . .473
20.4.5AES decryption round key preparation . . . . .476
20.4.6AES ciphertext stealing and data padding . . . . .476
20.4.7AES task suspend and resume . . . . .477
20.4.8AES basic chaining modes (ECB, CBC) . . . . .477
20.4.9AES counter (CTR) mode . . . . .482
20.4.10AES Galois/counter mode (GCM) . . . . .485
20.4.11AES Galois message authentication code (GMAC) . . . . .490
20.4.12AES counter with CBC-MAC (CCM) . . . . .492
20.4.13AES data registers and data swapping . . . . .497
20.4.14AES key registers . . . . .499
20.4.15AES initialization vector registers . . . . .499
20.4.16AES DMA interface . . . . .500
20.4.17AES error management . . . . .501
20.5AES interrupts . . . . .502
20.6AES processing latency . . . . .502
20.7AES registers . . . . .503
20.7.1AES control register (AES_CR) . . . . .503
20.7.2AES status register (AES_SR) . . . . .506
20.7.3AES data input register (AES_DINR) . . . . .507
20.7.4AES data output register (AES_DOUTR) . . . . .507
20.7.5AES key register 0 (AES_KEYR0) . . . . .508
20.7.6AES key register 1 (AES_KEYR1) . . . . .508
20.7.7AES key register 2 (AES_KEYR2) . . . . .509
20.7.8AES key register 3 (AES_KEYR3) . . . . .509
20.7.9AES initialization vector register 0 (AES_IVR0) . . . . .509
20.7.10AES initialization vector register 1 (AES_IVR1) . . . . .510
20.7.11AES initialization vector register 2 (AES_IVR2) . . . . .510
20.7.12AES initialization vector register 3 (AES_IVR3) . . . . .510
20.7.13AES key register 4 (AES_KEYR4) . . . . .511
20.7.14AES key register 5 (AES_KEYR5) . . . . .511
20.7.15AES key register 6 (AES_KEYR6) . . . . .511
20.7.16AES key register 7 (AES_KEYR7) . . . . .512
20.7.17AES suspend registers (AES_SUSPxR) . . . . .512
20.7.18AES register map . . . . .513
21Advanced-control timer (TIM1) . . . . .515
21.1TIM1 introduction . . . . .515
21.2TIM1 main features . . . . .516
21.3TIM1 functional description . . . . .518
21.3.1Time-base unit . . . . .518
21.3.2Counter modes . . . . .520
21.3.3Repetition counter . . . . .531
21.3.4External trigger input . . . . .533
21.3.5Clock selection . . . . .534
21.3.6Capture/compare channels . . . . .538
21.3.7Input capture mode . . . . .540
21.3.8PWM input mode . . . . .541
21.3.9Forced output mode . . . . .542
21.3.10Output compare mode . . . . .543
21.3.11PWM mode . . . . .544
21.3.12Asymmetric PWM mode . . . . .547
21.3.13Combined PWM mode . . . . .548
21.3.14Combined 3-phase PWM mode . . . . .549
21.3.15Complementary outputs and dead-time insertion . . . . .550
21.3.16Using the break function . . . . .552
21.3.17Bidirectional break inputs . . . . .558
21.3.18Clearing the OCxREF signal on an external event . . . . .560
21.3.196-step PWM generation . . . . .561
21.3.20One-pulse mode . . . . .562
21.3.21Retriggerable one pulse mode . . . . .563
21.3.22Encoder interface mode . . . . .564
21.3.23UIF bit remapping . . . . .566
21.3.24Timer input XOR function . . . . .567
21.3.25Interfacing with Hall sensors . . . . .567
21.3.26Timer synchronization . . . . .570
21.3.27ADC synchronization . . . . .574
21.3.28DMA burst mode . . . . .574
21.3.29Debug mode . . . . .575
21.4TIM1 registers . . . . .576
21.4.1TIM1 control register 1 (TIM1_CR1) . . . . .576
21.4.2TIM1 control register 2 (TIM1_CR2) . . . . .577
21.4.3TIM1 slave mode control register
(TIM1_SMCR) . . . . .		580
21.4.4TIM1 DMA/interrupt enable register
(TIM1_DIER) . . . . .		582
21.4.5TIM1 status register (TIM1_SR) . . . . .584
21.4.6TIM1 event generation register (TIM1_EGR) . . . . .586
21.4.7TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . .587
21.4.8TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . .		588
21.4.9TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . .591
21.4.10TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . .		592
21.4.11TIM1 capture/compare enable register
(TIM1_CCER) . . . . .		594
21.4.12TIM1 counter (TIM1_CNT) . . . . .597
21.4.13TIM1 prescaler (TIM1_PSC) . . . . .597
21.4.14TIM1 auto-reload register (TIM1_ARR) . . . . .597
21.4.15TIM1 repetition counter register (TIM1_RCR) . . . . .598
21.4.16TIM1 capture/compare register 1
(TIM1_CCR1) . . . . .		598
21.4.17TIM1 capture/compare register 2
(TIM1_CCR2) . . . . .		599
21.4.18TIM1 capture/compare register 3
(TIM1_CCR3) . . . . .		599
21.4.19TIM1 capture/compare register 4
(TIM1_CCR4) . . . . .		600
21.4.20TIM1 break and dead-time register
(TIM1_BDTR) . . . . .		600
21.4.21TIM1 DMA control register
(TIM1_DCR) . . . . .		604
21.4.22TIM1 DMA address for full transfer
(TIM1_DMAR) . . . . .		605
21.4.23TIM1 option register 1 (TIM1_OR1) . . . . .606
21.4.24TIM1 capture/compare mode register 3
(TIM1_CCMR3) . . . . .		606
21.4.25TIM1 capture/compare register 5
(TIM1_CCR5) . . . . .		607
21.4.26TIM1 capture/compare register 6
(TIM1_CCR6) . . . . .		608
21.4.27TIM1 alternate function option register 1 (TIM1_AF1) . . . . .609
21.4.28TIM1 Alternate function register 2 (TIM1_AF2) . . . . .611
21.4.29TIM1 timer input selection register (TIM1_TISEL) . . . . .612
21.4.30TIM1 register map . . . . .614
22General-purpose timers (TIM2/TIM3/TIM4) . . . . .617
22.1TIM2/TIM3/TIM4 introduction . . . . .617
22.2TIM2/TIM3/TIM4 main features . . . . .617
22.3TIM2/TIM3/TIM4 functional description . . . . .619
22.3.1Time-base unit . . . . .619
22.3.2Counter modes . . . . .621
22.3.3Clock selection . . . . .631
22.3.4Capture/Compare channels . . . . .635
22.3.5Input capture mode . . . . .637
22.3.6PWM input mode . . . . .638
22.3.7Forced output mode . . . . .639
22.3.8Output compare mode . . . . .639
22.3.9PWM mode . . . . .640
22.3.10Asymmetric PWM mode . . . . .644
22.3.11Combined PWM mode . . . . .644
22.3.12Clearing the OCxREF signal on an external event . . . . .645
22.3.13One-pulse mode . . . . .647
22.3.14Retriggerable one pulse mode . . . . .648
22.3.15Encoder interface mode . . . . .649
22.3.16UIF bit remapping . . . . .651
22.3.17Timer input XOR function . . . . .651
22.3.18Timers and external trigger synchronization . . . . .652
22.3.19Timer synchronization . . . . .655
22.3.20DMA burst mode . . . . .660
22.3.21Debug mode . . . . .661
22.4TIM2/TIM3/TIM4 registers . . . . .662
22.4.1TIMx control register 1 (TIMx_CR1)(x = 2 to 4) . . . . .662
22.4.2TIMx control register 2 (TIMx_CR2)(x = 2 to 4) . . . . .663
22.4.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 4) . . . . .665
22.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 4) . . . . .668
22.4.5TIMx status register (TIMx_SR)(x = 2 to 4) . . . . .669
22.4.6TIMx event generation register (TIMx_EGR)(x = 2 to 4) . . . . .671
22.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 4) . . . . .672
22.4.8TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 4) . . . . .		674
22.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 4) . . . . .676
22.4.10TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 4) . . . . .		677
22.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 4) . . . . .		678
22.4.12TIMx counter (TIMx_CNT)(x = 2 to 4) . . . . .679
22.4.13TIMx counter [alternate] (TIMx_CNT)(x = 2 to 4) . . . . .680
22.4.14TIMx prescaler (TIMx_PSC)(x = 2 to 4) . . . . .680
22.4.15TIMx auto-reload register (TIMx_ARR)(x = 2 to 4) . . . . .681
22.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 4) . . . . .681
22.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 4) . . . . .682
22.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 4) . . . . .682
22.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 4) . . . . .683

23 Basic timers (TIM6/TIM7) . . . . . 694


24 General-purpose timers (TIM14) . . . . . 707

24.3TIM14 functional description . . . . .709
24.3.1Time-base unit . . . . .709
24.3.2Counter modes . . . . .711
24.3.3Clock selection . . . . .714
24.3.4Capture/compare channels . . . . .715
24.3.5Input capture mode . . . . .716
24.3.6Forced output mode . . . . .717
24.3.7Output compare mode . . . . .718
24.3.8PWM mode . . . . .719
24.3.9One-pulse mode . . . . .720
24.3.10UIF bit remapping . . . . .720
24.3.11Using timer output as trigger for other timers (TIM14) . . . . .721
24.3.12Debug mode . . . . .721
24.4TIM14 registers . . . . .722
24.4.1TIM14 control register 1 (TIM14_CR1) . . . . .722
24.4.2TIM14 Interrupt enable register (TIM14_DIER) . . . . .723
24.4.3TIM14 status register (TIM14_SR) . . . . .723
24.4.4TIM14 event generation register (TIM14_EGR) . . . . .724
24.4.5TIM14 capture/compare mode register 1 (TIM14_CCMR1) . . . . .725
24.4.6TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1) . . . . .726
24.4.7TIM14 capture/compare enable register (TIM14_CCER) . . . . .728
24.4.8TIM14 counter (TIM14_CNT) . . . . .729
24.4.9TIM14 prescaler (TIM14_PSC) . . . . .730
24.4.10TIM14 auto-reload register (TIM14_ARR) . . . . .730
24.4.11TIM14 capture/compare register 1 (TIM14_CCR1) . . . . .730
24.4.12TIM14 timer input selection register (TIM14_TISEL) . . . . .731
24.4.13TIM14 register map . . . . .731
25General-purpose timers (TIM15/TIM16/TIM17) . . . . .733
25.1TIM15/TIM16/TIM17 introduction . . . . .733
25.2TIM15 main features . . . . .733
25.3TIM16/TIM17 main features . . . . .734
25.4TIM15/TIM16/TIM17 functional description . . . . .737
25.4.1Time-base unit . . . . .737
25.4.2Counter modes . . . . .739
25.4.3Repetition counter . . . . .743
25.4.4Clock selection . . . . .744
25.4.5Capture/compare channels . . . . .746
25.4.6Input capture mode . . . . .748
25.4.7PWM input mode (only for TIM15) . . . . .749
25.4.8Forced output mode . . . . .750
25.4.9Output compare mode . . . . .751
25.4.10PWM mode . . . . .752
25.4.11Combined PWM mode (TIM15 only) . . . . .753
25.4.12Complementary outputs and dead-time insertion . . . . .754
25.4.13Using the break function . . . . .756
25.4.14Bidirectional break inputs . . . . .761
25.4.156-step PWM generation . . . . .762
25.4.16One-pulse mode . . . . .764
25.4.17Retriggerable one pulse mode (TIM15 only) . . . . .765
25.4.18UIF bit remapping . . . . .766
25.4.19Timer input XOR function (TIM15 only) . . . . .767
25.4.20External trigger synchronization (TIM15 only) . . . . .768
25.4.21Slave mode – combined reset + trigger mode . . . . .770
25.4.22DMA burst mode . . . . .770
25.4.23Timer synchronization (TIM15) . . . . .772
25.4.24Using timer output as trigger for other timers (TIM16/TIM17) . . . . .772
25.4.25Debug mode . . . . .772
25.5TIM15 registers . . . . .773
25.5.1TIM15 control register 1 (TIM15_CR1) . . . . .773
25.5.2TIM15 control register 2 (TIM15_CR2) . . . . .774
25.5.3TIM15 slave mode control register (TIM15_SMCR) . . . . .776
25.5.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .777
25.5.5TIM15 status register (TIM15_SR) . . . . .778
25.5.6TIM15 event generation register (TIM15_EGR) . . . . .780
25.5.7TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .781
25.5.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		782
25.5.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .785
25.5.10TIM15 counter (TIM15_CNT) . . . . .788
25.5.11TIM15 prescaler (TIM15_PSC) . . . . .788
25.5.12TIM15 auto-reload register (TIM15_ARR) . . . . .788
25.5.13TIM15 repetition counter register (TIM15_RCR) . . . . .789
25.5.14TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .789
25.5.15TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .790
25.5.16TIM15 break and dead-time register (TIM15_BDTR) . . . . .790
25.5.17TIM15 DMA control register (TIM15_DCR) . . . . .793
25.5.18TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .793
25.5.19TIM15 alternate register 1 (TIM15_AF1) . . . . .794
25.5.20TIM15 input selection register (TIM15_TISEL) . . . . .795
25.5.21TIM15 register map . . . . .796
25.6TIM16/TIM17 registers . . . . .799
25.6.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .799
25.6.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .800
25.6.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .801
25.6.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .802
25.6.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .803
25.6.6TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 16 to 17) . . . . .		804
25.6.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . .		805
25.6.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .807
25.6.9TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .809
25.6.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .810
25.6.11TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . .810
25.6.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .811
25.6.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .811
25.6.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .812
25.6.15TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .815
25.6.16TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . .815
25.6.17TIM16 alternate function register 1 (TIM16_AF1) . . . . .816
25.6.18TIM16 input selection register (TIM16_TISEL) . . . . .817
25.6.19TIM17 alternate function register 1 (TIM17_AF1) . . . . .818
25.6.20TIM17 input selection register (TIM17_TISEL) . . . . .819
25.6.21TIM16/TIM17 register map . . . . .821
26Low-power timer (LPTIM) . . . . .823
26.1Introduction . . . . .823
26.2LPTIM main features . . . . .823
26.3LPTIM implementation . . . . .824
28.3IWDG functional description . . . . .850
28.3.1IWDG block diagram . . . . .850
28.3.2Window option . . . . .851
28.3.3Hardware watchdog . . . . .852
28.3.4Register access protection . . . . .852
28.3.5Debug mode . . . . .852
28.4IWDG registers . . . . .853
28.4.1IWDG key register (IWDG_KR) . . . . .853
28.4.2IWDG prescaler register (IWDG_PR) . . . . .854
28.4.3IWDG reload register (IWDG_RLR) . . . . .855
28.4.4IWDG status register (IWDG_SR) . . . . .856
28.4.5IWDG window register (IWDG_WINR) . . . . .857
28.4.6IWDG register map . . . . .858
29System window watchdog (WWDG) . . . . .859
29.1Introduction . . . . .859
29.2WWDG main features . . . . .859
29.3WWDG functional description . . . . .859
29.3.1WWDG block diagram . . . . .860
29.3.2Enabling the watchdog . . . . .860
29.3.3Controlling the down-counter . . . . .860
29.3.4How to program the watchdog timeout . . . . .860
29.3.5Debug mode . . . . .862
29.4WWDG interrupts . . . . .862
29.5WWDG registers . . . . .862
29.5.1WWDG control register (WWDG_CR) . . . . .862
29.5.2WWDG configuration register (WWDG_CFR) . . . . .863
29.5.3WWDG status register (WWDG_SR) . . . . .864
29.5.4WWDG register map . . . . .864
30Real-time clock (RTC) . . . . .865
30.1Introduction . . . . .865
30.2RTC main features . . . . .865
30.3RTC functional description . . . . .866
30.3.1RTC block diagram . . . . .866
30.3.2RTC pins and internal signals . . . . .867
30.3.3GPIOs controlled by the RTC and TAMP . . . . .868
30.3.4Clock and prescalers . . . . .870
30.3.5Real-time clock and calendar . . . . .871
30.3.6Programmable alarms . . . . .872
30.3.7Periodic auto-wake-up . . . . .872
30.3.8RTC initialization and configuration . . . . .873
30.3.9Reading the calendar . . . . .875
30.3.10Resetting the RTC . . . . .876
30.3.11RTC synchronization . . . . .876
30.3.12RTC reference clock detection . . . . .877
30.3.13RTC smooth digital calibration . . . . .877
30.3.14Timestamp function . . . . .879
30.3.15Calibration clock output . . . . .880
30.3.16Tamper and alarm output . . . . .880
30.4RTC low-power modes . . . . .881
30.5RTC interrupts . . . . .882
30.6RTC registers . . . . .882
30.6.1RTC time register (RTC_TR) . . . . .882
30.6.2RTC date register (RTC_DR) . . . . .883
30.6.3RTC sub second register (RTC_SSR) . . . . .884
30.6.4RTC initialization control and status register (RTC_ICSR) . . . . .884
30.6.5RTC prescaler register (RTC_PRER) . . . . .886
30.6.6RTC wake-up timer register (RTC_WUTR) . . . . .887
30.6.7RTC control register (RTC_CR) . . . . .887
30.6.8RTC write protection register (RTC_WPR) . . . . .890
30.6.9RTC calibration register (RTC_CALR) . . . . .891
30.6.10RTC shift control register (RTC_SHIFT) . . . . .892
30.6.11RTC timestamp time register (RTC_TSTR) . . . . .893
30.6.12RTC timestamp date register (RTC_TSDR) . . . . .893
30.6.13RTC timestamp sub second register (RTC_TSSSR) . . . . .894
30.6.14RTC alarm A register (RTC_ALRMAR) . . . . .895
30.6.15RTC alarm A sub second register (RTC_ALRMASSR) . . . . .896
30.6.16RTC alarm B register (RTC_ALRMBR) . . . . .897
30.6.17RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .898
30.6.18RTC status register (RTC_SR) . . . . .898
30.6.19RTC masked interrupt status register (RTC_MISR) . . . . .899
30.6.20RTC status clear register (RTC_SCR) . . . . .900
30.6.21RTC register map .....902
31Tamper and backup registers (TAMP) .....904
31.1Introduction .....904
31.2TAMP main features .....904
31.3TAMP functional description .....905
31.3.1TAMP block diagram .....905
31.3.2TAMP pins and internal signals .....906
31.3.3TAMP register write protection .....906
31.3.4Tamper detection .....907
31.4TAMP low-power modes .....909
31.5TAMP interrupts .....909
31.6TAMP registers .....909
31.6.1TAMP control register 1 (TAMP_CR1) .....910
31.6.2TAMP control register 2 (TAMP_CR2) .....911
31.6.3TAMP filter control register (TAMP_FLTCR) .....912
31.6.4TAMP interrupt enable register (TAMP_IER) .....913
31.6.5TAMP status register (TAMP_SR) .....914
31.6.6TAMP masked interrupt status register (TAMP_MISR) .....915
31.6.7TAMP status clear register (TAMP_SCR) .....916
31.6.8TAMP backup x register (TAMP_BKPxR) .....917
31.6.9TAMP register map .....918
32Inter-integrated circuit interface (I2C) .....919
32.1Introduction .....919
32.2I2C main features .....919
32.3I2C implementation .....920
32.4I2C functional description .....920
32.4.1I2C block diagram .....921
32.4.2I2C pins and internal signals .....922
32.4.3I2C clock requirements .....922
32.4.4I2C mode selection .....922
32.4.5I2C initialization .....923
32.4.6I2C reset .....927
32.4.7I2C data transfer .....928
32.4.8I2C target mode .....930
32.4.9I2C controller mode . . . . .939
32.4.10I2C_TIMINGR register configuration examples . . . . .950
32.4.11SMBus specific features . . . . .952
32.4.12SMBus initialization . . . . .955
32.4.13SMBus I2C_TIMEOUTR register configuration examples . . . . .957
32.4.14SMBus target mode . . . . .958
32.4.15SMBus controller mode . . . . .961
32.4.16Wake-up from Stop mode on address match . . . . .964
32.4.17Error conditions . . . . .965
32.5I2C in low-power modes . . . . .967
32.6I2C interrupts . . . . .967
32.7I2C DMA requests . . . . .968
32.7.1Transmission using DMA . . . . .968
32.7.2Reception using DMA . . . . .968
32.8I2C debug modes . . . . .969
32.9I2C registers . . . . .969
32.9.1I2C control register 1 (I2C_CR1) . . . . .969
32.9.2I2C control register 2 (I2C_CR2) . . . . .972
32.9.3I2C own address 1 register (I2C_OAR1) . . . . .974
32.9.4I2C own address 2 register (I2C_OAR2) . . . . .975
32.9.5I2C timing register (I2C_TIMINGR) . . . . .976
32.9.6I2C timeout register (I2C_TIMEOUTR) . . . . .977
32.9.7I2C interrupt and status register (I2C_ISR) . . . . .978
32.9.8I2C interrupt clear register (I2C_ICR) . . . . .980
32.9.9I2C PEC register (I2C_PECR) . . . . .981
32.9.10I2C receive data register (I2C_RXDR) . . . . .981
32.9.11I2C transmit data register (I2C_TXDR) . . . . .982
32.9.12I2C register map . . . . .983
33Universal synchronous receiver transmitter (USART) . . . . .984
33.1USART introduction . . . . .984
33.2USART main features . . . . .985
33.3USART extended features . . . . .986
33.4USART implementation . . . . .986
33.5USART functional description . . . . .988
33.5.1USART block diagram . . . . .988
33.5.2USART signals . . . . .989
33.5.3USART character description . . . . .990
33.5.4USART FIFOs and thresholds . . . . .992
33.5.5USART transmitter . . . . .992
33.5.6USART receiver . . . . .996
33.5.7USART baud rate generation . . . . .1003
33.5.8Tolerance of the USART receiver to clock deviation . . . . .1004
33.5.9USART auto baud rate detection . . . . .1006
33.5.10USART multiprocessor communication . . . . .1008
33.5.11USART Modbus communication . . . . .1010
33.5.12USART parity control . . . . .1011
33.5.13USART LIN (local interconnection network) mode . . . . .1012
33.5.14USART synchronous mode . . . . .1014
33.5.15USART single-wire half-duplex communication . . . . .1018
33.5.16USART receiver timeout . . . . .1018
33.5.17USART smartcard mode . . . . .1019
33.5.18USART IrDA SIR ENDEC block . . . . .1023
33.5.19Continuous communication using USART and DMA . . . . .1026
33.5.20RS232 hardware flow control and RS485 Driver Enable . . . . .1028
33.5.21USART low-power management . . . . .1031
33.6USART in low-power modes . . . . .1034
33.7USART interrupts . . . . .1035
33.8USART registers . . . . .1036
33.8.1USART control register 1 (USART_CR1) . . . . .1036
33.8.2USART control register 1 [alternate] (USART_CR1) . . . . .1039
33.8.3USART control register 2 (USART_CR2) . . . . .1043
33.8.4USART control register 3 (USART_CR3) . . . . .1047
33.8.5USART baud rate register (USART_BRR) . . . . .1051
33.8.6USART guard time and prescaler register (USART_GTPR) . . . . .1051
33.8.7USART receiver timeout register (USART_RTOR) . . . . .1052
33.8.8USART request register (USART_RQR) . . . . .1053
33.8.9USART interrupt and status register (USART_ISR) . . . . .1054
33.8.10USART interrupt and status register [alternate] (USART_ISR) . . . . .1060
33.8.11USART interrupt flag clear register (USART_ICR) . . . . .1065
33.8.12USART receive data register (USART_RDR) . . . . .1067
33.8.13USART transmit data register (USART_TDR) . . . . .1067
33.8.14USART prescaler register (USART_PRESC) . . . . .1068
33.8.15USART register map . . . . .1069
34Low-power universal asynchronous receiver transmitter (LPUART) . . . . .1071
34.1LPUART introduction . . . . .1071
34.2LPUART main features . . . . .1072
34.3LPUART implementation . . . . .1073
34.4LPUART functional description . . . . .1074
34.4.1LPUART block diagram . . . . .1074
34.4.2LPUART signals . . . . .1075
34.4.3LPUART character description . . . . .1076
34.4.4LPUART FIFOs and thresholds . . . . .1077
34.4.5LPUART transmitter . . . . .1078
34.4.6LPUART receiver . . . . .1081
34.4.7LPUART baud rate generation . . . . .1085
34.4.8Tolerance of the LPUART receiver to clock deviation . . . . .1086
34.4.9LPUART multiprocessor communication . . . . .1087
34.4.10LPUART parity control . . . . .1089
34.4.11LPUART single-wire half-duplex communication . . . . .1090
34.4.12Continuous communication using DMA and LPUART . . . . .1090
34.4.13RS232 hardware flow control and RS485 Driver Enable . . . . .1093
34.4.14LPUART low-power management . . . . .1095
34.5LPUART in low-power modes . . . . .1098
34.6LPUART interrupts . . . . .1099
34.7LPUART registers . . . . .1100
34.7.1LPUART control register 1 (LPUART_CR1) . . . . .1100
34.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .1103
34.7.3LPUART control register 2 (LPUART_CR2) . . . . .1106
34.7.4LPUART control register 3 (LPUART_CR3) . . . . .1108
34.7.5LPUART baud rate register (LPUART_BRR) . . . . .1111
34.7.6LPUART request register (LPUART_RQR) . . . . .1111
34.7.7LPUART interrupt and status register (LPUART_ISR) . . . . .1112
34.7.8LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .1116
34.7.9LPUART interrupt flag clear register (LPUART_ICR) . . . . .1119
34.7.10LPUART receive data register (LPUART_RDR) . . . . .1120
34.7.11LPUART transmit data register (LPUART_TDR) . . . . .1120
34.7.12LPUART prescaler register (LPUART_PRESC) .....1121
34.7.13LPUART register map .....1122
35Serial peripheral interface / integrated interchip sound (SPI/I2S) .1124
35.1Introduction .....1124
35.2SPI main features .....1124
35.3I2S main features .....1125
35.4SPI/I2S implementation .....1125
35.5SPI functional description .....1126
35.5.1General description .....1126
35.5.2Communications between one master and one slave .....1127
35.5.3Standard multislave communication .....1129
35.5.4Multimaster communication .....1130
35.5.5Slave select (NSS) pin management .....1131
35.5.6Communication formats .....1132
35.5.7Configuration of SPI .....1134
35.5.8Procedure for enabling SPI .....1135
35.5.9Data transmission and reception procedures .....1135
35.5.10SPI status flags .....1145
35.5.11SPI error flags .....1146
35.5.12NSS pulse mode .....1147
35.5.13TI mode .....1147
35.5.14CRC calculation .....1148
35.6SPI interrupts .....1150
35.7I2S functional description .....1151
35.7.1I2S general description .....1151
35.7.2Supported audio protocols .....1152
35.7.3Start-up description .....1159
35.7.4Clock generator .....1161
35.7.5I 2 S master mode .....1164
35.7.6I 2 S slave mode .....1165
35.7.7I2S status flags .....1167
35.7.8I2S error flags .....1168
35.7.9DMA features .....1169
35.8I2S interrupts .....1169
35.9SPI and I2S registers .....1170
36.4.10FDCAN timeout counter configuration register (FDCAN_TOCC) . . .1222
36.4.11FDCAN timeout counter value register (FDCAN_TOCV) . . . . .1223
36.4.12FDCAN error counter register (FDCAN_ECR) . . . . .1223
36.4.13FDCAN protocol status register (FDCAN_PSR) . . . . .1224
36.4.14FDCAN transmitter delay compensation register (FDCAN_TDCR) . .1226
36.4.15FDCAN interrupt register (FDCAN_IR) . . . . .1226
36.4.16FDCAN interrupt enable register (FDCAN_IE) . . . . .1229
36.4.17FDCAN interrupt line select register (FDCAN_ILS) . . . . .1231
36.4.18FDCAN interrupt line enable register (FDCAN_ILE) . . . . .1232
36.4.19FDCAN global filter configuration register (FDCAN_RXGFC) . . . . .1232
36.4.20FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . .1234
36.4.21FDCAN high-priority message status register (FDCAN_HPMS) . . . .1234
36.4.22FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . .1235
36.4.23CAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . .1236
36.4.24FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . .1236
36.4.25FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . .1237
36.4.26FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . .1237
36.4.27FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . .1238
36.4.28FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . .1238
36.4.29FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . .1239
36.4.30FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . .1240
36.4.31FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO)1240
36.4.32FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . .1241
36.4.33FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE) . . . . .		1241
36.4.34FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_TXBCIE) . . . . .		1242
36.4.35FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . .1242
36.4.36FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . .1243
36.4.37FDCAN CFG clock divider register (FDCAN_CKDIV) . . . . .1243
36.4.38FDCAN register map . . . . .1244
37Universal serial bus full-speed host/device interface (USB) . . . . .1248
37.1Introduction . . . . .1248
37.2USB main features . . . . .1248
37.3USB implementation . . . . .1248
37.4USB functional description . . . . .1249
38.4UCPD functional description . . . . .1297
38.4.1UCPD block diagram . . . . .1298
38.4.2UCPD reset and clocks . . . . .1299
38.4.3Physical layer protocol . . . . .1300
38.4.4UCPD BMC transmitter . . . . .1306
38.4.5UCPD BMC receiver . . . . .1308
38.4.6UCPD Type-C pull-ups (Rp) and pull-downs (Rd) . . . . .1309
38.4.7UCPD Type-C voltage monitoring and de-bouncing . . . . .1310
38.4.8UCPD fast role swap (FRS) . . . . .1310
38.4.9UCPD DMA Interface . . . . .1310
38.4.10Wake-up from Stop mode . . . . .1310
38.5UCPD programming sequences . . . . .1311
38.5.1Initialization phase . . . . .1311
38.5.2Type-C state machine handling . . . . .1311
38.5.3USB PD transmit . . . . .1313
38.5.4USB PD receive . . . . .1314
38.6UCPD low-power modes . . . . .1315
38.7UCPD interrupts . . . . .1316
38.8UCPD registers . . . . .1317
38.8.1UCPD configuration register 1 (UCPD_CFGR1) . . . . .1317
38.8.2UCPD configuration register 2 (UCPD_CFGR2) . . . . .1319
38.8.3UCPD control register (UCPD_CR) . . . . .1320
38.8.4UCPD interrupt mask register (UCPD_IMR) . . . . .1322
38.8.5UCPD status register (UCPD_SR) . . . . .1324
38.8.6UCPD interrupt clear register (UCPD_ICR) . . . . .1327
38.8.7UCPD Tx ordered set type register (UCPD_TX_ORDSETR) . . . . .1328
38.8.8UCPD Tx payload size register (UCPD_TX_PAYSZR) . . . . .1328
38.8.9UCPD Tx data register (UCPD_TXDR) . . . . .1329
38.8.10UCPD Rx ordered set register (UCPD_RX_ORDSETR) . . . . .1329
38.8.11UCPD Rx payload size register (UCPD_RX_PAYSZR) . . . . .1330
38.8.12UCPD receive data register (UCPD_RXDR) . . . . .1331
38.8.13UCPD Rx ordered set extension register 1
(UCPD_RX_ORDEXTR1) . . . . .		1331
38.8.14UCPD Rx ordered set extension register 2
(UCPD_RX_ORDEXTR2) . . . . .		1332
38.8.15UCPD register map . . . . .1332
39HDMI-CEC controller (CEC) . . . . .1335
39.1HDMI-CEC introduction . . . . .1335
39.2HDMI-CEC controller main features . . . . .1335
39.3HDMI-CEC functional description . . . . .1336
39.3.1HDMI-CEC pin . . . . .1336
39.3.2HDMI-CEC block diagram . . . . .1336
39.3.3Message description . . . . .1336
39.3.4Bit timing . . . . .1337
39.4Arbitration . . . . .1338
39.4.1SFT option bit . . . . .1339
39.5Error handling . . . . .1340
39.5.1Bit error . . . . .1340
39.5.2Message error . . . . .1340
39.5.3Bit rising error (BRE) . . . . .1340
39.5.4Short bit period error (SBPE) . . . . .1341
39.5.5Long bit period error (LBPE) . . . . .1341
39.5.6Transmission error detection (TXERR) . . . . .1342
39.6HDMI-CEC interrupts . . . . .1344
39.7HDMI-CEC registers . . . . .1345
39.7.1CEC control register (CEC_CR) . . . . .1345
39.7.2CEC configuration register (CEC_CFGR) . . . . .1346
39.7.3CEC Tx data register (CEC_TXDR) . . . . .1348
39.7.4CEC Rx data register (CEC_RXDR) . . . . .1348
39.7.5CEC interrupt and status register (CEC_ISR) . . . . .1348
39.7.6CEC interrupt enable register (CEC_IER) . . . . .1350
39.7.7HDMI-CEC register map . . . . .1352
40Debug support (DBG) . . . . .1353
40.1Overview . . . . .1353
40.2Reference Arm documentation . . . . .1354
40.3Pinout and debug port pins . . . . .1354
40.3.1SWD port pins . . . . .1354
40.3.2SW-DP pin assignment . . . . .1354
40.3.3Internal pull-up & pull-down on SWD pins . . . . .1355
40.4ID codes and locking mechanism . . . . .1355
40.5SWD port . . . . .1355
40.5.1SWD protocol introduction . . . . .1355
40.5.2SWD protocol sequence . . . . .1355
40.5.3SW-DP state machine (reset, idle states, ID code) . . . . .1356
40.5.4DP and AP read/write accesses . . . . .1357
40.5.5SW-DP registers . . . . .1357
40.5.6SW-AP registers . . . . .1358
40.6Core debug . . . . .1359
40.7BPU (Break Point Unit) . . . . .1359
40.7.1BPU functionality . . . . .1360
40.8DWT (Data Watchpoint) . . . . .1360
40.8.1DWT functionality . . . . .1360
40.8.2DWT Program Counter Sample Register . . . . .1360
40.9MCU debug component (DBG) . . . . .1360
40.9.1Debug support for low-power modes . . . . .1360
40.9.2Debug support for timers, watchdog and I 2 C . . . . .1361
40.10DBG registers . . . . .1361
40.10.1DBG device ID code register (DBG_IDCODE) . . . . .1361
40.10.2DBG configuration register (DBG_CR) . . . . .1362
40.10.3DBG APB freeze register 1 (DBG_APB_FZ1) . . . . .1363
40.10.4DBG APB freeze register 2 (DBG_APB_FZ2) . . . . .1365
40.10.5DBG register map . . . . .1366
41Device electronic signature . . . . .1368
41.1Unique device ID register (96 bits) . . . . .1368
41.2Flash memory size data register . . . . .1369
41.3Package data register . . . . .1369
42Important security notice . . . . .1371
43Revision history . . . . .1372

List of tables

Table 1. Peripherals versus devices . . . . . 56

Table 2. STM32G0B1xx and STM32G0C1xx memory boundary addresses . . . . . 62

Table 3. STM32G071xx and STM32G081xx memory boundary addresses . . . . . 62

Table 4. STM32G051xx and STM32G061xx memory boundary addresses . . . . . 62

Table 5. STM32G031xx and STM32G041xx memory boundary addresses . . . . . 63

Table 6. STM32G0x1 peripheral register boundary addresses . . . . . 64

Table 7. SRAM size . . . . . 66

Table 8. Boot modes . . . . . 68

Table 9. Flash memory organization for single-bank devices . . . . . 71

Table 10. Flash memory organization for 256 KB dual-bank devices . . . . . 72

Table 11. Flash memory organization for 512 KB devices . . . . . 73

Table 12. Flash memory bank mapping . . . . . 73

Table 13. Number of wait states according to flash memory clock (HCLK) frequency . . . . . 75

Table 14. Page erase overview . . . . . 78

Table 15. Mass erase overview . . . . . 78

Table 16. Option byte format . . . . . 82

Table 17. Organization of option bytes . . . . . 83

Table 18. Flash memory read protection status . . . . . 86

Table 20. Access status versus protection level and execution modes . . . . . 88

Table 23. Securable memory erase at RDP Level 1 to Level 0 change . . . . . 92

Table 24. FLASH interrupt requests . . . . . 93

Table 25. FLASH register map and reset values . . . . . 112

Table 26. Low-power mode summary . . . . . 123

Table 27. Functionalities depending on the working mode . . . . . 124

Table 28. Low-power run . . . . . 127

Table 29. Sleep mode summary . . . . . 128

Table 30. Low-power sleep mode summary . . . . . 129

Table 31. Stop 0 mode summary . . . . . 131

Table 32. Stop 1 mode summary . . . . . 132

Table 33. Standby mode summary . . . . . 134

Table 34. Shutdown mode summary . . . . . 136

Table 35. PWR register map and reset values . . . . . 153

Table 36. Clock source frequency . . . . . 166

Table 37. RCC register map and reset values . . . . . 213

Table 38. CRS features . . . . . 217

Table 39. CRS internal input/output signals . . . . . 218

Table 40. CRS interconnection . . . . . 219

Table 41. Effect of low-power modes on CRS . . . . . 222

Table 42. Interrupt control bits . . . . . 222

Table 43. CRS register map and reset values . . . . . 227

Table 44. Port bit configuration table . . . . . 229

Table 45. Effect of low-power modes on the GPIO . . . . . 238

Table 46. GPIO register map and reset values . . . . . 245

Table 47. SYSCFG register map and reset values . . . . . 265

Table 48. Interconnect matrix . . . . . 268

Table 49. DMA implementation . . . . . 276

Table 50. DMA internal input/output signals . . . . . 277

Table 51. Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . 283

ST logo
ST logo
Table 52.DMA interrupt requests . . . . .285
Table 53.DMA register map and reset values . . . . .293
Table 54.DMAMUX instantiation . . . . .297
Table 55.DMAMUX: assignment of multiplexer inputs to resources . . . . .298
Table 56.DMAMUX: assignment of trigger inputs to resources . . . . .298
Table 57.DMAMUX: assignment of synchronization inputs to resources . . . . .299
Table 58.DMAMUX signals . . . . .301
Table 59.DMAMUX interrupts . . . . .305
Table 60.DMAMUX register map and reset values . . . . .310
Table 61.Vector table . . . . .312
Table 62.EXTI signal overview . . . . .316
Table 63.EVG pin overview . . . . .316
Table 64.EXTI event input configurations and register control . . . . .318
Table 65.EXTI line connections . . . . .320
Table 66.Masking functionality . . . . .321
Table 67.EXTI register map sections . . . . .322
Table 68.EXTI controller register map and reset values . . . . .332
Table 69.CRC internal input/output signals . . . . .335
Table 70.CRC register map and reset values . . . . .340
Table 71.ADC input/output pins . . . . .343
Table 72.ADC internal input/output signals . . . . .344
Table 73.External triggers . . . . .344
Table 74.Latency between trigger and start of conversion . . . . .350
Table 75.Configuring the trigger polarity . . . . .357
Table 76.tSAR timings depending on resolution . . . . .359
Table 77.Analog watchdog comparison . . . . .368
Table 78.Analog watchdog 1 channel selection . . . . .368
Table 79.Maximum output results vs N and M. Grayed values indicates truncation . . . . .373
Table 80.ADC interrupts . . . . .378
Table 81.ADC register map and reset values . . . . .397
Table 82.DAC features . . . . .401
Table 83.DAC input/output pins . . . . .403
Table 84.DAC internal input/output signals . . . . .403
Table 85.DAC interconnection . . . . .404
Table 86.Sample and refresh timings . . . . .411
Table 87.Channel output modes summary . . . . .412
Table 88.Effect of low-power modes on DAC . . . . .419
Table 89.DAC interrupts . . . . .420
Table 90.DAC register map and reset values . . . . .435
Table 91.VREF buffer modes . . . . .437
Table 92.VREFBUF register map and reset values . . . . .439
Table 93.COMP1 non-inverting input assignment . . . . .441
Table 94.COMP1 inverting input assignment . . . . .442
Table 95.COMP2 non-inverting input assignment . . . . .442
Table 96.COMP2 inverting input assignment . . . . .442
Table 97.COMP3 non-inverting input assignment . . . . .443
Table 98.COMP3 inverting input assignment . . . . .443
Table 99.Comparator behavior in the low power modes . . . . .446
Table 100.Interrupt control bits . . . . .446
Table 101.COMP register map and reset values . . . . .453
Table 102.RNG internal input/output signals . . . . .455
Table 103.RNG interrupt requests . . . . .461
Table 104.RNG configurations . . . . .462
Table 105.RNG register map and reset map . . . . .465
Table 106.AES internal input/output signals . . . . .467
Table 107.CTR mode initialization vector definition . . . . .484
Table 108.GCM last block definition . . . . .486
Table 109.Initialization of AES_IVRx registers in GCM mode . . . . .487
Table 110.Initialization of AES_IVRx registers in CCM mode . . . . .494
Table 111.Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .499
Table 112.AES interrupt requests . . . . .502
Table 113.Processing latency for ECB, CBC and CTR . . . . .502
Table 114.Processing latency for GCM and CCM (in clock cycles) . . . . .503
Table 115.AES register map and reset values . . . . .513
Table 116.Behavior of timer outputs versus BRK/BRK2 inputs . . . . .557
Table 117.Break protection disarming conditions . . . . .559
Table 118.Counting direction versus encoder signals . . . . .565
Table 119.TIM1 internal trigger connection . . . . .582
Table 120.Output control bits for complementary OCx and OCxN channels with break feature . . . . .596
Table 121.TIM1 register map and reset values . . . . .614
Table 122.Counting direction versus encoder signals . . . . .650
Table 123.TIMx internal trigger connection . . . . .668
Table 124.Output control bit for standard OCx channels . . . . .679
Table 125.TIM2/TIM3/TIM4 register map and reset values . . . . .691
Table 126.TIMx register map and reset values . . . . .706
Table 127.Output control bit for standard OCx channels . . . . .729
Table 128.TIM14 register map and reset values . . . . .731
Table 129.Break protection disarming conditions . . . . .761
Table 130.TIMx Internal trigger connection . . . . .777
Table 131.Output control bits for complementary OCx and OCxN channels with break feature (TIM15) . . . . .787
Table 132.TIM15 register map and reset values . . . . .796
Table 133.Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . . . . .809
Table 134.TIM16/TIM17 register map and reset values . . . . .821
Table 135.STM32G0x1 LPTIM features . . . . .824
Table 136.LPTIM input/output pins . . . . .825
Table 137.LPTIM internal signals . . . . .825
Table 138.LPTIM1 external trigger connection . . . . .825
Table 139.LPTIM2 external trigger connection . . . . .826
Table 140.LPTIM1 input 1 connection . . . . .826
Table 141.LPTIM1 input 2 connection . . . . .826
Table 142.LPTIM2 input 1 connection . . . . .826
Table 143.Prescaler division ratios . . . . .828
Table 144.Encoder counting scenarios . . . . .835
Table 145.Effect of low-power modes on the LPTIM . . . . .836
Table 146.Interrupt events . . . . .837
Table 147.LPTIM register map and reset values . . . . .848
Table 148.IWDG register map and reset values . . . . .858
Table 149.WWDG register map and reset values . . . . .864
Table 150.RTC input/output pins . . . . .867
Table 151.RTC internal input/output signals . . . . .867
Table 152.RTC interconnection . . . . .868
Table 153.PC13 configuration . . . . .868
Table 154.RTC_OUT mapping . . . . .870
Table 155.Effect of low-power modes on RTC . . . . .881
Table 156.RTC pins functionality over modes . . . . .881
Table 157.Interrupt requests . . . . .882
Table 158.RTC register map and reset values . . . . .902
Table 159.TAMP input/output pins . . . . .906
Table 160.TAMP internal input/output signals . . . . .906
Table 161.TAMP interconnection . . . . .906
Table 162.Effect of low-power modes on TAMP . . . . .909
Table 163.Interrupt requests . . . . .909
Table 164.TAMP register map and reset values . . . . .918
Table 165.I 2 C implementation . . . . .920
Table 166.I 2 C input/output pins . . . . .922
Table 167.I 2 C internal input/output signals . . . . .922
Table 168.Comparison of analog and digital filters . . . . .924
Table 169.I 2 C-bus and SMBus specification data setup and hold times . . . . .926
Table 170.I 2 C configuration . . . . .930
Table 171.I 2 C-bus and SMBus specification clock timings . . . . .941
Table 172.Timing settings for f I2CCLK of 8 MHz . . . . .951
Table 173.Timing settings for f I2CCLK of 16 MHz . . . . .951
Table 174.Timing settings for f I2CCLK of 48 MHz . . . . .952
Table 175.SMBus timeout specifications . . . . .954
Table 176.SMBus with PEC configuration . . . . .956
Table 177.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms . . . . .957
Table 178.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .957
Table 179.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .957
Table 180.Effect of low-power modes to I 2 C . . . . .967
Table 181.I 2 C interrupt requests . . . . .967
Table 182.I 2 C register map and reset values . . . . .983
Table 183.Instance implementation on STM32G0x1 . . . . .986
Table 184.USART / LPUART features . . . . .987
Table 185.USART input/output pins . . . . .990
Table 186.USART internal input/output signals . . . . .990
Table 187.Noise detection from sampled data . . . . .1002
Table 188.Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .1005
Table 189.Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . .1006
Table 190.USART frame formats . . . . .1011
Table 191.Effect of low-power modes on the USART . . . . .1034
Table 192.USART interrupt requests . . . . .1035
Table 193.USART register map and reset values . . . . .1069
Table 194.Instance implementation on STM32G0x1 . . . . .1073
Table 195.USART / LPUART features . . . . .1073
Table 196.LPUART input/output pins . . . . .1075
Table 197.LPUART internal input/output signals . . . . .1075
Table 198.Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz . . . . .1085
Table 199.Error calculation for programmed baud rates at fCK = 100 MHz . . . . .1086
Table 200.Tolerance of the LPUART receiver . . . . .1087
Table 202.Effect of low-power modes on the LPUART . . . . .1098
Table 203.LPUART interrupt requests . . . . .1099
Table 204.LPUART register map and reset values . . . . .1122
Table 205.STM32G0x1 SPI and SPI/I2S implementation . . . . .1125
Table 206.SPI interrupt requests . . . . .1150
Table 207.Audio-frequency precision using 48 MHz clock derived from HSE . . . . .1163
Table 208.I2S interrupt requests . . . . .1169
Table 209.SPI/I2S register map and reset values . . . . .1181
Table 210.CAN subsystem I/O signals . . . . .1186
Table 211.CAN subsystem I/O pins . . . . .1186
Table 212.DLC coding in FDCAN . . . . .1190
Table 213.Possible configurations for frame transmission . . . . .1204
Table 214.Rx FIFO element . . . . .1207
Table 215.Rx FIFO element description . . . . .1207
Table 216.Tx buffer and FIFO element . . . . .1209
Table 217.Tx buffer element description . . . . .1209
Table 218.Tx event FIFO element . . . . .1211
Table 219.Tx event FIFO element description . . . . .1211
Table 220.Standard message ID filter element . . . . .1212
Table 221.Standard message ID filter element field description . . . . .1213
Table 222.Extended message ID filter element . . . . .1213
Table 223.Extended message ID filter element field description . . . . .1214
Table 224.FDCAN register map and reset values . . . . .1244
Table 225.STM32G0x1 USB implementation . . . . .1248
Table 226.USB input/output pins . . . . .1249
Table 227.Double-buffering buffer flag definition . . . . .1262
Table 228.Bulk double-buffering memory buffers usage (Device mode) . . . . .1262
Table 229.Bulk double-buffering memory buffers usage (Host mode) . . . . .1264
Table 230.Isochronous memory buffers usage . . . . .1265
Table 231.Isochronous memory buffers usage . . . . .1266
Table 232.Resume event detection . . . . .1268
Table 233.Resume event detection for host . . . . .1269
Table 234.Reception status encoding . . . . .1287
Table 235.Endpoint/channel type encoding . . . . .1287
Table 236.Endpoint/channel kind meaning . . . . .1287
Table 237.Transmission status encoding . . . . .1287
Table 238.USB register map and reset values . . . . .1289
Table 239.Definition of allocated buffer memory . . . . .1292
Table 240.USBFSRAM register map and reset values . . . . .1295
Table 241.UCPD implementation . . . . .1297
Table 242.UCPD signals on pins . . . . .1298
Table 243.UCPD internal signals . . . . .1299
Table 244.4b5b symbol encoding table . . . . .1300
Table 245.Ordered sets . . . . .1302
Table 246.Validation of ordered sets . . . . .1302
Table 247.Data size . . . . .1303
Table 248.Coding for ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx . . . . .1311
Table 249.Type-C sequence (source: 3A); cable/sink connected (Rd on CC1; Ra on CC2) . . . . .1313
Table 250.Effect of low power modes on the UCPD . . . . .1315
Table 251.UCPD interrupt requests . . . . .1316
Table 252.UCPD register map and reset values . . . . .1332
Table 253.HDMI pin . . . . .1336
Table 254.Error handling timing parameters . . . . .1342
Table 255.TXERR timing parameters . . . . .1343
Table 256.HDMI-CEC interrupts . . . . .1344
Table 257.HDMI-CEC register map and reset values . . . . .1352
Table 258.SW debug port pins . . . . .1354
Table 259.Packet request (8-bits) . . . . .1356
Table 260.ACK response (3 bits). . . . .1356
Table 261.DATA transfer (33 bits). . . . .1356
Table 262.SW-DP registers . . . . .1357
Table 263.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .1358
Table 264.Core debug registers . . . . .1359
Table 265.DEV_ID and REV_ID field values. . . . .1361
Table 266.DBG register map and reset values . . . . .1366
Table 267.Document revision history . . . . .1372

List of figures

Figure 1. System architecture . . . . . 58

Figure 2. Memory map . . . . . 61

Figure 3. Changing read protection (RDP) level . . . . . 88

Figure 4. Example of disabling core debug access . . . . . 92

Figure 5. Power supply overview . . . . . 115

Figure 6. POR, PDR, and BOR thresholds . . . . . 119

Figure 7. PVD thresholds . . . . . 120

Figure 8. Low-power modes state diagram . . . . . 122

Figure 9. Simplified diagram of the reset circuit . . . . . 156

Figure 10. Clock tree . . . . . 161

Figure 11. HSE/ LSE clock sources . . . . . 162

Figure 12. Frequency measurement with TIM14 in capture mode . . . . . 170

Figure 13. Frequency measurement with TIM16 in capture mode . . . . . 171

Figure 14. Frequency measurement with TIM17 in capture mode . . . . . 171

Figure 15. CRS block diagram . . . . . 218

Figure 16. CRS counter behavior . . . . . 220

Figure 17. Basic structure of an I/O port bit . . . . . 229

Figure 18. Input floating/pull up/pull down configurations . . . . . 234

Figure 19. Output configuration . . . . . 235

Figure 20. Alternate function configuration- . . . . . 236

Figure 21. High impedance-analog configuration . . . . . 236

Figure 22. DMA block diagram . . . . . 277

Figure 23. DMAMUX block diagram . . . . . 300

Figure 24. Synchronization mode of the DMAMUX request line multiplexer channel . . . . . 303

Figure 25. Event generation of the DMA request line multiplexer channel . . . . . 303

Figure 26. EXTI block diagram . . . . . 316

Figure 27. Configurable event trigger logic CPU wake-up . . . . . 318

Figure 28. Direct event trigger logic CPU wake-up . . . . . 319

Figure 29. EXTI GPIO mux . . . . . 320

Figure 30. CRC calculation unit block diagram . . . . . 335

Figure 31. ADC block diagram . . . . . 343

Figure 32. ADC calibration . . . . . 346

Figure 33. Calibration factor forcing . . . . . 347

Figure 34. Enabling/disabling the ADC . . . . . 348

Figure 35. ADC clock scheme . . . . . 349

Figure 36. ADC connectivity . . . . . 351

Figure 37. Analog-to-digital conversion time . . . . . 356

Figure 38. ADC conversion timings . . . . . 356

Figure 39. Stopping an ongoing conversion . . . . . 357

Figure 40. Single conversions of a sequence, software trigger . . . . . 360

Figure 41. Continuous conversion of a sequence, software trigger . . . . . 360

Figure 42. Single conversions of a sequence, hardware trigger . . . . . 361

Figure 43. Continuous conversions of a sequence, hardware trigger . . . . . 361

Figure 44. Data alignment and resolution (oversampling disabled: OVSE = 0). . . . . 362

Figure 45. Example of overrun (OVR) . . . . . 363

Figure 46. Wait mode conversion (continuous mode, software trigger). . . . . 366

Figure 47. Behavior with WAIT = 0, AUTOFF = 1 . . . . . 367

Figure 48. Behavior with WAIT = 1, AUTOFF = 1 . . . . . 367

Figure 49.Analog watchdog guarded area . . . . .368
Figure 50.ADC_AWDx_OUT signal generation . . . . .370
Figure 51.ADC_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . .370
Figure 52.ADC_AWDx_OUT signal generation (on a single channel) . . . . .371
Figure 53.Analog watchdog threshold update . . . . .371
Figure 54.20-bit to 16-bit result truncation . . . . .372
Figure 55.Numerical example with 5-bit shift and rounding . . . . .372
Figure 56.Triggered oversampling mode (TOVS bit = 1) . . . . .374
Figure 57.Temperature sensor and VREFINT channel block diagram . . . . .375
Figure 58.VBAT channel block diagram . . . . .377
Figure 59.Dual-channel DAC block diagram . . . . .402
Figure 60.Data registers in single DAC channel mode . . . . .405
Figure 61.Data registers in dual DAC channel mode . . . . .405
Figure 62.Timing diagram for conversion with trigger disabled TEN = 0 . . . . .406
Figure 63.DAC LFSR register calculation algorithm . . . . .408
Figure 64.DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .408
Figure 65.DAC triangle wave generation . . . . .409
Figure 66.DAC conversion (SW trigger enabled) with triangle wave generation . . . . .409
Figure 67.DAC sample and hold mode phase diagram . . . . .412
Figure 68.Comparator block diagram . . . . .441
Figure 69.Window mode . . . . .444
Figure 70.Comparator hysteresis . . . . .444
Figure 71.Comparator output blanking . . . . .445
Figure 72.RNG block diagram . . . . .455
Figure 73.Entropy source model . . . . .456
Figure 74.RNG initialization overview . . . . .458
Figure 75.AES block diagram . . . . .467
Figure 76.ECB encryption and decryption principle . . . . .469
Figure 77.CBC encryption and decryption principle . . . . .470
Figure 78.CTR encryption and decryption principle . . . . .471
Figure 79.GCM encryption and authentication principle . . . . .472
Figure 80.GMAC authentication principle . . . . .472
Figure 81.CCM encryption and authentication principle . . . . .473
Figure 82.Example of suspend mode management . . . . .477
Figure 83.ECB encryption . . . . .478
Figure 84.ECB decryption . . . . .478
Figure 85.CBC encryption . . . . .479
Figure 86.CBC decryption . . . . .479
Figure 87.ECB/CBC encryption (Mode 1) . . . . .480
Figure 88.ECB/CBC decryption (Mode 3) . . . . .481
Figure 89.Message construction in CTR mode . . . . .483
Figure 90.CTR encryption . . . . .483
Figure 91.CTR decryption . . . . .484
Figure 92.Message construction in GCM . . . . .485
Figure 93.GCM authenticated encryption . . . . .487
Figure 94.Message construction in GMAC mode . . . . .491
Figure 95.GMAC authentication mode . . . . .491
Figure 96.Message construction in CCM mode . . . . .492
Figure 97.CCM mode authenticated encryption . . . . .494
Figure 98.128-bit block construction with respect to data swap . . . . .498
Figure 99.DMA transfer of a 128-bit data block during input phase . . . . .500
Figure 100.DMA transfer of a 128-bit data block during output phase . . . . .501
Figure 101. Advanced-control timer block diagram . . . . .517
Figure 102. Counter timing diagram with prescaler division change from 1 to 2 . . . . .519
Figure 103. Counter timing diagram with prescaler division change from 1 to 4 . . . . .519
Figure 104. Counter timing diagram, internal clock divided by 1 . . . . .521
Figure 105. Counter timing diagram, internal clock divided by 2 . . . . .521
Figure 106. Counter timing diagram, internal clock divided by 4 . . . . .522
Figure 107. Counter timing diagram, internal clock divided by N . . . . .522
Figure 108. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .523
Figure 109. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .523
Figure 110. Counter timing diagram, internal clock divided by 1 . . . . .525
Figure 111. Counter timing diagram, internal clock divided by 2 . . . . .525
Figure 112. Counter timing diagram, internal clock divided by 4 . . . . .526
Figure 113. Counter timing diagram, internal clock divided by N . . . . .526
Figure 114. Counter timing diagram, update event when repetition counter is not used . . . . .527
Figure 115. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .528
Figure 116. Counter timing diagram, internal clock divided by 2 . . . . .529
Figure 117. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .529
Figure 118. Counter timing diagram, internal clock divided by N . . . . .530
Figure 119. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .530
Figure 120. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .531
Figure 121. Update rate examples depending on mode and TIMx_RCR register settings . . . . .532
Figure 122. External trigger input block . . . . .533
Figure 123. TIM1 ETR input circuitry . . . . .533
Figure 124. Control circuit in normal mode, internal clock divided by 1 . . . . .534
Figure 125. TI2 external clock connection example . . . . .535
Figure 126. Control circuit in external clock mode 1 . . . . .536
Figure 127. External trigger input block . . . . .536
Figure 128. Control circuit in external clock mode 2 . . . . .537
Figure 129. Capture/compare channel (example: channel 1 input stage) . . . . .538
Figure 130. Capture/compare channel 1 main circuit . . . . .538
Figure 131. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .539
Figure 132. Output stage of capture/compare channel (channel 4) . . . . .539
Figure 133. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .540
Figure 134. PWM input mode timing . . . . .542
Figure 135. Output compare mode, toggle on OC1 . . . . .544
Figure 136. Edge-aligned PWM waveforms (ARR=8) . . . . .545
Figure 137. Center-aligned PWM waveforms (ARR=8) . . . . .546
Figure 138. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .548
Figure 139. Combined PWM mode on channel 1 and 3 . . . . .549
Figure 140. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .550
Figure 141. Complementary output with dead-time insertion . . . . .551
Figure 142. Dead-time waveforms with delay greater than the negative pulse . . . . .551
Figure 143. Dead-time waveforms with delay greater than the positive pulse . . . . .552
Figure 144. Break and Break2 circuitry overview . . . . .554
Figure 145. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .556
Figure 146. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .557
Figure 147. PWM output state following BRK assertion (OSSI=0) . . . . .558
Figure 148. Output redirection (BRK2 request not represented) . . . . .559
Figure 149. Clearing TIMx_OCxREF . . . . .560
Figure 150. 6-step generation, COM example (OSSR=1) . . . . .561
Figure 151. Example of one pulse mode . . . . .562
Figure 152. Retriggerable one pulse mode . . . . .564
Figure 153. Example of counter operation in encoder interface mode. . . . .565
Figure 154. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .566
Figure 155. Measuring time interval between edges on 3 signals . . . . .567
Figure 156. Example of Hall sensor interface . . . . .569
Figure 157. Control circuit in reset mode . . . . .570
Figure 158. Control circuit in Gated mode . . . . .571
Figure 159. Control circuit in trigger mode . . . . .572
Figure 160. Control circuit in external clock mode 2 + trigger mode . . . . .573
Figure 161. General-purpose timer block diagram . . . . .618
Figure 162. Counter timing diagram with prescaler division change from 1 to 2 . . . . .620
Figure 163. Counter timing diagram with prescaler division change from 1 to 4 . . . . .620
Figure 164. Counter timing diagram, internal clock divided by 1 . . . . .621
Figure 165. Counter timing diagram, internal clock divided by 2 . . . . .622
Figure 166. Counter timing diagram, internal clock divided by 4 . . . . .622
Figure 167. Counter timing diagram, internal clock divided by N . . . . .623
Figure 168. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .623
Figure 169. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .624
Figure 170. Counter timing diagram, internal clock divided by 1 . . . . .625
Figure 171. Counter timing diagram, internal clock divided by 2 . . . . .625
Figure 172. Counter timing diagram, internal clock divided by 4 . . . . .626
Figure 173. Counter timing diagram, internal clock divided by N . . . . .626
Figure 174. Counter timing diagram, Update event . . . . .627
Figure 175. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .628
Figure 176. Counter timing diagram, internal clock divided by 2 . . . . .629
Figure 177. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .629
Figure 178. Counter timing diagram, internal clock divided by N . . . . .630
Figure 179. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .630
Figure 180. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .631
Figure 181. Control circuit in normal mode, internal clock divided by 1 . . . . .632
Figure 182. TI2 external clock connection example. . . . .632
Figure 183. Control circuit in external clock mode 1 . . . . .633
Figure 184. External trigger input block . . . . .634
Figure 185. Control circuit in external clock mode 2 . . . . .635
Figure 186. Capture/Compare channel (example: channel 1 input stage) . . . . .635
Figure 187. Capture/Compare channel 1 main circuit . . . . .636
Figure 188. Output stage of Capture/Compare channel (channel 1). . . . .636
Figure 189. PWM input mode timing . . . . .638
Figure 190. Output compare mode, toggle on OC1 . . . . .640
Figure 191. Edge-aligned PWM waveforms (ARR=8) . . . . .641
Figure 192. Center-aligned PWM waveforms (ARR=8). . . . .643
Figure 193. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .644
Figure 194. Combined PWM mode on channels 1 and 3 . . . . .645
Figure 195. Clearing TIMx_OCxREF . . . . .646
Figure 196. Example of one-pulse mode. . . . .647
Figure 197. Retriggerable one-pulse mode . . . . .649
Figure 198. Example of counter operation in encoder interface mode . . . . .650
Figure 199. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .651
Figure 200. Control circuit in reset mode . . . . .652
Figure 201. Control circuit in gated mode . . . . .653
Figure 202. Control circuit in trigger mode . . . . .654
Figure 203. Control circuit in external clock mode 2 + trigger mode . . . . .655
Figure 204. Master/Slave timer example . . . . .656
Figure 205. Master/slave connection example with 1 channel only timers . . . . .656
Figure 206. Gating TIM2 with OC1REF of TIM3 . . . . .657
Figure 207. Gating TIM2 with Enable of TIM3 . . . . .658
Figure 208. Triggering TIM2 with update of TIM3 . . . . .659
Figure 209. Triggering TIM2 with Enable of TIM3 . . . . .659
Figure 210. Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . .660
Figure 211. Basic timer block diagram. . . . .694
Figure 212. Counter timing diagram with prescaler division change from 1 to 2 . . . . .696
Figure 213. Counter timing diagram with prescaler division change from 1 to 4 . . . . .696
Figure 214. Counter timing diagram, internal clock divided by 1 . . . . .697
Figure 215. Counter timing diagram, internal clock divided by 2 . . . . .698
Figure 216. Counter timing diagram, internal clock divided by 4 . . . . .698
Figure 217. Counter timing diagram, internal clock divided by N . . . . .699
Figure 218. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .699
Figure 219. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .700
Figure 220. Control circuit in normal mode, internal clock divided by 1 . . . . .701
Figure 221. General-purpose timer block diagram (TIM14). . . . .708
Figure 222. Counter timing diagram with prescaler division change from 1 to 2 . . . . .710
Figure 223. Counter timing diagram with prescaler division change from 1 to 4 . . . . .710
Figure 224. Counter timing diagram, internal clock divided by 1 . . . . .711
Figure 225. Counter timing diagram, internal clock divided by 2 . . . . .712
Figure 226. Counter timing diagram, internal clock divided by 4 . . . . .712
Figure 227. Counter timing diagram, internal clock divided by N . . . . .713
Figure 228. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .713
Figure 229. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .714
Figure 230. Control circuit in normal mode, internal clock divided by 1 . . . . .715
Figure 231. Capture/compare channel (example: channel 1 input stage). . . . .715
Figure 232. Capture/compare channel 1 main circuit . . . . .716
Figure 233. Output stage of capture/compare channel (channel 1). . . . .716
Figure 234. Output compare mode, toggle on OC1. . . . .719
Figure 235. Edge-aligned PWM waveforms (ARR=8). . . . .720
Figure 236. TIM15 block diagram . . . . .735
Figure 237. TIM16/TIM17 block diagram . . . . .736
Figure 238. Counter timing diagram with prescaler division change from 1 to 2 . . . . .738
Figure 239. Counter timing diagram with prescaler division change from 1 to 4 . . . . .738
Figure 240. Counter timing diagram, internal clock divided by 1 . . . . .740
Figure 241. Counter timing diagram, internal clock divided by 2 . . . . .740
Figure 242. Counter timing diagram, internal clock divided by 4 . . . . .741
Figure 243. Counter timing diagram, internal clock divided by N . . . . .741
Figure 244. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .742
Figure 245. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .742
Figure 246. Update rate examples depending on mode and TIMx_RCR register settings . . . . .744
Figure 247. Control circuit in normal mode, internal clock divided by 1 . . . . .745
Figure 248. TI2 external clock connection example. . . . .745
Figure 249. Control circuit in external clock mode 1 . . . . .746
Figure 250. Capture/compare channel (example: channel 1 input stage). . . . .747
Figure 251. Capture/compare channel 1 main circuit . . . . .747
Figure 252. Output stage of capture/compare channel (channel 1). . . . .748
Figure 253. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .748
Figure 254. PWM input mode timing . . . . .750
Figure 255. Output compare mode, toggle on OC1 . . . . .752
Figure 256. Edge-aligned PWM waveforms (ARR=8) . . . . .753
Figure 257. Combined PWM mode on channel 1 and 2 . . . . .754
Figure 258. Complementary output with dead-time insertion. . . . .755
Figure 259. Dead-time waveforms with delay greater than the negative pulse. . . . .755
Figure 260. Dead-time waveforms with delay greater than the positive pulse. . . . .756
Figure 261. Break circuitry overview . . . . .758
Figure 262. Output behavior in response to a break . . . . .760
Figure 263. Output redirection . . . . .762
Figure 264. 6-step generation, COM example (OSSR=1) . . . . .763
Figure 265. Example of one pulse mode . . . . .764
Figure 266. Retriggerable one pulse mode . . . . .766
Figure 267. Measuring time interval between edges on 2 signals . . . . .767
Figure 268. Control circuit in reset mode . . . . .768
Figure 269. Control circuit in gated mode . . . . .769
Figure 270. Control circuit in trigger mode . . . . .770
Figure 271. Low-power timer block diagram (LPTIM1 and LPTIM2 (1) ) . . . . .824
Figure 272. Glitch filter timing diagram . . . . .828
Figure 273. LPTIM output waveform, single counting mode configuration . . . . .829
Figure 274. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set). . . . .		830
Figure 275. LPTIM output waveform, Continuous counting mode configuration . . . . .830
Figure 276. Waveform generation . . . . .832
Figure 277. Encoder mode counting sequence . . . . .836
Figure 278. IRTIM internal hardware connections . . . . .849
Figure 279. Independent watchdog block diagram . . . . .850
Figure 280. Watchdog block diagram . . . . .860
Figure 281. Window watchdog timing diagram . . . . .861
Figure 282. RTC block diagram . . . . .866
Figure 283. TAMP block diagram . . . . .905
Figure 284. Block diagram . . . . .921
Figure 285. I 2 C-bus protocol . . . . .923
Figure 286. Setup and hold timings . . . . .925
Figure 287. I2C initialization flow . . . . .927
Figure 288. Data reception . . . . .928
Figure 289. Data transmission . . . . .929
Figure 290. Target initialization flow . . . . .932
Figure 291. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .934
Figure 292. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .935
Figure 293. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .936
Figure 294. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .937
Figure 295. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .938
Figure 296. Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . .		938
Figure 297. Controller clock generation . . . . .940
Figure 298. Controller initialization flow . . . . .942
Figure 299. 10-bit address read access with HEAD10R = 0 . . . . .942
Figure 300. 10-bit address read access with HEAD10R = 1 . . . . .943
Figure 301.Transfer sequence flow for I2C controller transmitter, \( N \leq 255 \) bytes . . . . .944
Figure 302.Transfer sequence flow for I2C controller transmitter, \( N > 255 \) bytes . . . . .945
Figure 303.Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . .		946
Figure 304.Transfer sequence flow for I2C controller receiver, \( N \leq 255 \) bytes . . . . .948
Figure 305.Transfer sequence flow for I2C controller receiver, \( N > 255 \) bytes . . . . .949
Figure 306.Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . .		950
Figure 307.Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .955
Figure 308.Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .958
Figure 309.Transfer bus diagram for SMBus target transmitter (SBC = 1) . . . . .959
Figure 310.Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .960
Figure 311.Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .961
Figure 312.Bus transfer diagrams for SMBus controller transmitter . . . . .962
Figure 313.Bus transfer diagrams for SMBus controller receiver . . . . .964
Figure 314.USART block diagram . . . . .988
Figure 315.Word length programming . . . . .991
Figure 316.Configurable stop bits . . . . .993
Figure 317.TC/TXE behavior when transmitting . . . . .996
Figure 318.Start bit detection when oversampling by 16 or 8 . . . . .997
Figure 319.usart_ker_ck clock divider block diagram . . . . .1000
Figure 320.Data sampling when oversampling by 16 . . . . .1001
Figure 321.Data sampling when oversampling by 8 . . . . .1002
Figure 322.Mute mode using Idle line detection . . . . .1009
Figure 323.Mute mode using address mark detection . . . . .1010
Figure 324.Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .1013
Figure 325.Break detection in LIN mode vs. Framing error detection. . . . .1014
Figure 326.USART example of synchronous master transmission. . . . .1015
Figure 327.USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		1015
Figure 328.USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		1016
Figure 329.USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		1017
Figure 330.ISO 7816-3 asynchronous protocol . . . . .1019
Figure 331.Parity error detection using the 1.5 stop bits . . . . .1021
Figure 332.IrDA SIR ENDEC block diagram. . . . .1025
Figure 333.IrDA data modulation (3/16) - normal mode . . . . .1025
Figure 334.Transmission using DMA . . . . .1027
Figure 335.Reception using DMA . . . . .1028
Figure 336.Hardware flow control between 2 USARTs . . . . .1028
Figure 337.RS232 RTS flow control . . . . .1029
Figure 338.RS232 CTS flow control . . . . .1030
Figure 339.Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .1033
Figure 340.Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		1033
Figure 341.LPUART block diagram . . . . .1074
Figure 342.LPUART word length programming . . . . .1077
Figure 343.Configurable stop bits . . . . .1079
Figure 344.TC/TXE behavior when transmitting . . . . .1081
Figure 345.lpuart_ker_ck clock divider block diagram . . . . .1084
Figure 346.Mute mode using Idle line detection . . . . .1088
Figure 347. Mute mode using address mark detection . . . . .1089
Figure 348. Transmission using DMA . . . . .1091
Figure 349. Reception using DMA . . . . .1092
Figure 350. Hardware flow control between 2 LPUARTs . . . . .1093
Figure 351. RS232 RTS flow control . . . . .1093
Figure 352. RS232 CTS flow control . . . . .1094
Figure 353. Wake-up event verified (wake-up event = address match,
FIFO disabled) . . . . .		1097
Figure 354. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		1097
Figure 355. SPI block diagram. . . . .1126
Figure 356. Full-duplex single master/ single slave application. . . . .1127
Figure 357. Half-duplex single master/ single slave application . . . . .1128
Figure 358. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		1129
Figure 359. Master and three independent slaves. . . . .1130
Figure 360. Multimaster application. . . . .1131
Figure 361. Hardware/software slave select management . . . . .1132
Figure 362. Data clock timing diagram . . . . .1133
Figure 363. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .1134
Figure 364. Packing data in FIFO for transmission and reception. . . . .1138
Figure 365. Master full-duplex communication . . . . .1141
Figure 366. Slave full-duplex communication . . . . .1142
Figure 367. Master full-duplex communication with CRC . . . . .1143
Figure 368. Master full-duplex communication in packed mode . . . . .1144
Figure 369. NSSP pulse generation in Motorola SPI master mode. . . . .1147
Figure 370. TI mode transfer . . . . .1148
Figure 371. I2S block diagram . . . . .1151
Figure 372. I 2 S Philips protocol waveforms (16/32-bit full accuracy). . . . .1153
Figure 373. I 2 S Philips standard waveforms (24-bit frame) . . . . .1153
Figure 374. Transmitting 0x8EAA33 . . . . .1154
Figure 375. Receiving 0x8EAA33 . . . . .1154
Figure 376. I 2 S Philips standard (16-bit extended to 32-bit packet frame) . . . . .1154
Figure 377. Example of 16-bit data frame extended to 32-bit channel frame . . . . .1154
Figure 378. MSB Justified 16-bit or 32-bit full-accuracy length . . . . .1155
Figure 379. MSB justified 24-bit frame length . . . . .1155
Figure 380. MSB justified 16-bit extended to 32-bit packet frame . . . . .1156
Figure 381. LSB justified 16-bit or 32-bit full-accuracy . . . . .1156
Figure 382. LSB justified 24-bit frame length. . . . .1156
Figure 383. Operations required to transmit 0x3478AE. . . . .1157
Figure 384. Operations required to receive 0x3478AE . . . . .1157
Figure 385. LSB justified 16-bit extended to 32-bit packet frame . . . . .1157
Figure 386. Example of 16-bit data frame extended to 32-bit channel frame . . . . .1158
Figure 387. PCM standard waveforms (16-bit) . . . . .1158
Figure 388. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .1159
Figure 389. Start sequence in master mode . . . . .1160
Figure 390. Audio sampling frequency definition . . . . .1161
Figure 391. I 2 S clock generator architecture . . . . .1161
Figure 392. CAN subsystem. . . . .1183
Figure 393. FDCAN block diagram . . . . .1185
Figure 394. Bit timing . . . . .1187
Figure 395. Transceiver delay measurement . . . . .1192
Figure 396. Pin control in bus monitoring mode . . . . .1193
Figure 397. Pin control in loop-back mode . . . . .1196
Figure 398. CAN error state diagram. . . . .1197
Figure 399. Message RAM configuration. . . . .1198
Figure 400. Standard message ID filter path . . . . .1201
Figure 401. Extended message ID filter path. . . . .1202
Figure 402. USB peripheral block diagram . . . . .1249
Figure 403. Packet buffer areas with examples of buffer description table locations . . . . .1256
Figure 404. UCPD block diagram . . . . .1298
Figure 405. Clock division and timing elements. . . . .1299
Figure 406. K-code transmission . . . . .1302
Figure 407. Transmit order for various sizes of data . . . . .1303
Figure 408. Packet format . . . . .1304
Figure 409. Line format of Hard Reset. . . . .1304
Figure 410. Line format of Cable Reset. . . . .1305
Figure 411. BIST test data frame. . . . .1306
Figure 412. BIST Carrier Mode 2 frame. . . . .1306
Figure 413. UCPD BMC transmitter architecture. . . . .1307
Figure 414. UCPD BMC receiver architecture . . . . .1308
Figure 415. HDMI-CEC block diagram . . . . .1336
Figure 416. Message structure . . . . .1337
Figure 417. Blocks . . . . .1337
Figure 418. Bit timings . . . . .1338
Figure 419. Signal free time. . . . .1338
Figure 420. Arbitration phase. . . . .1339
Figure 421. SFT of three nominal bit periods. . . . .1339
Figure 422. Error bit timing . . . . .1340
Figure 423. Error handling . . . . .1341
Figure 424. TXERR detection . . . . .1343
Figure 425. Block diagram of STM32G0x1 MCU and Cortex ® -M0+-level debug support . . . . .1353

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