50. Revision history

Document convention section

• – Updated Table 2: Product specific features .

System architecture section

• – Updated Section 2.1: System architecture replacing FMC by FSMC.
• – Updated Figure 2: Memory map replacing FMC by FSMC.

Memory organization section

• – Updated Table 3: Memory map and peripheral register boundary addresses
• – Updated Table 2.4: Embedded SRAM SRAM2 (mapped at address 0x2000 4000).
• – Updated Table 7: Flash module - 512/256/128 KB dual bank organization (64 bits read width) .
• – Updated Table 8: Flash module - 512/256/128 KB single bank organization (128 bits read width) .

Power control section

• – Updated Section 6.1: Power supplies .

Reset and clock control section

• – Updated Figure 17: Clock tree .

Updated FMC into FSMC in:

• – Section 7.4.10: AHB3 peripheral reset register (RCC_AHB3RSTR) .
• – Section 7.4.16: AHB3 peripheral clock enable register(RCC_AHB3ENR) .
• – Section 7.4.22: AHB3 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB3SMENR) .

System controller configuration section

• – Updated Section 10.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP) bits[2:0] description.

Peripherals interconnect matrix section

• – Updated Table 84: Interconnect 11 on-chip source FLTxSRC[1:0] = 01 column.

Nested vectored interrupt controller section

• – Updated Table 100: STM32G4 series vector table .

Flexible static memory controller (FSMC) section

• – Updated Section 19: Flexible static memory controller (FSMC) .

CORDIC co-processor (CORDIC) section

• – Updated Section 17: CORDIC coprocessor (CORDIC) .

Analog digital converter (ADC) section

• – Updated Section 21.4.33: Monitoring the internal voltage reference .
• – Updated Section : Sampling time control trigger mode .

• – Updated Section 22: Digital-to-analog converter (DAC) .

• – Updated Section 24.6.2: COMP register map .

• – Updated Section 27: AES hardware accelerator (AES) .

• – Updated Section 46: USB Type-C®/USB Power Delivery interface (UCPD) .

• – Updated Section 47.4.2: Flexible SWJ-DP pin assignment .
• – Updated Section 47.8.3: SW-DP state machine (reset, idle states, ID code) ID code by 0x2BA01477.
• – Updated Table 459: Flexible TRACE pin assignment .
• – Updated Table 447: JTAG debug port data registers .

• – Table 1: STM32G4 series memory density .
• – Table 2: Product specific features .
• – Section 2.4: Embedded SRAM .
• – Section 2.4.1: Parity check .
• – Table 4: CCM SRAM organization .
• – Section 2.5: Flash memory overview .
• – Section 4: Embedded flash memory (FLASH) for category 4 devices .
• – Table 92: DMAMUX instantiation .

• – Number of wait states according to CPU clock (HCLK) frequency tables for all categories.
• – Table 11: Option byte organization .
• – Table 21: Option byte organization .
• – Section 3.4.2: Option bytes programming 'activating dual bank mode (switching from DBANK=0 to DBANK=1)' paragraph.
• – Section 4.7.6: Flash control register (FLASH_CR) PNB[7:0] bits.
• – 'User and read protection option bytes' and Section 4.7.8: Flash option register (FLASH_OPTR) register description adding PB4_PUPEN bit.
• – Section 5.7.14: FLASH register map .

• – Table 38: Range 1 boost mode configuration removing the lower SYSCLK limits.
• – Section 6.4.2: Power control register 2 (PWR_CR2) PLS[2:0] bit description.

• – Figure 17: Clock tree .
• – Table 51: RCC register map and reset values .

• – Updated Table 62: STM32G4 series peripherals interconnect matrix .

Embedded Flash memory (FLASH) section:
Updated:
– Table 9: Number of wait states according to CPU clock (HCLK) frequency.
– Table 19: Number of wait states according to CPU clock (HCLK) frequency.
– Table 29: Number of wait states according to CPU clock (HCLK) frequency.
– Section 5.4.1: Option bytes description ‘Securable memory area option bytes’ paragraph.
– Section 5.7.13: Flash securable area register (FLASH_SEC1R).

Reset and clock control (RCC) section:
Updated:
– Section 7.2.4: PLL.
– Section 7.4.4: PLL configuration register (RCC_PLLCFGR) PLLN[6:0] and PLLM[3:0] description.

High-resolution timer (HRTIM) section:
– Updated Section 27.3.1: General description.

Memory map section:
Updated Table 3: Memory map and peripheral register boundary addresses USB SRAM to 1 Kbyte.
Updated Figure 2: Memory map.

Embedded Flash section:
Updated for category 3 devices:
– ‘User and read protection option bytes’ register bit 29,28 name at NRST_MODE.
– ‘Securable memory area Bank 1 option bytes’ register BOOT_LOCK description removing caution.
– Section 3.7.17: Flash securable area bank1 register (FLASH_SEC1R) BOOT_LOCK description.

Updated for category 4 devices:
– ‘User and read protection option bytes’ register bit 29,28 name at NRST_MODE.
– ‘Securable memory area option bytes’ register BOOT_LOCK description removing caution.
– Section 4.7.1: Flash access control register (FLASH_ACR) reset value.
– Section 4.7.13: Flash securable area register (FLASH_SEC1R) BOOT_LOCK description.
– Section 4.7.14: FLASH register map

Updated for category 2 devices:
– ‘User and read protection option bytes’ register bit 29,28 name at NRST_MODE.
– ‘Securable memory area option bytes’ register BOOT_LOCK description removing caution.
– Section 5.7.13: Flash securable area register (FLASH_SEC1R) BOOT_LOCK description.

Updated ‘rw’ to ‘r’ for all option bytes.

Replaced 'default' by 'production value' for RDP level 0 instead of RDP level 1 in:

• – Table 12: Flash memory read protection status.
• – Figure 4: Changing the read protection (RDP) level.
• – Table 22: Flash memory read protection status.
• – Figure 7: Changing the read protection (RDP) level.
• – Table 32: Flash memory read protection status.
• – Figure 10: Changing the read protection (RDP) level.

Power control (PWR) section:
Updated Section 6.4.22: Power control register (PWR_CR5) .

Reset and clock control (RCC) section:
Updated

• – Section 7.2.11: ADC clock.
• – Section 7.4.19: APB2 peripheral clock enable register (RCC_APB2ENR) SPI4EN bit description.

Peripherals interconnect matrix section:

• – Updated Table 75: Interconnect 2 .

DMA request multiplexer (DMAMUX) section:
Updated:

• – Section 13.3.2: DMAMUX mapping.
• – Section 13.6.1: DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR) .

Nested vectored interrupt controller (NVIC) section:
Updated Table 100: STM32G4 series vector table .

Analog-to-digital converters (ADC) section:
Updated Section 21.2: ADC main features .

High-resolution timer (HRTIM) section:
Updated:

• – Table 223: EExFLTR[3:0] codes depending on UDM bit setting.
• – Table 224: External events features.
• – Section 27.3.8: External events global conditioning.
• – Section 27.3.9: External event filtering in timing units.
• – Section 27.5.28: HRTIM timer x output 1 reset register (HRTIM_RSTx1R) (x = A to F).
• – Section 27.5.66: HRTIM ADC trigger 1 register (HRTIM_ADC1R).
• – Section 27.5.67: HRTIM ADC trigger 2 register (HRTIM_ADC2R).
• – Section 27.5.68: HRTIM ADC trigger 3 register (HRTIM_ADC3R) adding note.

General-purpose timers (TIM2/TIM3/TIM4/TIM5) section:
Updated Table 302: TIM2/TIM3/TIM4/TIM5 register map and reset values .

General purpose timers (TIM15/TIM16/TIM17):
Updated:

• – Section 31.8.19: TIMx option register 1 (TIMx_OR1)(x = 16 to 17) address offset to 0x68.
• – Section 31.8.22: TIM16/TIM17 register map.

Debug support (DBG) section:
– Updated Section 47.6.1: MCU device ID code REV_ID[15:0] bits description.

Embedded Flash section:
Updated:
– Section 3.5.3: Write protection (WRP) .
– Section 3.5.4: Securable memory area .
– Section 3.7.1: Flash access control register (FLASH_ACR) reset value
– Section 4.5.3: Write protection (WRP) .
– Section 4.5.4: Securable memory area .
– Section 5.4.1: Option bytes description securable memory area option bytes paragraph.
– Section 5.5.3: Write protection (WRP) .
– Section 5.5.4: Securable memory area .
– Section 5.7.1: Flash access control register (FLASH_ACR) reset value.

Filter math accelerator (FMAC) section:
Updated Section 18.4: FMAC registers

Analog digital converter section:
Updated:
– Table 181: ADC register map and reset values for each ADC (offset = 0x000 for master ADC, 0x100 for slave ADC) ADC_CFGR2 address.
– Section 21.7.6: ADC sample time register 1 (ADC_SMPR1) SMPPLUS bit.

Operational amplifier (OPAMP) section:
– Updated Table 204: Operational amplifier possible connection .

USB Type-C™ / USB Power Delivery interface (UCPD) section:
Updated:
– Section 46.8.3: UCPD control register (UCPD_CR) .
– Section 46.8.15: UCPD register map .
Removed UCPD configuration register 3 (UCPD_CFGR3).

Debug support (DBG) section:
Updated Section 47.4.2: Flexible SWJ-DP pin assignment removing note.

Updated Section 2.2.2: Memory map and register boundary addresses , Section 3.5.1: Read protection (RDP) , Section 5.7.6: Flash control register (FLASH_CR) , Section 7.4.1: Clock control register (RCC_CR) , Section 7.4.20: AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR) , Section 9.3: GPIO functional description , Section 8.7.1: CRS control register (CRS_CR) , Section 12.2: DMA main features , Section 21.4.10: Constraints when writing the ADC control bits , Section 21.7.16: ADC injected sequence register (ADC_JSQR) , Section 24.5: COMP interrupts , Section 28.2: Main features , Section 28.3.17: Fault protection , Section 30.5.10: TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)(x = 2 to 5) , Section 31.7.3: TIM15 slave mode control register (TIM15_SMCR) , Section 37.3.4: Clock and prescalers , note in sections 37.6.18 and 37.6.19 , Section 41.4.2: LPUART signals , Section 42.3: I2S main features , Section 42.7.1: I2S general description , Power-down (Sleep mode) , Rx handling , Standard message ID filtering , Extended message ID filtering , and Section 44.3.7: FIFO acknowledge handling .

Updated User and read protection option bytes in sections 3 , 4 , and 5 .

Reorganized description of registers in Section 28: High-resolution timer (HRTIM) and in Section 43: Serial audio interface (SAI) .

Updated Table 11: Option byte organization , Table 31: Option byte organization , Table 51: RCC register map and reset values , Table 55: Effect of low-power modes on CRS , Table 100: STM32G4 series vector table , tables 166 to 169 , Table 198: VREFBUF register map and reset values , tables in Section 28.3.2: HRTIM pins and internal signals , Table 260: HRTIM register map and reset values – common functions , Table 402: CAN subsystem I/O signals , Table 424: Bulk double-buffering memory buffers usage , and Table 441: Type-C sequence (source: 3A); cable/sink connected (Rd on CC1; Ra on CC2) .

Added footnote to Table 5: Boot modes .

Added Table 371: USART/UART input/output pins , Table 372: USART internal input/output signals , Table 381: LPUART input/output pins , and Table 382: LPUART internal input/output signals .

Updated figures in Section 20: Quad-SPI interface (QUADSPI) , Figure 83: ADC clock scheme , figures 99 to 104 , Figure 156: Dual-channel DAC block diagram , Figure 171: Standalone mode: external gain setting mode , Figure 244: Latency to external events (counter reset and output set) , Figure 245: Latency to external events (output reset on external event) , Figure 385: General-purpose timer block diagram , Figure 591: LPUART block diagram , Figure 543: Transfer bus diagrams for I2C target transmitter (mandatory events only) , Figure 546: Transfer bus diagrams for I2C target receiver (mandatory events only) , Figure 553: Transfer bus diagrams for I2C controller transmitter (mandatory events only) , Figure 556: Transfer bus diagrams for I2C controller receiver (mandatory events only) , Figure 529: Independent watchdog block diagram , Figure 530: Watchdog block diagram , and Figure 663: CAN subsystem..

Added Section 49: Important security notice .

Minor text edits across the whole document.

Rearranged sequence of sections.

Updated Introduction , Section 3.3.1: Flash memory organization , Section 3.4.1: Option bytes description , Modifying user options , Flash securable area bank1 register (FLASH_SEC1R) , Section 3.5.4: Securable memory area , Section 3.7.17: Flash securable area bank1 register (FLASH_SEC1R) , Section 4.4.1: Option bytes description , Modifying user options , Section 4.5.6: Forcing boot from flash memory , Section 4.7.12: Flash WRP area B address register (FLASH_WRP1BR) , Section 4.7.13: Flash securable area register (FLASH_SEC1R) , Section 5.4.1: Option bytes description , Section 5.5.6: Forcing boot from flash memory , Section 5.7.12: Flash WRP area B address register (FLASH_WRP1BR) , Section 5.7.13: Flash securable area register (FLASH_SEC1R) , Section 7.1.2: System reset , Section 7.2.7: System clock (SYSCLK) selection , Section 9.3.2: I/O pin alternate function multiplexer and mapping , Section 15.5.6: Pending register 1 (EXTI_PR1) , Section 15.5.12: Pending register 2 (EXTI_PR2) , Auto-injection mode , Analog watchdog filter for watchdog 1 , ADC configuration register (ADC_CFGR) , Section 22.4.11: DAC sawtooth wave generation , Section 22.4.13: DAC channel buffer calibration , Section 22.7.23: DAC sawtooth mode register (DAC_STMODR) , Section 40.5.7: USART baud rate generation , and Section 48.3: Package data register .

Replaced SQRx and JSQRx by ADC_SQRy and ADC_JSQR registers, when referring to registers, JSQRi and SQRi registers by JSQi and SQi bits, when referring to bits in Section 21: Analog-to-digital converters (ADC) .

Updated Table 1: STM32G4 series memory density , Table 28: Flash module - 32/64/128 Kbytes organization (64-bit read width) , Table 99: DMAMUX register map and reset values for category 3 and 4 devices , and Table 265: Interconnect to the tim_ti3 input multiplexer .

Added footnote to Section 13.6.1: DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR) and Table 98: DMAMUX register map and reset values for category 2 devices .

Updated Figure 17: Clock tree and Figure 379: Measuring time interval between edges on three signals .

Minor text edits across the whole document.