32. Basic timers (TIM6/TIM7)

32.1 TIM6/TIM7 introduction

The basic timers TIM6/TIM7 consist in a 16-bit autoreload counter driven by a programmable prescaler.

They can be used as generic timers for time-base generation.

The basic timer can also be used for triggering the digital-to-analog converter. This is done with the trigger output of the timer.

The timers are completely independent, and do not share any resources.

32.2 TIM6/TIM7 main features

Basic timer (TIM6/TIM7) features include:

• 16-bit autoreload upcounter.
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535.
• Synchronization circuit to trigger the DAC.
• Interrupt/DMA generation on the update event: counter overflow.

32.3 TIM6/TIM7 functional description

32.3.1 TIM6/TIM7 block diagram

Figure 507. Basic timer block diagram

Notes:
Reg Preload registers transferred to active registers on U event according to control bit
Event
Interrupt & DMA

MSv62381V1

Figure 507: Basic timer block diagram. The diagram shows the internal architecture of the TIM6/TIM7 peripheral. It includes a 32-bit APB bus interface connecting to an IRQ interface (tim_upd_it) and a DMA interface (tim_upd_dma). The main clock input is tim_pclk. A kernel clock tim_ker_ck feeds into a Trigger controller which contains a Control block and outputs tim_trgo and an Enable Count signal. The tim_ker_ck also feeds into a PSC prescaler (controlled by tim_psc_ck) which outputs tim_cnt_ck to a CNT counter. An Auto-reload register (with UEV and Update signals) provides 'Stop, clear or up' control to the CNT counter. The diagram also includes a legend for 'Reg' (Preload registers), 'Event' (lightning bolt symbol), and 'Interrupt & DMA' (curved arrow symbol). Event symbol Interrupt & DMA symbol

32.3.2 TIM6/TIM7 internal signals

The table in this section summarizes the TIM inputs and outputs.

Table 320. TIM internal input/output signals

Internal signal name	Signal type	Description
tim_pclk	Input	Timer APB clock
tim_ker_ck	Input	Timer kernel clock. This clock must be synchronous with tim_pclk (derived from the same source). The clock ratio tim_ker_ck/tim_pclk must be an integer: 1, 2, 3, ..., 16 (maximum value)
tim_trgo	Output	Internal trigger output. This trigger can trigger other on-chip peripherals (DAC).
tim_upd_it	Output	Timer update event interrupt
tim_upd_dma	Output	Timer update dma request

32.3.3 TIM6/TIM7 clocks

The timer bus interface is clocked by the tim_pclk APB clock.

The counter clock tim_ker_ck is connected to the tim_pclk input.

The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock tim_ker_ck.

Figure 508 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Figure 508. Control circuit in normal mode, internal clock divided by 1

Timing diagram showing the control circuit and upcounter behavior. The diagram includes five signal lines: tim_ker_ck (internal clock), CEN (counter enable), UG (update generation), counter initialization (internal), and tim_cnt_ck, tim_psc_ck (counter/prescaler clock). The Counter register shows values 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. The diagram illustrates that the counter starts at 31, increments to 36, and then overflows to 00 when CEN is high and UG is asserted. The counter clock is derived from the internal clock divided by 1.

The timing diagram shows the following signals and their behavior over time:

tim_ker_ck : A continuous square wave representing the internal clock.
CEN : Counter Enable. It is initially low, then goes high, and then low again. The counter only increments when CEN is high.
UG : Update Generation. It is initially low. When CEN is high and the counter reaches 36, UG goes high briefly and then returns to low. This event triggers the counter to reset to 00.
counter initialization (internal) : A signal that goes high when UG is asserted and then returns to low.
tim_cnt_ck, tim_psc_ck : The clock for the counter and prescaler. It is a square wave that is only active (high) when CEN is high.
Counter register : Shows the sequence of values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. The counter increments by 1 at each rising edge of tim_cnt_ck while CEN is high. It overflows from 36 to 00 when UG is asserted.

MSV62317V2

Timing diagram showing the control circuit and upcounter behavior. The diagram includes five signal lines: tim_ker_ck (internal clock), CEN (counter enable), UG (update generation), counter initialization (internal), and tim_cnt_ck, tim_psc_ck (counter/prescaler clock). The Counter register shows values 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. The diagram illustrates that the counter starts at 31, increments to 36, and then overflows to 00 when CEN is high and UG is asserted. The counter clock is derived from the internal clock divided by 1.

32.3.4 Time-base unit

The main block of the programmable timer is a 16-bit upcounter with its related autoreload register. The counter clock can be divided by a prescaler.

The counter, the autoreload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter register (TIMx_CNT)
• Prescaler register (TIMx_PSC)
• Auto-Reload register (TIMx_ARR).

The autoreload register is preloaded. The preload register is accessed each time an attempt is made to write or read the autoreload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the autoreload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

The counter is clocked by the prescaler output tim_cnt_ck, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1register is set.

Note that the actual counter enable signal tim_cnt_enis set one clock cycle after CEN bit set.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSCregister). It can be changed on the fly as the TIMx_PSCcontrol register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 509 and Figure 510 give some examples of the counter behavior when the prescaler ratio is changed on the fly.

Figure 509. Counter timing diagram with prescaler division change from 1 to 2

Timing diagram showing the effect of changing the prescaler division from 1 to 2 on a counter.

The timing diagram illustrates the relationship between several signals over time:

tim_psc_ck : A high-frequency square wave clock signal.
CEN : Counter Enable bit. It is initially low and goes high at the first rising edge of tim_psc_ck.
tim_cnt_ck : The clock signal for the counter. It is initially a divided version of tim_psc_ck(division by 1). After the prescaler change, its frequency halves (division by 2).
Counter register : Shows the counter values. It increments from F7to FC(hexadecimal). Upon reaching FC, an Update Event (UEV) occurs, and the counter resets to 00. It then continues to increment: 00, 01, 02, 03.
Update event (UEV) : A pulse that occurs when the counter reaches its maximum value ( FC).
Prescaler control register : Initially set to 0. A note "Write a new value in TIMx_PSC" points to a transition where it is changed to 1. This change takes effect at the next Update Event (UEV).
Prescaler buffer : A buffer register that latches the new prescaler value ( 1) at the UEV.
Prescaler counter : A counter that divides the tim_psc_ckfrequency. It counts from 0to 1(binary) when the division is 2. The diagram shows the sequence: 0, 1, 0, 1, 0, 1, 0, 1.

The diagram shows that after the prescaler control register is updated to 1at the first UEV, the prescaler buffer updates at the second UEV, causing the tim_cnt_ckfrequency to halve. The counter register continues to increment based on the new, slower clock frequency.

MSV50998V1

Timing diagram showing the effect of changing the prescaler division from 1 to 2 on a counter.

Figure 510. Counter timing diagram with prescaler division change from 1 to 4

The timing diagram illustrates the behavior of a basic timer (TIM6/TIM7) when the prescaler division is changed from 1 to 4. The signals shown are:

tim_psc_ck : Prescaler clock signal, a periodic square wave.
CEN : Counter Enable signal, which is high to enable counting.
tim_cnt_ck : Counter clock signal, which is derived from the prescaler output.
Counter register : Shows the counter values. It counts from F7 to FC, then overflows to 00. After the prescaler division change, it counts from 01 to 03, then overflows to 00.
Update event (UEV) : Generated when the counter overflows or when the UG bit in the TIMx_EGR register is set.
Prescaler control register : Shows the prescaler division value. It is initially 0 (division by 1) and is changed to 3 (division by 4) by writing a new value in TIMx_PSC.
Prescaler buffer : A shadow register that holds the new prescaler division value (3) until the next update event.
Prescaler counter : A counter that divides the tim_psc_ck frequency by the value in the prescaler buffer. It counts from 0 to 3 (division by 4) before overflowing to 0.

The diagram shows that when the prescaler control register is changed from 0 to 3, the prescaler buffer is updated to 3. The prescaler counter then counts from 0 to 3 (division by 4) before overflowing to 0. This overflow generates an update event (UEV), which in turn causes the counter register to overflow from FC to 00. The counter then resumes counting from 01.

MSv50999V1

Figure 510. Counter timing diagram with prescaler division change from 1 to 4. The diagram shows the relationship between tim_psc_ck, CEN, tim_cnt_ck, Counter register, Update event (UEV), Prescaler control register, Prescaler buffer, and Prescaler counter over time. The counter counts from F7 to FC, then overflows to 00. The prescaler control register is changed from 0 to 3. The prescaler buffer and prescaler counter are updated accordingly. The counter then counts from 01 to 03, then overflows to 00.

32.3.5 Counting mode

The counter counts from 0 to the autoreload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent).

When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register).
• The autoreload shadow register is updated with the preload value (TIMx_ARR).

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36.

Figure 511. Counter timing diagram, internal clock divided by 1

This timing diagram illustrates the operation of a basic timer with the internal clock divided by 1. The top signal, tim_psc_ck , is a continuous square wave. The CEN (Counter Enable) signal is shown as a low-level active signal that goes high to enable counting. The tim_cnt_ck signal is a square wave with a frequency twice that of tim_psc_ck . The Counter register displays a sequence of values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. Vertical dashed lines indicate the rising edges of tim_cnt_ck that correspond to the counter increments. When the counter reaches 36, a Counter overflow pulse occurs. Simultaneously, an Update event (UEV) is generated, and the Update interrupt flag (UIF) is set. The diagram is identified by the code MSv50997V1.

Timing diagram for internal clock divided by 1. It shows the relationship between tim_psc_ck, CEN, tim_cnt_ck, Counter register values (31 to 07), Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

Figure 512. Counter timing diagram, internal clock divided by 2

This timing diagram illustrates the operation of a basic timer with the internal clock divided by 2. The tim_psc_ck signal is a continuous square wave. The CEN signal is active-low and goes high to enable counting. The tim_cnt_ck signal is a square wave with a frequency half that of tim_psc_ck . The Counter register displays a sequence of values: 0034, 0035, 0036, 0000, 0001, 0002, 0003. Vertical dashed lines indicate the rising edges of tim_cnt_ck that correspond to the counter increments. When the counter reaches 0036, a Counter overflow pulse occurs. Simultaneously, an Update event (UEV) is generated, and the Update interrupt flag (UIF) is set. The diagram is identified by the code MSv62300V1.

Timing diagram for internal clock divided by 2. It shows the relationship between tim_psc_ck, CEN, tim_cnt_ck, Counter register values (0034 to 0003), Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

Figure 513. Counter timing diagram, internal clock divided by 4

Timing diagram for internal clock divided by 4. It shows the relationship between tim_psc_ck, CEN, tim_cnt_ck, Counter register values (0035, 0036, 0000, 0001), Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

This timing diagram illustrates the operation of a basic timer when the internal clock is divided by 4. The top signal, tim_psc_ck , is a high-frequency square wave. The CEN (Counter Enable) signal is shown as a horizontal line that goes high at the start. The tim_cnt_ck (counter clock) is a lower-frequency square wave, derived from the prescaler clock. The Counter register shows a sequence of values: 0035, 0036, 0000, and 0001. The transition from 0036 to 0000 represents a counter overflow. The Counter overflow signal is a pulse that goes high when the counter reaches 0000. The Update event (UEV) is a pulse that goes high at the same time as the counter overflow. The Update interrupt flag (UIF) is a signal that goes high at the same time as the counter overflow and remains high until it is cleared.

MSv62301V1

Timing diagram for internal clock divided by 4. It shows the relationship between tim_psc_ck, CEN, tim_cnt_ck, Counter register values (0035, 0036, 0000, 0001), Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

Figure 514. Counter timing diagram, internal clock divided by N

Timing diagram for internal clock divided by N. It shows the relationship between tim_psc_ck, tim_cnt_ck, Counter register values (1F, 20, 00), Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

This timing diagram illustrates the operation of a basic timer when the internal clock is divided by N. The top signal, tim_psc_ck , is a high-frequency square wave. The tim_cnt_ck (counter clock) is a lower-frequency square wave, derived from the prescaler clock. The Counter register shows a sequence of values: 1F, 20, and 00. The transition from 20 to 00 represents a counter overflow. The Counter overflow signal is a pulse that goes high when the counter reaches 00. The Update event (UEV) is a pulse that goes high at the same time as the counter overflow. The Update interrupt flag (UIF) is a signal that goes high at the same time as the counter overflow and remains high until it is cleared.

MSv62302V1

Timing diagram for internal clock divided by N. It shows the relationship between tim_psc_ck, tim_cnt_ck, Counter register values (1F, 20, 00), Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

Figure 515. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded)

Timing diagram for a basic timer (TIM6/TIM7) showing the relationship between tim_psc_ck, CEN, tim_cnt_ck, Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), and Auto-reload preload register. The diagram illustrates the counter sequence from 31 to 07, the overflow at 36, and the update event triggered by a write to TIMx_ARR.

The timing diagram illustrates the operation of a basic timer (TIM6/TIM7) when ARPE = 0 and the auto-reload register (TIMx_ARR) is not preloaded. The signals shown are:

tim_psc_ck : Prescaler clock signal, shown as a square wave.
CEN : Counter Enable signal, shown as a high-level signal.
tim_cnt_ck : Counter clock signal, derived from tim_psc_ck.
Counter register : Shows the counter value sequence: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07.
Counter overflow : A pulse generated when the counter reaches 36.
Update event (UEV) : A pulse generated when the counter overflows.
Update interrupt flag (UIF) : A pulse generated when the counter overflows.
Auto-reload preload register : Shows the initial value FF, which is updated to 36 when a new value is written to TIMx_ARR.

An annotation "Write a new value in TIMx_ARR" points to the transition in the Auto-reload preload register from FF to 36.

MSV62303V1

Timing diagram for a basic timer (TIM6/TIM7) showing the relationship between tim_psc_ck, CEN, tim_cnt_ck, Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), and Auto-reload preload register. The diagram illustrates the counter sequence from 31 to 07, the overflow at 36, and the update event triggered by a write to TIMx_ARR.

Figure 516. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR preloaded)

Timing diagram showing the relationship between tim_psc_ck, CEN, tim_cnt_ck, Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), Auto-reload preload register, and Auto-reload shadow register. It illustrates the update event occurring when the counter reaches the preloaded value in the Auto-reload shadow register.

The timing diagram illustrates the operation of a basic timer (TIM6/TIM7) in update event mode with ARPE = 1. The signals shown are:

tim_psc_ck : Prescaler clock signal, a periodic square wave.
CEN : Counter Enable signal, which goes high to enable counting.
tim_cnt_ck : Counter clock signal, derived from tim_psc_ck when CEN is high.
Counter register : Shows the counter values F0, F1, F2, F3, F4, F5, 00, 01, 02, 03, 04, 05, 06, 07. The counter increments by 1 at each tim_cnt_ck rising edge.
Counter overflow : A pulse generated when the counter reaches 00 after F5.
Update event (UEV) : A pulse generated when the counter reaches the value in the Auto-reload shadow register (F5).
Update interrupt flag (UIF) : A flag that is set by the UEV pulse.
Auto-reload preload register : Contains the value F5 initially, then is updated to 36. An arrow indicates a write to TIMx_ARR.
Auto-reload shadow register : Contains the value F5 initially, then is updated to 36 at the next UEV.

The diagram shows that the update event (UEV) occurs when the counter reaches the value in the Auto-reload shadow register (F5). The Auto-reload preload register is updated with a new value (36) via a write to TIMx_ARR. The UEV pulse is generated when the counter reaches the value in the Auto-reload shadow register (36).

MSv62304V1

Timing diagram showing the relationship between tim_psc_ck, CEN, tim_cnt_ck, Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), Auto-reload preload register, and Auto-reload shadow register. It illustrates the update event occurring when the counter reaches the preloaded value in the Auto-reload shadow register.

Dithering mode

The time base effective resolution can be increased by enabling the dithering mode, using the DITHEN bit in the TIMx_CR1 register. This affects the way the TIMx_ARR is behaving, and is useful for adjusting the average counter period when the timer is used as a trigger (typically for a DAC).

The operating principle is to have the actual ARR value slightly changed (adding or not one timer clock period) over 16 consecutive counting periods, with predefined patterns. This allows a 16-fold resolution increase, considering the average counting period.

Figure 517 presents the dithering principle applied to four consecutive counting periods.

Figure 517. Dithering principle

The figure illustrates the dithering principle for a timer over four consecutive counting periods. The top row shows a constant period of 12. The subsequent rows show how varying the period between 12 and 13 can achieve different average periods:

Average period: 12, 12, 12, 12 (T = 12)
Average period: 13, 12, 12, 12 (T = 12 + 1/4)
Average period: 13, 12, 13, 12 (T = 12 + 1/2)
Average period: 13, 13, 13, 12 (T = 12 + 3/4)
Average period: 13, 13, 13, 13 (T = 13)

MSv47466V1

Figure 517. Dithering principle. A diagram showing five horizontal timelines representing different average periods (T) over four consecutive counting periods. The top timeline shows a constant period of 12. The subsequent timelines show dithering between 12 and 13 to achieve average periods of T = 12 + 1/4, T = 12 + 1/2, T = 12 + 3/4, and T = 13. Vertical dashed lines mark the boundaries of the four counting periods.

When the dithering mode is enabled, the register coding is changed as follows (see Figure 518 for example):

• The four LSBs are coding for the enhanced resolution part (fractional part).
• The MSBs are left-shifted to the bits 19:4 and are coding for the base value.

Note: The ARR values are updated automatically if the DITHEN bit is set/reset (for instance, if ARR= 0x05 with DITHEN = 0, it is updated to ARR = 0x50 with DITHEN = 1). The following sequence must be followed when resetting the DITHEN bit:

1. CEN and ARPE bits must be reset
2. The ARR[3:0] bits must be reset
3. The DITHEN bit must be reset
4. The CEN bit can be set (eventually with ARPE = 1).

Figure 518. Data format and register coding in dithering mode

$Diagram showing the data format and register coding in dithering mode. It includes two register diagrams: one for the general format and one for an example. The general format shows a 20-bit register with bits b19 to b0, split into a 16-bit integer part (MSB) and a 4-bit fractional part (LSB). The example shows a value of 326, which is 20 in the integer part and 6 in the fractional part. Below the diagrams, text explains that the base compare value is 20 during 16 periods, and additional 6 cycles are spread over the 16 periods. The diagram is labeled MSV45753V2.$

b19 b0

MSB: 16-bits, integer part

LSB: 4-bits fractional part

Example

b19 b0

326

20 6

↓ ↓

Base compare value is 20 during 16 periods Additional 6 cycles are spread over the 16 periods

MSV45753V2

Diagram showing the data format and register coding in dithering mode. It includes two register diagrams: one for the general format and one for an example. The general format shows a 20-bit register with bits b19 to b0, split into a 16-bit integer part (MSB) and a 4-bit fractional part (LSB). The example shows a value of 326, which is 20 in the integer part and 6 in the fractional part. Below the diagrams, text explains that the base compare value is 20 during 16 periods, and additional 6 cycles are spread over the 16 periods. The diagram is labeled MSV45753V2.

The minimum frequency is given by the following formula:

\text{Resolution} = \frac{F_{\text{Tim}}}{F_{\text{pwm}}} \Rightarrow F_{\text{pwmMin}} = \frac{F_{\text{Tim}}}{\text{MaxResolution}}

\text{Dithering mode disabled: } F_{\text{pwmMin}} = \frac{F_{\text{Tim}}}{65536}

\text{Dithering mode enabled: } F_{\text{pwmMin}} = \frac{F_{\text{Tim}}}{65535 + \frac{15}{16}}

Note: The maximum TIMx_ARR value is limited to 0xFFFEF in dithering mode (corresponds to 65534 for the integer part and 15 for the dithered part).

As shown on Figure 519 , the dithering mode is used to increase the PWM resolution whatever the PWM frequency.

Figure 519. $F_{Cnt}$ resolution vs frequency

Figure 519: F_Cnt resolution vs frequency graph. The y-axis is labeled 'Resolution' with marks for 16-bit and 20-bit. The x-axis is labeled 'F_Cnt' with a starting point 'F_Cnt min'. Two curves are shown: the upper curve is labeled 'Dithering' and starts at the 20-bit level; the lower curve is labeled 'No Dithering' and starts at the 16-bit level. Both curves decay as frequency increases.

The period changes are spread over 16 consecutive periods, as described in Figure 520 .

Figure 520. PWM dithering pattern

Figure 520: PWM dithering pattern diagram. It shows three horizontal rows. Top row: 'Counter period' with sawtooth waves numbered 1 to 16. Middle row: 'ARR value' showing a constant value of 643. Bottom row: 'Auto-Reload value' showing a sequence of values: 41, 40, 40, 40, 41, 40, 40, 40, 41, 40, 40, 40, 40, 40, 40, 40.

The autoreload and compare values increments are spread following the specific patterns described in Table 321 . The dithering sequence is done to have increments distributed as evenly as possible and minimize the overall ripple.

Table 321. TIMx_ARR register change dithering pattern

-	PWM period
-	LSB value	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16
0000	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0001	+1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0010	+1	-	-	-	-	-	-	-	+1	-	-	-	-	-	-	-
0011	+1	-	-	-	+1	-	-	-	+1	-	-	-	-	-	-	-
0100	+1	-	-	-	+1	-	-	-	+1	-	-	-	+1	-	-	-
0101	+1	-	+1	-	+1	-	-	-	+1	-	-	-	+1	-	-	-
0110	+1	-	+1	-	+1	-	-	-	+1	-	+1	-	+1	-	-	-

Table 321. TIMx_ARR register change dithering pattern (continued)

-	PWM period
-	LSB value	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16
0111		+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	-	-
1000		+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-
1001		+1	+1	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-	+1	-
1010		+1	+1	+1	-	+1	-	+1	-	+1	+1	+1	-	+1	-	+1	-
1011		+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-	+1	-	+1	-
1100		+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-
1101		+1	+1	+1	+1	+1	+1	+1	-	+1	+1	+1	-	+1	+1	+1	-
1110		+1	+1	+1	+1	+1	+1	+1	-	+1	+1	+1	+1	+1	+1	+1	-
1111		+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	+1	-

32.3.6 UIF bit remapping

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the update interrupt flag UIF into the timer counter register's bit 31 (TIMxCNT[31]). This is used to atomically read both the counter value and a potential roll-over condition signaled by the UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions caused for instance by a processing shared between a background task (counter reading) and an interrupt (update interrupt).

There is no latency between the assertions of the UIF and UIFCPY flags.

32.3.7 ADC triggers

The timer can generate an ADC triggering event with various internal signals, such as reset, enable or compare events.

Note: The clock of the slave peripherals (such as timer, ADC) receiving the tim_trgo signal must be enabled prior to receiving events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.

32.3.8 TIM6/TIM7 DMA requests

The TIM6/TIM7 can generate a single DMA request, as shown in Table 322 .

Table 322. DMA request

DMA request signal	DMA acronym	DMA request	Enable control bit
tim_upd_dma	TIM_UP	Update	UDE

32.3.9 Debug mode

When the microcontroller enters debug mode (Cortex®-M4 with FPU core halted), the TIMx counter can either continue to work normally or be stopped.

The behavior in debug mode can be programmed with a dedicated configuration bit per timer in the Debug support (DBG) module.

For more details, refer to section Debug support (DBG).

32.3.10 TIM6/TIM7 low-power modes

Table 323. Effect of low-power modes on TIM6/TIM7

Mode	Description
Sleep	No effect, peripheral is active. The interrupts can cause the device to exit from Sleep mode.
Stop	The timer operation is stopped and the register content is kept. No interrupt can be generated.
Standby	The timer is powered-down and must be reinitialized after exiting the Standby mode.

32.3.11 TIM6/TIM7 interrupts

The TIM6/TIM7 can generate a single interrupt, as shown in Table 324 .

Table 324. Interrupt request

Interrupt acronym	Interrupt event	Event flag	Enable control bit	Interrupt clear method	Exit from Sleep mode	Exit from Stop and Standby mode
TIM6 TIM7	Update	UIF	UIE	write 0 in UIF	Yes	No

32.4 TIM6/TIM7 registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

32.4.1 TIMx control register 1 (TIMx_CR1)(x = 6 to 7)

Address offset: 0x00

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	DITH EN	UIFRE MAP	Res.	Res.	Res.	ARPE	Res.	Res.	Res.	OPM	URS	UDIS	CEN
			rw	rw				rw				rw	rw	rw	rw

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 DITHEN : Dithering enable

0: Dithering disabled

1: Dithering enabled

Note: The DITHEN bit can only be modified when CEN bit is reset.

Bit 11 UIFREMAP : UIF status bit remapping

0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.

1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

Bits 10:8 Reserved, must be kept at reset value.

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered.

1: TIMx_ARR register is buffered.

Bits 6:4 Reserved, must be kept at reset value.

Bit 3 OPM : One-pulse mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the CEN bit).

Bit 2 URS: Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generates an update interrupt or DMA request if enabled.

These events can be:

- Counter overflow/underflow
- Setting the UG bit
- Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS: Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

- Counter overflow/underflow
- Setting the UG bit
- Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN: Counter enable

0: Counter disabled

1: Counter enabled

CEN is cleared automatically in one-pulse mode, when an update event occurs.

32.4.2 TIMx control register 2 (TIMx_CR2)(x = 6 to 7)

Address offset: 0x04

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MMS[2:0]			Res.	Res.	Res.	Res.
									rw	rw	rw

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 MMS[2:0] : Master mode selection

These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:

000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo).

001: Enable - the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated when the CEN control bit is written.

010: Update - The update event is selected as a trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer.

Note: The clock of the slave timer or the peripheral receiving the tim_trgo must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Bits 3:0 Reserved, must be kept at reset value.

32.4.3 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7)

Address offset: 0x0C

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	UDE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIE
							rw								rw

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 UDE : Update DMA request enable

0: Update DMA request disabled.

1: Update DMA request enabled.

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 UIE : Update interrupt enable

0: Update interrupt disabled.

1: Update interrupt enabled.

32.4.4 TIM x status register (TIM x _SR)( x = 6 to 7)

Address offset: 0x10

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIF
															rc_w0

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UIF : Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

–On counter overflow if UDIS = 0 in the TIM x _CR1 register.
–When CNT is reinitialized by software using the UG bit in the TIM x _EGR register, if URS = 0 and UDIS = 0 in the TIM x _CR1 register.

32.4.5 TIM x event generation register (TIM x _EGR)( x = 6 to 7)

Address offset: 0x14

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UG
															w

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UG : Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action.

1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).

32.4.6 TIM x counter (TIM x _CNT)( x = 6 to 7)

Address offset: 0x24

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIF CPY	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 UIFCPY : UIF copy

This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0.

Bits 30:16 Reserved, must be kept at reset value.

Bits 15:0 CNT[15:0] : Counter value

Non-dithering mode (DITHEN = 0)

The register holds the counter value.

Dithering mode (DITHEN = 1)

The register only holds the non-dithered part in CNT[15:0]. The fractional part is not available.

32.4.7 TIMx prescaler (TIMx_PSC)(x = 6 to 7)

Address offset: 0x28

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency $f_{tim\_cnt\_ck}$ is equal to $f_{tim\_psc\_ck} / (PSC[15:0] + 1)$ .

PSC contains the value to be loaded into the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register.

32.4.8 TIMx autoreload register (TIMx_ARR)(x = 6 to 7)

Address offset: 0x2C

Reset value: 0x0000 FFFF

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ARR[19:16]
												rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 ARR[19:0] : Auto-reload value

ARR is the value to be loaded into the actual auto-reload register.

Refer to Section 32.3.4: Time-base unit for more details about ARR update and behavior.

The counter is blocked while the auto-reload value is null.

Non-dithering mode (DITHEN = 0)

The register holds the auto-reload value in ARR[15:0]. The ARR[19:16] bits are reserved.

Dithering mode (DITHEN = 1)

The register holds the integer part in ARR[19:4]. The ARR[3:0] bitfield contains the dithered part.

32.4.9 TIMx register map

TIMx registers are mapped as 16-bit addressable registers as described in the table below:

Table 325. TIMx register map and reset values

Offset	Register name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	TIMx_CR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DITHEN	UIFREMA	Res.	Res.	Res.	ARPE	Res.	Res.	Res.	OPM	URS	UDIS	CEN
0x00	Reset value																				0	0				0				0	0	0	0
0x04	TIMx_CR2	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MMS [2:0]		Res.	Res.	Res.	Res.	Res.
0x04	Reset value																										0	0	0
0x08	Reserved
0x0C	TIMx_DIER	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UDE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIE
0x0C	Reset value																								0								0
0x10	TIMx_SR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIF
0x10	Reset value																																0
0x14	TIMx_EGR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UG
0x14	Reset value																																0
0x18-0x20	Reserved
0x24	TIMx_CNT	UIFCPY or Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CNT[15:0]
0x24	Reset value	0																			0	0	0	0	0	0	0	0	0	0	0	0	0
0x28	TIMx_PSC	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PSC[15:0]
0x28	Reset value																				0	0	0	0	0	0	0	0	0	0	0	0	0
0x2C	TIMx_ARR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ARR[19:0]
0x2C	Reset value																				0	0	0	0	1	1	1	1	1	1	1	1	1

Refer to Section 2.2 for the register boundary addresses.