11. Peripherals interconnect matrix

11.1 Introduction

Several peripherals have direct connections between them.

This allows autonomous communication and or synchronization between peripherals, saving CPU resources thus power supply consumption.

In addition, these hardware connections remove software latency and allow design of predictable system.

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and sleep, Stop 0 and Stop 1 modes.

11.2 Connection summary

Table 62. STM32G4 series peripherals interconnect matrix ^{(1) (2)}

Table 62. STM32G4 series peripherals interconnect matrix ^{(1) (2)} (continued)

1. 1. Numbers inside table link to corresponding interconnect number detailed in Section 11.3: Interconnection details .
2. 2. The “-” symbol in grayed cells means no interconnect.

11.3 Interconnection details

11.3.1 From timer (TIMx, HRTIM) to timer (TIMx)

Table 63. Interconnect 1

The HRTIM burst operation can be triggered by on chip event coming from other general purpose timer.

The burst mode controller counter can be clocked by general purpose timers as well as shown in the Table 64 .

Table 64. Interconnect 12

Table 65. Interconnect 13

The HRTIM can be synchronized by external sources as shown in the Table 66 .

Table 66. Interconnect 14

Some of the TIMx timers are linked together internally for timer synchronization or chaining. When one timer is configured in Master Mode, it can reset, start, stop or clock the counter of another timer configured in Slave Mode.

A description of the feature is provided in: Section 29.3.30: Timer synchronization .

The modes of synchronization are detailed in:

• • Section 29.3.30: Timer synchronization for advanced-control timers (TIM1/TIM8/TIM20)
• • Section 30.4.23: Timer synchronization for general-purpose timers (TIM2/TIM3/TIM4/TIM5)
• • Section 31.4.26: Timer synchronization (TIM15 only) for general-purpose timer (TIM15)

Triggering signals

The output (from Master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1/TIM8/TIM20) following a configurable timer event.

The input (to slave) is on signals TIMx_ITRx

The input and output signals for TIM1/TIM8/TIM20 are shown in Figure 296: Advanced-control timer block diagram .

The possible master/slave connections are given in:

• • Table 267: Internal trigger connection

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

11.3.2 From timer (TIMx, HRTIM) and EXTI to ADC (ADCx)

Table 67. Interconnect 19

Table 67. Interconnect 19 (continued)

Timers (TIMx, HRTIM) can be used to generate an ADC triggering event.

TIMx synchronization is described in: Section 29.3.31: ADC triggers (TIM1/TIM8).

ADC synchronization is described in: Section 21.4.18: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) .

Triggering signals

The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.

The input (to ADC) is on signal EXT[15:0], JEXT[15:0].

The connection between timers and ADC is provided in:

• • Table 166: ADC1/2 - External triggers for regular channels
• • Table 167: ADC1/2 - External trigger for injected channels

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

11.3.3 From ADC (ADCx) to timer (TIMx, HRTIM)

See please Table 75: Interconnect 2 and Table 83: Interconnect 10

ADCs Analog watchdogs are connected to TIM1/8/20 for digital power applications (cycle-by-cycle current regulation with ADC).

A description of the ADC analog watchdog setting is provided in: Section 21.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) .

Trigger settings on the timer are provided in: Section 29.3.6: External trigger input .

Triggering signals

The output (from ADC) is on signals ADCn_AWDx_OUT and the input (to timer) on signal TIMx_ETR (external trigger) or hrtim_eevx[4:1].

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

11.3.4 From timer (TIMx, HRTIM) and EXTI to DAC (DACx)

Table 68. Interconnect 20

Table 68. Interconnect 20 (continued)

Timers (TIMx, HRTIM) and EXTI can be used as triggering event to start a DAC conversion.

Triggering signals

The output (from timer) is on signal TIMx_TRGO directly connected to corresponding DAC inputs.

Selection of input triggers on DAC is provided in Section 22.4.7: DAC trigger selection (single and dual mode).

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

11.3.5 From HSE, LSE, LSI, HSI16, MCO, RTC to timer (TIMx)

See please Table 77: Interconnect 4 and Table 75: Interconnect 2

External clocks (HSE, LSE), internal clocks (LSI, HSI16), microcontroller output clock (MCO), GPIO and RTC wakeup interrupt can be used as input to timer (TIMx).

This allows to calibrate the HSI16 and precisely measure the LSI oscillator frequency.

When Low Speed External (LSE) oscillator is used, no additional hardware connections are required.

This feature is described in Section 7.2.16: Internal/external clock measurement with TIM5/TIM15/TIM16/TIM17 .

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

11.3.6 From RTC, COMPx to low-power timer (LPTIM1)

Table 69. Interconnect 17

RTC alarm A/B, RTC_TAMP1/2/3 input detection, COMPx_OUT can be used as trigger to start LPTIM counters (LPTIM1).

Triggering signals

This trigger feature is described in Section 33.4.6: Trigger multiplexer (and following sections).

The input selection is described in Table 327: LPTIM1 external trigger connection .

Active power mode

Run, Sleep, Low-power run, Low-power sleep, Stop 0, Stop 1.

11.3.7 From timer (TIMx) to comparators (COMPx)

Table 70. Interconnect 15

Timers (TIMx) can be used as blanking window to COMPx (x = 1...7)

The blanking function is described in Section 24.3.6: COMP output blanking .

The blanking sources are given in comparators control and status register (COMP_CxCSR) bits BLANKSEL[2:0].

Triggering signals

Timer output signal TIMx_Ocx are the inputs to blanking source of COMPx.

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

11.3.8 From internal analog source to ADC (ADCx), comparator (COMPx) and OPAMP (OPAMPx)

Table 71 provides the ADC channels mapping on GPIOs or internal connections to temperature sensor (VTS), internal reference voltage VREFINT, VBAT/3 or opampint_vout.

Table 71. Interconnect 21

Table 71. Interconnect 21 (continued)

1. 1. Internal OPAMP output connected directly to ADC input only (no available externally on a pin).
2. 2. For Category 3 devices only.
3. 3. For Category 4 devices only.

The DAC outputs are available on GPIOs or can be internally connected to comparators and operational amplifiers.

Table 72. Interconnect 22

Table 72. Interconnect 22 (continued)

Table 73. Interconnect 23

Table 73. Interconnect 23 (continued)

1. It is an internal connection.

Table 74. Interconnect 24

Table 74. Interconnect 24 (continued)

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

11.3.9 From comparators (COMPx) to timers (TIMx, HRTIM)

Comparators (COMPx) output values can be connected to:

• • Timers (TIMx) input captures or TIMx_ETR signals or TIMx_OCREFCLR signals.
• • hrtim_eevx[4:1] and hrtim_in_filtx[4:1]

Comparators (COMPx) output values can also generate break input signals for timers (TIMx) see Section 30.3.17: Bidirectional break inputs.

Table 75. Interconnect 2

Table 75. Interconnect 2 (continued)

Table 76. Interconnect 3

Table 77. Interconnect 4

Table 78. Interconnect 5

Table 79. Interconnect 6

Table 80. Interconnect 7

The timer break input features two channels:

• • A break channel which gathers both application fault (from input pins and built-in comparators) and system-level fault (clock failure, parity error, ...).
• • A break2 channel which only includes application faults (from input pins and built-in comparators).

Refer to Table 81 , Table 82 and Table 85 .

Table 81. Interconnect 8

Table 82. Interconnect 9

Table 83. Interconnect 10

Table 84. Interconnect 11

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

11.3.10 From system errors to timers (TIMx) and HRTIM

TIMx (TIM1/TIM8/TIM20/TIM15/TIM16/TIM17) break inputs and HRTIM system fault input gather MCU internal fault events coming from:

• • the clock failure event generated by the clock security system (CSS),
• • the PVD output,
• • the SRAM parity error signal,
• • the Cortex-M4 LOCKUP (Hardfault) output
• • Flash ECC double error detection

The purpose of the break function is to protect power switches driven by PWM signals generated by the timers.

The functionality is described in:

• • Section 29.3.18: Using the break function (TIM1/TIM8/TIM20)
• • Section 31.4.15: Using the break function (TIM15/TIM16/TIM17/TIM20)

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

Table 85. Interconnect 18

11.3.11 From timers (TIM16/TIM17) to IRTIM

Table 86. Interconnect 16

General-purpose timer (TIM16/TIM17) output channel TIMx_OC1 are used to generate the waveform of infrared signal output.

The functionality is described in Section 34: Infrared interface (IRTIM) .

Active power mode

Run, Sleep, Low-power run, Low-power sleep.