4. Embedded flash memory (FLASH) for category 4 devices . . . . . 149

4.1 Introduction . . . . . 149
4.2 FLASH main features . . . . . 149
4.3 FLASH functional description . . . . . 150
4.3.1 Flash memory organization . . . . . 150
4.3.2 Error code correction (ECC) . . . . . 151
4.3.3 Read access latency . . . . . 151
4.3.4 Adaptive real-time memory accelerator (ART Accelerator) . . . . . 152
4.3.5 Flash program and erase operations . . . . . 155
4.3.6 Flash main memory erase sequences . . . . . 156
4.3.7 Flash main memory programming sequences . . . . . 157
4.4 FLASH option bytes . . . . . 161
4.4.1 Option bytes description . . . . . 161
4.4.2 Option bytes programming . . . . . 165
4.5 FLASH memory protection . . . . . 167
4.5.1 Read protection (RDP) . . . . . 167
4.5.2 Proprietary code readout protection (PCROP) . . . . . 170
4.5.3 Write protection (WRP) . . . . . 171
4.5.4 Securable memory area . . . . . 172
4.5.5 Disabling core debug access . . . . . 173
4.5.6 Forcing boot from flash memory . . . . . 173
4.6 FLASH interrupts . . . . . 173
4.7 FLASH registers . . . . . 174
4.7.1 Flash access control register (FLASH_ACR) . . . . . 174
4.7.2 Flash power-down key register (FLASH_PDKEYR) . . . . . 175
4.7.3 Flash key register (FLASH_KEYR) . . . . . 175
4.7.4 Flash option key register (FLASH_OPTKEYR) . . . . . 176
4.7.5 Flash status register (FLASH_SR) . . . . . 176
4.7.6 Flash control register (FLASH_CR) . . . . . 178
4.7.7 Flash ECC register (FLASH_ECCR) . . . . . 180
4.7.8 Flash option register (FLASH_OPTR) . . . . . 181

ST logo
ST logo
4.7.9Flash PCROP1 Start address register (FLASH_PCROP1SR) . . . . .183
4.7.10Flash PCROP1 End address register (FLASH_PCROP1ER) . . . . .183
4.7.11Flash WRP area A address register (FLASH_WRP1AR) . . . . .184
4.7.12Flash WRP area B address register (FLASH_WRP1BR) . . . . .184
4.7.13Flash securable area register (FLASH_SEC1R) . . . . .185
4.7.14FLASH register map . . . . .186
5Embedded flash memory (FLASH)
for category 2 devices . . . . .188
5.1Introduction . . . . .188
5.2FLASH main features . . . . .188
5.3FLASH functional description . . . . .189
5.3.1Flash memory organization . . . . .189
5.3.2Error code correction (ECC) . . . . .190
5.3.3Read access latency . . . . .190
5.3.4Adaptive real-time memory accelerator (ART Accelerator) . . . . .191
5.3.5Flash program and erase operations . . . . .194
5.3.6Flash main memory erase sequences . . . . .195
5.3.7Flash main memory programming sequences . . . . .196
5.4FLASH option bytes . . . . .200
5.4.1Option bytes description . . . . .200
5.4.2Option bytes programming . . . . .205
5.5FLASH memory protection . . . . .206
5.5.1Read protection (RDP) . . . . .206
5.5.2Proprietary code readout protection (PCROP) . . . . .209
5.5.3Write protection (WRP) . . . . .210
5.5.4Securable memory area . . . . .211
5.5.5Disabling core debug access . . . . .212
5.5.6Forcing boot from flash memory . . . . .212
5.6FLASH interrupts . . . . .213
5.7FLASH registers . . . . .214
5.7.1Flash access control register (FLASH_ACR) . . . . .214
5.7.2Flash Power-down key register (FLASH_PDKEYR) . . . . .215
5.7.3Flash key register (FLASH_KEYR) . . . . .216
5.7.4Flash option key register (FLASH_OPTKEYR) . . . . .216
5.7.5Flash status register (FLASH_SR) . . . . .216
5.7.6Flash control register (FLASH_CR) . . . . .218
5.7.7Flash ECC register (FLASH_ECCR) . . . . .220
5.7.8Flash option register (FLASH_OPTR) . . . . .221
5.7.9Flash PCROP1 Start address register (FLASH_PCROP1SR) . . . . .223
5.7.10Flash PCROP1 End address register (FLASH_PCROP1ER) . . . . .223
5.7.11Flash WRP area A address register (FLASH_WRP1AR) . . . . .224
5.7.12Flash WRP area B address register (FLASH_WRP1BR) . . . . .224
5.7.13Flash securable area register (FLASH_SEC1R) . . . . .225
5.7.14FLASH register map . . . . .226
6Power control (PWR) . . . . .228
6.1Power supplies . . . . .228
6.1.1Independent analog peripherals supply . . . . .229
6.1.2USB transceivers supply . . . . .230
6.1.3Battery backup domain . . . . .230
6.1.4Voltage regulator . . . . .231
6.1.5Dynamic voltage scaling management . . . . .232
6.2Power supply supervisor . . . . .234
6.2.1Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) . . . . .234
6.2.2Programmable voltage detector (PVD) . . . . .234
6.2.3Peripheral Voltage Monitoring (PVM) . . . . .235
6.3Low-power modes . . . . .236
6.3.1Run mode . . . . .241
6.3.2Low-power run mode (LP run) . . . . .241
6.3.3Low power modes . . . . .242
6.3.4Sleep mode . . . . .243
6.3.5Low-power sleep mode (LP sleep) . . . . .244
6.3.6Stop 0 mode . . . . .245
6.3.7Stop 1 mode . . . . .247
6.3.8Standby mode . . . . .248
6.3.9Shutdown mode . . . . .251
6.3.10Auto-wakeup from low-power mode . . . . .252
6.4PWR registers . . . . .253
6.4.1Power control register 1 (PWR_CR1) . . . . .253
6.4.2Power control register 2 (PWR_CR2) . . . . .254
6.4.3Power control register 3 (PWR_CR3) . . . . .254
6.4.4Power control register 4 (PWR_CR4) . . . . .256
6.4.5Power status register 1 (PWR_SR1) . . . . .257
6.4.6Power status register 2 (PWR_SR2) . . . . .258
6.4.7Power status clear register (PWR_SCR) . . . . .259
6.4.8Power Port A pull-up control register (PWR_PUCRA) . . . . .260
6.4.9Power Port A pull-down control register (PWR_PDCRA) . . . . .260
6.4.10Power Port B pull-up control register (PWR_PUCRB) . . . . .261
6.4.11Power Port B pull-down control register (PWR_PDCRB) . . . . .261
6.4.12Power Port C pull-up control register (PWR_PUCRC) . . . . .262
6.4.13Power Port C pull-down control register (PWR_PDCRC) . . . . .262
6.4.14Power Port D pull-up control register (PWR_PUCRD) . . . . .263
6.4.15Power Port D pull-down control register (PWR_PDCRD) . . . . .263
6.4.16Power Port E pull-up control register (PWR_PUCRE) . . . . .264
6.4.17Power Port E pull-down control register (PWR_PDCRE) . . . . .264
6.4.18Power Port F pull-up control register (PWR_PUCRF) . . . . .265
6.4.19Power Port F pull-down control register (PWR_PDCRF) . . . . .265
6.4.20Power Port G pull-up control register (PWR_PUCRG) . . . . .266
6.4.21Power Port G pull-down control register (PWR_PDCRG) . . . . .266
6.4.22Power control register (PWR_CR5) . . . . .267
6.4.23PWR register map and reset value table . . . . .268
7Reset and clock control (RCC) . . . . .270
7.1Reset . . . . .270
7.1.1Power reset . . . . .270
7.1.2System reset . . . . .270
7.1.3RTC domain reset . . . . .272
7.2Clocks . . . . .272
7.2.1HSE clock . . . . .276
7.2.2HSI16 clock . . . . .277
7.2.3HSI48 clock . . . . .278
7.2.4PLL . . . . .278
7.2.5LSE clock . . . . .278
7.2.6LSI clock . . . . .279
7.2.7System clock (SYSCLK) selection . . . . .279
7.2.8Clock source frequency versus voltage scaling . . . . .280
7.2.9Clock security system (CSS) . . . . .280
7.2.10Clock security system on LSE . . . . .280
7.2.11ADC clock .....281
7.2.12RTC clock .....281
7.2.13Timer clock .....281
7.2.14Watchdog clock .....282
7.2.15Clock-out capability .....282
7.2.16Internal/external clock measurement with TIM5/TIM15/TIM16/TIM17 .282
7.2.17Peripheral clock enable register
(RCC_AHBxENR, RCC_APBxENRy) .....		285
7.3Low-power modes .....286
7.4RCC registers .....287
7.4.1Clock control register (RCC_CR) .....287
7.4.2Internal clock sources calibration register (RCC_ICSCR) .....288
7.4.3Clock configuration register (RCC_CFGR) .....289
7.4.4PLL configuration register (RCC_PLLCFGR) .....291
7.4.5Clock interrupt enable register (RCC_CIER) .....294
7.4.6Clock interrupt flag register (RCC_CIFR) .....295
7.4.7Clock interrupt clear register (RCC_CICR) .....296
7.4.8AHB1 peripheral reset register (RCC_AHB1RSTR) .....297
7.4.9AHB2 peripheral reset register (RCC_AHB2RSTR) .....298
7.4.10AHB3 peripheral reset register (RCC_AHB3RSTR) .....300
7.4.11APB1 peripheral reset register 1 (RCC_APB1RSTR1) .....301
7.4.12APB1 peripheral reset register 2 (RCC_APB1RSTR2) .....303
7.4.13APB2 peripheral reset register (RCC_APB2RSTR) .....303
7.4.14AHB1 peripheral clock enable register (RCC_AHB1ENR) .....305
7.4.15AHB2 peripheral clock enable register (RCC_AHB2ENR) .....306
7.4.16AHB3 peripheral clock enable register(RCC_AHB3ENR) .....308
7.4.17APB1 peripheral clock enable register 1 (RCC_APB1ENR1) .....309
7.4.18APB1 peripheral clock enable register 2 (RCC_APB1ENR2) .....311
7.4.19APB2 peripheral clock enable register (RCC_APB2ENR) .....312
7.4.20AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR) .....		313
7.4.21AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR) .....		315
7.4.22AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR) .....		317
7.4.23APB1 peripheral clocks enable in Sleep and Stop modes register 1
(RCC_APB1SMENR1) .....		317
7.4.24APB1 peripheral clocks enable in Sleep and Stop modes register 2
(RCC_APB1SMENR2) .....		320
7.4.25APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) . . . . .321
7.4.26Peripherals independent clock configuration register (RCC_CCIPR) . . . . .322
7.4.27RTC domain control register (RCC_BDCR) . . . . .325
7.4.28Control/status register (RCC_CSR) . . . . .327
7.4.29Clock recovery RC register (RCC_CRRCR) . . . . .328
7.4.30Peripherals independent clock configuration register (RCC_CCIPR2) . . . . .329
7.4.31RCC register map . . . . .330
8Clock recovery system (CRS) . . . . .334
8.1CRS introduction . . . . .334
8.2CRS main features . . . . .334
8.3CRS implementation . . . . .334
8.4CRS functional description . . . . .335
8.4.1CRS block diagram . . . . .335
8.4.2CRS internal signals . . . . .335
8.4.3Synchronization input . . . . .336
8.4.4Frequency error measurement . . . . .336
8.4.5Frequency error evaluation and automatic trimming . . . . .337
8.4.6CRS initialization and configuration . . . . .338
8.5CRS in low-power modes . . . . .339
8.6CRS interrupts . . . . .339
8.7CRS registers . . . . .339
8.7.1CRS control register (CRS_CR) . . . . .339
8.7.2CRS configuration register (CRS_CFGR) . . . . .340
8.7.3CRS interrupt and status register (CRS_ISR) . . . . .341
8.7.4CRS interrupt flag clear register (CRS_ICR) . . . . .343
8.7.5CRS register map . . . . .344
9General-purpose I/Os (GPIO) . . . . .345
9.1Introduction . . . . .345
9.2GPIO main features . . . . .345
9.3GPIO functional description . . . . .345
9.3.1General-purpose I/O (GPIO) . . . . .348
9.3.2I/O pin alternate function multiplexer and mapping . . . . .348
9.3.3I/O port control registers . . . . .349
9.3.4I/O port data registers . . . . .349
9.3.5I/O data bitwise handling . . . . .349
9.3.6GPIO locking mechanism . . . . .350
9.3.7I/O alternate function input/output . . . . .350
9.3.8External interrupt/wakeup lines . . . . .350
9.3.9Input configuration . . . . .351
9.3.10Output configuration . . . . .351
9.3.11Alternate function configuration . . . . .352
9.3.12Analog configuration . . . . .353
9.3.13Using the HSE or LSE oscillator pins as GPIOs . . . . .353
9.3.14Using the GPIO pins in the RTC supply domain . . . . .353
9.3.15Using PB8 as GPIO . . . . .354
9.3.16Using PG10 as GPIO . . . . .354
9.4GPIO registers . . . . .355
9.4.1GPIO port mode register (GPIOx_MODER)
(x =A to G) . . . . .		355
9.4.2GPIO port output type register (GPIOx_OTYPER)
(x = A to G) . . . . .		355
9.4.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to G) . . . . .		356
9.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to G) . . . . .		356
9.4.5GPIO port input data register (GPIOx_IDR)
(x = A to G) . . . . .		357
9.4.6GPIO port output data register (GPIOx_ODR)
(x = A to G) . . . . .		357
9.4.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to G) . . . . .		357
9.4.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to G) . . . . .		358
9.4.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to G) . . . . .		359
9.4.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to G) . . . . .		360
9.4.11GPIO port bit reset register (GPIOx_BRR) (x = A to G) . . . . .361
9.4.12GPIO register map . . . . .362
10System configuration controller (SYSCFG) . . . . .364
10.1SYSCFG main features . . . . .364
10.2SYSCFG registers . . . . .364
10.2.1SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .364
10.2.2SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .365
10.2.3SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . .		367
10.2.4SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . .		368
10.2.5SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . .		369
10.2.6SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . .		371
10.2.7SYSCFG CCM SRAM control and status register (SYSCFG_SCSR) .372
10.2.8SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .373
10.2.9SYSCFG CCM SRAM write protection register (SYSCFG_SWPR) . .374
10.2.10SYSCFG CCM SRAM key register (SYSCFG_SKR) . . . . .374
10.2.11SYSCFG register map . . . . .375
11Peripherals interconnect matrix . . . . .376
11.1Introduction . . . . .376
11.2Connection summary . . . . .377
11.3Interconnection details . . . . .379
11.3.1From timer (TIMx, HRTIM) to timer (TIMx) . . . . .379
11.3.2From timer (TIMx, HRTIM) and EXTI to ADC (ADCx) . . . . .381
11.3.3From ADC (ADCx) to timer (TIMx, HRTIM) . . . . .383
11.3.4From timer (TIMx, HRTIM) and EXTI to DAC (DACx) . . . . .383
11.3.5From HSE, LSE, LSI, HSI16, MCO, RTC to timer (TIMx) . . . . .384
11.3.6From RTC, COMPx to low-power timer (LPTIM1) . . . . .385
11.3.7From timer (TIMx) to comparators (COMPx) . . . . .386
11.3.8From internal analog source to ADC (ADCx), comparator (COMPx)
and OPAMP (OPAMPx) . . . . .		386
11.3.9From comparators (COMPx) to timers (TIMx, HRTIM) . . . . .390
11.3.10From system errors to timers (TIMx) and HRTIM . . . . .396
11.3.11From timers (TIM16/TIM17) to IRTIM . . . . .396
12Direct memory access controller (DMA) . . . . .397
12.1Introduction . . . . .397
12.2DMA main features . . . . .397
12.3DMA implementation . . . . .398
12.3.1DMA1 and DMA2 . . . . .398
12.3.2DMA request mapping . . . . .398
12.4DMA functional description . . . . .399
12.4.1DMA block diagram . . . . .399
12.4.2DMA pins and internal signals . . . . .400
12.4.3DMA transfers . . . . .400
12.4.4DMA arbitration . . . . .401
12.4.5DMA channels . . . . .401
12.4.6DMA data width, alignment, and endianness . . . . .405
12.4.7DMA error management . . . . .406
12.5DMA interrupts . . . . .407
12.6DMA registers . . . . .407
12.6.1DMA interrupt status register (DMA_ISR) . . . . .407
12.6.2DMA interrupt flag clear register (DMA_IFCR) . . . . .409
12.6.3DMA channel x configuration register (DMA_CCRx) . . . . .411
12.6.4DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . .413
12.6.5DMA channel x peripheral address register (DMA_CPARx) . . . . .414
12.6.6DMA channel x memory address register (DMA_CMARx) . . . . .415
12.6.7DMA register map . . . . .415
13DMA request multiplexer (DMAMUX) . . . . .418
13.1Introduction . . . . .418
13.2DMAMUX main features . . . . .419
13.3DMAMUX implementation . . . . .419
13.3.1DMAMUX instantiation . . . . .419
13.3.2DMAMUX mapping . . . . .419
13.4DMAMUX functional description . . . . .423
13.4.1DMAMUX block diagram . . . . .423
13.4.2DMAMUX signals . . . . .424
13.4.3DMAMUX channels . . . . .424
13.4.4DMAMUX request line multiplexer . . . . .424
13.4.5DMAMUX request generator . . . . .427
13.5DMAMUX interrupts . . . . .428
13.6DMAMUX registers . . . . .429
13.6.1DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR) . . . . .		429
13.6.2DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR) . . . . .		430
13.6.3DMAMUX request line multiplexer interrupt clear flag register (DMAMUX_CFR) . . . . .430
13.6.4DMAMUX request generator channel x configuration register (DMAMUX_RGxCR) . . . . .431
13.6.5DMAMUX request generator interrupt status register (DMAMUX_RGSR) . . . . .432
13.6.6DMAMUX request generator interrupt clear flag register (DMAMUX_RGCFR) . . . . .432
13.6.7DMAMUX register map . . . . .433
14Nested vectored interrupt controller (NVIC) . . . . .436
14.1NVIC main features . . . . .436
14.2SysTick calibration value register . . . . .436
14.3Interrupt and exception vectors . . . . .437
15Extended interrupts and events controller (EXTI) . . . . .441
15.1Introduction . . . . .441
15.2EXTI main features . . . . .441
15.3EXTI functional description . . . . .441
15.3.1EXTI block diagram . . . . .442
15.3.2Wake-up event management . . . . .442
15.3.3Peripherals asynchronous Interrupts . . . . .443
15.3.4Hardware interrupt selection . . . . .443
15.3.5Hardware event selection . . . . .443
15.3.6Software interrupt/event selection . . . . .443
15.4EXTI interrupt/event line mapping . . . . .443
15.5EXTI registers . . . . .446
15.5.1Interrupt mask register 1 (EXTI_IMR1) . . . . .446
15.5.2Event mask register 1 (EXTI_EM1) . . . . .446
15.5.3Rising trigger selection register 1 (EXTI_RTSR1) . . . . .446
15.5.4Falling trigger selection register 1 (EXTI_FTSR1) . . . . .447
15.5.5Software interrupt event register 1 (EXTI_SWIER1) . . . . .448
15.5.6Pending register 1 (EXTI_PR1) . . . . .449
15.5.7Interrupt mask register 2 (EXTI_IMR2) . . . . .449
15.5.8Event mask register 2 (EXTI_EM2) . . . . .450
15.5.9Rising trigger selection register 2 (EXTI_RTSR2) . . . . .450
15.5.10Falling trigger selection register 2 (EXTI_FTSR2) . . . . .451
17.4.4CORDIC register map .....478
18Filter math accelerator (FMAC) .....479
18.1FMAC introduction .....479
18.2FMAC main features .....479
18.3FMAC functional description .....480
18.3.1General description .....480
18.3.2Local memory and buffers .....481
18.3.3Input buffers .....481
18.3.4Output buffer .....484
18.3.5Initialization functions .....486
18.3.6Filter functions .....487
18.3.7Fixed point representation .....491
18.3.8Implementing FIR filters with the FMAC .....491
18.3.9Implementing IIR filters with the FMAC .....493
18.3.10Examples of filter initialization .....495
18.3.11Examples of filter operation .....496
18.3.12Filter design tips .....498
18.4FMAC registers .....499
18.4.1FMAC X1 buffer configuration register (FMAC_X1BUFCFG) .....499
18.4.2FMAC X2 buffer configuration register (FMAC_X2BUFCFG) .....499
18.4.3FMAC Y buffer configuration register (FMAC_YBUFCFG) .....500
18.4.4FMAC parameter register (FMAC_PARAM) .....501
18.4.5FMAC control register (FMAC_CR) .....502
18.4.6FMAC status register (FMAC_SR) .....503
18.4.7FMAC write data register (FMAC_WDATA) .....504
18.4.8FMAC read data register (FMAC_RDATA) .....505
18.4.9FMAC register map .....505
19Flexible static memory controller (FSMC) .....507
19.1Introduction .....507
19.2FMC main features .....507
19.3FMC block diagram .....508
19.4AHB interface .....508
19.4.1Supported memories and transactions .....509
19.5External device address mapping .....510
20.3.14QUADSPI busy bit and abort functionality . . . . .575
20.3.15NCS behavior . . . . .576
20.4QUADSPI interrupts . . . . .578
20.5QUADSPI registers . . . . .578
20.5.1QUADSPI control register (QUADSPI_CR) . . . . .578
20.5.2QUADSPI device configuration register (QUADSPI_DCR) . . . . .581
20.5.3QUADSPI status register (QUADSPI_SR) . . . . .582
20.5.4QUADSPI flag clear register (QUADSPI_FCR) . . . . .583
20.5.5QUADSPI data length register (QUADSPI_DLR) . . . . .583
20.5.6QUADSPI communication configuration register (QUADSPI_CCR) . . . . .584
20.5.7QUADSPI address register (QUADSPI_AR) . . . . .586
20.5.8QUADSPI alternate-byte register (QUADSPI_ABR) . . . . .586
20.5.9QUADSPI data register (QUADSPI_DR) . . . . .587
20.5.10QUADSPI polling status mask register (QUADSPI_PSMKR) . . . . .587
20.5.11QUADSPI polling status match register (QUADSPI_PSMAR) . . . . .588
20.5.12QUADSPI polling interval register (QUADSPI_PIR) . . . . .588
20.5.13QUADSPI low-power timeout register (QUADSPI_LPTR) . . . . .589
20.5.14QUADSPI register map . . . . .589
21Analog-to-digital converters (ADC) . . . . .591
21.1Introduction . . . . .591
21.2ADC main features . . . . .592
21.3ADC implementation . . . . .593
21.4ADC functional description . . . . .594
21.4.1ADC block diagram . . . . .594
21.4.2ADC pins and internal signals . . . . .595
21.4.3ADC clocks . . . . .596
21.4.4ADC1/2/3/4/5 connectivity . . . . .598
21.4.5Slave AHB interface . . . . .603
21.4.6ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) . . . . .603
21.4.7Single-ended and differential input channels . . . . .604
21.4.8Calibration (ADCAL, ADCALDIF, ADC_CALFACT) . . . . .604
21.4.9ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .607
21.4.10Constraints when writing the ADC control bits . . . . .608
21.4.11Channel selection (ADC_SQRy, ADC_JSQR) . . . . .609
21.4.12Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .610
21.4.13Single conversion mode (CONT = 0) . . . . .612
21.4.14Continuous conversion mode (CONT = 1) . . . . .612
21.4.15Starting conversions (ADSTART, JADSTART) . . . . .613
21.4.16ADC timing . . . . .614
21.4.17Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .614
21.4.18Conversion on external trigger and trigger polarity
(EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . .		616
21.4.19Injected channel management . . . . .621
21.4.20Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .623
21.4.21Queue of context for injected conversions . . . . .624
21.4.22Programmable resolution (RES) - Fast conversion mode . . . . .632
21.4.23End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . . . .633
21.4.24End of conversion sequence (EOS, JEOS) . . . . .633
21.4.25Timing diagrams example (single/continuous modes,
hardware/software triggers) . . . . .		634
21.4.26Data management . . . . .636
21.4.27Dynamic low-power features . . . . .642
21.4.28Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,
AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . .		647
21.4.29Oversampler . . . . .651
21.4.30Dual ADC modes . . . . .657
21.4.31Temperature sensor . . . . .671
21.4.32VBAT supply monitoring . . . . .673
21.4.33Monitoring the internal voltage reference . . . . .674
21.5ADC in low-power mode . . . . .675
21.6ADC interrupts . . . . .676
21.7ADC registers (for each ADC) . . . . .677
21.7.1ADC interrupt and status register (ADC_ISR) . . . . .677
21.7.2ADC interrupt enable register (ADC_IER) . . . . .679
21.7.3ADC control register (ADC_CR) . . . . .681
21.7.4ADC configuration register (ADC_CFGR) . . . . .684
21.7.5ADC configuration register 2 (ADC_CFGR2) . . . . .688
21.7.6ADC sample time register 1 (ADC_SMPR1) . . . . .691
21.7.7ADC sample time register 2 (ADC_SMPR2) . . . . .691
21.7.8ADC watchdog threshold register 1 (ADC_TR1) . . . . .692
21.7.9ADC watchdog threshold register 2 (ADC_TR2) . . . . .693
21.7.10ADC watchdog threshold register 3 (ADC_TR3) . . . . .694
21.7.11ADC regular sequence register 1 (ADC_SQR1) . . . . .694
21.7.12ADC regular sequence register 2 (ADC_SQR2) . . . . .695
21.7.13ADC regular sequence register 3 (ADC_SQR3) . . . . .696
21.7.14ADC regular sequence register 4 (ADC_SQR4) . . . . .697
21.7.15ADC regular data register (ADC_DR) . . . . .698
21.7.16ADC injected sequence register (ADC_JSQR) . . . . .698
21.7.17ADC offset y register (ADC_OFRy) . . . . .700
21.7.18ADC injected channel y data register (ADC_JDRy) . . . . .701
21.7.19ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . .702
21.7.20ADC analog watchdog 3 configuration register (ADC_AWD3CR) . . . . .702
21.7.21ADC differential mode selection register (ADC_DIFSEL) . . . . .703
21.7.22ADC calibration factors (ADC_CALFACT) . . . . .703
21.7.23ADC Gain compensation Register (ADC_GCOMP) . . . . .704
21.8ADC common registers . . . . .705
21.8.1ADCx common status register (ADCx_CSR) (x = 12 or 345) . . . . .705
21.8.2ADCx common control register (ADCx_CCR) (x = 12 or 345) . . . . .706
21.8.3ADCx common regular data register for dual mode (ADCx_CDR)
(x = 12 or 345) . . . . .		710
21.9ADC register map . . . . .710
22Digital-to-analog converter (DAC) . . . . .714
22.1Introduction . . . . .714
22.2DAC main features . . . . .714
22.3DAC implementation . . . . .715
22.4DAC functional description . . . . .716
22.4.1DAC block diagram . . . . .716
22.4.2DAC pins and internal signals . . . . .717
22.4.3DAC channel enable . . . . .723
22.4.4DAC data format . . . . .723
22.4.5DAC conversion . . . . .725
22.4.6DAC output voltage . . . . .726
22.4.7DAC trigger selection . . . . .726
22.4.8DMA requests . . . . .727
22.4.9Noise generation . . . . .728
22.4.10Triangle-wave generation . . . . .729
22.4.11DAC sawtooth wave generation . . . . .730
22.4.12DAC channel modes . . . . .731
22.4.13DAC channel buffer calibration . . . . .734
22.4.14DAC channel conversion modes . . . . .735
22.4.15Dual DAC channel conversion modes (if dual channels are available) . . . . .737
22.5DAC in low-power modes . . . . .742
22.6DAC interrupts . . . . .742
22.7DAC registers . . . . .742
22.7.1DAC control register (DAC_CR) . . . . .742
22.7.2DAC software trigger register (DAC_SWTRGR) . . . . .746
22.7.3DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . .747
22.7.4DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . .747
22.7.5DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . .748
22.7.6DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . .748
22.7.7DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . .749
22.7.8DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . .749
22.7.9Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . .750
22.7.10Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . .750
22.7.11Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . .751
22.7.12DAC channel1 data output register (DAC_DOR1) . . . . .751
22.7.13DAC channel2 data output register (DAC_DOR2) . . . . .752
22.7.14DAC status register (DAC_SR) . . . . .752
22.7.15DAC calibration control register (DAC_CCR) . . . . .754
22.7.16DAC mode control register (DAC_MCR) . . . . .755
22.7.17DAC channel1 sample and hold sample time register (DAC_SHSR1) . . . . .756
22.7.18DAC channel2 sample and hold sample time register (DAC_SHSR2) . . . . .757
22.7.19DAC sample and hold time register (DAC_SHHR) . . . . .757
22.7.20DAC sample and hold refresh time register (DAC_SHRR) . . . . .758
22.7.21DAC channel1 sawtooth register (DAC_STR1) . . . . .759
22.7.22DAC channel2 sawtooth register (DAC_STR2) . . . . .759
22.7.23DAC sawtooth mode register (DAC_STMODR) . . . . .760
22.7.24DAC register map .....761
23Voltage reference buffer (VREFBUF) .....764
23.1Introduction .....764
23.2VREFBUF functional description .....764
23.3VREFBUF trimming .....765
23.4VREFBUF registers .....766
23.4.1VREFBUF control and status register (VREFBUF_CSR) .....766
23.4.2VREFBUF calibration control register (VREFBUF_CCR) .....767
23.4.3VREFBUF register map .....767
24Comparator (COMP) .....768
24.1COMP introduction .....768
24.2COMP main features .....768
24.3COMP functional description .....768
24.3.1COMP block diagram .....768
24.3.2COMP pins and internal signals .....769
24.3.3COMP reset and clocks .....769
24.3.4COMP LOCK mechanism .....770
24.3.5COMP hysteresis .....770
24.3.6COMP output blanking .....770
24.4COMP low-power modes .....771
24.5COMP interrupts .....772
24.6COMP registers .....772
24.6.1Comparator x control and status register (COMP_CxCSR) .....772
24.6.2COMP register map .....774
25Operational amplifiers (OPAMP) .....776
25.1Introduction .....776
25.2OPAMP main features .....776
25.3OPAMP functional description .....776
25.3.1OPAMP output redirection to internal ADC channels .....776
25.3.2OPAMP reset and clocks .....776
25.3.3Initial configuration .....777
25.3.4Signal routing .....777
25.3.5OPAMP modes .....779
25.3.6OPAMP PGA gain . . . . .784
25.3.7Calibration . . . . .785
25.3.8Timer controlled Multiplexer mode . . . . .786
25.4OPAMP low-power modes . . . . .787
25.5OPAMP registers . . . . .788
25.5.1OPAMP1 control/status register (OPAMP1_CSR) . . . . .788
25.5.2OPAMP2 control/status register (OPAMP2_CSR) . . . . .791
25.5.3OPAMP3 control/status register (OPAMP3_CSR) . . . . .794
25.5.4OPAMP4 control/status register (OPAMP4_CSR) . . . . .797
25.5.5OPAMP5 control/status register (OPAMP5_CSR) . . . . .800
25.5.6OPAMP6 control/status register (OPAMP6_CSR) . . . . .803
25.5.7OPAMP1 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) . . . . .806
25.5.8OPAMP2 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) . . . . .808
25.5.9OPAMP3 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) . . . . .810
25.5.10OPAMP4 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) . . . . .812
25.5.11OPAMP5 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) . . . . .814
25.5.12OPAMP6 timer controlled mode register (OPAMPx_TCMR) (x = 1...6) . . . . .816
25.5.13OPAMP register map . . . . .818
26True random number generator (RNG) . . . . .820
26.1Introduction . . . . .820
26.2RNG main features . . . . .820
26.3RNG functional description . . . . .821
26.3.1RNG block diagram . . . . .821
26.3.2RNG internal signals . . . . .821
26.3.3Random number generation . . . . .822
26.3.4RNG initialization . . . . .824
26.3.5RNG operation . . . . .825
26.3.6RNG clocking . . . . .826
26.3.7Error management . . . . .826
26.3.8RNG low-power use . . . . .827
26.4RNG interrupts . . . . .827
26.5RNG processing time . . . . .827
26.6RNG entropy source validation . . . . .828
26.6.1Introduction . . . . .828
26.6.2Validation conditions . . . . .828
26.6.3Data collection .....828
26.7RNG registers .....829
26.7.1RNG control register (RNG_CR) .....829
26.7.2RNG status register (RNG_SR) .....829
26.7.3RNG data register (RNG_DR) .....830
26.7.4RNG register map .....831
27AES hardware accelerator (AES) .....832
27.1Introduction .....832
27.2AES main features .....832
27.3AES implementation .....832
27.4AES functional description .....833
27.4.1AES block diagram .....833
27.4.2AES internal signals .....833
27.4.3AES cryptographic core .....833
27.4.4AES procedure to perform a cipher operation .....839
27.4.5AES decryption round key preparation .....842
27.4.6AES ciphertext stealing and data padding .....843
27.4.7AES task suspend and resume .....843
27.4.8AES basic chaining modes (ECB, CBC) .....844
27.4.9AES counter (CTR) mode .....849
27.4.10AES Galois/counter mode (GCM) .....851
27.4.11AES Galois message authentication code (GMAC) .....856
27.4.12AES counter with CBC-MAC (CCM) .....858
27.4.13AES data registers and data swapping .....863
27.4.14AES key registers .....865
27.4.15AES initialization vector registers .....865
27.4.16AES DMA interface .....866
27.4.17AES error management .....867
27.5AES interrupts .....868
27.6AES processing latency .....868
27.7AES registers .....869
27.7.1AES control register (AES_CR) .....869
27.7.2AES status register (AES_SR) .....872
27.7.3AES data input register (AES_DINR) .....873
27.7.4AES data output register (AES_DOUTR) .....873

27.7.5 AES key register 0 (AES_KEYR0) . . . . . 874

27.7.6 AES key register 1 (AES_KEYR1) . . . . . 875

27.7.7 AES key register 2 (AES_KEYR2) . . . . . 875

27.7.8 AES key register 3 (AES_KEYR3) . . . . . 875

27.7.9 AES initialization vector register 0 (AES_IVR0) . . . . . 876

27.7.10 AES initialization vector register 1 (AES_IVR1) . . . . . 876

27.7.11 AES initialization vector register 2 (AES_IVR2) . . . . . 876

27.7.12 AES initialization vector register 3 (AES_IVR3) . . . . . 877

27.7.13 AES key register 4 (AES_KEYR4) . . . . . 877

27.7.14 AES key register 5 (AES_KEYR5) . . . . . 877

27.7.15 AES key register 6 (AES_KEYR6) . . . . . 878

27.7.16 AES key register 7 (AES_KEYR7) . . . . . 878

27.7.17 AES suspend registers (AES_SUSPxR) . . . . . 878

27.7.18 AES register map . . . . . 879

28 High-resolution timer (HRTIM) . . . . . 881

28.1 Introduction . . . . . 881

28.2 Main features . . . . . 882

28.3 Functional description . . . . . 883

28.3.1 General description . . . . . 883

28.3.2 HRTIM pins and internal signals . . . . . 885

28.3.3 Clocks . . . . . 889

28.3.4 Timer A..F timing units . . . . . 892

28.3.5 Master timer . . . . . 913

28.3.6 Up-down counting mode . . . . . 915

28.3.7 Set / reset events priorities and narrow pulses management . . . . . 922

28.3.8 External events global conditioning . . . . . 925

28.3.9 External event filtering in timing units . . . . . 929

28.3.10 Delayed protection . . . . . 935

28.3.11 Register preload and update management . . . . . 942

28.3.12 PWM mode with “greater than” comparison . . . . . 946

28.3.13 Events propagation within or across multiple timers . . . . . 947

28.3.14 Output management . . . . . 952

28.3.15 Burst mode controller . . . . . 954

28.3.16 Chopper . . . . . 962

28.3.17 Fault protection . . . . . 963

28.3.18 Auxiliary outputs . . . . . 967

28.3.19Synchronizing the HRTIM with other timers or HRTIM instances . . . .970
28.3.20ADC triggers . . . . .973
28.3.21DAC triggers . . . . .977
28.3.22Interrupts . . . . .981
28.3.23DMA . . . . .983
28.3.24HRTIM initialization . . . . .987
28.3.25Debug . . . . .988
28.4Application use cases . . . . .989
28.4.1Buck converter . . . . .989
28.4.2Buck converter with synchronous rectification . . . . .990
28.4.3Multiphase converters . . . . .991
28.4.4Transition mode power factor correction . . . . .992
28.5HRTIM registers . . . . .995
28.5.1HRTIM master timer control register (HRTIM_MCR) . . . . .995
28.5.2HRTIM master timer interrupt status register (HRTIM_MISR) . . . . .998
28.5.3HRTIM master timer interrupt clear register (HRTIM_MICR) . . . . .999
28.5.4HRTIM master timer DMA interrupt enable register
(HRTIM_MDIER) . . . . .		1000
28.5.5HRTIM master timer counter register (HRTIM_MCNTR) . . . . .1002
28.5.6HRTIM master timer period register (HRTIM_MPER) . . . . .1002
28.5.7HRTIM master timer repetition register (HRTIM_MREP) . . . . .1003
28.5.8HRTIM master timer compare 1 register (HRTIM_MCMP1R) . . . . .1003
28.5.9HRTIM master timer compare 2 register (HRTIM_MCMP2R) . . . . .1004
28.5.10HRTIM master timer compare 3 register (HRTIM_MCMP3R) . . . . .1004
28.5.11HRTIM master timer compare 4 register (HRTIM_MCMP4R) . . . . .1005
28.5.12HRTIM timer x control register (HRTIM_TIMxCR) (x = A to F) . . . . .1006
28.5.13HRTIM timer x interrupt status register
(HRTIM_TIMxISR) (x = A to F) . . . . .		1010
28.5.14HRTIM timer x interrupt clear register
(HRTIM_TIMxICR) (x = A to F) . . . . .		1012
28.5.15HRTIM timer x DMA interrupt enable register
(HRTIM_TIMxDIER) (x = A to F) . . . . .		1013
28.5.16HRTIM timer x counter register (HRTIM_CNTxR) (x = A to F) . . . . .1017
28.5.17HRTIM timer x period register (HRTIM_PERxR) (x = A to F) . . . . .1017
28.5.18HRTIM timer x repetition register (HRTIM_REPxR) (x = A to F) . . . . .1019
28.5.19HRTIM timer x compare 1 register (HRTIM_CMP1xR) (x = A to F) . . . . .1019
28.5.20HRTIM timer x compare 1 compound register (HRTIM_CMP1CxR)
(x = A to F) . . . . .		1021
28.5.21HRTIM timer x compare 2 register (HRTIM_CMP2xR) (x = A to F) . . .1021
28.5.22HRTIM timer x compare 3 register (HRTIM_CMP3xR) (x = A to F) . . .1023
28.5.23HRTIM timer x compare 4 register (HRTIM_CMP4xR) (x = A to F) . . .1024
28.5.24HRTIM timer x capture 1 register (HRTIM_CPT1xR) (x = A to F) . . .1025
28.5.25HRTIM timer x capture 2 register (HRTIM_CPT2xR)
(x = A to F) . . . . .		1026
28.5.26HRTIM timer x deadtime register (HRTIM_DTxR) (x = A to F) . . . . .1027
28.5.27HRTIM timer x output 1 set register (HRTIM_SETx1R) (x = A to F) . .1029
28.5.28HRTIM timer x output 1 reset register (HRTIM_RSTx1R) (x = A to F)1032
28.5.29HRTIM timer x output 2 set register (HRTIM_SETx2R) (x = A to F) . .1034
28.5.30HRTIM timer x output 2 reset register (HRTIM_RSTx2R) (x = A to F)1037
28.5.31HRTIM timer x external event filtering register 1 (HRTIM_EEFxR1)
(x = A to F) . . . . .		1040
28.5.32HRTIM timer x external event filtering register 2 (HRTIM_EEFxR2)
(x = A to F) . . . . .		1042
28.5.33HRTIM timer A reset register (HRTIM_RSTAR) . . . . .1043
28.5.34HRTIM timer B reset register (HRTIM_RSTBR) . . . . .1045
28.5.35HRTIM timer C reset register (HRTIM_RSTCR) . . . . .1047
28.5.36HRTIM timer D reset register (HRTIM_RSTDR) . . . . .1049
28.5.37HRTIM timer E reset register (HRTIM_RSTER) . . . . .1051
28.5.38HRTIM timer F reset register (HRTIM_RSTFR) . . . . .1053
28.5.39HRTIM timer x chopper register (HRTIM_CHPxR) (x = A to F) . . . . .1055
28.5.40HRTIM timer A capture 1 control register (HRTIM_CPT1ACR) . . . . .1056
28.5.41HRTIM timer B capture 1 control register (HRTIM_CPT1BCR) . . . . .1058
28.5.42HRTIM timer C capture 1 control register (HRTIM_CPT1CCR) . . . . .1060
28.5.43HRTIM timer D capture 1 control register (HRTIM_CPT1DCR) . . . . .1062
28.5.44HRTIM timer E capture 1 control register (HRTIM_CPT1ECR) . . . . .1064
28.5.45HRTIM timer F capture 1 control register (HRTIM_CPT1FCR) . . . . .1066
28.5.46HRTIM timer A capture 2 control register (HRTIM_CPT2ACR) . . . . .1068
28.5.47HRTIM timer B capture 2 control register (HRTIM_CPT2BCR) . . . . .1070
28.5.48HRTIM timer C capture 2 control register (HRTIM_CPT2CCR) . . . . .1072
28.5.49HRTIM timer D capture 2 control register (HRTIM_CPT2DCR) . . . . .1074
28.5.50HRTIM timer E capture 2 control register (HRTIM_CPT2ECR) . . . . .1076
28.5.51HRTIM timer F capture 2 control register (HRTIM_CPT2FCR) . . . . .1078
28.5.52HRTIM timer x output register (HRTIM_OUTxR) (x = A to F) . . . . .1080
28.5.53HRTIM timer x fault register (HRTIM_FLTxR) (x = A to F) . . . . .1083
28.5.54HRTIM timer x control register 2 (HRTIM_TIMxCR2) (x = A to F) . . .1084
28.5.55HRTIM timer x external event filtering register 3 (HRTIM_TIMxEEFR3) (x = A to F) . . . . .1087
28.5.56HRTIM control register 1 (HRTIM_CR1) . . . . .1088
28.5.57HRTIM control register 2 (HRTIM_CR2) . . . . .1090
28.5.58HRTIM interrupt status register (HRTIM_ISR) . . . . .1091
28.5.59HRTIM interrupt clear register (HRTIM_ICR) . . . . .1093
28.5.60HRTIM interrupt enable register (HRTIM_IER) . . . . .1094
28.5.61HRTIM output enable register (HRTIM_OENR) . . . . .1095
28.5.62HRTIM output disable register (HRTIM_ODISR) . . . . .1096
28.5.63HRTIM output disable status register (HRTIM_ODSR) . . . . .1097
28.5.64HRTIM burst mode control register (HRTIM_BMCR) . . . . .1098
28.5.65HRTIM burst mode trigger register (HRTIM_BMTRGR) . . . . .1100
28.5.66HRTIM burst mode compare register (HRTIM_BMCMR) . . . . .1102
28.5.67HRTIM burst mode period register (HRTIM_BMPER) . . . . .1102
28.5.68HRTIM timer external event control register 1 (HRTIM_EECR1) . . . . .1103
28.5.69HRTIM timer external event control register 2 (HRTIM_EECR2) . . . . .1105
28.5.70HRTIM timer external event control register 3 (HRTIM_EECR3) . . . . .1106
28.5.71HRTIM ADC trigger 1 register (HRTIM_ADC1R) . . . . .1107
28.5.72HRTIM ADC trigger 2 register (HRTIM_ADC2R) . . . . .1110
28.5.73HRTIM ADC trigger 3 register (HRTIM_ADC3R) . . . . .1112
28.5.74HRTIM ADC trigger 4 register (HRTIM_ADC4R) . . . . .1114
28.5.75HRTIM DLL control register (HRTIM_DLLCR) . . . . .1116
28.5.76HRTIM fault input register 1 (HRTIM_FLTINR1) . . . . .1117
28.5.77HRTIM fault input register 2 (HRTIM_FLTINR2) . . . . .1119
28.5.78HRTIM burst DMA master timer update register (HRTIM_BDMUPR) . . . . .1121
28.5.79HRTIM burst DMA timer x update register (HRTIM_BDTxUPR) (x = A to F) . . . . .1122
28.5.80HRTIM burst DMA data register (HRTIM_BDMADR) . . . . .1123
28.5.81HRTIM ADC extended trigger register (HRTIM_ADCER) . . . . .1124
28.5.82HRTIM ADC trigger update register (HRTIM_ADCUR) . . . . .1127
28.5.83HRTIM ADC post scaler register 1 (HRTIM_ADCPS1) . . . . .1128
28.5.84HRTIM ADC post scaler register 2 (HRTIM_ADCPS2) . . . . .1129
28.5.85HRTIM fault input register 3 (HRTIM_FLTINR3) . . . . .1130
28.5.86HRTIM fault input register 4 (HRTIM_FLTINR4) . . . . .1132
28.5.87HRTIM register map . . . . .1134
29Advanced-control timers (TIM1/TIM8/TIM20) . . . . .1144
29.1TIM1/TIM8/TIM20 introduction . . . . .1144
29.5TIM1/TIM8/TIM20 interrupts . . . . .1234
29.6TIM1/TIM8/TIM20 registers . . . . .1235
29.6.1TIMx control register 1 (TIMx_CR1)(x = 1, 8, 20) . . . . .1235
29.6.2TIMx control register 2 (TIMx_CR2)(x = 1, 8, 20) . . . . .1236
29.6.3TIMx slave mode control register (TIMx_SMCR)(x = 1, 8, 20) . . . . .1240
29.6.4TIMx DMA/interrupt enable register (TIMx_DIER)(x = 1, 8, 20) . . . . .1244
29.6.5TIMx status register (TIMx_SR)(x = 1, 8, 20) . . . . .1245
29.6.6TIMx event generation register (TIMx_EGR)(x = 1, 8, 20) . . . . .1248
29.6.7TIMx capture/compare mode register 1 (TIMx_CCMR1)
(x = 1, 8, 20) . . . . .		1249
29.6.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8, 20) . . . . .		1251
29.6.9TIMx capture/compare mode register 2 (TIMx_CCMR2)
(x = 1, 8, 20) . . . . .		1254
29.6.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8, 20) . . . . .		1255
29.6.11TIMx capture/compare enable register (TIMx_CCER)(x = 1, 8, 20) . . . . .1258
29.6.12TIMx counter (TIMx_CNT)(x = 1, 8, 20) . . . . .1262
29.6.13TIMx prescaler (TIMx_PSC)(x = 1, 8, 20) . . . . .1262
29.6.14TIMx autoreload register (TIMx_ARR)(x = 1, 8, 20) . . . . .1263
29.6.15TIMx repetition counter register (TIMx_RCR)(x = 1, 8, 20) . . . . .1263
29.6.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 1, 8, 20) . . . . .1264
29.6.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 1, 8, 20) . . . . .1264
29.6.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 1, 8, 20) . . . . .1265
29.6.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 1, 8, 20) . . . . .1266
29.6.20TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8, 20) . . . . .1267
29.6.21TIMx capture/compare register 5 (TIMx_CCR5)(x = 1, 8, 20) . . . . .1271
29.6.22TIMx capture/compare register 6 (TIMx_CCR6)(x = 1, 8, 20) . . . . .1272
29.6.23TIMx capture/compare mode register 3 (TIMx_CCMR3)
(x = 1, 8, 20) . . . . .		1273
29.6.24TIMx timer deadtime register 2 (TIMx_DTR2)(x = 1, 8, 20) . . . . .1274
29.6.25TIMx timer encoder control register (TIMx_ECR)(x = 1, 8, 20) . . . . .1275
29.6.26TIMx timer input selection register (TIMx_TISEL)(x = 1, 8, 20) . . . . .1276
29.6.27TIMx alternate function option register 1 (TIMx_AF1)(x = 1, 8, 20) . . . . .1277
29.6.28TIMx alternate function register 2 (TIMx_AF2)(x = 1, 8, 20) . . . . .1280
29.6.29TIMx DMA control register (TIMx_DCR)(x = 1, 8, 20) . . . . .1282
29.6.30TIMx DMA address for full transfer (TIMx_DMAR)(x = 1, 8, 20) . . . . .1283
29.6.31TIMx register map . . . . .1284
30General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . .1287
30.1TIM2/TIM3/TIM4/TIM5 introduction . . . . .1287
30.2TIM2/TIM3/TIM4/TIM5 main features . . . . .1287
30.3TIM2/TIM3/TIM4/TIM5 implementation . . . . .1288
30.4TIM2/TIM3/TIM4/TIM5 functional description . . . . .1289
30.4.1Block diagram . . . . .1289
30.4.2TIM2/TIM3/TIM4/TIM5 pins and internal signals . . . . .1290
30.4.3Time-base unit . . . . .1294
30.4.4Counter modes . . . . .1296
30.4.5Clock selection . . . . .1308
30.4.6Capture/compare channels . . . . .1312
30.4.7Input capture mode . . . . .1314
30.4.8PWM input mode . . . . .1315
30.4.9Forced output mode . . . . .1316
30.4.10Output compare mode . . . . .1316
30.4.11PWM mode . . . . .1318
30.4.12Asymmetric PWM mode . . . . .1326
30.4.13Combined PWM mode . . . . .1327
30.4.14Clearing the tim_ocxref signal on an external event . . . . .1328
30.4.15One-pulse mode . . . . .1330
30.4.16Retriggerable one-pulse mode . . . . .1331
30.4.17Pulse on compare mode . . . . .1332
30.4.18Encoder interface mode . . . . .1334
30.4.19Direction bit output . . . . .1352
30.4.20UIF bit remapping . . . . .1353
30.4.21Timer input XOR function . . . . .1353
30.4.22Timers and external trigger synchronization . . . . .1353
30.4.23Timer synchronization . . . . .1357
30.4.24ADC triggers . . . . .1362
30.4.25DMA burst mode . . . . .1363
30.4.26TIM2/TIM3/TIM4/TIM5 DMA requests . . . . .1364
30.4.27Debug mode . . . . .1364
30.4.28TIM2/TIM3/TIM4/TIM5 low-power modes . . . . .1364
30.4.29TIM2/TIM3/TIM4/TIM5 interrupts . . . . .1365
30.5TIM2/TIM3/TIM4/TIM5 registers . . . . .1366
30.5.1TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . .1366
30.5.2TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . .1367
30.5.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . .1369
30.5.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . .1373
30.5.5TIMx status register (TIMx_SR)(x = 2 to 5) . . . . .1374
30.5.6TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . .1376
30.5.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) . . . . .1377
30.5.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 2 to 5) . . . . .		1379
30.5.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) . . . . .1381
30.5.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 2 to 5) . . . . .		1382
30.5.11TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 5) . . . . .1385
30.5.12TIMx counter (TIMx_CNT)(x = 3, 4) . . . . .1386
30.5.13TIMx counter (TIMx_CNT)(x = 2, 5) . . . . .1387
30.5.14TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . .1387
30.5.15TIMx autoreload register (TIMx_ARR)(x = 3, 4) . . . . .1388
30.5.16TIMx autoreload register (TIMx_ARR)(x = 2, 5) . . . . .1388
30.5.17TIMx capture/compare register 1 (TIMx_CCR1)(x = 3, 4) . . . . .1389
30.5.18TIMx capture/compare register 1 (TIMx_CCR1)(x = 2, 5) . . . . .1390
30.5.19TIMx capture/compare register 2 (TIMx_CCR2)(x = 3, 4) . . . . .1390
30.5.20TIMx capture/compare register 2 (TIMx_CCR2)(x = 2, 5) . . . . .1391
30.5.21TIMx capture/compare register 3 (TIMx_CCR3)(x = 3, 4) . . . . .1392
30.5.22TIMx capture/compare register 3 (TIMx_CCR3)(x = 2, 5) . . . . .1393
30.5.23TIMx capture/compare register 4 (TIMx_CCR4)(x = 3, 4) . . . . .1394
30.5.24TIMx capture/compare register 4 (TIMx_CCR4)(x = 2, 5) . . . . .1395
30.5.25TIMx timer encoder control register (TIMx_ECR)(x = 2 to 5) . . . . .1396
30.5.26TIMx timer input selection register (TIMx_TISEL)(x = 2 to 5) . . . . .1397
30.5.27TIMx alternate function register 1 (TIMx_AF1)(x = 2 to 5) . . . . .1398
30.5.28TIMx alternate function register 2 (TIMx_AF2)(x = 2 to 5) . . . . .1399
30.5.29TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . .1400
30.5.30TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . .1401
30.5.31TIMx register map . . . . .1401
31General purpose timers (TIM15/TIM16/TIM17) . . . . .1404
31.1TIM15/TIM16/TIM17 introduction . . . . .1404
31.2TIM15 main features . . . . .1404
31.3TIM16/TIM17 main features . . . . .1405
31.4TIM15/TIM16/TIM17 functional description . . . . .1406
31.4.1Block diagram . . . . .1406
31.4.2TIM15/TIM16/TIM17 pins and internal signals . . . . .1407
31.4.3Time-base unit . . . . .1411
31.4.4Counter modes . . . . .1413
31.4.5Repetition counter . . . . .1417
31.4.6Clock selection . . . . .1418
31.4.7Capture/compare channels . . . . .1420
31.4.8Input capture mode . . . . .1422
31.4.9PWM input mode (only for TIM15) . . . . .1424
31.4.10Forced output mode . . . . .1425
31.4.11Output compare mode . . . . .1425
31.4.12PWM mode . . . . .1427
31.4.13Combined PWM mode (TIM15 only) . . . . .1432
31.4.14Complementary outputs and dead-time insertion . . . . .1433
31.4.15Using the break function . . . . .1436
31.4.16Bidirectional break input . . . . .1440
31.4.17Clearing the tim_ocxref signal on an external event . . . . .1441
31.4.186-step PWM generation . . . . .1442
31.4.19One-pulse mode . . . . .1444
31.4.20Retriggerable one pulse mode (TIM15 only) . . . . .1445
31.4.21UIF bit remapping . . . . .1446
31.4.22Timer input XOR function (TIM15 only) . . . . .1446
31.4.23External trigger synchronization (TIM15 only) . . . . .1446
31.4.24Slave mode – combined reset + trigger mode (TIM15 only) . . . . .1449
31.4.25Slave mode – combined reset + gated mode (TIM15 only) . . . . .1449
31.4.26Timer synchronization (TIM15 only) . . . . .1450
31.4.27Using timer output as trigger for other timers (TIM16/TIM17 only) . . . . .1450
31.4.28ADC triggers (TIM15 only) . . . . .1450
31.4.29DMA burst mode . . . . .1450
31.4.30TIM15/TIM16/TIM17 DMA requests . . . . .1451
31.4.31Debug mode . . . . .1451
31.5TIM15/TIM16/TIM17 low-power modes . . . . .1452
31.6TIM15/TIM16/TIM17 interrupts . . . . .1452
31.7TIM15 registers . . . . .1453
31.7.1TIM15 control register 1 (TIM15_CR1) . . . . .1453
31.7.2TIM15 control register 2 (TIM15_CR2) . . . . .1454
31.7.3TIM15 slave mode control register (TIM15_SMCR) . . . . .1456
31.7.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .1458
31.7.5TIM15 status register (TIM15_SR) . . . . .1459
31.7.6TIM15 event generation register (TIM15_EGR) . . . . .1461
31.7.7TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .1462
31.7.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		1463
31.7.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .1466
31.7.10TIM15 counter (TIM15_CNT) . . . . .1469
31.7.11TIM15 prescaler (TIM15_PSC) . . . . .1469
31.7.12TIM15 autoreload register (TIM15_ARR) . . . . .1470
31.7.13TIM15 repetition counter register (TIM15_RCR) . . . . .1470
31.7.14TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .1471
31.7.15TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .1472
31.7.16TIM15 break and dead-time register (TIM15_BDTR) . . . . .1472
31.7.17TIM15 timer deadtime register 2 (TIM15_DTR2) . . . . .1475
31.7.18TIM15 input selection register (TIM15_TISEL) . . . . .1476
31.7.19TIM15 alternate function register 1 (TIM15_AF1) . . . . .1477
31.7.20TIM15 alternate function register 2 (TIM15_AF2) . . . . .1479
31.7.21TIM15 DMA control register (TIM15_DCR) . . . . .1480
31.7.22TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .1480
31.7.23TIM15 register map . . . . .1481
31.8TIM16/TIM17 registers . . . . .1484
31.8.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .1484
31.8.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .1485
31.8.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .1486
31.8.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .1487
31.8.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .1488
31.8.6TIMx capture/compare mode register 1 (TIMx_CCMR1)
(x = 16 to 17) . . . . .		1489
31.8.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . .		1490
31.8.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .1492
31.8.9TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .1495
31.8.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .1495
31.8.11TIMx auto-reautoreload register (TIMx_ARR)(x = 16 to 17) . . . . .1496
31.8.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .1496
31.8.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .1497
31.8.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . .1498
31.8.15TIMx timer deadtime register 2 (TIMx_DTR2)(x = 16 to 17) . . . . .1501
31.8.16TIMx input selection register (TIMx_TISEL)(x = 16 to 17) . . . . .1502
31.8.17TIMx alternate function register 1 (TIMx_AF1)(x = 16 to 17) . . . . .1502
31.8.18TIMx alternate function register 2 (TIMx_AF2)(x = 16 to 17) . . . . .1505
31.8.19TIMx option register 1 (TIMx_OR1)(x = 16 to 17) . . . . .1505
31.8.20TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .1506
31.8.21TIM16/TIM17 DMA address for full transfer
(TIMx_DMAR)(x = 16 to 17) . . . . .		1506
31.8.22TIM16/TIM17 register map . . . . .1508
32Basic timers (TIM6/TIM7) . . . . .1510
32.1TIM6/TIM7 introduction . . . . .1510
32.2TIM6/TIM7 main features . . . . .1510
32.3TIM6/TIM7 functional description . . . . .1511
32.3.1TIM6/TIM7 block diagram . . . . .1511
32.3.2TIM6/TIM7 internal signals . . . . .1511
32.3.3TIM6/TIM7 clocks . . . . .1512
32.3.4Time-base unit . . . . .1512
32.3.5Counting mode . . . . .1514
32.3.6UIF bit remapping . . . . .1522
32.3.7ADC triggers . . . . .1523
32.3.8TIM6/TIM7 DMA requests . . . . .1523
32.3.9Debug mode . . . . .1523
32.3.10TIM6/TIM7 low-power modes . . . . .1523
32.3.11TIM6/TIM7 interrupts . . . . .1523
32.4TIM6/TIM7 registers . . . . .1524
32.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . .1524
32.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . .1526
32.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . .1526
32.4.4TIMx status register (TIMx_SR)(x = 6 to 7) . . . . .1527
32.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . .1527
32.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . .1527
32.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . .1528
32.4.8TIMx autoreload register (TIMx_ARR)(x = 6 to 7) . . . . .1528
32.4.9TIMx register map . . . . .1529
33Low-power timer (LPTIM) . . . . .1530
33.1Introduction . . . . .1530
33.2LPTIM main features . . . . .1530
33.3LPTIM implementation . . . . .1531
33.4LPTIM functional description . . . . .1531
33.4.1LPTIM block diagram . . . . .1531
33.4.2LPTIM input and trigger mapping . . . . .1531
33.4.3LPTIM reset and clocks . . . . .1532
33.4.4Glitch filter . . . . .1533
33.4.5Prescaler . . . . .1534
33.4.6Trigger multiplexer . . . . .1534
33.4.7Operating mode . . . . .1535
33.4.8Timeout function . . . . .1537
33.4.9Waveform generation . . . . .1537
33.4.10Register update . . . . .1538
33.4.11Counter mode . . . . .1539
33.4.12Timer enable . . . . .1539
33.4.13Timer counter reset . . . . .1540
33.4.14Encoder mode . . . . .1540
33.4.15Debug mode . . . . .1542
33.5LPTIM low-power modes . . . . .1542
33.6LPTIM interrupts . . . . .1543
33.7LPTIM registers . . . . .1543
33.7.1LPTIM interrupt and status register (LPTIM_ISR) . . . . .1544
33.7.2LPTIM interrupt clear register (LPTIM_ICR) . . . . .1545
33.7.3LPTIM interrupt enable register (LPTIM_IER) . . . . .1545
33.7.4LPTIM configuration register (LPTIM_CFGR) . . . . .1546
33.7.5LPTIM control register (LPTIM_CR) . . . . .1549
33.7.6LPTIM compare register (LPTIM_CMP) . . . . .1551
33.7.7LPTIM autoreload register (LPTIM_ARR) . . . . .1551
33.7.8LPTIM counter register (LPTIM_CNT) . . . . .1552
33.7.9LPTIM option register (LPTIM_OR) . . . . .1552
33.7.10LPTIM register map . . . . .1554
34Infrared interface (IRTIM) . . . . .1555

35 Independent watchdog (IWDG) . . . . . 1556

35.1 Introduction . . . . . 1556

35.2 IWDG main features . . . . . 1556

35.3 IWDG functional description . . . . . 1556

35.3.1 IWDG block diagram . . . . . 1556

35.3.2 Window option . . . . . 1557

35.3.3 Hardware watchdog . . . . . 1558

35.3.4 Low-power freeze . . . . . 1558

35.3.5 Register access protection . . . . . 1558

35.3.6 Debug mode . . . . . 1558

35.4 IWDG registers . . . . . 1559

35.4.1 IWDG key register (IWDG_KR) . . . . . 1559

35.4.2 IWDG prescaler register (IWDG_PR) . . . . . 1560

35.4.3 IWDG reload register (IWDG_RLR) . . . . . 1561

35.4.4 IWDG status register (IWDG_SR) . . . . . 1562

35.4.5 IWDG window register (IWDG_WINR) . . . . . 1563

35.4.6 IWDG register map . . . . . 1564

36 System window watchdog (WWDG) . . . . . 1565

36.1 Introduction . . . . . 1565

36.2 WWDG main features . . . . . 1565

36.3 WWDG functional description . . . . . 1565

36.3.1 WWDG block diagram . . . . . 1566

36.3.2 Enabling the watchdog . . . . . 1566

36.3.3 Controlling the down-counter . . . . . 1566

36.3.4 How to program the watchdog timeout . . . . . 1566

36.3.5 Debug mode . . . . . 1568

36.4 WWDG interrupts . . . . . 1568

36.5 WWDG registers . . . . . 1568

36.5.1 WWDG control register (WWDG_CR) . . . . . 1569

36.5.2 WWDG configuration register (WWDG_CFR) . . . . . 1569

36.5.3 WWDG status register (WWDG_SR) . . . . . 1570

36.5.4 WWDG register map . . . . . 1570

37 Real-time clock (RTC) . . . . . 1571

37.1 Introduction . . . . . 1571

37.2RTC main features . . . . .1571
37.3RTC functional description . . . . .1572
37.3.1RTC block diagram . . . . .1572
37.3.2RTC pins and internal signals . . . . .1573
37.3.3GPIOs controlled by the RTC and TAMP . . . . .1574
37.3.4Clock and prescalers . . . . .1576
37.3.5Real-time clock and calendar . . . . .1577
37.3.6Programmable alarms . . . . .1578
37.3.7Periodic auto-wakeup . . . . .1578
37.3.8RTC initialization and configuration . . . . .1579
37.3.9Reading the calendar . . . . .1581
37.3.10Resetting the RTC . . . . .1582
37.3.11RTC synchronization . . . . .1582
37.3.12RTC reference clock detection . . . . .1583
37.3.13RTC smooth digital calibration . . . . .1583
37.3.14Timestamp function . . . . .1585
37.3.15Calibration clock output . . . . .1586
37.3.16Tamper and alarm output . . . . .1586
37.4RTC low-power modes . . . . .1587
37.5RTC interrupts . . . . .1588
37.6RTC registers . . . . .1588
37.6.1RTC time register (RTC_TR) . . . . .1588
37.6.2RTC date register (RTC_DR) . . . . .1589
37.6.3RTC sub second register (RTC_SSR) . . . . .1590
37.6.4RTC initialization control and status register (RTC_ICSR) . . . . .1590
37.6.5RTC prescaler register (RTC_PRER) . . . . .1592
37.6.6RTC wakeup timer register (RTC_WUTR) . . . . .1593
37.6.7RTC control register (RTC_CR) . . . . .1593
37.6.8RTC write protection register (RTC_WPR) . . . . .1596
37.6.9RTC calibration register (RTC_CALR) . . . . .1597
37.6.10RTC shift control register (RTC_SHIFTTR) . . . . .1598
37.6.11RTC timestamp time register (RTC_TSTR) . . . . .1599
37.6.12RTC timestamp date register (RTC_TSDR) . . . . .1599
37.6.13RTC timestamp sub second register (RTC_TSSSR) . . . . .1600
37.6.14RTC alarm A register (RTC_ALRMAR) . . . . .1601
37.6.15RTC alarm A sub second register (RTC_ALRMASSR) . . . . .1602
37.6.16RTC alarm B register (RTC_ALRMBR) .....1603
37.6.17RTC alarm B sub second register (RTC_ALRMBSSR) .....1604
37.6.18RTC status register (RTC_SR) .....1604
37.6.19RTC masked interrupt status register (RTC_MISR) .....1605
37.6.20RTC status clear register (RTC_SCR) .....1606
37.6.21RTC register map .....1608
38Tamper and backup registers (TAMP) .....1610
38.1Introduction .....1610
38.2TAMP main features .....1610
38.3TAMP functional description .....1611
38.3.1TAMP block diagram .....1611
38.3.2TAMP pins and internal signals .....1612
38.3.3TAMP register write protection .....1612
38.3.4Tamper detection .....1613
38.4TAMP low-power modes .....1615
38.5TAMP interrupts .....1615
38.6TAMP registers .....1615
38.6.1TAMP control register 1 (TAMP_CR1) .....1616
38.6.2TAMP control register 2 (TAMP_CR2) .....1617
38.6.3TAMP filter control register (TAMP_FLTCR) .....1618
38.6.4TAMP interrupt enable register (TAMP_IER) .....1619
38.6.5TAMP status register (TAMP_SR) .....1620
38.6.6TAMP masked interrupt status register (TAMP_MISR) .....1621
38.6.7TAMP status clear register (TAMP_SCR) .....1622
38.6.8TAMP backup x register (TAMP_BKPxR) .....1623
38.6.9TAMP register map .....1624
39Inter-integrated circuit interface (I2C) .....1625
39.1I2C introduction .....1625
39.2I2C main features .....1625
39.3I2C implementation .....1626
39.4I2C functional description .....1626
39.4.1I2C block diagram .....1627
39.4.2I2C pins and internal signals .....1627
39.4.3I2C clock requirements .....1628
39.4.4I2C mode selection . . . . .1628
39.4.5I2C initialization . . . . .1629
39.4.6I2C reset . . . . .1633
39.4.7I2C data transfer . . . . .1634
39.4.8I2C target mode . . . . .1636
39.4.9I2C controller mode . . . . .1645
39.4.10I2C_TIMINGR register configuration examples . . . . .1656
39.4.11SMBus specific features . . . . .1658
39.4.12SMBus initialization . . . . .1661
39.4.13SMBus I2C_TIMEOUTR register configuration examples . . . . .1663
39.4.14SMBus target mode . . . . .1663
39.4.15SMBus controller mode . . . . .1667
39.4.16Wake-up from Stop mode on address match . . . . .1670
39.4.17Error conditions . . . . .1671
39.5I2C in low-power modes . . . . .1673
39.6I2C interrupts . . . . .1673
39.7I2C DMA requests . . . . .1674
39.7.1Transmission using DMA . . . . .1674
39.7.2Reception using DMA . . . . .1674
39.8I2C debug modes . . . . .1674
39.9I2C registers . . . . .1675
39.9.1I2C control register 1 (I2C_CR1) . . . . .1675
39.9.2I2C control register 2 (I2C_CR2) . . . . .1677
39.9.3I2C own address 1 register (I2C_OAR1) . . . . .1679
39.9.4I2C own address 2 register (I2C_OAR2) . . . . .1680
39.9.5I2C timing register (I2C_TIMINGR) . . . . .1681
39.9.6I2C timeout register (I2C_TIMEOUTR) . . . . .1682
39.9.7I2C interrupt and status register (I2C_ISR) . . . . .1683
39.9.8I2C interrupt clear register (I2C_ICR) . . . . .1685
39.9.9I2C PEC register (I2C_PECR) . . . . .1686
39.9.10I2C receive data register (I2C_RXDR) . . . . .1686
39.9.11I2C transmit data register (I2C_TXDR) . . . . .1687
39.9.12I2C register map . . . . .1688
40Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .1689
40.1USART introduction . . . . .1689
40.8.9USART interrupt and status register (USART_ISR) .....1758
40.8.10USART interrupt and status register [alternate] (USART_ISR) .....1764
40.8.11USART interrupt flag clear register (USART_ICR) .....1769
40.8.12USART receive data register (USART_RDR) .....1771
40.8.13USART transmit data register (USART_TDR) .....1771
40.8.14USART prescaler register (USART_PRESC) .....1772
40.8.15USART register map .....1773
41Low-power universal asynchronous receiver transmitter (LPUART) .....1775
41.1LPUART introduction .....1775
41.2LPUART main features .....1776
41.3LPUART implementation .....1777
41.4LPUART functional description .....1778
41.4.1LPUART block diagram .....1778
41.4.2LPUART signals .....1779
41.4.3LPUART character description .....1780
41.4.4LPUART FIFOs and thresholds .....1781
41.4.5LPUART transmitter .....1782
41.4.6LPUART receiver .....1785
41.4.7LPUART baud rate generation .....1789
41.4.8Tolerance of the LPUART receiver to clock deviation .....1790
41.4.9LPUART multiprocessor communication .....1791
41.4.10LPUART parity control .....1793
41.4.11LPUART single-wire half-duplex communication .....1794
41.4.12Continuous communication using DMA and LPUART .....1794
41.4.13RS232 hardware flow control and RS485 Driver Enable .....1797
41.4.14LPUART low-power management .....1799
41.5LPUART in low-power modes .....1802
41.6LPUART interrupts .....1803
41.7LPUART registers .....1804
41.7.1LPUART control register 1 (LPUART_CR1) .....1804
41.7.2LPUART control register 1 [alternate] (LPUART_CR1) .....1807
41.7.3LPUART control register 2 (LPUART_CR2) .....1810
41.7.4LPUART control register 3 (LPUART_CR3) .....1812
41.7.5LPUART baud rate register (LPUART_BRR) .....1815
41.7.6LPUART request register (LPUART_RQR) . . . . .1815
41.7.7LPUART interrupt and status register (LPUART_ISR) . . . . .1816
41.7.8LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .1820
41.7.9LPUART interrupt flag clear register (LPUART_ICR) . . . . .1823
41.7.10LPUART receive data register (LPUART_RDR) . . . . .1824
41.7.11LPUART transmit data register (LPUART_TDR) . . . . .1824
41.7.12LPUART prescaler register (LPUART_PRESC) . . . . .1825
41.7.13LPUART register map . . . . .1826
42Serial peripheral interface / integrated interchip sound (SPI/I2S) . . . . .1828
42.1Introduction . . . . .1828
42.2SPI main features . . . . .1828
42.3I2S main features . . . . .1829
42.4SPI/I2S implementation . . . . .1829
42.5SPI functional description . . . . .1830
42.5.1General description . . . . .1830
42.5.2Communications between one master and one slave . . . . .1831
42.5.3Standard multislave communication . . . . .1833
42.5.4Multimaster communication . . . . .1834
42.5.5Slave select (NSS) pin management . . . . .1835
42.5.6Communication formats . . . . .1836
42.5.7Configuration of SPI . . . . .1838
42.5.8Procedure for enabling SPI . . . . .1839
42.5.9Data transmission and reception procedures . . . . .1839
42.5.10SPI status flags . . . . .1849
42.5.11SPI error flags . . . . .1850
42.5.12NSS pulse mode . . . . .1851
42.5.13TI mode . . . . .1851
42.5.14CRC calculation . . . . .1852
42.6SPI interrupts . . . . .1854
42.7I2S functional description . . . . .1855
42.7.1I2S general description . . . . .1855
42.7.2Supported audio protocols . . . . .1856
42.7.3Start-up description . . . . .1863
42.7.4Clock generator . . . . .1865
42.7.5I 2 S master mode . . . . .1868
42.7.6I 2 S slave mode .....1869
42.7.7I 2 S status flags .....1871
42.7.8I 2 S error flags .....1872
42.7.9DMA features .....1873
42.8I 2 S interrupts .....1873
42.9SPI and I 2 S registers .....1874
42.9.1SPI control register 1 (SPIx_CR1) .....1874
42.9.2SPI control register 2 (SPIx_CR2) .....1876
42.9.3SPI status register (SPIx_SR) .....1878
42.9.4SPI data register (SPIx_DR) .....1880
42.9.5SPI CRC polynomial register (SPIx_CRCPR) .....1880
42.9.6SPI Rx CRC register (SPIx_RXCRCR) .....1880
42.9.7SPI Tx CRC register (SPIx_TXCRCR) .....1881
42.9.8SPIx_I 2 S configuration register (SPIx_I 2 SCFGR) .....1881
42.9.9SPIx_I 2 S prescaler register (SPIx_I 2 SPR) .....1883
42.9.10SPI/I 2 S register map .....1885
43Serial audio interface (SAI) .....1886
43.1Introduction .....1886
43.2SAI main features .....1886
43.3SAI implementation .....1887
43.4SAI functional description .....1888
43.4.1SAI block diagram .....1888
43.4.2SAI pins and internal signals .....1889
43.4.3Main SAI modes .....1889
43.4.4SAI synchronization mode .....1890
43.4.5Audio data size .....1891
43.4.6Frame synchronization .....1891
43.4.7Slot configuration .....1894
43.4.8SAI clock generator .....1896
43.4.9Internal FIFOs .....1899
43.4.10PDM interface .....1901
43.4.11AC'97 link controller .....1909
43.4.12SPDIF output .....1910
43.4.13Specific features .....1913
43.4.14Error flags .....1917
44.3.10FDCAN Tx event FIFO element . . . . .1980
44.3.11FDCAN standard message ID filter element . . . . .1981
44.3.12FDCAN extended message ID filter element . . . . .1982
44.4FDCAN registers . . . . .1984
44.4.1FDCAN core release register (FDCAN_CREL) . . . . .1984
44.4.2FDCAN endian register (FDCAN_ENDN) . . . . .1984
44.4.3FDCAN data bit timing and prescaler register (FDCAN_DBTP) . . . . .1984
44.4.4FDCAN test register (FDCAN_TEST) . . . . .1985
44.4.5FDCAN RAM watchdog register (FDCAN_RWD) . . . . .1986
44.4.6FDCAN CC control register (FDCAN_CCCR) . . . . .1987
44.4.7FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . . . . .1988
44.4.8FDCAN timestamp counter configuration register (FDCAN_TSCC) . . . . .1990
44.4.9FDCAN timestamp counter value register (FDCAN_TSCV) . . . . .1990
44.4.10FDCAN timeout counter configuration register (FDCAN_TOCC) . . . . .1991
44.4.11FDCAN timeout counter value register (FDCAN_TOCV) . . . . .1992
44.4.12FDCAN error counter register (FDCAN_ECR) . . . . .1992
44.4.13FDCAN protocol status register (FDCAN_PSR) . . . . .1993
44.4.14FDCAN transmitter delay compensation register (FDCAN_TDCR) . . . . .1995
44.4.15FDCAN interrupt register (FDCAN_IR) . . . . .1995
44.4.16FDCAN interrupt enable register (FDCAN_IE) . . . . .1998
44.4.17FDCAN interrupt line select register (FDCAN_ILS) . . . . .2000
44.4.18FDCAN interrupt line enable register (FDCAN_ILE) . . . . .2001
44.4.19FDCAN global filter configuration register (FDCAN_RXGFC) . . . . .2001
44.4.20FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . .2003
44.4.21FDCAN high-priority message status register (FDCAN_HPMS) . . . . .2003
44.4.22FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . .2004
44.4.23CAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . .2005
44.4.24FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . .2005
44.4.25FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . .2006
44.4.26FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . .2006
44.4.27FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . .2007
44.4.28FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . .2007
44.4.29FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . .2008
44.4.30FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . . . . .2009
44.4.31FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) . . . . .2009
44.4.32FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . . . . .2010
46.4.7UCPD Type-C voltage monitoring and de-bouncing . . . . .2064
46.4.8UCPD fast role swap (FRS) . . . . .2064
46.4.9UCPD DMA Interface . . . . .2064
46.4.10Wake-up from Stop mode . . . . .2064
46.5UCPD programming sequences . . . . .2065
46.5.1Initialization phase . . . . .2065
46.5.2Type-C state machine handling . . . . .2065
46.5.3USB PD transmit . . . . .2067
46.5.4USB PD receive . . . . .2068
46.6UCPD low-power modes . . . . .2069
46.7UCPD interrupts . . . . .2070
46.8UCPD registers . . . . .2071
46.8.1UCPD configuration register 1 (UCPD_CFGR1) . . . . .2071
46.8.2UCPD configuration register 2 (UCPD_CFGR2) . . . . .2073
46.8.3UCPD control register (UCPD_CR) . . . . .2073
46.8.4UCPD interrupt mask register (UCPD_IMR) . . . . .2076
46.8.5UCPD status register (UCPD_SR) . . . . .2077
46.8.6UCPD interrupt clear register (UCPD_ICR) . . . . .2080
46.8.7UCPD Tx ordered set type register (UCPD_TX_ORDSETR) . . . . .2081
46.8.8UCPD Tx payload size register (UCPD_TX_PAYSZR) . . . . .2081
46.8.9UCPD Tx data register (UCPD_TXDR) . . . . .2082
46.8.10UCPD Rx ordered set register (UCPD_RX_ORDSETR) . . . . .2082
46.8.11UCPD Rx payload size register (UCPD_RX_PAYSZR) . . . . .2083
46.8.12UCPD receive data register (UCPD_RXDR) . . . . .2084
46.8.13UCPD Rx ordered set extension register 1
(UCPD_RX_ORDEXTR1) . . . . .		2084
46.8.14UCPD Rx ordered set extension register 2
(UCPD_RX_ORDEXTR2) . . . . .		2085
46.8.15UCPD register map . . . . .2085
47Debug support (DBG) . . . . .2088
47.1Overview . . . . .2088
47.2Reference Arm® documentation . . . . .2089
47.3SWJ debug port (serial wire and JTAG) . . . . .2089
47.3.1Mechanism to select the JTAG-DP or the SW-DP . . . . .2090
47.4Pinout and debug port pins . . . . .2090
47.4.1SWJ debug port pins . . . . .2091
47.4.2Flexible SWJ-DP pin assignment . . . . .2091
47.4.3Internal pull-up and pull-down on JTAG pins . . . . .2092
47.4.4Using serial wire and releasing the unused debug pins as GPIOs . . . . .2093
47.5STM32G4 series JTAG TAP connection . . . . .2093
47.6ID codes and locking mechanism . . . . .2094
47.6.1MCU device ID code . . . . .2095
47.6.2Boundary scan TAP . . . . .2095
47.6.3Cortex ® -M4 with FPU TAP . . . . .2095
47.6.4Cortex ® -M4 with FPU JEDEC-106 ID code . . . . .2096
47.7JTAG debug port . . . . .2096
47.8SW debug port . . . . .2098
47.8.1SW protocol introduction . . . . .2098
47.8.2SW protocol sequence . . . . .2098
47.8.3SW-DP state machine (reset, idle states, ID code) . . . . .2099
47.8.4DP and AP read/write accesses . . . . .2099
47.8.5SW-DP registers . . . . .2100
47.8.6SW-AP registers . . . . .2101
47.9AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP . . . . .		2101
47.10Core debug . . . . .2102
47.11Capability of the debugger host to connect under system reset . . . . .2102
47.12FPB (Flash patch breakpoint) . . . . .2103
47.13DWT (data watchpoint trigger) . . . . .2103
47.14ITM (instrumentation trace macrocell) . . . . .2104
47.14.1General description . . . . .2104
47.14.2Time stamp packets, synchronization and overflow packets . . . . .2104
47.15ETM (Embedded Trace Macrocell ™ ) . . . . .2106
47.15.1General description . . . . .2106
47.15.2Signal protocol, packet types . . . . .2106
47.15.3Main ETM registers . . . . .2106
47.15.4Configuration example . . . . .2107
47.16MCU debug component (DBGMCU) . . . . .2107
47.16.1Debug support for low-power modes . . . . .2107
47.16.2Debug support for timers, RTC, watchdog and I 2 C . . . . .2108
47.16.3Debug MCU configuration register (DBGMCU_CR) . . . . .2108
47.16.4Debug MCU APB1 freeze register1 (DBGMCU_APB1FZR1) . . . . .2109
47.16.5Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2) . . . . .2111
47.16.6Debug MCU APB2 freeze register (DBGMCU_APB2FZR) . . . . .2111
47.17TPIU (trace port interface unit) . . . . .2113
47.17.1Introduction . . . . .2113
47.17.2TRACE pin assignment . . . . .2113
47.17.3TPUI formatter . . . . .2115
47.17.4TPUI frame synchronization packets . . . . .2116
47.17.5Transmission of the synchronization frame packet . . . . .2116
47.17.6Synchronous mode . . . . .2116
47.17.7Asynchronous mode . . . . .2117
47.17.8TRACECLKIN connection inside the
STM32G4 series . . . . .		2117
47.17.9TPIU registers . . . . .2118
47.17.10Example of configuration . . . . .2119
47.18DBG register map . . . . .2120
48Device electronic signature . . . . .2121
48.1Unique device ID register (96 bits) . . . . .2121
48.2Flash size data register . . . . .2122
48.3Package data register . . . . .2122
49Important security notice . . . . .2124
50Revision history . . . . .2125

List of tables

Table 1.STM32G4 series memory density . . . . .75
Table 2.Product specific features . . . . .76
Table 3.Memory map and peripheral register boundary addresses . . . . .84
Table 4.CCM SRAM organization . . . . .89
Table 5.Boot modes . . . . .91
Table 6.Memory mapping versus boot mode/physical remap . . . . .93
Table 7.Flash module - 512/256/128 KB dual bank organization (64 bits read width). . . . .96
Table 8.Flash module - 512/256/128 KB single bank organization (128 bits read width) . . . . .96
Table 9.Number of wait states according to CPU clock (HCLK) frequency. . . . .98
Table 10.Option byte format . . . . .110
Table 11.Option byte organization. . . . .110
Table 12.Flash memory read protection status . . . . .121
Table 13.Access status versus protection level and execution modes . . . . .123
Table 14.PCROP protection . . . . .125
Table 15.WRP protection. . . . .127
Table 16.Flash interrupt request . . . . .129
Table 17.Flash interface - register map and reset values . . . . .147
Table 18.Flash module - 256/512 Kbytes organization (64 bits read width) . . . . .150
Table 19.Number of wait states according to CPU clock (HCLK) frequency. . . . .151
Table 20.Option byte format . . . . .161
Table 21.Option byte organization. . . . .161
Table 22.Flash memory read protection status . . . . .167
Table 23.Access status versus protection level and execution modes . . . . .169
Table 24.PCROP protection . . . . .171
Table 25.WRP protection. . . . .172
Table 26.Flash interrupt request . . . . .173
Table 27.Flash interface - register map and reset values . . . . .186
Table 28.Flash module - 32/64/128 Kbytes organization (64-bit read width). . . . .189
Table 29.Number of wait states according to CPU clock (HCLK) frequency. . . . .190
Table 30.Option byte format . . . . .200
Table 31.Option byte organization. . . . .200
Table 32.Flash memory read protection status . . . . .206
Table 33.Access status versus protection level and execution modes . . . . .208
Table 34.PCROP protection . . . . .210
Table 35.WRP protection. . . . .211
Table 36.Flash interrupt request . . . . .213
Table 37.Flash interface - Register map and reset values . . . . .226
Table 38.Range 1 boost mode configuration. . . . .232
Table 39.PVM features . . . . .235
Table 40.Low-power mode summary . . . . .238
Table 41.Functionalities depending on the working mode. . . . .239
Table 42.Low-power run . . . . .242
Table 43.Sleep. . . . .244
Table 44.Low-power sleep. . . . .245
Table 45.Stop 0 mode . . . . .247
Table 46.Stop 1 mode . . . . .248
Table 47.Standby mode. . . . .250
Table 48.Shutdown mode . . . . .252
Table 49.PWR register map . . . . .268
Table 50.Clock source frequency . . . . .280
Table 51.RCC register map and reset values . . . . .330
Table 52.CRS features . . . . .334
Table 53.CRS internal input/output signals . . . . .335
Table 54.CRS interconnection . . . . .336
Table 55.Effect of low-power modes on CRS . . . . .339
Table 56.Interrupt control bits . . . . .339
Table 57.CRS register map and reset values . . . . .344
Table 58.Port bit configuration table . . . . .347
Table 59.GPIO register map and reset values . . . . .362
Table 60.BOOSTEN and ANASWVDD set/reset . . . . .367
Table 61.SYSCFG register map and reset values . . . . .375
Table 62.STM32G4 series peripherals interconnect matrix . . . . .377
Table 63.Interconnect 1 . . . . .379
Table 64.Interconnect 12 . . . . .380
Table 65.Interconnect 13 . . . . .380
Table 66.Interconnect 14 . . . . .380
Table 67.Interconnect 19 . . . . .381
Table 68.Interconnect 20 . . . . .383
Table 69.Interconnect 17 . . . . .385
Table 70.Interconnect 15 . . . . .386
Table 71.Interconnect 21 . . . . .386
Table 72.Interconnect 22 . . . . .387
Table 73.Interconnect 23 . . . . .388
Table 74.Interconnect 24 . . . . .389
Table 75.Interconnect 2 . . . . .390
Table 76.Interconnect 3 . . . . .391
Table 77.Interconnect 4 . . . . .392
Table 78.Interconnect 5 . . . . .393
Table 79.Interconnect 6 . . . . .393
Table 80.Interconnect 7 . . . . .393
Table 81.Interconnect 8 . . . . .394
Table 82.Interconnect 9 . . . . .394
Table 83.Interconnect 10 . . . . .395
Table 84.Interconnect 11 . . . . .395
Table 85.Interconnect 18 . . . . .396
Table 86.Interconnect 16 . . . . .396
Table 87.DMA1 and DMA2 implementation . . . . .398
Table 88.DMA internal input/output signals . . . . .400
Table 89.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .405
Table 90.DMA interrupt requests . . . . .407
Table 91.DMA register map and reset values . . . . .415
Table 92.DMAMUX instantiation . . . . .419
Table 93.DMAMUX: assignment of multiplexer inputs to resources . . . . .420
Table 95.DMAMUX: assignment of synchronization inputs to resources . . . . .421
Table 94.DMAMUX: assignment of trigger inputs to resources . . . . .421
Table 96.DMAMUX signals . . . . .424
Table 97.DMAMUX interrupts . . . . .428
Table 98.DMAMUX register map and reset values for category 2 devices . . . . .433
Table 99.DMAMUX register map and reset values for category 3 and 4 devices . . . . .434
Table 100.STM32G4 series vector table . . . . .437
Table 101.EXTI lines connections . . . . .444
Table 102.Extended interrupt/event controller register map and reset values. . . . .453
Table 103.CRC internal input/output signals . . . . .455
Table 104.CRC register map and reset values . . . . .460
Table 105.CORDIC functions . . . . .462
Table 106.Cosine parameters . . . . .462
Table 107.Sine parameters . . . . .463
Table 108.Phase parameters . . . . .463
Table 109.Modulus parameters . . . . .464
Table 110.Arctangent parameters . . . . .465
Table 111.Hyperbolic cosine parameters . . . . .465
Table 112.Hyperbolic sine parameters . . . . .466
Table 113.Hyperbolic arctangent parameters . . . . .466
Table 114.Natural logarithm parameters . . . . .467
Table 115.Natural log scaling factors and corresponding ranges . . . . .467
Table 116.Square root parameters . . . . .468
Table 117.Square root scaling factors and corresponding ranges . . . . .468
Table 118.Precision vs. number of iterations. . . . .471
Table 119.CORDIC register map and reset value . . . . .478
Table 120.Valid combinations for read and write methods . . . . .492
Table 121.FMAC register map and reset values . . . . .505
Table 122.NOR/PSRAM bank selection . . . . .510
Table 123.NOR/PSRAM External memory address . . . . .511
Table 124.NAND memory mapping and timing registers. . . . .511
Table 125.NAND bank selection . . . . .511
Table 126.Programmable NOR/PSRAM access parameters . . . . .513
Table 127.Non-multiplexed I/O NOR flash memory. . . . .513
Table 128.16-bit multiplexed I/O NOR flash memory . . . . .514
Table 129.Non-multiplexed I/Os PSRAM/SRAM . . . . .514
Table 130.16-Bit multiplexed I/O PSRAM . . . . .515
Table 131.NOR flash/PSRAM: example of supported memories
and transactions . . . . .		516
Table 132.FMC_BCRx bitfields (mode 1) . . . . .519
Table 133.FMC_BTRx bitfields (mode 1) . . . . .519
Table 134.FMC_BCRx bitfields (mode A) . . . . .521
Table 135.FMC_BTRx bitfields (mode A) . . . . .521
Table 136.FMC_BWTRx bitfields (mode A). . . . .522
Table 137.FMC_BCRx bitfields (mode 2/B). . . . .524
Table 138.FMC_BTRx bitfields (mode 2/B). . . . .524
Table 139.FMC_BWTRx bitfields (mode 2/B) . . . . .525
Table 140.FMC_BCRx bitfields (mode C) . . . . .526
Table 141.FMC_BTRx bitfields (mode C) . . . . .527
Table 142.FMC_BWTRx bitfields (mode C). . . . .527
Table 143.FMC_BCRx bitfields (mode D) . . . . .529
Table 144.FMC_BTRx bitfields (mode D) . . . . .530
Table 145.FMC_BWTRx bitfields (mode D). . . . .530
Table 146.FMC_BCRx bitfields (Muxed mode) . . . . .532
Table 147.FMC_BTRx bitfields (Muxed mode) . . . . .533
Table 148.FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .538
Table 149.FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .539
Table 150.FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .540
Table 151.FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .541
Table 152.Programmable NAND flash access parameters . . . . .550
Table 153.8-bit NAND flash . . . . .550
Table 154.16-bit NAND flash . . . . .551
Table 155.Supported memories and transactions . . . . .551
Table 156.ECC result relevant bits . . . . .560
Table 157.FMC register map and reset values . . . . .561
Table 158.QUADSPI pins . . . . .564
Table 159.QUADSPI interrupt requests. . . . .578
Table 160.QUADSPI register map and reset values . . . . .589
Table 161.ADC features . . . . .593
Table 162.ADC internal input/output signals . . . . .595
Table 163.ADC input/output pins. . . . .595
Table 164.Configuring the trigger polarity for regular external triggers . . . . .616
Table 165.Configuring the trigger polarity for injected external triggers . . . . .616
Table 166.ADC1/2 - External triggers for regular channels . . . . .617
Table 167.ADC1/2 - External trigger for injected channels . . . . .618
Table 168.ADC3/4/5 - External triggers for regular channels . . . . .619
Table 169.ADC3/4/5 - External triggers for injected channels . . . . .620
Table 170.TSAR timings depending on resolution . . . . .633
Table 171.Offset computation versus data resolution . . . . .636
Table 172.Analog watchdog channel selection . . . . .647
Table 173.Analog watchdog 1 comparison . . . . .648
Table 174.Analog watchdog 2 and 3 comparison . . . . .649
Table 175.Maximum output results versus N and M (gray cells indicate truncation). . . . .652
Table 176.Oversampler operating modes summary . . . . .657
Table 177.Effect of low-power modes on the ADC . . . . .675
Table 178.ADC interrupts per each ADC. . . . .676
Table 179.DELAY bits versus ADC resolution. . . . .708
Table 180.ADC global register map. . . . .710
Table 181.ADC register map and reset values for each ADC (offset = 0x000
for master ADC, 0x100 for slave ADC). . . . .		711
Table 182.ADC register map and reset values (master and slave ADC
common registers) offset = 0x300 . . . . .		713
Table 183.DAC features . . . . .715
Table 184.DAC input/output pins. . . . .717
Table 185.DAC input/output signals . . . . .717
Table 186.DAC1 interconnection. . . . .718
Table 187.DAC2 interconnection. . . . .719
Table 188.DAC3 interconnection. . . . .720
Table 189.DAC4 interconnection. . . . .721
Table 190.Data format (case of 12-bit data) . . . . .724
Table 191.HFSEL description . . . . .725
Table 192.Sample and refresh timings . . . . .732
Table 193.Channel output modes summary . . . . .734
Table 194.Effect of low-power modes on DAC . . . . .742
Table 195.DAC interrupts . . . . .742
Table 196.DAC register map and reset values . . . . .761
Table 197.VREF buffer modes . . . . .764
Table 198.VREFBUF register map and reset values. . . . .767
Table 199.COMPx non-inverting input assignment . . . . .769
Table 200.COMPx inverting input assignment . . . . .769
Table 201.Blanking sources . . . . .771
Table 202.Comparator behavior in low-power modes . . . . .771
Table 203.COMP register map and reset values . . . . .774
Table 204.Operational amplifier possible connection . . . . .777
Table 205.Operating modes and calibration . . . . .785
Table 206.Effect of low-power modes on the OPAMP . . . . .787
Table 207.OPAMP register map and reset values . . . . .818
Table 208.RNG internal input/output signals . . . . .821
Table 209.RNG interrupt requests . . . . .827
Table 210.RNG configurations . . . . .828
Table 211.RNG register map and reset map . . . . .831
Table 212.AES internal input/output signals . . . . .833
Table 213.CTR mode initialization vector definition . . . . .850
Table 214.GCM last block definition . . . . .852
Table 215.Initialization of AES_IVRx registers in GCM mode . . . . .853
Table 216.Initialization of AES_IVRx registers in CCM mode . . . . .860
Table 217.Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .865
Table 218.AES interrupt requests . . . . .868
Table 219.Processing latency for ECB, CBC and CTR . . . . .868
Table 220.Processing latency for GCM and CCM (in clock cycles) . . . . .869
Table 221.AES register map and reset values . . . . .879
Table 222.HRTIM inputs/outputs summary . . . . .885
Table 223.External events mapping and associated features . . . . .887
Table 224.Update enable inputs and sources . . . . .887
Table 225.Burst mode clock sources . . . . .887
Table 226.Burst mode trigger source . . . . .888
Table 227.Internal synchronization source . . . . .888
Table 228.Fault inputs . . . . .888
Table 229.HRTIM DAC triggers connections . . . . .888
Table 230.System fault connected to hrtim_sys_fltr input . . . . .889
Table 231.Timer resolution and min. PWM frequency for \( f_{HRTIM} = 170 \) MHz . . . . .889
Table 232.Period and compare registers min and max values . . . . .893
Table 233.Timer operating modes . . . . .893
Table 234.Events mapping across timer A to F . . . . .899
Table 235.Interleaved mode selection . . . . .900
Table 236.Compare 1..3 values in interleaved mode . . . . .901
Table 237.Deadtime resolution and max absolute values . . . . .912
Table 238.Roll-over event destination and mode programming . . . . .919
Table 239.EExFLTR[3:0] codes depending on UDM bit setting . . . . .921
Table 240.External events features . . . . .927
Table 241.Output set/reset latency and jitter versus external event operating mode . . . . .928
Table 242.Filtering signals mapping per timer . . . . .931
Table 243.Windowing signals mapping per timer (EEFLTR[3:0] = 1111) . . . . .933
Table 244.HRTIM preloadable control registers and associated update sources . . . . .943
Table 245.Master timer update event propagation . . . . .948
Table 246.TIMx update event propagation . . . . .948
Table 247.Reset events able to generate an update . . . . .950
Table 248.Update event propagation for a timer reset . . . . .950
Table 249.Output state programming, x= A..F, y = 1 or 2 . . . . .952
Table 250.Timer output programming for burst mode . . . . .955
Table 251.Sampling rate and filter length vs FLTFxF[3:0] and clock setting . . . . .965
Table 252.Fault input blanking events . . . . .966
Table 253.Fault 1..6 counter reset source . . . . .967
Table 254.Effect of sync event versus timer operating modes . . . . .971
Table 255.DAC dual channel trigger example . . . . .979
Table 256.HRTIM interrupt summary . . . . .982
Table 257.HRTIM DMA request summary . . . . .984
Table 258.HRTIM Register map and reset values – master timer. . . . .1134
Table 259.HRTIM register map and reset values – TIMx (x= A..F) . . . . .1135
Table 260.HRTIM register map and reset values – common functions . . . . .1140
Table 261.TIM input/output pins . . . . .1146
Table 262.TIM internal input/output signals . . . . .1146
Table 263.Interconnect to the tim_ti1 input multiplexer . . . . .1147
Table 264.Interconnect to the tim_ti2 input multiplexer . . . . .1148
Table 265.Interconnect to the tim_ti3 input multiplexer . . . . .1148
Table 266.Interconnect to the tim_ti4 input multiplexer . . . . .1148
Table 267.Internal trigger connection . . . . .1148
Table 268.Interconnect to the tim_etr input multiplexer . . . . .1149
Table 269.Timer break interconnect . . . . .1149
Table 270.Timer break2 interconnect . . . . .1150
Table 271.System break interconnect . . . . .1150
Table 272.Interconnect to the ocref_clr input multiplexer . . . . .1150
Table 273.CCR and ARR register change dithering pattern . . . . .1184
Table 274.CCR register change dithering pattern in center-aligned PWM mode . . . . .1185
Table 275.Behavior of timer outputs versus tim_brk/tim_brk2 inputs . . . . .1197
Table 276.Break protection disarming conditions . . . . .1199
Table 277.Counting direction versus encoder signals (CC1P = CC2P = 0) . . . . .1208
Table 278.Counting direction versus encoder signals and polarity settings . . . . .1212
Table 279.DMA request . . . . .1233
Table 280.Effect of low-power modes on TIM1/TIM8/TIM20 . . . . .1234
Table 281.Interrupt requests . . . . .1234
Table 282.Output control bits for complementary tim_ocx and tim_ocxn channels
with break feature . . . . .		1261
Table 283.TIMx register map and reset values . . . . .1284
Table 284.STM32G4 series general purpose timers . . . . .1288
Table 285.TIM input/output pins . . . . .1290
Table 286.TIM internal input/output signals . . . . .1290
Table 287.Interconnect to the tim_ti1 input multiplexer . . . . .1291
Table 288.Interconnect to the tim_ti2 input multiplexer . . . . .1291
Table 289.Interconnect to the tim_ti3 input multiplexer . . . . .1292
Table 290.Interconnect to the tim_ti4 input multiplexer . . . . .1292
Table 291.TIMx internal trigger connection . . . . .1292
Table 292.Interconnect to the tim_etr input multiplexer . . . . .1293
Table 293.Interconnect to the tim_ocref_clr input multiplexer . . . . .1294
Table 294.CCR and ARR register change dithering pattern . . . . .1325
Table 295.CCR register change dithering pattern in center-aligned PWM mode . . . . .1326
Table 296.Counting direction versus encoder signals(CC1P = CC2P = 0) . . . . .1335
Table 297.Counting direction versus encoder signals and polarity settings . . . . .1340
Table 298.DMA request . . . . .1364
Table 299.Effect of low-power modes on TIM2/TIM3/TIM4/TIM5 . . . . .1364
Table 300.Interrupt requests . . . . .1365
Table 301.Output control bit for standard tim_ocx channels . . . . .1386
Table 302.TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . .1401
Table 303.TIM input/output pins . . . . .1407
Table 304.TIM internal input/output signals . . . . .1408
Table 305.Interconnect to the tim_ti1 input multiplexer . . . . .1408
Table 306.Interconnect to the tim_ti2 input multiplexer . . . . .1409
Table 307.TIMx internal trigger connection . . . . .1409
Table 308.Timer break interconnect . . . . .1410
Table 309.System break interconnect . . . . .1410
Table 310.Interconnect to the ocref_clr input multiplexer . . . . .1410
Table 311.CCR and ARR register change dithering pattern . . . . .1431
Table 312.Break protection disarming conditions . . . . .1440
Table 313.DMA request . . . . .1451
Table 314.Effect of low-power modes on TIM15/TIM16/TIM17 . . . . .1452
Table 315.Interrupt requests . . . . .1452
Table 316.Output control bits for complementary tim_ocx and tim_ocxn channels with break feature (TIM15). . . . .1468
Table 317.TIM15 register map and reset values . . . . .1481
Table 318.Output control bits for complementary tim_oc1 and tim_oc1n channels with break feature (TIM16/TIM17) . . . . .1494
Table 319.TIM16/TIM17 register map and reset values . . . . .1508
Table 320.TIM internal input/output signals . . . . .1511
Table 321.TIMx_ARR register change dithering pattern . . . . .1521
Table 322.DMA request . . . . .1523
Table 323.Effect of low-power modes on TIM6/TIM7 . . . . .1523
Table 324.Interrupt request . . . . .1523
Table 325.TIMx register map and reset values . . . . .1529
Table 326.STM32G4 series LPTIM features . . . . .1531
Table 327.LPTIM1 external trigger connection . . . . .1531
Table 328.LPTIM1 input 1 connection . . . . .1532
Table 329.LPTIM1 input 2 connection . . . . .1532
Table 330.Prescaler division ratios . . . . .1534
Table 331.Encoder counting scenarios . . . . .1541
Table 332.Effect of low-power modes on the LPTIM . . . . .1542
Table 333.Interrupt events . . . . .1543
Table 334.LPTIM register map and reset values . . . . .1554
Table 335.IWDG register map and reset values . . . . .1564
Table 336.WWDG register map and reset values . . . . .1570
Table 337.RTC input/output pins . . . . .1573
Table 338.RTC internal input/output signals . . . . .1573
Table 339.RTC interconnection . . . . .1574
Table 340.PC13 configuration . . . . .1574
Table 341.RTC_OUT mapping . . . . .1576
Table 342.Effect of low-power modes on RTC . . . . .1587
Table 343.RTC pins functionality over modes . . . . .1587
Table 344.Interrupt requests . . . . .1588
Table 345.RTC register map and reset values . . . . .1608
Table 346.TAMP input/output pins . . . . .1612
Table 347.TAMP internal input/output signals . . . . .1612
Table 348.TAMP interconnection . . . . .1612
Table 349.Effect of low-power modes on TAMP . . . . .1615
Table 350.Interrupt requests . . . . .1615
Table 351.TAMP register map and reset values . . . . .1624
Table 352.I2C implementation . . . . .1626
Table 353.I2C input/output pins . . . . .1627
Table 354.I2C internal input/output signals . . . . .1628
Table 355.Comparison of analog and digital filters . . . . .1630
Table 356.I 2 C-bus and SMBus specification data setup and hold times . . . . .1632
Table 357.I 2 C configuration. . . . .1636
Table 358.I 2 C-bus and SMBus specification clock timings . . . . .1647
Table 359.Timing settings for f I2CCLK of 8 MHz. . . . .1657
Table 360.Timing settings for f I2CCLK of 16 MHz. . . . .1657
Table 361.Timing settings for f I2CCLK of 48 MHz. . . . .1658
Table 362.SMBus timeout specifications . . . . .1660
Table 363.SMBus with PEC configuration . . . . .1662
Table 364.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms. . . . .1663
Table 365.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .1663
Table 366.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .1663
Table 367.Effect of low-power modes to I 2 C. . . . .1673
Table 368.I 2 C interrupt requests . . . . .1673
Table 369.I 2 C register map and reset values . . . . .1688
Table 370.USART / LPUART features . . . . .1691
Table 371.USART/UART input/output pins . . . . .1694
Table 372.USART internal input/output signals . . . . .1694
Table 373.Noise detection from sampled data . . . . .1706
Table 374.Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .1709
Table 375.Tolerance of the USART receiver when BRR[3:0] is different from 0000. . . . .1710
Table 376.USART frame formats . . . . .1715
Table 377.Effect of low-power modes on the USART . . . . .1738
Table 378.USART interrupt requests. . . . .1739
Table 379.USART register map and reset values . . . . .1773
Table 380.USART / LPUART features . . . . .1777
Table 381.LPUART input/output pins . . . . .1779
Table 382.LPUART internal input/output signals . . . . .1779
Table 383.Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz . . . . .1789
Table 384.Error calculation for programmed baud rates at f CK = 100 MHz . . . . .1790
Table 385.Tolerance of the LPUART receiver. . . . .1791
Table 387.Effect of low-power modes on the LPUART . . . . .1802
Table 388.LPUART interrupt requests. . . . .1803
Table 389.LPUART register map and reset values . . . . .1826
Table 390.STM32G4 series SPI and SPI/I2S implementation . . . . .1829
Table 391.SPI interrupt requests . . . . .1854
Table 392.Audio-frequency precision using 48 MHz clock derived from HSE. . . . .1867
Table 393.I2S interrupt requests . . . . .1873
Table 394.SPI/I2S register map and reset values . . . . .1885
Table 395.STM32G4 series SAI features . . . . .1887
Table 396.SAI internal input/output signals . . . . .1889
Table 397.SAI input/output pins. . . . .1889
Table 398.MCLK_x activation conditions. . . . .1896
Table 399.Clock generator programming examples . . . . .1899
Table 400.SAI_A configuration for TDM mode . . . . .1906
Table 401.TDM frame configuration examples . . . . .1908
Table 402.SOPD pattern . . . . .1911
Table 403.Parity bit calculation . . . . .1911
Table 404.Audio sampling frequency versus symbol rates . . . . .1912
Table 405.SAI interrupt sources . . . . .1921
Table 406.SAI register map and reset values . . . . .1949
Table 407.CAN subsystem I/O signals . . . . .1955
Table 408.CAN subsystem I/O pins. . . . .1955
Table 409.DLC coding in FDCAN . . . . .1959
Table 410.Possible configurations for frame transmission . . . . .1973
Table 411.Rx FIFO element . . . . .1976
Table 412.Rx FIFO element description . . . . .1976
Table 413.Tx buffer and FIFO element . . . . .1978
Table 414.Tx buffer element description . . . . .1978
Table 415.Tx event FIFO element. . . . .1980
Table 416.Tx event FIFO element description. . . . .1980
Table 417.Standard message ID filter element . . . . .1981
Table 418.Standard message ID filter element field description . . . . .1982
Table 419.Extended message ID filter element. . . . .1982
Table 420.Extended message ID filter element field description. . . . .1983
Table 421.FDCAN register map and reset values . . . . .2013
Table 422.STM32G4 series USB implementation . . . . .2017
Table 423.Double-buffering buffer flag definition. . . . .2027
Table 424.Bulk double-buffering memory buffers usage . . . . .2027
Table 425.Isochronous memory buffers usage . . . . .2029
Table 426.Resume event detection. . . . .2030
Table 427.Reception status encoding . . . . .2043
Table 428.Endpoint type encoding . . . . .2043
Table 429.Endpoint kind meaning . . . . .2043
Table 430.Transmission status encoding . . . . .2044
Table 431.Definition of allocated buffer memory . . . . .2047
Table 432.USB register map and reset values . . . . .2048
Table 433.UCPD implementation . . . . .2051
Table 434.UCPD signals on pins. . . . .2052
Table 435.UCPD internal signals. . . . .2053
Table 436.4b5b symbol encoding table. . . . .2054
Table 437.Ordered sets . . . . .2056
Table 438.Validation of ordered sets. . . . .2056
Table 439.Data size. . . . .2057
Table 440.Coding for ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx . . . . .2065
Table 441.Type-C sequence (source: 3A); cable/sink connected (Rd on CC1; Ra on CC2) . . . . .2067
Table 442.Effect of low power modes on the UCPD . . . . .2069
Table 443.UCPD interrupt requests. . . . .2070
Table 444.UCPD register map and reset values . . . . .2085
Table 445.SWJ debug port pins . . . . .2091
Table 446.Flexible SWJ-DP pin assignment . . . . .2091
Table 447.JTAG debug port data registers . . . . .2096
Table 448.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .2097
Table 449.Packet request (8-bits) . . . . .2098
Table 450.ACK response (3 bits). . . . .2099
Table 451.DATA transfer (33 bits). . . . .2099
Table 452.SW-DP registers. . . . .2100
Table 453.Cortex ® -M4 with FPU AHB-AP registers . . . . .2101
Table 454.Core debug registers . . . . .2102
Table 455.Main ITM registers . . . . .2105
Table 456.Main ETM registers. . . . .2106
Table 457.Asynchronous TRACE pin assignment. . . . .2113
Table 458.Synchronous TRACE pin assignment . . . . .2114
Table 459.Flexible TRACE pin assignment. . . . .2114
Table 460. Important TPIU registers. . . . .2118
Table 461. DBG register map and reset values . . . . .2120
Table 462. Document revision history . . . . .2125

List of figures

Figure 1.System architecture . . . . .80
Figure 2.Memory map . . . . .83
Figure 3.Sequential 16-bit instructions execution (64-bit read data width) . . . . .101
Figure 4.Changing the read protection (RDP) level . . . . .123
Figure 5.Example of disabling core debug access . . . . .128
Figure 6.Sequential 16-bit instructions execution (64-bit read data width) . . . . .154
Figure 7.Changing the read protection (RDP) level . . . . .169
Figure 8.Example of disabling core debug access . . . . .173
Figure 9.Sequential 16-bit instructions execution (64-bit read data width) . . . . .193
Figure 10.Changing the read protection (RDP) level . . . . .208
Figure 11.Example of disabling core debug access . . . . .212
Figure 12.STM32G4 series power supply overview . . . . .229
Figure 13.Brown-out reset waveform . . . . .234
Figure 14.PVD thresholds . . . . .235
Figure 15.Low-power modes possible transitions . . . . .237
Figure 16.Simplified diagram of the reset circuit . . . . .271
Figure 17.Clock tree . . . . .275
Figure 18.HSE/ LSE clock sources . . . . .276
Figure 19.Frequency measurement with TIM15 in capture mode . . . . .283
Figure 20.Frequency measurement with TIM16 in capture mode . . . . .283
Figure 21.Frequency measurement with TIM17 in capture mode . . . . .284
Figure 22.Frequency measurement with TIM5 in capture mode . . . . .284
Figure 23.CRS block diagram . . . . .335
Figure 24.CRS counter behavior . . . . .337
Figure 25.Basic structure of an I/O port bit . . . . .346
Figure 26.Basic structure of a 3- or 5-Volt tolerant I/O port bit . . . . .346
Figure 27.Input floating/pull up/pull down configurations . . . . .351
Figure 28.Output configuration . . . . .352
Figure 29.Alternate function configuration . . . . .352
Figure 30.High impedance-analog configuration . . . . .353
Figure 31.DMA block diagram . . . . .399
Figure 32.DMAMUX block diagram . . . . .423
Figure 33.Synchronization mode of the DMAMUX request line multiplexer channel . . . . .426
Figure 34.Event generation of the DMA request line multiplexer channel . . . . .426
Figure 35.Configurable interrupt/event block diagram . . . . .442
Figure 36.External interrupt/event GPIO mapping . . . . .444
Figure 37.CRC calculation unit block diagram . . . . .455
Figure 38.CORDIC convergence for trigonometric functions . . . . .469
Figure 39.CORDIC convergence for hyperbolic functions . . . . .470
Figure 40.CORDIC convergence for square root . . . . .471
Figure 41.Block diagram . . . . .480
Figure 42.Input buffer areas . . . . .482
Figure 43.Circular input buffer . . . . .483
Figure 44.Circular input buffer operation . . . . .484
Figure 45.Circular output buffer . . . . .485
Figure 46.Circular output buffer operation . . . . .486
Figure 47.FIR filter structure . . . . .488
Figure 48.IIR filter structure (direct form 1) . . . . .490
Figure 49.X1 buffer initialization . . . . .495
Figure 50.Filtering example 1 . . . . .496
Figure 51.Filtering example 2 . . . . .497
Figure 52.FMC block diagram. . . . .508
Figure 53.FMC memory banks . . . . .510
Figure 54.Mode 1 read access waveforms . . . . .518
Figure 55.Mode 1 write access waveforms. . . . .518
Figure 56.Mode A read access waveforms. . . . .520
Figure 57.Mode A write access waveforms . . . . .520
Figure 58.Mode 2 and mode B read access waveforms. . . . .522
Figure 59.Mode 2 write access waveforms. . . . .523
Figure 60.Mode B write access waveforms . . . . .523
Figure 61.Mode C read access waveforms . . . . .525
Figure 62.Mode C write access waveforms . . . . .526
Figure 63.Mode D read access waveforms . . . . .528
Figure 64.Mode D write access waveforms . . . . .529
Figure 65.Muxed read access waveforms . . . . .531
Figure 66.Muxed write access waveforms . . . . .532
Figure 67.Asynchronous wait during a read access waveforms. . . . .534
Figure 68.Asynchronous wait during a write access waveforms. . . . .535
Figure 69.Wait configuration waveforms. . . . .537
Figure 70.Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM). . . . .538
Figure 71.Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . .540
Figure 72.NAND flash controller waveforms for common memory access. . . . .552
Figure 73.Access to non 'CE don't care' NAND-flash. . . . .554
Figure 74.QUADSPI block diagram when dual-flash mode is disabled . . . . .563
Figure 75.QUADSPI block diagram when dual-flash mode is enabled. . . . .564
Figure 76.Example of read command in quad-SPI mode . . . . .565
Figure 77.Example of a DDR command in quad-SPI mode . . . . .568
Figure 78.NCS when CKMODE = 0 (T = CLK period) . . . . .576
Figure 79.NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .576
Figure 80.NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . .577
Figure 81.NCS when CKMODE = 1 with an abort (T = CLK period). . . . .577
Figure 82.ADC block diagram . . . . .594
Figure 83.ADC clock scheme . . . . .597
Figure 84.ADC1 connectivity . . . . .598
Figure 85.ADC2 connectivity . . . . .599
Figure 86.ADC3 connectivity . . . . .600
Figure 87.ADC4 connectivity . . . . .601
Figure 88.ADC5 connectivity . . . . .602
Figure 89.ADC calibration. . . . .605
Figure 90.Updating the ADC calibration factor . . . . .606
Figure 91.Mixing single-ended and differential channels . . . . .607
Figure 92.Enabling / disabling the ADC . . . . .608
Figure 93.Bulb mode timing diagram . . . . .611
Figure 94.Analog-to-digital conversion time . . . . .614
Figure 95.Stopping ongoing regular conversions . . . . .615
Figure 96.Stopping ongoing regular and injected conversions . . . . .615
Figure 97.Triggers sharing between ADC master and ADC slave . . . . .617
Figure 98.Injected conversion latency . . . . .622
Figure 99.Example of ADC_JSQR queue of context (sequence change) . . . . .626
Figure 100.Example of ADC_JSQR queue of context (trigger change) . . . . .626
Figure 101.Example of ADC_JSQR queue of context with overflow before conversion. . . . .627
Figure 102.Example of ADC_JSQR queue of context with overflow during conversion . . . . .627
Figure 103.Example of ADC_JSQR queue of context with empty queue (case JQM = 0) . . . . .628
Figure 104.Example of ADC_JSQR queue of context with empty queue (case JQM = 1) . . . . .629
Figure 105.Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs during an ongoing conversion . . . . .		629
Figure 106.Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . .		630
Figure 107.Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs outside an ongoing conversion . . . . .		630
Figure 108.Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 1) . . . . .631
Figure 109.Flushing ADC_JSQR queue of context by setting ADDIS = 1 (JQM = 0) . . . . .631
Figure 110.Flushing ADC_JSQR queue of context by setting ADDIS = 1 (JQM = 1) . . . . .632
Figure 111.Single conversions of a sequence, software trigger . . . . .634
Figure 112.Continuous conversion of a sequence, software trigger . . . . .634
Figure 113.Single conversions of a sequence, hardware trigger . . . . .635
Figure 114.Continuous conversions of a sequence, hardware trigger . . . . .635
Figure 115.Right alignment (offset disabled, unsigned value) . . . . .637
Figure 116.Right alignment (offset enabled, signed value) . . . . .638
Figure 117.Left alignment (offset disabled, unsigned value) . . . . .638
Figure 118.Left alignment (offset enabled, signed value) . . . . .639
Figure 119.Example of overrun (OVR) . . . . .640
Figure 120.AUTODLY = 1, regular conversion in continuous mode, software trigger . . . . .643
Figure 121.AUTODLY = 1, regular HW conversions interrupted by injected conversions
(DISCEN = 0; JDISCEN = 0) . . . . .		644
Figure 122.AUTODLY = 1, regular HW conversions interrupted by injected conversions
(DISCEN = 1, JDISCEN = 1) . . . . .		645
Figure 123.AUTODLY = 1, regular continuous conversions interrupted by injected conversions . . . . .646
Figure 124.AUTODLY = 1 in auto- injected mode (JAUTO = 1) . . . . .646
Figure 125.Analog watchdog guarded area . . . . .647
Figure 126.ADC y _AWD x _OUT signal generation (on all regular channels) . . . . .649
Figure 127.ADC y _AWD x _OUT signal generation (AWD x flag not cleared by software) . . . . .650
Figure 128.ADC y _AWD x _OUT signal generation (on a single regular channel) . . . . .650
Figure 129.ADC y _AWD x _OUT signal generation (on all injected channels) . . . . .650
Figure 130.20-bit to 16-bit result truncation . . . . .652
Figure 131.Numerical example with 5-bit shift and rounding . . . . .652
Figure 132.Triggered regular oversampling mode (TROVS bit = 1) . . . . .654
Figure 133.Regular oversampling modes (4x ratio) . . . . .655
Figure 134.Regular and injected oversampling modes used simultaneously . . . . .655
Figure 135.Triggered regular oversampling with injection . . . . .656
Figure 136.Oversampling in auto-injected mode . . . . .656
Figure 137.Dual ADC block diagram (1) . . . . .659
Figure 138.Injected simultaneous mode on 4 channels: dual ADC mode . . . . .660
Figure 139.Regular simultaneous mode on 16 channels: dual ADC mode . . . . .662
Figure 140.Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . .663
Figure 141.Interleaved mode on 1 channel in single conversion mode: dual ADC mode. . . . .664
Figure 142.Interleaved conversion with injection . . . . .664
Figure 143.Alternate trigger: injected group of each ADC . . . . .665
Figure 144.Alternate trigger: 4 injected channels (each ADC) in discontinuous mode. . . . .666
Figure 145.Alternate + regular simultaneous . . . . .667
Figure 146.Case of trigger occurring during injected conversion . . . . .667
Figure 147. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . .668
Figure 148. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . .		668
Figure 149. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . .		668
Figure 150. DMA Requests in regular simultaneous mode when MDMA = 00 . . . . .669
Figure 151. DMA requests in regular simultaneous mode when MDMA = 10 . . . . .670
Figure 152. DMA requests in interleaved mode when MDMA = 10 . . . . .670
Figure 153. Temperature sensor channel block diagram . . . . .672
Figure 154. VBAT channel block diagram . . . . .673
Figure 155. VREFINT channel block diagram . . . . .674
Figure 156. Dual-channel DAC block diagram . . . . .716
Figure 157. Data registers in single DAC channel mode . . . . .723
Figure 158. Data registers in dual DAC channel mode . . . . .724
Figure 159. Timing diagram for conversion with trigger disabled TEN = 0 . . . . .726
Figure 160. DAC LFSR register calculation algorithm . . . . .728
Figure 161. DAC conversion (SW trigger enabled) with LFSR wave generation. . . . .728
Figure 162. DAC triangle wave generation . . . . .729
Figure 163. DAC conversion (SW trigger enabled) with triangle wave generation . . . . .729
Figure 164. DAC sawtooth wave generation (STDIRx = 0) . . . . .730
Figure 165. DAC sawtooth wave generation (STDIRx = 1) . . . . .730
Figure 166. DAC sawtooth STINCTRIG and STRSTTRIG priority (STDIR = 0) . . . . .731
Figure 167. DAC sample and hold mode phase diagram . . . . .733
Figure 168. Comparator block diagram . . . . .768
Figure 169. Comparator hysteresis . . . . .770
Figure 170. Comparator output blanking . . . . .771
Figure 171. Standalone mode: external gain setting mode . . . . .779
Figure 172. Follower configuration. . . . .780
Figure 173. PGA mode, internal gain setting (x2/x4/x8/x16/x32/x64),
inverting input not used. . . . .		781
Figure 174. PGA mode, internal gain setting (x2/x4/x8/x16/x32/x64),
inverting input used for filtering. . . . .		782
Figure 175. PGA mode, non-inverting gain setting (x2/x4/x8/x16/x32/x64)
or inverting gain setting (x-1/x-3/x-7/x-15/x-31/x-63) . . . . .		783
Figure 176. PGA mode, non-inverting gain setting (x2/x4/x8/x16/x32/x64)
or inverting gain setting (x-1/x-3/x-7/x-15/x-31/x-63) with filtering . . . . .		784
Figure 177. Example configuration . . . . .784
Figure 178. Timer controlled Multiplexer mode . . . . .787
Figure 179. RNG block diagram . . . . .821
Figure 180. Entropy source model. . . . .822
Figure 181. RNG initialization overview. . . . .824
Figure 182. AES block diagram . . . . .833
Figure 183. ECB encryption and decryption principle . . . . .835
Figure 184. CBC encryption and decryption principle . . . . .836
Figure 185. CTR encryption and decryption principle . . . . .837
Figure 186. GCM encryption and authentication principle. . . . .838
Figure 187. GMAC authentication principle . . . . .838
Figure 188. CCM encryption and authentication principle . . . . .839
Figure 189. Encryption key derivation for ECB/CBC decryption (Mode 2). . . . .842
Figure 190. Example of suspend mode management . . . . .843
Figure 191. ECB encryption. . . . .844
Figure 192. ECB decryption. . . . .844
Figure 193. CBC encryption. . . . .845
Figure 194. CBC decryption. . . . .845
Figure 195. ECB/CBC encryption (Mode 1). . . . .846
Figure 196. ECB/CBC decryption (Mode 3). . . . .847
Figure 197. Message construction in CTR mode. . . . .849
Figure 198. CTR encryption. . . . .850
Figure 199. CTR decryption. . . . .850
Figure 200. Message construction in GCM . . . . .852
Figure 201. GCM authenticated encryption . . . . .853
Figure 202. Message construction in GMAC mode . . . . .857
Figure 203. GMAC authentication mode . . . . .857
Figure 204. Message construction in CCM mode . . . . .858
Figure 205. CCM mode authenticated encryption . . . . .860
Figure 206. 128-bit block construction with respect to data swap . . . . .864
Figure 207. DMA transfer of a 128-bit data block during input phase . . . . .866
Figure 208. DMA transfer of a 128-bit data block during output phase . . . . .867
Figure 209. High-resolution timer overview . . . . .884
Figure 210. Counter and capture register format vs clock prescaling factor . . . . .890
Figure 211. Timer A..F overview . . . . .892
Figure 212. Continuous timer operation. . . . .894
Figure 213. Single-shot timer operation. . . . .894
Figure 214. Timer reset resynchronization (prescaling ratio above 32). . . . .896
Figure 215. Repetition rate versus HRTIM_REPxR content in continuous mode . . . . .897
Figure 216. Repetition counter behavior in single-shot mode . . . . .897
Figure 217. Compare events action on outputs: set on compare 1, reset on compare 2 . . . . .899
Figure 218. Timer A timing unit capture circuitry . . . . .903
Figure 219. Auto-delayed overview (compare 2 only) . . . . .904
Figure 220. Auto-delayed compare . . . . .905
Figure 221. Triggered-half mode example. . . . .907
Figure 222. Push-pull mode block diagram . . . . .908
Figure 223. Push-pull mode example . . . . .909
Figure 224. Push-pull with deadtime . . . . .910
Figure 225. Complementary outputs with deadtime insertion . . . . .911
Figure 226. Deadtime insertion versus deadtime sign (1 indicates negative deadtime) . . . . .911
Figure 227. Complementary outputs for low pulsewidth (SDTRx = SDTFx = 0) . . . . .912
Figure 228. Complementary outputs for low pulsewidth (SDTRx = SDTFx = 1) . . . . .912
Figure 229. Complementary outputs for low pulsewidth (SDTRx = 0, SDTFx = 1) . . . . .913
Figure 230. Complementary outputs for low pulsewidth (SDTRx = 1, SDTFx=0) . . . . .913
Figure 231. Master timer overview. . . . .914
Figure 232. Basic symmetric waveform in up-down counting mode . . . . .915
Figure 233. Complex symmetric waveform in up-down counting mode. . . . .916
Figure 234. Asymmetric waveform in up-down counting mode . . . . .916
Figure 235. External event management in up-down counting mode . . . . .917
Figure 236. Interleaved up-down counter operation . . . . .917
Figure 237. Interleaved up-down counter operation . . . . .918
Figure 238. Push-pull up-down mode example . . . . .918
Figure 239. Up-down mode with “greater than” comparison . . . . .919
Figure 240. Up-down mode with output set on period event, for OUTROM[1:0]=10 . . . . .920
Figure 241. Repetition counter behavior in up-down counting mode. . . . .921
Figure 242. Short distance set/reset management for narrow pulse generation . . . . .923
Figure 243. External event conditioning overview (1 channel represented) . . . . .926
Figure 244. Latency to external events (counter reset and output set) . . . . .929
Figure 245. Latency to external events (output reset on external event) . . . . .929
Figure 246. Event blanking mode . . . . .930
Figure 247. Event postpone mode . . . . .930
Figure 248. External trigger blanking with edge-sensitive trigger . . . . .931
Figure 249. External trigger blanking, level sensitive triggering . . . . .932
Figure 250. Event windowing mode . . . . .932
Figure 251. External trigger windowing with edge-sensitive trigger . . . . .933
Figure 252. External trigger windowing, level sensitive triggering . . . . .934
Figure 253. External event counter – channel A . . . . .934
Figure 254. External event counter cumulative mode (EEVxRSTM = 1, EEVxCNT = 2). . . . .935
Figure 255. Delayed Idle mode entry . . . . .937
Figure 256. Burst mode and delayed protection priorities (DIDL = 0) . . . . .938
Figure 257. Burst mode and delayed protection priorities (DIDL = 1) . . . . .939
Figure 258. Balanced Idle protection example . . . . .940
Figure 259. Resynchronized timer update (TAU=1 in HRTIM_TIMBCR) . . . . .945
Figure 260. Early turn-ON and early turn-OFF behavior in “greater than” PWM mode . . . . .947
Figure 261. Output management overview . . . . .952
Figure 262. HRTIM output states and transitions . . . . .953
Figure 263. Burst mode operation example . . . . .954
Figure 264. Burst mode trigger on external event . . . . .957
Figure 265. Delayed burst mode entry with deadtime enabled and IDLESx = 1 . . . . .958
Figure 266. Delayed burst mode entry during deadtime . . . . .959
Figure 267. Burst mode exit when the deadtime generator is enabled . . . . .960
Figure 268. Burst mode emulation example . . . . .962
Figure 269. Carrier frequency signal insertion . . . . .962
Figure 270. HRTIM outputs with Chopper mode enabled . . . . .963
Figure 271. Fault protection circuitry (FAULT1 fully represented, FAULT2..6 partially). . . . .964
Figure 272. Fault signal filtering (FLTxF[3:0] = 0010: f SAMPLING = f HRTIM , N = 4) . . . . .965
Figure 273. Fault counter cumulative mode (FLTxRSTM = 1, FLTxCNT[3:0] = 2) . . . . .966
Figure 274. Auxiliary outputs . . . . .968
Figure 275. Auxiliary and main outputs during burst mode (DIDLx = 0) . . . . .969
Figure 276. Deadtime distortion on auxiliary output when exiting burst mode. . . . .969
Figure 277. Counter behavior in synchronized start mode . . . . .973
Figure 278. ADC trigger selection overview . . . . .974
Figure 279. ADC triggers . . . . .975
Figure 280. ADC trigger post-scaling in up-counting mode . . . . .976
Figure 281. ADC trigger post-scaling in up/down counting mode . . . . .976
Figure 282. Combining several updates on a single hrtim_dac_trgx output . . . . .977
Figure 283. DAC triggers for slope compensation . . . . .980
Figure 284. DAC triggers overview . . . . .981
Figure 285. DMA burst overview . . . . .985
Figure 286. Burst DMA operation flowchart . . . . .986
Figure 287. Registers update following DMA burst transfer . . . . .987
Figure 288. Buck converter topology . . . . .989
Figure 289. Dual Buck converter management . . . . .990
Figure 290. Synchronous rectification depending on output current . . . . .990
Figure 291. Buck with synchronous rectification . . . . .991
Figure 292. 3-phase interleaved buck converter . . . . .991
Figure 293. 3-phase interleaved buck converter control . . . . .992
Figure 294. Transition mode PFC . . . . .993
Figure 295. Transition mode PFC waveforms . . . . .994
Figure 296. Advanced-control timer block diagram . . . . .1145
Figure 297.Counter timing diagram with prescaler division change from 1 to 2 . . . . .1152
Figure 298.Counter timing diagram with prescaler division change from 1 to 4 . . . . .1152
Figure 299.Counter timing diagram, internal clock divided by 1 . . . . .1154
Figure 300.Counter timing diagram, internal clock divided by 2 . . . . .1154
Figure 301.Counter timing diagram, internal clock divided by 4 . . . . .1155
Figure 302.Counter timing diagram, internal clock divided by N . . . . .1155
Figure 303.Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded). . . . .		1156
Figure 304.Counter timing diagram, update event when ARPE = 1
(TIMx_ARR preloaded). . . . .		1157
Figure 305.Counter timing diagram, internal clock divided by 1 . . . . .1158
Figure 306.Counter timing diagram, internal clock divided by 2 . . . . .1159
Figure 307.Counter timing diagram, internal clock divided by 4 . . . . .1159
Figure 308.Counter timing diagram, internal clock divided by N . . . . .1160
Figure 309.Counter timing diagram, update event when repetition counter is not used. . . . .1160
Figure 310.Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .1162
Figure 311.Counter timing diagram, internal clock divided by 2 . . . . .1162
Figure 312.Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .1163
Figure 313.Counter timing diagram, internal clock divided by N . . . . .1163
Figure 314.Counter timing diagram, update event with ARPE = 1 (counter underflow) . . . . .1164
Figure 315.Counter timing diagram, Update event with ARPE = 1 (counter overflow) . . . . .1165
Figure 316.Update rate examples depending on mode and TIMx_RCR register settings . . . . .1166
Figure 318.Control circuit in normal mode, internal clock divided by 1 . . . . .1168
Figure 319.tim_ti2 external clock connection example . . . . .1168
Figure 320.Control circuit in external clock mode 1 . . . . .1169
Figure 321.External trigger input block . . . . .1170
Figure 322.Control circuit in external clock mode 2 . . . . .1171
Figure 323.Capture/compare channel (example: channel 1 input stage) . . . . .1171
Figure 324.Capture/compare channel 1 main circuit . . . . .1172
Figure 325.Output stage of capture/compare channel (channel 1, idem ch. 2, 3 and 4) . . . . .1173
Figure 326.Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .1173
Figure 327.PWM input mode timing . . . . .1176
Figure 328.Output compare mode, toggle on tim_oc1 . . . . .1178
Figure 329.Edge-aligned PWM waveforms (ARR = 8) . . . . .1179
Figure 330.Center-aligned PWM waveforms (ARR = 8). . . . .1180
Figure 331.Dithering principle . . . . .1181
Figure 332.Data format and register coding in dithering mode . . . . .1182
Figure 333.PWM resolution vs frequency . . . . .1183
Figure 334.PWM dithering pattern . . . . .1184
Figure 335.Dithering effect on duty cycle in center-aligned PWM mode . . . . .1185
Figure 336.Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1187
Figure 337.Combined PWM mode on channel 1 and 3 . . . . .1188
Figure 338.3-phase combined PWM signals with multiple trigger pulses per period . . . . .1189
Figure 339.Complementary output with symmetrical dead-time insertion . . . . .1190
Figure 340.Asymmetrical deadtime . . . . .1191
Figure 341.Dead-time waveforms with delay greater than the negative pulse . . . . .1191
Figure 342.Dead-time waveforms with delay greater than the positive pulse. . . . .1191
Figure 343.Break and Break2 circuitry overview . . . . .1194
Figure 344.Various output behavior in response to a break event on tim_brk (OSSI = 1) . . . . .1196
Figure 345.PWM output state following tim_brk and tim_brk2 assertion (OSSI = 1) . . . . .1197
Figure 346.PWM output state following tim_brk assertion (OSSI = 0) . . . . .1198
Figure 347.Output redirection (tim_brk2 request not represented). . . . .1199
Figure 348. tim_ocref_clr input selection multiplexer . . . . .1200
Figure 349. Clearing TIMx tim_ocxref . . . . .1201
Figure 350. 6-step generation, COM example (OSSR = 1) . . . . .1202
Figure 351. Example of one pulse mode. . . . .1203
Figure 352. Retriggerable one-pulse mode . . . . .1204
Figure 353. Pulse generator circuitry . . . . .1205
Figure 354. Pulse generation on compare event, for edge-aligned and encoder modes . . . . .1206
Figure 355. Extended pulselwidth in case of concurrent triggers . . . . .1207
Figure 356. Example of counter operation in encoder interface mode. . . . .1209
Figure 357. Example of encoder interface mode with tim_ti1fp1 polarity inverted. . . . .1209
Figure 358. Quadrature encoder counting modes . . . . .1210
Figure 359. Direction plus clock encoder mode. . . . .1211
Figure 360. Directional clock encoder mode (CC1P = CC2P = 0). . . . .1211
Figure 361. Directional clock encoder mode (CC1P = CC2P = 1). . . . .1212
Figure 362. Index gating options . . . . .1213
Figure 363. Jittered Index signals . . . . .1213
Figure 364. Index generation for IPOS[1:0] = 11 . . . . .1214
Figure 365. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .1214
Figure 366. Counter reading with index ungated (IPOS[1:0] = 00) . . . . .1215
Figure 367. Counter reading with index gated on channel A and B. . . . .1215
Figure 368. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11). . . . .1216
Figure 369. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .1217
Figure 370. Index behavior in x1 and x2 mode (IPOS[1:0] = 01). . . . .1218
Figure 371. Directional index sensitivity. . . . .1219
Figure 372. Counter reset as function of FIDX bit setting . . . . .1219
Figure 373. Index behavior in clock + direction mode, IPOS[0] = 1. . . . .1220
Figure 374. Index behavior in directional clock mode, IPOS[0] = 1 . . . . .1220
Figure 375. State diagram for quadrature encoded signals. . . . .1221
Figure 376. Up-counting encoder error detection . . . . .1222
Figure 377. Down-counting encode error detection. . . . .1223
Figure 378. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .1224
Figure 379. Measuring time interval between edges on three signals. . . . .1225
Figure 380. Example of Hall sensor interface . . . . .1227
Figure 381. Control circuit in reset mode . . . . .1228
Figure 382. Control circuit in Gated mode . . . . .1229
Figure 383. Control circuit in trigger mode. . . . .1230
Figure 384. Control circuit in external clock mode 2 + trigger mode . . . . .1231
Figure 385. General-purpose timer block diagram . . . . .1289
Figure 386. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1295
Figure 387. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1296
Figure 388. Counter timing diagram, internal clock divided by 1 . . . . .1297
Figure 389. Counter timing diagram, internal clock divided by 2 . . . . .1297
Figure 390. Counter timing diagram, internal clock divided by 4 . . . . .1298
Figure 391. Counter timing diagram, internal clock divided by N. . . . .1298
Figure 392. Counter timing diagram, Update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .1299
Figure 393. Counter timing diagram, Update event when ARPE = 1 (TIMx_ARR preloaded). . . . .1300
Figure 394. Counter timing diagram, internal clock divided by 1 . . . . .1301
Figure 395. Counter timing diagram, internal clock divided by 2 . . . . .1302
Figure 396. Counter timing diagram, internal clock divided by 4 . . . . .1302
Figure 397. Counter timing diagram, internal clock divided by N. . . . .1303
Figure 398. Counter timing diagram, Update event. . . . .1303
Figure 399. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .1305
Figure 400. Counter timing diagram, internal clock divided by 2 . . . . .1305
Figure 401. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .1306
Figure 402. Counter timing diagram, internal clock divided by N . . . . .1306
Figure 403. Counter timing diagram, Update event with ARPE = 1 (counter underflow). . . . .1307
Figure 404. Counter timing diagram, Update event with ARPE = 1 (counter overflow). . . . .1308
Figure 405. Control circuit in normal mode, internal clock divided by 1 . . . . .1309
Figure 406. tim_ti2 external clock connection example . . . . .1309
Figure 407. Control circuit in external clock mode 1 . . . . .1310
Figure 408. External trigger input block . . . . .1311
Figure 409. Control circuit in external clock mode 2 . . . . .1312
Figure 410. Capture/compare channel (example: channel 1 input stage). . . . .1312
Figure 411. Capture/compare channel 1 main circuit . . . . .1313
Figure 412. Output stage of capture/compare channel (channel 1, idem ch.2, 3 and 4). . . . .1313
Figure 413. PWM input mode timing . . . . .1316
Figure 414. Output compare mode, toggle on tim_oc1 . . . . .1318
Figure 415. Edge-aligned PWM waveforms (ARR = 8). . . . .1319
Figure 416. Center-aligned PWM waveforms (ARR = 8). . . . .1320
Figure 417. Dithering principle . . . . .1321
Figure 418. Data format and register coding in dithering mode. . . . .1322
Figure 419. PWM resolution vs frequency (16-bit mode). . . . .1323
Figure 420. PWM resolution vs frequency (32-bit mode). . . . .1323
Figure 421. PWM dithering pattern . . . . .1324
Figure 422. Dithering effect on duty cycle in center-aligned PWM mode . . . . .1325
Figure 423. Generation of two phase-shifted PWM signals with 50% duty cycle . . . . .1327
Figure 424. Combined PWM mode on channels 1 and 3 . . . . .1328
Figure 425. OCREF_CLR input selection multiplexer . . . . .1329
Figure 426. Clearing TIMx tim_ocxref . . . . .1329
Figure 427. Example of One-pulse mode . . . . .1330
Figure 428. Retriggerable one-pulse mode . . . . .1332
Figure 429. Pulse generator circuitry . . . . .1333
Figure 430. Pulse generation on compare event, for edge-aligned and encoder modes . . . . .1333
Figure 431. Extended pulse width in case of concurrent triggers . . . . .1334
Figure 432. Example of counter operation in encoder interface mode . . . . .1336
Figure 433. Example of encoder interface mode with tim_ti1fp1 polarity inverted . . . . .1336
Figure 434. Quadrature encoder counting modes . . . . .1337
Figure 435. Direction plus clock encoder mode. . . . .1338
Figure 436. Directional clock encoder mode (CC1P = CC2P = 0). . . . .1339
Figure 437. Directional clock encoder mode (CC1P = CC2P = 1). . . . .1339
Figure 438. Index gating options . . . . .1341
Figure 439. Jittered Index signals . . . . .1341
Figure 440. Index generation for IPOS[1:0] = 11 . . . . .1342
Figure 441. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .1342
Figure 442. Counter reading with index ungated (IPOS[1:0] = 00) . . . . .1343
Figure 443. Counter reading with index gated on channel A and B. . . . .1343
Figure 444. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11). . . . .1344
Figure 445. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .1345
Figure 446. Index behavior in x1 and x2 mode (IPOS[1:0] = 01). . . . .1346
Figure 447. Directional index sensitivity. . . . .1347
Figure 448. Counter reset as function of FIDX bit setting . . . . .1347
Figure 449. Index behavior in clock + direction mode, IPOS[0] = 1. . . . .1348
Figure 450. Index behavior in directional clock mode, IPOS[0] = 1 . . . . .1348
Figure 451. State diagram for quadrature encoded signals. . . . .1349
Figure 452. Up-counting encoder error detection . . . . .1350
Figure 453. Down-counting encode error detection . . . . .1351
Figure 454. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .1352
Figure 455. Control circuit in reset mode . . . . .1354
Figure 456. Control circuit in gated mode . . . . .1355
Figure 457. Control circuit in trigger mode . . . . .1355
Figure 458. Control circuit in external clock mode 2 + trigger mode . . . . .1357
Figure 459. Master/Slave timer example . . . . .1357
Figure 460. Master/slave connection example with 1 channel only timers . . . . .1358
Figure 461. Gating TIM_slv with tim_oc1ref of TIM_mstr . . . . .1359
Figure 462. Gating TIM_slv with Enable of TIM_mstr . . . . .1360
Figure 463. Triggering TIM_slv with update of TIM_mstr. . . . .1361
Figure 464. Triggering TIM_slv with Enable of TIM_mstr . . . . .1361
Figure 465. Triggering TIM_mstr and TIM_slv with TIM_mstr tim_ti1 input. . . . .1362
Figure 466. TIM15 block diagram . . . . .1406
Figure 467. TIM16/TIM17 block diagram . . . . .1407
Figure 468. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1412
Figure 469. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1412
Figure 470. Counter timing diagram, internal clock divided by 1 . . . . .1414
Figure 471. Counter timing diagram, internal clock divided by 2 . . . . .1414
Figure 472. Counter timing diagram, internal clock divided by 4 . . . . .1415
Figure 473. Counter timing diagram, internal clock divided by N . . . . .1415
Figure 474. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded). . . . .		1416
Figure 475. Counter timing diagram, update event when ARPE = 1
(TIMx_ARR preloaded). . . . .		1417
Figure 476. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1418
Figure 477. Control circuit in normal mode, internal clock divided by 1 . . . . .1419
Figure 478. tim_ti2 external clock connection example . . . . .1419
Figure 479. Control circuit in external clock mode 1 . . . . .1420
Figure 480. Capture/compare channel (example: channel 1 input stage) . . . . .1421
Figure 481. Capture/compare channel 1 main circuit . . . . .1421
Figure 482. Output stage of capture/compare channel (channel 1). . . . .1422
Figure 483. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .1422
Figure 484. PWM input mode timing . . . . .1425
Figure 485. Output compare mode, toggle on tim_oc1 . . . . .1427
Figure 486. Edge-aligned PWM waveforms (ARR = 8) . . . . .1428
Figure 487. Dithering principle . . . . .1429
Figure 488. Data format and register coding in dithering mode . . . . .1429
Figure 489. PWM resolution vs frequency . . . . .1430
Figure 490. PWM dithering pattern . . . . .1431
Figure 491. Combined PWM mode on channel 1 and 2 . . . . .1433
Figure 492. Complementary output with symmetrical dead-time insertion. . . . .1434
Figure 493. Asymmetrical deadtime . . . . .1435
Figure 494. Dead-time waveforms with delay greater than the negative pulse. . . . .1435
Figure 495. Dead-time waveforms with delay greater than the positive pulse. . . . .1435
Figure 496. Break circuitry overview . . . . .1437
Figure 497. Output behavior in response to a break event on tim_brk . . . . .1439
Figure 498. Output redirection . . . . .1441
Figure 499. tim_ocref_clr input selection multiplexer. . . . .1442
Figure 500. 6-step generation, COM example (OSSR = 1) . . . . .1443
Figure 501. Example of one pulse mode. . . . .1444
Figure 502. Retriggerable one pulse mode . . . . .1446
Figure 503. Measuring time interval between edges on 2 signals . . . . .1446
Figure 504. Control circuit in reset mode . . . . .1447
Figure 505. Control circuit in gated mode . . . . .1448
Figure 506. Control circuit in trigger mode . . . . .1449
Figure 507. Basic timer block diagram . . . . .1511
Figure 508. Control circuit in normal mode, internal clock divided by 1 . . . . .1512
Figure 509. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1513
Figure 510. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1514
Figure 511. Counter timing diagram, internal clock divided by 1 . . . . .1515
Figure 512. Counter timing diagram, internal clock divided by 2 . . . . .1515
Figure 513. Counter timing diagram, internal clock divided by 4 . . . . .1516
Figure 514. Counter timing diagram, internal clock divided by N . . . . .1516
Figure 515. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .1517
Figure 516. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR preloaded). . . . .1518
Figure 517. Dithering principle . . . . .1519
Figure 518. Data format and register coding in dithering mode . . . . .1520
Figure 519. FCnt resolution vs frequency . . . . .1521
Figure 520. PWM dithering pattern . . . . .1521
Figure 521. Low-power timer block diagram . . . . .1531
Figure 522. Glitch filter timing diagram . . . . .1534
Figure 523. LPTIM output waveform, single counting mode configuration . . . . .1535
Figure 524. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set). . . . .1536
Figure 525. LPTIM output waveform, Continuous counting mode configuration . . . . .1536
Figure 526. Waveform generation . . . . .1538
Figure 527. Encoder mode counting sequence . . . . .1542
Figure 528. IRTIM internal hardware connections with TIM16 and TIM17 . . . . .1555
Figure 529. Independent watchdog block diagram . . . . .1556
Figure 530. Watchdog block diagram . . . . .1566
Figure 531. Window watchdog timing diagram . . . . .1567
Figure 532. RTC block diagram . . . . .1572
Figure 533. TAMP block diagram . . . . .1611
Figure 534. Block diagram . . . . .1627
Figure 535. I 2 C-bus protocol . . . . .1629
Figure 536. Setup and hold timings . . . . .1631
Figure 537. I2C initialization flow . . . . .1633
Figure 538. Data reception . . . . .1634
Figure 539. Data transmission . . . . .1635
Figure 540. Target initialization flow . . . . .1638
Figure 541. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .1640
Figure 542. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .1641
Figure 543. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .1642
Figure 544. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .1643
Figure 545. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .1644
Figure 546. Transfer bus diagrams for I2C target receiver (mandatory events only). . . . .1644
Figure 547. Controller clock generation . . . . .1646
Figure 548. Controller initialization flow . . . . .1648
Figure 549. 10-bit address read access with HEAD10R = 0 . . . . .1648
Figure 550.10-bit address read access with HEAD10R = 1 . . . . .1649
Figure 551.Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .1650
Figure 552.Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .1651
Figure 553.Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . .		1652
Figure 554.Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .1654
Figure 555.Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .1655
Figure 556.Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . .		1656
Figure 557.Timeout intervals for t LOW:SEXT , t LOW:MEXT . . . . .1660
Figure 558.Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .1664
Figure 559.Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .1664
Figure 560.Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .1666
Figure 561.Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .1667
Figure 562.Bus transfer diagrams for SMBus controller transmitter . . . . .1668
Figure 563.Bus transfer diagrams for SMBus controller receiver . . . . .1670
Figure 564.USART block diagram . . . . .1692
Figure 565.Word length programming . . . . .1695
Figure 566.Configurable stop bits . . . . .1697
Figure 567.TC/TXE behavior when transmitting . . . . .1700
Figure 568.Start bit detection when oversampling by 16 or 8. . . . .1701
Figure 569.usart_ker_ck clock divider block diagram. . . . .1704
Figure 570.Data sampling when oversampling by 16. . . . .1705
Figure 571.Data sampling when oversampling by 8. . . . .1706
Figure 572.Mute mode using Idle line detection . . . . .1713
Figure 573.Mute mode using address mark detection . . . . .1714
Figure 574.Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .1717
Figure 575.Break detection in LIN mode vs. Framing error detection. . . . .1718
Figure 576.USART example of synchronous master transmission. . . . .1719
Figure 577.USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		1719
Figure 578.USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		1720
Figure 579.USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		1721
Figure 580.ISO 7816-3 asynchronous protocol . . . . .1723
Figure 581.Parity error detection using the 1.5 stop bits . . . . .1725
Figure 582.IrDA SIR ENDEC block diagram. . . . .1729
Figure 583.IrDA data modulation (3/16) - normal mode . . . . .1729
Figure 584.Transmission using DMA . . . . .1731
Figure 585.Reception using DMA . . . . .1732
Figure 586.Hardware flow control between 2 USARTs . . . . .1732
Figure 587.RS232 RTS flow control . . . . .1733
Figure 588.RS232 CTS flow control . . . . .1734
Figure 589.Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .1737
Figure 590.Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		1737
Figure 591.LPUART block diagram . . . . .1778
Figure 592.LPUART word length programming . . . . .1781
Figure 593.Configurable stop bits . . . . .1783
Figure 594.TC/TXE behavior when transmitting . . . . .1785
Figure 595.lpuart_ker_ck clock divider block diagram . . . . .1788
Figure 596. Mute mode using Idle line detection . . . . .1792
Figure 597. Mute mode using address mark detection . . . . .1793
Figure 598. Transmission using DMA . . . . .1795
Figure 599. Reception using DMA . . . . .1796
Figure 600. Hardware flow control between 2 LPUARTs . . . . .1797
Figure 601. RS232 RTS flow control . . . . .1797
Figure 602. RS232 CTS flow control . . . . .1798
Figure 603. Wake-up event verified (wake-up event = address match,
FIFO disabled) . . . . .		1801
Figure 604. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		1801
Figure 605. SPI block diagram. . . . .1830
Figure 606. Full-duplex single master/ single slave application. . . . .1831
Figure 607. Half-duplex single master/ single slave application . . . . .1832
Figure 608. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		1833
Figure 609. Master and three independent slaves. . . . .1834
Figure 610. Multimaster application. . . . .1835
Figure 611. Hardware/software slave select management . . . . .1836
Figure 612. Data clock timing diagram . . . . .1837
Figure 613. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .1838
Figure 614. Packing data in FIFO for transmission and reception. . . . .1842
Figure 615. Master full-duplex communication . . . . .1845
Figure 616. Slave full-duplex communication . . . . .1846
Figure 617. Master full-duplex communication with CRC . . . . .1847
Figure 618. Master full-duplex communication in packed mode . . . . .1848
Figure 619. NSSP pulse generation in Motorola SPI master mode. . . . .1851
Figure 620. TI mode transfer . . . . .1852
Figure 621. I2S block diagram . . . . .1855
Figure 622. I 2 S Philips protocol waveforms (16/32-bit full accuracy). . . . .1857
Figure 623. I 2 S Philips standard waveforms (24-bit frame) . . . . .1857
Figure 624. Transmitting 0x8EAA33 . . . . .1858
Figure 625. Receiving 0x8EAA33 . . . . .1858
Figure 626. I 2 S Philips standard (16-bit extended to 32-bit packet frame) . . . . .1858
Figure 627. Example of 16-bit data frame extended to 32-bit channel frame . . . . .1858
Figure 628. MSB Justified 16-bit or 32-bit full-accuracy length . . . . .1859
Figure 629. MSB justified 24-bit frame length . . . . .1859
Figure 630. MSB justified 16-bit extended to 32-bit packet frame . . . . .1860
Figure 631. LSB justified 16-bit or 32-bit full-accuracy . . . . .1860
Figure 632. LSB justified 24-bit frame length. . . . .1860
Figure 633. Operations required to transmit 0x3478AE. . . . .1861
Figure 634. Operations required to receive 0x3478AE . . . . .1861
Figure 635. LSB justified 16-bit extended to 32-bit packet frame . . . . .1861
Figure 636. Example of 16-bit data frame extended to 32-bit channel frame . . . . .1862
Figure 637. PCM standard waveforms (16-bit) . . . . .1862
Figure 638. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .1863
Figure 639. Start sequence in master mode . . . . .1864
Figure 640. Audio sampling frequency definition . . . . .1865
Figure 641. I 2 S clock generator architecture . . . . .1865
Figure 642. SAI functional block diagram . . . . .1888
Figure 643. Audio frame . . . . .1891
Figure 644. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .1893
Figure 645. FS role is start of frame (FSDEF = 0) . . . . .1894
Figure 646. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .1895
Figure 647. First bit offset . . . . .1895
Figure 648. Audio block clock generator overview . . . . .1897
Figure 649. PDM typical connection and timing . . . . .1901
Figure 650. Detailed PDM interface block diagram . . . . .1902
Figure 651. Start-up sequence . . . . .1903
Figure 652. SAI_ADR format in TDM mode, 32-bit slot width . . . . .1904
Figure 653. SAI_ADR format in TDM mode, 16-bit slot width . . . . .1905
Figure 654. SAI_ADR format in TDM mode, 8-bit slot width . . . . .1906
Figure 655. AC'97 audio frame . . . . .1909
Figure 656. SPDIF format . . . . .1910
Figure 657. SAI_xDR register ordering . . . . .1911
Figure 658. Data companding hardware in an audio block in the SAI . . . . .1914
Figure 659. Tristate strategy on SD output line on an inactive slot . . . . .1916
Figure 660. Tristate on output data line in a protocol like I2S . . . . .1917
Figure 661. Overrun detection error . . . . .1918
Figure 662. FIFO underrun event . . . . .1918
Figure 663. CAN subsystem . . . . .1952
Figure 664. FDCAN block diagram . . . . .1954
Figure 665. Bit timing . . . . .1956
Figure 666. Transceiver delay measurement . . . . .1961
Figure 667. Pin control in bus monitoring mode . . . . .1962
Figure 668. Pin control in loop-back mode . . . . .1965
Figure 669. CAN error state diagram . . . . .1966
Figure 670. Message RAM configuration . . . . .1967
Figure 671. Standard message ID filter path . . . . .1970
Figure 672. Extended message ID filter path . . . . .1971
Figure 673. USB peripheral block diagram . . . . .2018
Figure 674. Packet buffer areas with examples of buffer description table locations . . . . .2022
Figure 675. UCPD block diagram . . . . .2052
Figure 676. Clock division and timing elements . . . . .2053
Figure 677. K-code transmission . . . . .2056
Figure 678. Transmit order for various sizes of data . . . . .2057
Figure 679. Packet format . . . . .2058
Figure 680. Line format of Hard Reset . . . . .2058
Figure 681. Line format of Cable Reset . . . . .2059
Figure 682. BIST test data frame . . . . .2060
Figure 683. BIST Carrier Mode 2 frame . . . . .2060
Figure 684. UCPD BMC transmitter architecture . . . . .2061
Figure 685. UCPD BMC receiver architecture . . . . .2062
Figure 686. Block diagram of STM32 MCU and Cortex ® -M4 with FPU-level
debug support . . . . .		2088
Figure 687. SWJ debug port . . . . .2090
Figure 688. JTAG TAP connections . . . . .2094
Figure 689. TPIU block diagram . . . . .2113