RM0440-STM32G4

This document is addressed to application developers. It provides complete information on how to use the memory and peripherals of STM32G4 series microcontrollers. These devices come with different memory sizes, packages and peripherals, and include ST state-of-the-art patented technology.

For ordering information, mechanical and electrical device characteristics, refer to the corresponding datasheets.

For information on the Arm ® Cortex ® -M4 core, refer to the Cortex ® -M4 Technical Reference Manual .

STM32G4 series microcontrollers include ST state-of-the-art patented technology.

Contents

3.3.1Flash memory organization . . . . .95
3.3.2Error code correction (ECC) . . . . .97
3.3.3Read access latency . . . . .98
3.3.4Adaptive real-time memory accelerator (ART Accelerator) . . . . .99
3.3.5Flash program and erase operations . . . . .102
3.3.6Flash main memory erase sequences . . . . .103
3.3.7Flash main memory programming sequences . . . . .104
3.3.8Read-while-write (RWW) available only in dual bank mode
(DBANK = 1) . . . . .		108
3.4FLASH option bytes . . . . .110
3.4.1Option bytes description . . . . .110
3.4.2Option bytes programming . . . . .118
3.5FLASH memory protection . . . . .121
3.5.1Read protection (RDP) . . . . .121
3.5.2Proprietary code readout protection (PCROP) . . . . .124
3.5.3Write protection (WRP) . . . . .126
3.5.4Securable memory area . . . . .127
3.5.5Disabling core debug access . . . . .128
3.5.6Forcing boot from flash memory . . . . .128
3.6FLASH interrupts . . . . .129
3.7FLASH registers . . . . .130
3.7.1Flash access control register (FLASH_ACR) . . . . .130
3.7.2Flash power-down key register (FLASH_PDKEYR) . . . . .131
3.7.3Flash key register (FLASH_KEYR) . . . . .132
3.7.4Flash option key register (FLASH_OPTKEYR) . . . . .132
3.7.5Flash status register (FLASH_SR) . . . . .132
3.7.6Flash control register (FLASH_CR) . . . . .134
3.7.7Flash ECC register (FLASH_ECCR) . . . . .136
3.7.8Flash option register (FLASH_OPTR) . . . . .138
3.7.9Flash PCROP1 Start address register (FLASH_PCROP1SR) . . . . .140
3.7.10Flash PCROP1 End address register (FLASH_PCROP1ER) . . . . .141
3.7.11Flash Bank 1 WRP area A address register (FLASH_WRP1AR) . . . . .141
3.7.12Flash Bank 1 WRP area B address register (FLASH_WRP1BR) . . . . .142
3.7.13Flash PCROP2 Start address register (FLASH_PCROP2SR) . . . . .142
3.7.14Flash PCROP2 End address register (FLASH_PCROP2ER) . . . . .143
3.7.15Flash Bank 2 WRP area A address register (FLASH_WRP2AR) . . . . .143
3.7.16Flash Bank 2 WRP area B address register (FLASH_WRP2BR) . . . . .144

3.7.17 Flash securable area bank1 register (FLASH_SEC1R) . . . . . 145
3.7.18 Flash securable area bank2 register (FLASH_SEC2R) . . . . . 145
3.7.19 FLASH register map . . . . . 147

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