55. Revision history

Table 469. Document revision history

Date	Revision	Changes
08-Oct-2018	1	Initial release.
12-Apr-2019	2	Added: – Section 6.5.7: Flash registers privileged and unprivileged modes – Section 8.3.4: Upper voltage threshold monitoring – Section 8.3.5: Temperature threshold monitoring – Section 20.3: OCTOSPI implementation – Section 42.3.3: TAMP register write protection – Section 43.4.2: I2C pins and internal signals – Section 35.9.12: I2C autonomous mode control register (I2C_AUTOCR) – Section 52.9.14: I2C version register (I2C_VERR) – Section 52.9.15: I2C identification register (I2C_IPIDR) – Section 52.9.16: I2C size identification register (I2C_SIDR) – Section 48.8: SDMMC interrupts Updated: – Table 4: STM32L552xx and STM32L562xx memory map and peripheral register boundary addresses – Table 7: Boot modes when TrustZone is enabled (TZEN=1) – Table 8: Boot space versus RDP protection – Major changes to all sections (including figures, tables and registers) of Section 5: Global TrustZone® controller (GTZC) – Section 6.1: Introduction – Section 6.2: FLASH main features – Table 31: Flash module - 512 KB dual bank organization (64 bits read width) – Table 33: Flash module - 512 KB single bank organization (128 bits read width) – Section 6.3.5: Flash program and erase operations – Section 6.3.8: Flash errors flags – Section 6.4.2: Option bytes programming – Section 6.5.1: TrustZone security protection – Section 6.5.2: Secure watermark-based area protection – Table 37: Secure watermark-based area – Table 22: Secure hide protection – Section 5.5.4: Secure proprietary code readout protection (PCROP) – Section 6.5.4: Secure block-based area (SECBB) protection – Section 6.5.6: Flash security attribute state – Section 6.7: FLASH memory protection – Section 6.7.1: Write protection (WRP) – Major updates on content and tables of subsections of Section 6.7.2: Readout protection (RDP)

Date

Revision

Changes

08-Oct-2018

Initial release.

12-Apr-2019

Added:

Updated:

– Table 4: STM32L552xx and STM32L562xx memory map and peripheral register boundary addresses
– Table 7: Boot modes when TrustZone is enabled (TZEN=1)
– Table 8: Boot space versus RDP protection
– Major changes to all sections (including figures, tables and registers) of Section 5: Global TrustZone® controller (GTZC)
– Section 6.1: Introduction
– Section 6.2: FLASH main features
– Table 31: Flash module - 512 KB dual bank organization (64 bits read width)
– Table 33: Flash module - 512 KB single bank organization (128 bits read width)
– Section 6.3.5: Flash program and erase operations
– Section 6.3.8: Flash errors flags
– Section 6.4.2: Option bytes programming
– Section 6.5.1: TrustZone security protection
– Section 6.5.2: Secure watermark-based area protection
– Table 37: Secure watermark-based area
– Table 22: Secure hide protection
– Section 5.5.4: Secure proprietary code readout protection (PCROP)
– Section 6.5.4: Secure block-based area (SECBB) protection
– Section 6.5.6: Flash security attribute state
– Section 6.7: FLASH memory protection
– Section 6.7.1: Write protection (WRP)
– Major updates on content and tables of subsections of Section 6.7.2: Readout protection (RDP)

Table 469. Document revision history (continued)

Date	Revision	Changes
12-Apr-2019	2 (continued)	Updated: – Table 43: Flash memory readout protection status (TZEN=0) – Table 44: Access status versus protection level and execution modes when TZEN=0 – Table 45: Flash memory readout protection status (TZEN=1) – Table 46: Access status versus protection level and execution modes when TZEN=1 – Section 6.9.8: Flash status register (FLASH_SECSR) – Section 6.9.12: Flash option register (FLASH_OPTR) – Section 7.4.2: ICACHE reset and clocks – Section 7.4.5: ICACHE enable – Section 7.4.7: Address remapping – Figure 20: ICACHE remapping address mechanism – Table 61: ICACHE register map and reset values – Section 8: Power control (PWR) – Section 8.2.5: Dynamic voltage scaling management – Table 67: Functionalities depending on the working mode – Section 8.5: PWR TrustZone security – Section 11.6.6: GPIO port output data register (GPIOx_ODR) (x = A to H) – Section 11.6.12: GPIO secure configuration register (GPIOx_SECCFGR) (x = A to H) – Table 91: GPIO register map and reset values – Section 12.2: SYSCFG TrustZone security and privilege – Section Table 93.: BOOSTEN and ANASWVDD set/reset – Section 14.4.5: DMA channels – Section 14.6.3: DMA channel x configuration register (DMA_CCRx) – Table 101: DMAMUX instantiation – Section 15.4.6: DMAMUX request line multiplexer – Section 15.6.4: DMAMUX request generator channel x configuration register (DMAMUX_RGxCR) – Section 15.6.5: DMAMUX request generator interrupt status register (DMAMUX_RGSR) – Table 109: STM32L552xx and STM32L562xx vector table – All registers and tables of Section 18.4: CRC registers – Table 119: CRC register map and reset values – Section 20.1: OCTOSPI introduction – Section 20.4.1: OCTOSPI block diagram including all figures – Section 20.4.3: OCTOSPI interface to memory modes – Section 20.4.5: OCTOSPI regular-command protocol signal interface – Section 20.4.7: Specific features – Section 20.4.8: OCTOSPI operating mode introduction – Section 20.4.10: OCTOSPI automatic status-polling mode

Table 469. Document revision history (continued)

Date	Revision	Changes
12-Apr-2019	2 (continued)	Updated: – Section 20.4.12: OCTOSPI configuration introduction – Section 20.4.14: OCTOSPI device configuration – Section 20.4.15: OCTOSPI regular-command mode configuration – Section 20.4.17: OCTOSPI error management – Section 20.4.18: OCTOSPI BUSY and ABORT – Section 20.7.1: OCTOSPI control register (OCTOSPI_CR) – Section 20.7.2: OCTOSPI device configuration register 1 (OCTOSPI_DCR1) – Section 20.7.5: OCTOSPI device configuration register 4 (OCTOSPI_DCR4) – Section 21.2: ADC main features – Section 21.4.7: Single-ended and differential input channels – Section 21.4.9: ADC on-off control (ADEN, ADDIS, ADRDY) – Section 21.4.12: Channel-wise programmable sampling time (SMPR1, SMPR2) – Section 21.4.16: ADC timing – Table 171: TSAR timings depending on resolution – Table 175: Analog watchdog 2 and 3 comparison – Table 174: Analog watchdog 1 comparison – Figure 136: ADCy_AWDx_OUT signal generation (on all injected channels) – Section 21.4.31: Dual ADC modes – Figure 147: Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode – Figure 148: Interleaved mode on 1 channel in single conversion mode: dual ADC mode – Section 21.4.34: Monitoring the internal voltage reference – Section 22.4.13: Dual DAC channel conversion modes (if dual channels are available) – Section 22.7.17: DAC channel1 sample and hold sample time register (DAC_SHSR1) – Section 22.7.18: DAC channel2 sample and hold sample time register (DAC_SHSR2) – Section 24.6.1: Comparator 1 control and status register (COMP1_CSR) – Section 24.6.2: Comparator 2 control and status register (COMP2_CSR) – Table 206: DFSDM1 implementation – Major changes to all sections (including figures, tables and registers) of Section 28: True random number generator (RNG) – Section 29.4.5: AES decryption round key preparation – Section 29.4.8: AES basic chaining modes (ECB, CBC) – Section 29.4.10: AES Galois/counter mode (GCM) – Figure 215: Message construction in GMAC mode – Figure 216: GMAC authentication mode

Table 469. Document revision history (continued)

Date	Revision	Changes
12-Apr-2019	2 (continued)	Updated: – Figure 217: Message construction in CCM mode – Section 29.4.12: AES counter with CBC-MAC (CCM) – Section 29.4.14: AES key registers – Section 29.4.16: AES DMA interface – Section 29.7.2: AES status register (AES_SR) – Section 30.6.4: HASH digest registers – Section 30.6.7: HASH context swap registers – Major changes to all sections (including figures, tables and registers) of Section 32: Public key accelerator (PKA) – Section 33.3.8: PWM input mode – Section 33.4.2: TIMx control register 2 (TIMx_CR2)(x = 1, 8) – Section 33.4.20: TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) – Section 33.4.21: TIMx DMA control register (TIMx_DCR)(x = 1, 8) – Figure 291: General-purpose timer block diagram – Figure 317: Capture/Compare channel 1 main circuit – Section 34.3.3: Clock selection – Figure 318: Output stage of Capture/Compare channel (channel 1) – Section 34.4.1: TIMx control register 1 (TIMx_CR1)(x = 2 to 5) – Section 34.4.2: TIMx control register 2 (TIMx_CR2)(x = 2 to 5) – Section 34.4.5: TIMx status register (TIMx_SR)(x = 2 to 5) – Section 34.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) – Section 34.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 5) – Section 34.4.9: TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) – Section 34.4.11: TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 5) – Section 34.4.12: TIMx counter (TIMx_CNT)(x = 2 to 5) – Section 34.4.13: TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) – Figure 341: TIM15 block diagram – Figure 368: Output redirection – Section 35.5.2: TIM15 control register 2 (TIM15_CR2) – Section 35.5.5: TIM15 status register (TIM15_SR) – Section 35.5.7: TIM15 capture/compare mode register 1 (TIM15_CCMR1) – Section 35.5.8: TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) – Section 35.5.9: TIM15 capture/compare enable register (TIM15_CCER) – Section 35.5.16: TIM15 break and dead-time register (TIM15_BDTR) – Section 35.6.3: TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17)

Table 469. Document revision history (continued)

Date	Revision	Changes
12-Apr-2019	2 (continued)	Updated: – – Section 35.6.4: TIMx status register (TIMx_SR)(x = 16 to 17) – Section 35.6.6: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 16 to 17) – Section 35.6.7: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17) – Section 35.6.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) – Section 35.6.14: TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) – All registers on Section 36.4: TIM6/TIM7 registers – Figure 386: Low-power timer block diagram – Table 303: Effect of low-power modes on the LPTIM – Section 37.7.1: LPTIM interrupt and status register (LPTIM_ISR) – Section 37.7.2: LPTIM interrupt clear register (LPTIM_ICR) – Section 37.7.3: LPTIM interrupt enable register (LPTIM_IER) – Section 37.7.4: LPTIM configuration register (LPTIM_CFGR) – Major changes to all sections (including figures, tables and registers) of Section 39: Independent watchdog (IWDG) – Table 309: RTC internal input/output signals – Section 41.6.2: RTC date register (RTC_DR) – Figure 399: TAMP block diagram – Table 319: TAMP internal input/output signals – Table 320: TAMP interconnection – Section 42.3.6: Tamper detection – Section 42.6.1: TAMP control register 1 (TAMP_CR1) – Section 42.6.11: TAMP interrupt enable register (TAMP_IER) – Section 42.6.12: TAMP status register (TAMP_SR) – Section 42.6.13: TAMP non-secure masked interrupt status register (TAMP_MISR) – Section 42.6.14: TAMP secure masked interrupt status register (TAMP_SMISR) – Table 342: Effect of low-power modes to I2C – Table 343: I2C interrupt requests – Section 43.9.2: I2C control register 2 (I2C_CR2) – Section 43.9.3: I2C own address 1 register (I2C_OAR1) – Table 344: I2C register map and reset values – Section 44: Universal synchronous/asynchronous receiver transmitter (USART/UART) – Section 44.5.4: USART FIFOs and thresholds – Section 44.5.6: USART receiver – Figure 452: Reception using DMA – Table 354: USART interrupt requests – Registers and tables of Section 44.8: USART registers

Table 469. Document revision history (continued)

Date	Revision	Changes
12-Apr-2019	2 (continued)	Updated: – Section 45.4.4: LPUART FIFOs and thresholds – Figure 466: Reception using DMA – Table 365: LPUART interrupt requests – Registers and tables of Section 45.7: LPUART registers – Section 46.2: SPI main features – Section 46.3: SPI implementation – Section 47.4.12: SPDIF output – Section 48.4.4: SDMMC adapter – Table 396: Data path status flags and clear bits – Section 48.4.6: SDMMC AHB master interface – Section 48.5.2: CMD12 send timing – Section 48.9.10: SDMMC data counter register (SDMMC_DCNTR) – Section 48.9.11: SDMMC status register (SDMMC_STAR) – Major changes to all sections (including figures, tables and registers) of Section 49: FD controller area network (FDCAN) – Table 423: STM32L552xx and STM32L562xx USB implementation – Section 50.6.1: Common registers – Section 50.6.2: Buffer descriptor table – Section Table 433.: USB register map and reset values – Section 51.8.3: UCPD control register (UCPD_CR)

Table 469. Document revision history (continued)

Date	Revision	Changes
12-Jun-2019	3	Added: – Section 8.2.6: VDD12 domain and external SMPS – Table 262: ECC Fp scalar multiplication (Fast Mode) – Figure 25: Internal main regulator overview – Section 47.3: SAI implementation – Table 356: STM32L5 Series SAI features – Table 373: External synchronization selection – Table 374: MCLK_x activation conditions – Table 377: TDM frame configuration examples Updated: – Section 6.2: FLASH main features – Section 6.3.6: Flash main memory erase sequences – Section 6.3.8: Flash errors flags – Table 35: User option byte organization mapping – Section 6.4.2: Option bytes programming – Section 6.5.1: TrustZone security protection – Table 36: Default secure option bytes after TZEN activation – Table 22: Secure hide protection – Table 38: Secure, HDP protections summary – Section 6.7: FLASH memory protection – Section 6.7.1: Write protection (WRP) – Table 47: Flash access versus RDP level when TrustZone is active (TZEN=1) – Table 48: Flash access versus RDP level when TrustZone is disabled (TZEN=0) – Table 49: Flash mass erase versus RDP level when TrustZone is active (TZEN = 1) – Section 6.9.7: Flash status register (FLASH_NSSR) – Section 6.9.8: Flash status register (FLASH_SECSR) – Section 6.9.10: Flash secure control register (FLASH_SECCR) – Section 6.9.12: Flash option register (FLASH_OPTR) – Section 6.9.17: Flash secure watermark1 register 2 (FLASH_SECWM1R2) – Section 6.9.21: Flash secure watermark2 register 2 (FLASH_SECWM2R2) – Table 53: Flash interface - register map and reset values – Section 8.1: Power supplies and supply domains – Section 8.2.2: Embedded SMPS step down converter – Section 8.2.3: SMPS step down converter power supply scheme – Section 9.8.10: RCC AHB1 peripheral reset register (RCC_AHB1RSTR) – Table 82: RCC register map and reset values – Table 86: Effect of low-power modes on CRS – Section 12.3.11: SYSCFG RSS command register (SYSCFG_RSSCMDR) – Table 94: SYSCFG register map and reset values – Section 20.4.15: OCTOSPI regular-command mode configuration – Section 20.7.1: OCTOSPI control register (OCTOSPI_CR) – Section 20.7.2: OCTOSPI device configuration register 1 (OCTOSPI_DCR1)

Date

Revision

Changes

12-Jun-2019

Added:

Updated:

Table 469. Document revision history (continued)

Date	Revision	Changes
12-Jun-2019	3 (continued)	Updated (cont): – Section 24.6.1: Comparator 1 control and status register (COMP1_CSR) – Table 195: COMP1 input plus assignment – Table 201: COMP register map and reset values – Section 28.2: RNG main features – Section 28.3.3: Random number generation – Section 28.3.5: RNG operation – Section 28.5: RNG processing time – Table 28.5: RNG processing time – Table 223: RNG configurations – Section 28.7.4: RNG health test control register (RNG_HTCR) – Section 29.1: Introduction – Section 29.4.3: AES cryptographic core – Section 29.4.4: AES procedure to perform a cipher operation – Section 29.4.8: AES basic chaining modes (ECB, CBC) – Section 29.4.12: AES counter with CBC-MAC (CCM) – Table 232: AES interrupt requests – Section 30.4.5: Message digest computing – Section 30.6.1: HASH control register (HASH_CR) – Section 30.6.2: HASH data input register (HASH_DIN) – Major changes to all Section 31: On-the-fly decryption engine (OTFDEC) – Major changes to all Section 32: Public key accelerator (PKA) – External clock source mode 2 on Section 33.3.5: Clock selection – Section 33.4.5: TIMx status register (TIMx_SR)(x = 1, 8) – Section 33.4.11: TIMx capture/compare enable register (TIMx_CCER)(x = 1, 8) – Major changes to all Section 37: Low-power timer (LPTIM) – Section 42.2: TAMP main features – Table 320: TAMP interconnection – Section 44.8.9: USART interrupt and status register (USART_ISR) – Section 44.8.12: USART receive data register (USART_RDR) – Section 44.8.13: USART transmit data register (USART_TDR) – Major changes to all Section 47: Serial audio interface (SAI) – Major changes to all Section 51: USB Type-C ^®/USB Power Delivery interface (UCPD) – Section 52.11.1: DBGMCU registers Deleted: – Sections ECC complete addition, ECC double base ladder and ECC projective to affine from Section 22: Public key accelerator (PKA) – Tables Modular exponentiation (protected mode), ECC complete addition, ECC double base ladder, ECC projective to affine from Section 22: Public key accelerator (PKA) – Section Secure proprietary code readout protection (PCROP) from Section 5: Embedded flash memory (FLASH)

Date

Revision

Changes

12-Jun-2019

3
(continued)

Updated (cont):

– Section 24.6.1: Comparator 1 control and status register (COMP1_CSR)
– Table 195: COMP1 input plus assignment
– Table 201: COMP register map and reset values
– Section 28.2: RNG main features
– Section 28.3.3: Random number generation
– Section 28.3.5: RNG operation
– Section 28.5: RNG processing time
– Table 28.5: RNG processing time
– Table 223: RNG configurations
– Section 28.7.4: RNG health test control register (RNG_HTCR)
– Section 29.1: Introduction
– Section 29.4.3: AES cryptographic core
– Section 29.4.4: AES procedure to perform a cipher operation
– Section 29.4.8: AES basic chaining modes (ECB, CBC)
– Section 29.4.12: AES counter with CBC-MAC (CCM)
– Table 232: AES interrupt requests
– Section 30.4.5: Message digest computing
– Section 30.6.1: HASH control register (HASH_CR)
– Section 30.6.2: HASH data input register (HASH_DIN)
– Major changes to all Section 31: On-the-fly decryption engine (OTFDEC)
– Major changes to all Section 32: Public key accelerator (PKA)
– External clock source mode 2 on Section 33.3.5: Clock selection
– Section 33.4.5: TIMx status register (TIMx_SR)(x = 1, 8)
– Section 33.4.11: TIMx capture/compare enable register (TIMx_CCER)(x = 1, 8)
– Major changes to all Section 37: Low-power timer (LPTIM)
– Section 42.2: TAMP main features
– Table 320: TAMP interconnection
– Section 44.8.9: USART interrupt and status register (USART_ISR)
– Section 44.8.12: USART receive data register (USART_RDR)
– Section 44.8.13: USART transmit data register (USART_TDR)
– Major changes to all Section 47: Serial audio interface (SAI)
– Major changes to all Section 51: USB Type-C ^®/USB Power Delivery interface (UCPD)
– Section 52.11.1: DBGMCU registers

Deleted:

– Sections ECC complete addition, ECC double base ladder and ECC projective to affine from Section 22: Public key accelerator (PKA)
– Tables Modular exponentiation (protected mode), ECC complete addition, ECC double base ladder, ECC projective to affine from Section 22: Public key accelerator (PKA)
– Section Secure proprietary code readout protection (PCROP) from Section 5: Embedded flash memory (FLASH)

Table 469. Document revision history (continued)

Date	Revision	Changes
11-Oct-2019	4	Updated: – Section 2: Memory and bus architecture introduction – Figure 2: Memory map based on IDAU mapping. – Section 3: Boot configuration – Section 5.3.5: TrustZone illegal access controller (TZIC) – Section 5.3.6: Power-on/reset state – Section 5.3.5: TrustZone illegal access controller (TZIC) – Section 5.5.6: GTZC_TZSC external memory x non-secure watermark register 1 (GTZC_TZSC_MPCWMxANSR) – Section 5.5.7: GTZC_TZSC external memory x non-secure watermark register 2 (GTZC_TZSC_MPCWMxBNSR) – Section 5.6.2: GTZC_MPCBB1 lock register 1(GTZC_MPCBB1_LCKVTR1) – Section : Rules for modifying specific option bytes – Section : Level 1: readout protection – Section : Level 2: no debug – Section : Level 1: readout protection – Section : Level 2: no debug – Section 6.9.15: Flash secure boot address 0 register (FLASH_SECBOOTADD0R) – Section 8.2.2: Embedded SMPS step down converter – Table 62: SMPS modes summary – Section 8.2.3: SMPS step down converter power supply scheme – Section 8.2.4: SMPS step down converter versus low-power mode – Section 8.2.5: Dynamic voltage scaling management – Section 9.3: Clocks introduction – Section 9.3.3: MSI clock – Caution note in Section 9.8.4: RCC PLL configuration register (RCC_PLLCFGR) – Section 10.1: CRS introduction – Section 10.4.4: Frequency error measurement – Section 10.4.6: CRS initialization and configuration – Section 10.7: CRS registers – Section 11.3: GPIO functional description – Section 11.4: TrustZone security – Section 11.6.3: GPIO port output speed register (GPIOx_OSPEEDR) (x = A to H) – Section 17.6.7: EXTI privilege configuration register (EXTI_PRIVCFGGR1) – Section 17.6.16: EXTI lock register (EXTI_LOCKR) – Section 17.6.16: EXTI lock register (EXTI_LOCKR) – Section 19.6.4: NOR flash/PSRAM controller asynchronous transactions – Section 19.6.5: Synchronous transactions – Figure 93: ADC block diagram – Table 165: ADC internal input/output signals – Section 21.4.7: Single-ended and differential input channels – Section 21.4.11: Channel selection (ADC_SQRY, ADC_JSQR) – Section 21.4.20: Discontinuous mode (DISCEN, DISCNUM, JDISCEN) – Section 21.4.26: Data management – Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

Table 469. Document revision history (continued)

Date	Revision	Changes
11-Oct-2019	4 (continued)	– Section 21.7.6: ADC sample time register 1 (ADC_SMPR1) – Section 21.7.7: ADC sample time register 2 (ADC_SMPR2) – Section 21.7.11: ADC regular sequence register 1 (ADC_SQR1) – Section 21.7.12: ADC regular sequence register 2 (ADC_SQR2) – Section 21.7.13: ADC regular sequence register 3 (ADC_SQR3) – Section 21.7.14: ADC regular sequence register 4 (ADC_SQR4) – Section 21.7.16: ADC injected sequence register (ADC_JSQR) – Section 21.7.17: ADC offset y register (ADC_OF Ry) – Section 21.7.19: ADC analog watchdog 2 configuration register (ADC_AWD2CR) – Section 21.7.20: ADC analog watchdog 3 configuration register (ADC_AWD3CR) – Section 21.7.21: ADC differential mode selection register (ADC_DIFSEL) – Section 22.3: DAC implementation – Section 22.4.6: DAC trigger selection – Section 22.4.10: DAC channel modes – Section 22.4.11: DAC channel buffer calibration – Section 22.4.13: Dual DAC channel conversion modes (if dual channels are available) – Table 190: DAC interrupts – Section 22.7.1: DAC control register (DAC_CR) – Section 26.2: DFSDM main features – Section 26.4.3: DFSDM reset and clocks – Section 26.7: DFSDM channel y registers (y=0..3) introduction – Section 26.7.5: DFSDM channel y data input register (DFSDM_CHyDATINR) – Section 26.8: DFSDM filter x module registers (x=0..3) introduction – Table 216: Spread spectrum deviation versus AHB clock frequency – Section 28.2: RNG main features – Section 28.3.5: RNG operation – Section 28.5: RNG processing time – Section 28.7.3: RNG data register (RNG_DR) – Figure 211: CTR encryption – Section 30: Hash processor (HASH) – Section 33.3.3: Repetition counter – Table 285: TIMx internal trigger connection – Section 35.5: TIM15 registers introduction – Section 35.6: TIM16/TIM17 registers introduction – Figure 386: Low-power timer block diagram – Section 37.4.16: Repetition counter – Section 37.6: LPTIM interrupts – Section 37.7.8: LPTIM counter register (LPTIM_CNT) – Section 40: System window watchdog (WWDG) – Section 42.6.2: TAMP control register 2 (TAMP_CR2) – Table 354: USART interrupt requests – Table 44.8: USART registers introduction – Table 45.7: LPUART registers introduction – Table 371: SAI internal input/output signals – Figure 497: Start-up sequence

Table 469. Document revision history (continued)

Date	Revision	Changes
11-Oct-2019	4 (continued)	– Table 381: SAI interrupt sources – Section 47.6: SAI registers introduction Added – Section 6.5.5: Forcing boot from a secure memory address – Section 10.3: CRS implementation Deleted: – 3.6.3 GTZC_MPCBBx lock register 2 (GTZC_MPCBBx_LCKVTR2) (x = 1 to 2)
13-Feb-2020	5	Updated cover page. Updated Section 2: Memory and bus architecture introduction. Updated Section 2.1: System architecture introduction. Updated Figure 1: System architecture . Updated Section 3: Boot configuration . Added Section 4: System security . FLASH: Updated Section 6.3.1: Flash memory organization . Updated Table 31: Flash module - 512 KB dual bank organization (64 bits read width) . Updated Table 33: Flash module - 512 KB single bank organization (128 bits read width) . Updated Section 6.3.5: Flash program and erase operations . Updated Section 6.3.6: Flash main memory erase sequences . Updated Section 6.3.7: Flash main memory programming sequences . Updated Section 6.3.8: Flash errors flags . Updated Section 6.4.1: Option bytes description . Updated Section 6.4.2: Option bytes programming . Updated Section 6.5.1: TrustZone security protection . Updated Section 6.5.3: Secure hide protection (HDP) . Updated Table 38: Secure, HDP protections summary . Updated Section 6.5.4: Secure block-based area (SECB) protection . Added Section 6.6: Secure system memory . Updated Section 6.7.2: Readout protection (RDP) . Updated Table 43: Flash memory readout protection status (TZEN=0) . Updated Table 45: Flash memory readout protection status (TZEN=1) . Updated Table 50: Flash system memory, RSS and OTP accesses . Updated Section 6.9.7: Flash status register (FLASH_NSSR) . Updated Section 6.9.11: Flash ECC register (FLASH_ECCR) . PWR: Updated Figure 21: STM32L552xx and STM32L562xx power supply overview . Updated Figure 22: STM32L552xxxP and STM32L562xxxP power supply overview . Updated Table 64: SMPS step down converter versus low-power modes . Updated Section 8.2.6: VDD12 domain and external SMPS . Updated Section 8.3.4: Upper voltage threshold monitoring . Updated Section 8.3.5: Temperature threshold monitoring . RCC: Updated Section 9.8.1: RCC clock control register (RCC_CR) . Added Section 9.8.33: OCTOSPI delay configuration register (RCC_DLYCFGR) .

Date

Revision

Changes

11-Oct-2019

4
(continued)

– Table 381: SAI interrupt sources
– Section 47.6: SAI registers introduction
Added
– Section 6.5.5: Forcing boot from a secure memory address
– Section 10.3: CRS implementation
Deleted:
– 3.6.3 GTZC_MPCBBx lock register 2 (GTZC_MPCBBx_LCKVTR2) (x = 1 to 2)

13-Feb-2020

Updated cover page.

Updated Section 2: Memory and bus architecture introduction.

Updated Section 2.1: System architecture introduction.

Updated Figure 1: System architecture .

Updated Section 3: Boot configuration .

Added Section 4: System security .

FLASH:

Updated Section 6.3.1: Flash memory organization .

Updated Table 31: Flash module - 512 KB dual bank organization (64 bits read width) .

Updated Table 33: Flash module - 512 KB single bank organization (128 bits read width) .

Updated Section 6.3.5: Flash program and erase operations .

Updated Section 6.3.6: Flash main memory erase sequences .

Updated Section 6.3.7: Flash main memory programming sequences .

Updated Section 6.3.8: Flash errors flags .

Updated Section 6.4.1: Option bytes description .

Updated Section 6.4.2: Option bytes programming .

Updated Section 6.5.1: TrustZone security protection .

Updated Section 6.5.3: Secure hide protection (HDP) .

Updated Table 38: Secure, HDP protections summary .

Updated Section 6.5.4: Secure block-based area (SECB) protection .

Added Section 6.6: Secure system memory .

Updated Section 6.7.2: Readout protection (RDP) .

Updated Table 43: Flash memory readout protection status (TZEN=0) .

Updated Table 45: Flash memory readout protection status (TZEN=1) .

Updated Table 50: Flash system memory, RSS and OTP accesses .

Updated Section 6.9.7: Flash status register (FLASH_NSSR) .

Updated Section 6.9.11: Flash ECC register (FLASH_ECCR) .

PWR:

Updated Figure 21: STM32L552xx and STM32L562xx power supply overview .

Updated Figure 22: STM32L552xxxP and STM32L562xxxP power supply overview .

Updated Table 64: SMPS step down converter versus low-power modes .

Updated Section 8.2.6: VDD12 domain and external SMPS .

Updated Section 8.3.4: Upper voltage threshold monitoring .

Updated Section 8.3.5: Temperature threshold monitoring .

RCC:

Updated Section 9.8.1: RCC clock control register (RCC_CR) .

Added Section 9.8.33: OCTOSPI delay configuration register (RCC_DLYCFGR) .

Table 469. Document revision history (continued)

Date	Revision	Changes
13-Feb-2020	5 (continued)	SYSCFG: Updated Section 12.3.11: SYSCFG RSS command register (SYSCFG_RSSCMR) . NVIC: Updated Section 16.1: NVIC main features . OCTOSPI: Updated entire Section 20: Octo-SPI interface (OCTOSPI) . ADC: Updated Section 21.2: ADC main features . Updated Section : Reading the temperature . Updated Section : Calculating the actual V _REF+voltage using the internal reference voltage . VREFBUF: Added Section 23.3: VREFBUF trimming . Updated Section 23.4.2: VREFBUF calibration control register (VREFBUF_CCR) . RNG: Updated Section 28.1: RNG introduction . Updated Section 28.3.3: Random number generation . Updated Section 28.6.3: Data collection . PKA: Added Section 32.3.3: PKA reset and clocks . Updated Table 258: Arithmetic comparison . Updated Table 269: Modular exponentiation computation times . Updated Table 270: ECC scalar multiplication computation times . Updated Table 271: ECDSA signature average computation times . Updated Table 272: ECDSA verification average computation times . Updated Table 274: Montgomery parameters average computation times . USART: Updated Table 44.8.6: USART guard time and prescaler register (USART_GTPR) . LPUART: Added Table 45.3: LPUART implementation . FDCAN: Updated Figure 550: Message RAM configuration .

Table 469. Document revision history (continued)

Date	Revision	Changes
29-Apr-2020	6	Memory and bus architecture: Updated Section 2: Memory and bus architecture . Updated Section 2.1: System architecture . Updated Section 2.2: TrustZone security architecture . Updated Table 1: Example of memory map security attribution versus SAU regions configuration . Updated Section 2.2.1: Default TrustZone security state . Updated Section 2.2.2: TrustZone peripheral classification . Updated Table 2: Securable peripherals by TZSC . Updated Table 3: TrustZone-aware peripherals . Memory organization: Updated Section 2: Memory and bus architecture . Updated Section 2.1: System architecture . Embedded SRAM: Updated Section 2.4.1: SRAM2 parity check . Updated Section 2.4.2: SRAM2 Write protection . Updated Section 2.4.4: SRAM2 Erase . Embedded flash memory: Updated Section 6.7.2: Readout protection (RDP) notes. Updated Reset value by ST production value and SWAP_BANK bit description in Section 6.9.12: Flash option register (FLASH_OPTR) . Updated Reset value by ST production value in: – Section 6.9.13: Flash non-secure boot address 0 register (FLASH_NSBOOTADD0R) – Section 6.9.14: Flash non-secure boot address 1 register (FLASH_NSBOOTADD1R) – Section 6.9.15: Flash secure boot address 0 register (FLASH_SECBOOTADD0R) – Section 6.9.16: Flash bank 1 secure watermark1 register (FLASH_SECWM1R1) – Section 6.9.17: Flash secure watermark1 register 2 (FLASH_SECWM1R2) – Section 6.9.18: Flash WPR1 area A address register (FLASH_WRP1AR) – Section 6.9.19: Flash WPR1 area B address register (FLASH_WRP1BR) – Section 6.9.20: Flash secure watermark2 register (FLASH_SECWM2R1) – Section 6.9.21: Flash secure watermark2 register 2 (FLASH_SECWM2R2) – Section 6.9.22: Flash WPR2 area A address register (FLASH_WRP2AR) – Section 6.9.23: Flash WPR2 area B address register (FLASH_WRP2BR) – Table 53: Flash interface - register map and reset values ICACHE: Added Section 7.3: ICACHE implementation . Updated Figure 18: ICACHE block diagram . Updated Section 7.4.3: ICACHE TAG memory . Updated Table 55: TAG memory dimensioning parameters for n-way set associative operating mode (default) . Updated Figure 19: ICACHE TAG and data memories functional view . Updated Table 56: TAG memory dimensioning parameters for direct-mapped cache mode . Updated Section 7.4.5: ICACHE enable . Updated Table 61: ICACHE register map and reset values .

Date

Revision

Changes

29-Apr-2020

Memory and bus architecture:

Updated Section 2: Memory and bus architecture .

Updated Section 2.1: System architecture .

Updated Section 2.2: TrustZone security architecture .

Updated Table 1: Example of memory map security attribution versus SAU regions configuration .

Updated Section 2.2.1: Default TrustZone security state .

Updated Section 2.2.2: TrustZone peripheral classification .

Updated Table 2: Securable peripherals by TZSC .

Updated Table 3: TrustZone-aware peripherals .

Memory organization:

Updated Section 2: Memory and bus architecture .

Updated Section 2.1: System architecture .

Embedded SRAM:

Updated Section 2.4.1: SRAM2 parity check .

Updated Section 2.4.2: SRAM2 Write protection .

Updated Section 2.4.4: SRAM2 Erase .

Embedded flash memory:

Updated Section 6.7.2: Readout protection (RDP) notes.

Updated Reset value by ST production value and SWAP_BANK bit description in Section 6.9.12: Flash option register (FLASH_OPTR) .

Updated Reset value by ST production value in:

ICACHE:

Added Section 7.3: ICACHE implementation .

Updated Figure 18: ICACHE block diagram .

Updated Section 7.4.3: ICACHE TAG memory .

Updated Table 55: TAG memory dimensioning parameters for n-way set associative operating mode (default) .

Updated Figure 19: ICACHE TAG and data memories functional view .

Updated Table 56: TAG memory dimensioning parameters for direct-mapped cache mode .

Updated Section 7.4.5: ICACHE enable .

Updated Table 61: ICACHE register map and reset values .

Table 469. Document revision history (continued)

Date	Revision	Changes
29-Apr-2020	6 (continued)	SYSTEM SECURITY: Updated Section 4.6.6: Managing security in TrustZone-aware peripherals 'General-purpose I/Os (GPIO)' paragraph. Added Table 16: Summary of the I/Os that can be secured and connected to a non-secure peripheral . PWR: Updated Section 8.2.2: Embedded SMPS step down converter . Updated Table 62: SMPS modes summary note 1. Removed below the table. Updated Section 8.2.4: SMPS step down converter versus low-power mode . Updated Table 64: SMPS step down converter versus low-power modes . Added notes below the table. Moved Section 8.2.1: Voltage regulator before Section 8.2.2: Embedded SMPS step down converter . Updated Section 8.2.6: VDD12 domain and external SMPS . SYSCFG: Updated Table 92: TrustZone security and privilege register accesses . TSC: Updated Section 27.3.2: Surface charge transfer acquisition overview . Updated Section 27.3.4: Charge transfer acquisition sequence . Updated Figure 191: Charge transfer acquisition sequence . PKA: Updated Section 32.7.4: PKA RAM adding note. IRTIM: Added Figure 394: IRTIM internal hardware connections with TIM16 and TIM17 . USART: Replaced 'microcontroller' by 'device' in the whole document. Updated Section 44.4: USART implementation and Section 45.3: LPUART implementation . Updated PSC bitfield description in USART_GTPR register. Updated SBKF bit description in USART_ISR and LPUART_ISR registers. Updated decimal and hexadecimal notation for values in Section : How to derive USARTDIV from USART_BRR register values . SDMMC: Updated Section 48.1: SDMMC main features . DEBUG: Updated Section 52.11.1: DBGMCU registers : – DBGMCU identity code register (DBGMCU_IDCODE) – DBGMCU APB1 freeze register 1 (DBGMCU_APB1FZR1) – DBGMCU APB1 freeze register 2 (DBGMCU_APB1FZR2) Updated Table 468: DBGMCU register map and reset values .

Table 469. Document revision history (continued)

Date	Revision	Changes
07-Dec-2020	7	Updated: System security: – Section 4.4.1: Introduction – Section 4.4.3: Immutable root of trust in system flash memory – Section : Securing peripherals with TZSC – Table 10: MPCWMx instances – Section : General-purpose I/Os (GPIO) – Table 16: Summary of the I/Os that can be secured and connected to a non-secure peripheral – Section : Extended interrupts and event controller (EXTI) – Section 4.6.7: Activating TrustZone security – Figure 8: Flash memory secure hide protection (HDP) area – Section : Response to tampers – Section 4.9.1: Introduction – Section 4.11.2: Recommended option byte settings – Figure 13: External flash memory protection using SFI Embedded flash memory (FLASH): – Section 6.7.2: Readout protection (RDP) – Section 6.9.12: Flash option register (FLASH_OPTR) – Table 53: Flash interface - register map and reset values Power control (PWR): – Section 8.2.2: Embedded SMPS step down converter – Section 8.2.6: VDD12 domain and external SMPS – Section 8.3.1: Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) – Section 8.3.2: Programmable voltage detector (PVD) – Table 67: Functionalities depending on the working mode – Section : I/O states in Low-power run mode – Section 8.6.3: Power control register 3 (PWR_CR3) Clock recovery system (CRS): – Section 10.7.1: CRS control register (CRS_CR) Direct memory access controller (DMA): – Section 14.6.3: DMA channel x configuration register (DMA_CCRx) – Section 14.6.4: DMA channel x number of data to transfer register (DMA_CNDTRx) – Section 14.6.5: DMA channel x peripheral address register (DMA_CPARx) – Section 14.6.6: DMA channel x memory 0 address register (DMA_CM0ARx) – Section 14.6.7: DMA channel x memory 1 address register (DMA_CM1ARx) DMA request multiplexer (DMAMUX): – Section 15.4.6: DMAMUX request line multiplexer Octo-SPI interface (OCTOSPI): – Major updates in the whole section Analog-to-digital converters (ADC): – Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) – Section 21.4.7: Single-ended and differential input channels – Figure 103: Stopping ongoing regular and injected conversions

Date

Revision

Changes

07-Dec-2020

Updated:

System security:

Embedded flash memory (FLASH):

Power control (PWR):

Clock recovery system (CRS):

– Section 10.7.1: CRS control register (CRS_CR)

Direct memory access controller (DMA):

DMA request multiplexer (DMAMUX):

– Section 15.4.6: DMAMUX request line multiplexer

Octo-SPI interface (OCTOSPI):

– Major updates in the whole section

Analog-to-digital converters (ADC):

Table 469. Document revision history (continued)

Date	Revision	Changes
07-Dec-2020	7 (continued)	Update (continued): Analog-to-digital converters (ADC) (continued): – Section 21.4.19: Injected channel management – Figure 129: AUTODLY = 1, regular HW conversions interrupted by injected conversions (DISCEN = 1, JDISCEN = 1) – Figure 132: Analog watchdog guarded area – Section 21.4.34: Monitoring the internal voltage reference Digital-to-analog converter (DAC): – In this section, DAC_OUTx was replaced by DACxOUTy – Figure 163: Dual-channel DAC block diagram – Table 185: DAC input/output pins Voltage reference buffer (VREFBUF): – Section 23.4.2: VREFBUF calibration control register (VREFBUF_CCR) AES hardware accelerator (AES): – Section : GCM processing – Section 29.5: AES interrupts – Section 29.7.1: AES control register (AES_CR) – Section 29.7.17: AES suspend registers (AES_SUSPxR) – Table 235: AES register map and reset values Hash processor (HASH): – In this section “NBLW” is now referred to as “NBLW[4:0]” – Section 30.4.5: Message digest computing – Section : HMAC processing – Section 30.6.1: HASH control register (HASH_CR) – Section 30.6.7: HASH context swap registers – Table 240: HASH register map and reset values On-the-fly decryption engine (OTFDEC): – Section : OTFDEC architecture – Section 31.5.1: OTFDEC initialization process – Section 31.6.1: OTFDEC control register (OTFDEC_CR) – Section 31.6.2: OTFDEC privileged access control configuration register (OTFDEC_PRIVCFGR) – Section 31.6.3: OTFDEC region x configuration register (OTFDEC_RxCFGR) Public key accelerator (PKA): – Section 32.3.4: PKA public key acceleration – Section : Montgomery space and fast mode operations – Section 32.3.6: PKA procedure to perform an operation – Section : Using precomputed Montgomery parameters (PKA fast mode) – Section 32.5.1: Supported elliptic curves – Table 268: Family of supported curves for ECC operations – Table 269: Modular exponentiation computation times – Table 273: Point on elliptic curve Fp check average computation times – Table 274: Montgomery parameters average computation times – Table 275: PKA interrupt requests – Section 32.7.2: PKA status register (PKA_SR) – Section 32.7.3: PKA clear flag register (PKA_CLRFR)

Date

Revision

Changes

07-Dec-2020

7
(continued)

Update (continued):

Analog-to-digital converters (ADC) (continued):

Digital-to-analog converter (DAC):

– In this section, DAC_OUTx was replaced by DACxOUTy
– Figure 163: Dual-channel DAC block diagram
– Table 185: DAC input/output pins

Voltage reference buffer (VREFBUF):

– Section 23.4.2: VREFBUF calibration control register (VREFBUF_CCR)

AES hardware accelerator (AES):

Hash processor (HASH):

– In this section “NBLW” is now referred to as “NBLW[4:0]”
– Section 30.4.5: Message digest computing
– Section : HMAC processing
– Section 30.6.1: HASH control register (HASH_CR)
– Section 30.6.7: HASH context swap registers
– Table 240: HASH register map and reset values

On-the-fly decryption engine (OTFDEC):

Public key accelerator (PKA):

Table 469. Document revision history (continued)

Date	Revision	Changes
07-Dec-2020	7 (continued)	Update (continued): General-purpose timers (TIM2/TIM3/TIM4/TIM5): – Figure 315: Control circuit in external clock mode 2 Universal synchronous/asynchronous receiver transmitter (USART/UART): – Section 44.2: USART main features – Table 346: USART / LPUART features – Section 44.5.7: USART baud rate generation – Figure 454: RS232 RTS flow control – Figure 455: RS232 CTS flow control – Section 44.6: USART in low-power modes – Section 44.7: USART interrupts – Section 44.8.8: USART request register (USART_RQR) – Section 44.8.9: USART interrupt and status register (USART_ISR) – Section 44.8.10: USART interrupt and status register [alternate] (USART_ISR) Low-power universal asynchronous receiver transmitter (LPUART): – Table 346: USART / LPUART features – Table 360: Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz – Section 45.5: LPUART in low-power modes – Table 364: Effect of low-power modes on the LPUART – Table 365: LPUART interrupt requests Serial peripheral interface (SPI): – Table 367: STM32L552xx and STM32L562xx SPI implementation – Section 46.4.2: Communications between one master and one slave Serial audio interface (SAI): – Table 370: SAI features Secure digital input/output MultiMediaCard interface (SDMMC): – Section 48.9.2: SDMMC clock control register (SDMMC_CLKCR) FD controller area network (FDCAN): – Section 49.3.6: Message RAM – Figure 550: Message RAM configuration USB Type-C™ / USB Power Delivery interface (UCPD): – Section 51.1: UCPD introduction – Section 51.2: UCPD main features – Section 51.4.6: UCPD Type-C pull-ups (Rp) and pull-downs (Rd) – Section 51.8.1: UCPD configuration register 1 (UCPD_CFGR1) – Section 51.8.3: UCPD control register (UCPD_CR) – Section Table 445.: UCPD register map and reset values Added: – Table 15: Summary of the I/Os that cannot be connected to a non-secure peripheral when secure – Section 51.7.3: UCPD configuration register 2 (UCPD_CFGR3) Deleted: – On Section 45.3: LPUART implementation : Table USART /LPUART features – On Section 48.4: SDMMC functional description : Section Hardware flow control

Date

Revision

Changes

07-Dec-2020

7
(continued)

Update (continued):

General-purpose timers (TIM2/TIM3/TIM4/TIM5):

– Figure 315: Control circuit in external clock mode 2

Universal synchronous/asynchronous receiver transmitter (USART/UART):

Low-power universal asynchronous receiver transmitter (LPUART):

Serial peripheral interface (SPI):

Serial audio interface (SAI):

– Table 370: SAI features

Secure digital input/output MultiMediaCard interface (SDMMC):

– Section 48.9.2: SDMMC clock control register (SDMMC_CLKCR)

FD controller area network (FDCAN):

USB Type-C™ / USB Power Delivery interface (UCPD):

Added:

Deleted:

– On Section 45.3: LPUART implementation : Table USART /LPUART features
– On Section 48.4: SDMMC functional description : Section Hardware flow control

Table 469. Document revision history (continued)

Date	Revision	Changes
03-Jun-2025	8	Cover page: Added patented technology notice. Added errata sheet reference. Documentation conventions: Updated Section 1.1: General information . Updated Section 1.2: List of abbreviations for registers . Added Section 1.3: Register reset value . Memory and bus architecture: Updated Section : Embedded bootloader and RSS . Memory and bus architecture: Updated Section : Embedded bootloader and RSS . FLASH: Updated Section 6.3.1: Flash memory organization . Added Table 30: Flash module - 256 KB dual bank organization (64 bits read width) . Updated Table 31: Flash module - 512 KB dual bank organization (64 bits read width) . Added Table 32: Flash module - 256 KB single bank organization (128 bits read width) . Updated Table 33: Flash module - 512 KB single bank organization (128 bits read width) . ICACHE: Whole section re-edited. PWR: Updated Section 8.1.4: Battery backup domain . Updated Section 8.2.3: SMPS step down converter power supply scheme . Updated Figure 24: SMPS step down converter power supply scheme . Updated Section 8.3.2: Programmable voltage detector (PVD) . Updated Section 8.6.2: Power control register 2 (PWR_CR2) . Updated Section 8.6.6: Power status register 2 (PWR_SR2) . RCC: Updated Section 9.1.2: System reset . Updated Section : Software calibration . Updated Section 9.8.8: RCC clock interrupt flag register (RCC_CIFR) . Updated Section 9.8.29: RCC Backup domain control register (RCC_BDCR) . CRS: Whole section re-edited. RCC: Updated Section 11.3.2: I/O pin alternate function multiplexer and mapping . DMAMUX: Updated Section 15.3.2: DMAMUX mapping . Updated Section 15.4.6: DMAMUX request line multiplexer . Updated Section 15.4.7: DMAMUX request generator . NVIC: Updated Table 109: STM32L552xx and STM32L562xx vector table . CRC: Updated Section 18.2: CRC main features . Updated Table 51: CRC calculation unit block diagram . Updated Section 18.3.3: CRC operation .

Date

Revision

Changes

03-Jun-2025

Cover page:
Added patented technology notice.
Added errata sheet reference.

Documentation conventions:
Updated Section 1.1: General information .
Updated Section 1.2: List of abbreviations for registers .
Added Section 1.3: Register reset value .

Memory and bus architecture:
Updated Section : Embedded bootloader and RSS .

FLASH:
Updated Section 6.3.1: Flash memory organization .
Added Table 30: Flash module - 256 KB dual bank organization (64 bits read width) .
Updated Table 31: Flash module - 512 KB dual bank organization (64 bits read width) .
Added Table 32: Flash module - 256 KB single bank organization (128 bits read width) .
Updated Table 33: Flash module - 512 KB single bank organization (128 bits read width) .

ICACHE:
Whole section re-edited.

PWR:
Updated Section 8.1.4: Battery backup domain .
Updated Section 8.2.3: SMPS step down converter power supply scheme .
Updated Figure 24: SMPS step down converter power supply scheme .
Updated Section 8.3.2: Programmable voltage detector (PVD) .
Updated Section 8.6.2: Power control register 2 (PWR_CR2) .
Updated Section 8.6.6: Power status register 2 (PWR_SR2) .

RCC:
Updated Section 9.1.2: System reset .
Updated Section : Software calibration .
Updated Section 9.8.8: RCC clock interrupt flag register (RCC_CIFR) .
Updated Section 9.8.29: RCC Backup domain control register (RCC_BDCR) .

CRS:
Whole section re-edited.

RCC:
Updated Section 11.3.2: I/O pin alternate function multiplexer and mapping .

DMAMUX:
Updated Section 15.3.2: DMAMUX mapping .
Updated Section 15.4.6: DMAMUX request line multiplexer .
Updated Section 15.4.7: DMAMUX request generator .

NVIC:
Updated Table 109: STM32L552xx and STM32L562xx vector table .

CRC:
Updated Section 18.2: CRC main features .
Updated Table 51: CRC calculation unit block diagram .
Updated Section 18.3.3: CRC operation .

Table 469. Document revision history (continued)

Date	Revision	Changes
03-Jun-2025	8 (continued)	Updated introduction to Section 18.4: CRC registers . FSMC: Updated Figure 70: Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . Updated Figure 71: Synchronous multiplexed write mode waveforms - PSRAM (CRAM) . Updated Section : PSRAM chip select counter register (FMC_PCSCNTR) . OCTOSPI: Whole section re-edited. ADC: Updated Figure 94: ADC clock scheme . Updated Figure 95: ADC1 connectivity . Updated Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) . Updated Figure 100: Enabling / disabling the ADC . Updated Section 21.4.10: Constraints when writing the ADC control bits . Updated Section : Auto-injection mode . Updated Section : Analog watchdog . Updated Figure 142: Triggered regular oversampling with injection . Updated Figure 151: Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . Updated Figure 158: DMA requests in regular simultaneous mode when MDMA = 10 . Added Section 21.5: ADC in low-power mode . Updated Section 21.7.4: ADC configuration register (ADC_CFGR) . Updated Section 21.7.16: ADC injected sequence register (ADC_JSQR) . Updated Section 21.8.1: ADC common status register (ADC_CSR) . Updated Section 21.8.2: ADC common control register (ADC_CCR) . Updated Section 21.8.3: ADC common regular data register for dual mode (ADC_CDR) . ADC: Updated Section 22.2: DAC main features . Updated Section 22.3: DAC implementation . Updated Figure 163: Dual-channel DAC block diagram . Updated Figure 166: Timing diagram for conversion with trigger disabled TEN = 0 . Added Section 22.4.12: DAC channel conversion modes . COMP: Updated Section 24.6.2: Comparator 2 control and status register (COMP2_CSR) . DFSDM: Updated Section 26.3: DFSDM implementation . Updated Section 26.4.3: DFSDM reset and clocks . Updated Section : Manchester coded data input format operation . Updated Section : Clock absence detection . Updated Section : Manchester/SPI code synchronization . TSC: Updated Section 27.2: TSC main features . Updated Figure 189: Surface charge transfer analog I/O group structure . Updated Figure 215: Acquisition sequence summary .

Date

Revision

Changes

03-Jun-2025

8
(continued)

Updated introduction to Section 18.4: CRC registers .

FSMC:

Updated Figure 70: Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) .

Updated Figure 71: Synchronous multiplexed write mode waveforms - PSRAM (CRAM) .

Updated Section : PSRAM chip select counter register (FMC_PCSCNTR) .

OCTOSPI:

Whole section re-edited.

ADC:

Updated Figure 94: ADC clock scheme .

Updated Figure 95: ADC1 connectivity .

Updated Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) .

Updated Figure 100: Enabling / disabling the ADC .

Updated Section 21.4.10: Constraints when writing the ADC control bits .

Updated Section : Auto-injection mode .

Updated Section : Analog watchdog .

Updated Figure 142: Triggered regular oversampling with injection .

Updated Figure 151: Alternate trigger: 4 injected channels (each ADC) in discontinuous mode .

Updated Figure 158: DMA requests in regular simultaneous mode when MDMA = 10 .

Added Section 21.5: ADC in low-power mode .

Updated Section 21.7.4: ADC configuration register (ADC_CFGR) .

Updated Section 21.7.16: ADC injected sequence register (ADC_JSQR) .

Updated Section 21.8.1: ADC common status register (ADC_CSR) .

Updated Section 21.8.2: ADC common control register (ADC_CCR) .

Updated Section 21.8.3: ADC common regular data register for dual mode (ADC_CDR) .

ADC:

Updated Section 22.2: DAC main features .

Updated Section 22.3: DAC implementation .

Updated Figure 163: Dual-channel DAC block diagram .

Updated Figure 166: Timing diagram for conversion with trigger disabled TEN = 0 .

Added Section 22.4.12: DAC channel conversion modes .

COMP:

Updated Section 24.6.2: Comparator 2 control and status register (COMP2_CSR) .

DFSDM:

Updated Section 26.3: DFSDM implementation .

Updated Section 26.4.3: DFSDM reset and clocks .

Updated Section : Manchester coded data input format operation .

Updated Section : Clock absence detection .

Updated Section : Manchester/SPI code synchronization .

TSC:

Updated Section 27.2: TSC main features .

Updated Figure 189: Surface charge transfer analog I/O group structure .

Updated Figure 215: Acquisition sequence summary .

Table 469. Document revision history (continued)

Date	Revision	Changes
03-Jun-2025	8 (continued)	Updated Section 27.3.3: Reset and clocks . RNG: Whole section re-edited. AES: Updated Section : Suspend/resume operations in ECB/CBC modes . Updated Section : CTR encryption and decryption . Updated Figure 214: GCM authenticated encryption . Updated Table 229: Initialization of AES_IVRx registers in GCM mode . Updated Section : GCM processing . Updated Table 230: Initialization of AES_IVRx registers in CCM mode . Updated Section : DMA operation in different operating modes . Updated Section 29.5: AES interrupts . HASH: Updated Section 30.4.5: Message digest computing . Updated Section 30.4.7: HMAC operation . OTFDEC: Updated Section 31.3.3: OTFDEC on-the-fly decryption . Replaced Non-Tustzone by Nonsecure in Section 31.6: OTFDEC registers . PKA: Updated Section 32.4.5: Modular and Montgomery multiplication . TIM1/TIM8: Updated Figure 254: Control circuit in normal mode, internal clock divided by 1 . Updated Section 33.3.16: Using the break function . Updated Section 33.3.18: Clearing the OCxREF signal on an external event . Updated Figure 282: Retriggerable one pulse mode . Updated Section 33.3.22: Encoder interface mode . Updated Section 33.3.25: Interfacing with Hall sensors . Updated Section 33.4.3: TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) . Updated Section 33.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 1, 8) . Updated Section 33.4.20: TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) . TIM2/TIM3/TIM4/TIM5: Updated Figure 254: Control circuit in normal mode, internal clock divided by 1 . Updated Section 34.3.12: Clearing the OCxREF signal on an external event . Updated Section 34.3.15: Encoder interface mode . Updated Section : Slave mode: Trigger mode . Updated Section 34.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 5) . Updated Section 34.4.11: TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 5) . TIM15/TIM16/TIM17: Updated Figure 352: Control circuit in normal mode, internal clock divided by 1 . Updated Section 35.4.13: Using the break function . Added Section 35.4.15: 6-step PWM generation . Updated Figure 371: Retriggerable one pulse mode . Added Section 35.5.3: TIM15 slave mode control register (TIM15_SMCR) .

Date

Revision

Changes

03-Jun-2025

8
(continued)

Updated Section 27.3.3: Reset and clocks .

RNG:
Whole section re-edited.

AES:
Updated Section : Suspend/resume operations in ECB/CBC modes .
Updated Section : CTR encryption and decryption .
Updated Figure 214: GCM authenticated encryption .
Updated Table 229: Initialization of AES_IVRx registers in GCM mode .
Updated Section : GCM processing .
Updated Table 230: Initialization of AES_IVRx registers in CCM mode .
Updated Section : DMA operation in different operating modes .
Updated Section 29.5: AES interrupts .

HASH:
Updated Section 30.4.5: Message digest computing .
Updated Section 30.4.7: HMAC operation .

OTFDEC:
Updated Section 31.3.3: OTFDEC on-the-fly decryption .
Replaced Non-Tustzone by Nonsecure in Section 31.6: OTFDEC registers .

PKA:
Updated Section 32.4.5: Modular and Montgomery multiplication .

TIM1/TIM8:
Updated Figure 254: Control circuit in normal mode, internal clock divided by 1 .
Updated Section 33.3.16: Using the break function .
Updated Section 33.3.18: Clearing the OCxREF signal on an external event .
Updated Figure 282: Retriggerable one pulse mode .
Updated Section 33.3.22: Encoder interface mode .
Updated Section 33.3.25: Interfacing with Hall sensors .
Updated Section 33.4.3: TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) .
Updated Section 33.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 1, 8) .
Updated Section 33.4.20: TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) .

TIM2/TIM3/TIM4/TIM5:
Updated Figure 254: Control circuit in normal mode, internal clock divided by 1 .
Updated Section 34.3.12: Clearing the OCxREF signal on an external event .
Updated Section 34.3.15: Encoder interface mode .
Updated Section : Slave mode: Trigger mode .
Updated Section 34.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 5) .
Updated Section 34.4.11: TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 5) .

TIM15/TIM16/TIM17:
Updated Figure 352: Control circuit in normal mode, internal clock divided by 1 .
Updated Section 35.4.13: Using the break function .
Added Section 35.4.15: 6-step PWM generation .
Updated Figure 371: Retriggerable one pulse mode .
Added Section 35.5.3: TIM15 slave mode control register (TIM15_SMCR) .

Table 469. Document revision history (continued)

Date	Revision	Changes
03-Jun-2025	8 (continued)	Added Section 35.5.4: TIM15 DMA/interrupt enable register (TIM15_DIER) . Added Section 35.5.8: TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) . Added Section 35.5.9: TIM15 capture/compare enable register (TIM15_CCER) . Added Section 35.5.16: TIM15 break and dead-time register (TIM15_BDTR) . Added Section 35.6.7: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17) . Added Section 35.6.9: TIMx counter (TIMx_CNT)(x = 16 to 17) . Added Section 35.6.14: TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . TIM6/TIM7: Updated Section 36.3.2: Counting mode . TIM6/TIM7: Updated Figure 386: Low-power timer block diagram . Updated Section 37.4.3: LPTIM input and trigger mapping . Updated Section 37.4.5: Glitch filter . Updated Section 37.4.7: Trigger multiplexer . Updated introduction to Section 37.7: LPTIM registers . Updated Section 37.7.5: LPTIM control register (LPTIM_CR) . Updated Section 37.7.8: LPTIM counter register (LPTIM_CNT) . WWDG: Updated Figure 396: Watchdog block diagram . Updated Section 40.4: WWDG interrupts . Updated Section 40.5.2: WWDG configuration register (WWDG_CFR) . RTC: Updated Section 41.3.4: RTC secure protection modes . Updated Section 41.3.6: Clock and prescalers . Updated Section 41.3.8: Calendar ultra-low power mode . Updated Section 41.3.19: Tamper and alarm output . Updated Section 41.6.20: RTC status register (RTC_SR) . Updated Section 41.6.21: RTC non-secure masked interrupt status register (RTC_MISR) . Updated Section 41.6.22: RTC secure masked interrupt status register (RTC_SMISR) . TAMP: Updated Section : Active tamper detection . Updated Section 42.6.1: TAMP control register 1 (TAMP_CR1) . I2C: Whole section re-edited. USART/UART: Updated Table 346: USART / LPUART features . Updated Section 44.5.2: USART signals . Added Table 347: USART/UART input/output pins Added Table 348: USART internal input/output signals Updated Section 44.5.5: USART transmitter Updated Section 44.5.6: USART receiver Updated Section : Overrun error

Table 469. Document revision history (continued)

Date	Revision	Changes
03-Jun-2025	8 (continued)	Updated Section 44.5.13: USART LIN (local interconnection network) mode . Updated Figure 443: USART example of synchronous master transmission . Updated Figure 451: Transmission using DMA . Updated Figure 452: Reception using DMA . Updated Figure 455: RS232 CTS flow control . Updated Section 44.5.21: USART low-power management . Updated Section 44.8.3: USART control register 2 (USART_CR2) . Updated Section 44.8.9: USART interrupt and status register (USART_ISR) . Updated Section 44.8.10: USART interrupt and status register [alternate] (USART_ISR) . Updated Section 44.8.14: USART prescaler register (USART_PRESC) . LPUART: Updated Table 356: Instance implementation on STM32L552xx and STM32L562xx . Updated Figure 458: LPUART block diagram . Added Table 358: LPUART input/output pins . Added Table 359: LPUART internal input/output signals . Updated Section 45.4.6: LPUART receiver . Updated Figure 465: Transmission using DMA . Updated Figure 466: Reception using DMA . Updated Figure 468: RS232 RTS flow control . Updated Figure 469: RS232 CTS flow control . Updated Section 45.4.14: LPUART low-power management . Updated Section 45.7.3: LPUART control register 2 (LPUART_CR2) . Updated Section 45.7.7: LPUART interrupt and status register (LPUART_ISR) . Updated Section 45.7.8: LPUART interrupt and status register [alternate] (LPUART_ISR) . Updated Section 45.7.12: LPUART prescaler register (LPUART_PRESC) . SAI: Whole section re-edited. SDMMC: Updated Section 48.3: SDMMC operation modes . Updated Section 48.4.4: SDMMC adapter . Updated Section : Normal boot operation . Updated Section 48.9.2: SDMMC clock control register (SDMMC_CLKCR) . Updated Section 48.9.3: SDMMC argument register (SDMMC_ARGR) . FDCAN: Whole section re-edited. USB: Updated Table 425: Bulk double-buffering memory buffers usage . UCPD: Updated Section 51.1: UCPD introduction . Updated Section 51.2: UCPD main features . Updated Table 434: UCPD implementation . Updated Table 435: UCPD signals on pins . Updated Section 51.4.2: UCPD reset and clocks . Updated Section 51.4.8: UCPD fast role swap (FRS) .

Date

Revision

Changes

03-Jun-2025

8
(continued)

Updated Section 44.5.13: USART LIN (local interconnection network) mode .

Updated Figure 443: USART example of synchronous master transmission .

Updated Figure 451: Transmission using DMA .

Updated Figure 452: Reception using DMA .

Updated Figure 455: RS232 CTS flow control .

Updated Section 44.5.21: USART low-power management .

Updated Section 44.8.3: USART control register 2 (USART_CR2) .

Updated Section 44.8.9: USART interrupt and status register (USART_ISR) .

Updated Section 44.8.10: USART interrupt and status register [alternate] (USART_ISR) .

Updated Section 44.8.14: USART prescaler register (USART_PRESC) .

LPUART:

Updated Table 356: Instance implementation on STM32L552xx and STM32L562xx .

Updated Figure 458: LPUART block diagram .

Added Table 358: LPUART input/output pins .

Added Table 359: LPUART internal input/output signals .

Updated Section 45.4.6: LPUART receiver .

Updated Figure 465: Transmission using DMA .

Updated Figure 466: Reception using DMA .

Updated Figure 468: RS232 RTS flow control .

Updated Figure 469: RS232 CTS flow control .

Updated Section 45.4.14: LPUART low-power management .

Updated Section 45.7.3: LPUART control register 2 (LPUART_CR2) .

Updated Section 45.7.7: LPUART interrupt and status register (LPUART_ISR) .

Updated Section 45.7.8: LPUART interrupt and status register [alternate] (LPUART_ISR) .

Updated Section 45.7.12: LPUART prescaler register (LPUART_PRESC) .

SAI:

Whole section re-edited.

SDMMC:

Updated Section 48.3: SDMMC operation modes .

Updated Section 48.4.4: SDMMC adapter .

Updated Section : Normal boot operation .

Updated Section 48.9.2: SDMMC clock control register (SDMMC_CLKCR) .

Updated Section 48.9.3: SDMMC argument register (SDMMC_ARGR) .

FDCAN:

Whole section re-edited.

USB:

Updated Table 425: Bulk double-buffering memory buffers usage .

UCPD:

Updated Section 51.1: UCPD introduction .

Updated Section 51.2: UCPD main features .

Updated Table 434: UCPD implementation .

Updated Table 435: UCPD signals on pins .

Updated Section 51.4.2: UCPD reset and clocks .

Updated Section 51.4.8: UCPD fast role swap (FRS) .

Table 469. Document revision history (continued)

Date	Revision	Changes
03-Jun-2025	8 (continued)	Updated Table 442: Type-C sequence (source: 3A); cable/sink connected (Rd on CC1; Ra on CC2) . Removed section UCPD configuration register 3 (UCPD_CFGR3). Updated Section 51.8.3: UCPD control register (UCPD_CR) . DEBUG: Updated Section 52.2.9: Serial-wire debug port . Updated Section : DP event status register (DP_RESENR) .