17. Extended interrupts and event controller (EXTI)

The extended interrupts and event controller (EXTI) manages the individual CPU and system wakeup through configurable and direct event inputs. It provides wakeup requests to the power control, and generates an interrupt request to the CPU NVIC and events to the CPU event input. For the CPU an additional event generation block (EVG) is needed to generate the CPU event signal.

The EXTI wakeup requests allow the system to be woken up from Stop modes.

The interrupt request and event request generation can be used also in Run modes.

The EXTI also includes the EXTI mux I/Oport selection.

17.1 EXTI main features

The EXTI main features are the following:

• • 43 input events supported.
• • All event inputs allow the possibility to wake up the system.
• • Events which do not have an associated wakeup flag in the peripheral, have a flag in the EXTI and generate an interrupt to the CPU from the EXTI.
• • Events can be used to generate a CPU wakeup event.

The asynchronous event inputs are classified in two groups:

• • Configurable events (signals from I/Os or peripherals able to generate a pulse).
  The configurable events have the following features:
  • – Selectable active trigger edge
  • – Interrupt pending status register bits independent for the rising and falling edge
  • – Individual interrupt and event generation mask, used for conditioning the CPU wakeup, interrupt and event generation
  • – SW trigger possibility
• • Direct events (interrupt and wakeup sources from peripherals having an associated flag which requires to be cleared in the peripheral).
  The direct events have the following features:
  • – Fixed rising edge active trigger
  • – No interrupt pending status register bit in the EXTI. (The interrupt pending status flag is provided by the peripheral generating the event.)
  • – Individual interrupt and event generation mask, used for conditioning the CPU wakeup and event generation
  • – No SW trigger possibility
• • Secure events
  • – The access to control and configuration bits of secure input events can be made secure and or privilege.
• • EXTI IO port selection.

17.2 EXTI block diagram

The EXTI consists of a register block accessed via an AHB interface, the event input trigger block, the masking block, and EXTI mux as shown in Figure 47.

The register block contains all the EXTI registers.

The event input trigger block provides event input edge trigger logic.

The masking block provides the event input distribution to the different wakeup, interrupt and event outputs, and their masking.

The EXTI mux provides the IO port selection on to the EXTI event signal.

Figure 47. EXTI block diagram

Table 110. EXTI pin overview

17.2.1 EXTI connections between peripherals and CPU

The peripherals able to generate wakeup or interrupt events when the system is in Stop mode are connected to the EXTI.

• • Peripheral wakeup signals which generate a pulse or which do not have an interrupt status bits in the peripheral, are connected to an EXTI configurable event input. For these events the EXTI provides a status pending bit which requires to be cleared. It is the EXTI interrupt associated with the status bit that will interrupt the CPU.
• • Peripheral interrupt and wakeup signals that have a status bit in the peripheral which requires to be cleared in the peripheral, are connected to an EXTI direct event input. There is no status pending bit within the EXTI. The interrupt or wakeup is cleared by the CPU in the peripheral. It is the peripheral interrupt that interrupts the CPU directly.
• • All GPIO ports input to the EXTI multiplexer, allowing the selection of a port pin to wake up the system via a configurable event.

The EXTI configurable event interrupts are connected to the NVIC of the CPU.

The dedicated EXTI/EVG CPU event is connected to the CPU rxev input.

The EXTI CPU wakeup signals are connected to the PWR block, and are used to wake up the system and CPU sub-system bus clocks.

17.2.2 EXTI interrupt/event mapping

The EXTI lines are connected as shown in Table 112: EXTI line connections .

Table 112. EXTI line connections (continued)

17.3 EXTI functional description

Depending on the EXTI event input type and wakeup target(s), different logic implementations are used. The applicable features are controlled from register bits:

• Active trigger edge enable, by rising edge selection
  EXTI rising trigger selection register (EXTI_RTSR1) ,
  EXTI rising trigger selection register (EXTI_RTSR2) ,
  and falling edge selection
  EXTI falling trigger selection register (EXTI_FTSR1) ,
  EXTI falling trigger selection register (EXTI_FTSR2) .
• Software trigger, by
  EXTI software interrupt event register (EXTI_SWIER1) ,
  EXTI software interrupt event register (EXTI_SWIER2) .
• Interrupt pending flag, by
  EXTI rising edge pending register (EXTI_RPR1) ,
  EXTI falling edge pending register (EXTI_FPR1) ,
  EXTI rising edge pending register (EXTI_RPR2) ,
  EXTI falling edge pending register (EXTI_FPR2) .
• CPU wakeup and interrupt enable, by
  EXTI CPU wakeup with interrupt mask register (EXTI_IMR1) ,
  EXTI CPU wakeup with interrupt mask register (EXTI_IMR2) .
• CPU wakeup and event enable, by
  EXTI CPU wakeup with interrupt mask register (EXTI_IMR1) ,
  EXTI CPU wakeup with event mask register (EXTI_EMR2) .

Table 113. EXTI event input configurations and register control

1. Only for input events with configuration “rxev generation” enabled.

17.3.1 EXTI configurable event input wakeup

Figure 48 is a detailed representation of the logic associated with configurable event inputs which wakeup the CPU sub-system bus clocks and generated an EXTI pending flag and interrupt to the CPU and or a CPU wakeup event.

Figure 48. Configurable event trigger logic CPU wakeup

1. 1. Only for the input events that support CPU rxev generation c_event.

The software interrupt event register allows to trigger configurable events by software, writing the corresponding register bit, irrespective of the edge selection setting.

The rising edge and falling edge selection registers allow the enabling and selection of the configurable event active trigger edge or both edges.

The CPU has its dedicated wakeup (interrupt) mask register and a dedicated event mask registers. The enabled event make it possible to generate an event on the CPU. All events for a CPU are ordered together into a single CPU event signal. The event pending registers (EXTI_RPR and EXTI_FPR) is not set for an unmasked CPU event.

The configurable events have unique interrupt pending request registers, shared by the CPU. The pending register is only set for an unmasked interrupt. Each configurable event provides a common interrupt to the CPU. The configurable event interrupts need to be acknowledged by software in the EXTI_RPR and/or EXTI_FPR registers.

When a CPU wakeup (interrupt) or CPU event is enabled the asynchronous edge detection circuit is reset by the clocked delay and rising edge detect pulse generator. This guarantees that the EXTI hclk clock is woken up before the asynchronous edge detection circuit is reset.

Note: A detected configurable event interrupt pending request, may be cleared by any CPU with the correct access permission. The system is not able to enter into low-power modes as long as an interrupt pending request is active.

17.3.2 EXTI direct event input wakeup

Figure 49 is a detailed representation of the logic associated with direct event inputs waking up the system.

The direct events do not have an associated EXTI interrupt. The EXTI only wakes up the system and CPU sub-system clocks and may generate a CPU wakeup event. The peripheral synchronous interrupt, associated with the direct wakeup event wakes up the CPU.

The EXTI direct event is able to generate a CPU event. This CPU event wakes up the CPU. The CPU event may occur before the associated peripheral interrupt flag is set.

Figure 49. Direct event trigger logic CPU wakeup

1. Only for the input events that support CPU rxev generation c_event.

17.3.3 EXTI mux selection

The EXTI mux allow the selection of GPIOs as interrupts and wakeup. The GPIOs are connected via 16 EXTI mux lines to the first 16 EXTI events as configurable event. The selection of GPIO port as EXTI mux output, is controlled by registers: EXTI external interrupt selection register (EXTI_EXTICRn) .

Figure 50. EXTI mux GPIO selection

The EXTI mux outputs are available as output signals from the EXTI to trigger other IPs. The EXTI mux outputs are available independent from any masking in EXTI_IMRx and EXTI_EM Rx.

17.4 EXTI functional behavior

The direct event inputs are enabled in the respective peripheral generating the wakeup event. The configurable events are enabled by enabling at least one of the trigger edges.

Once an event input is enabled, the generation of a CPU wakeup is conditioned by the CPU interrupt mask and CPU event mask.

Table 114. Masking functionality

1. The single exti(n) interrupt will go to the CPU. If no interrupt is required for CPU, the exti(n) interrupt shall be masked in the CPU NVIC.

2. Only if CPU interrupt is enabled in EXTI_IMR.IMn.

For configurable event inputs, when the enabled edge(s) occur on the event input, an event request is generated. When the associated CPU interrupt is unmasked the corresponding pending bit EXTI_RPR.RPIFn and/or EXTI_FPR.FPIFn is/are set and the CPU sub-system is woken up and CPU interrupt signal is activated. The EXTI_RPR.RPIFn and/or EXTI_FPR.FPIFn pending bit shall be cleared by software writing it to '1'. This action clears the CPU interrupt.

For direct event inputs, when enabled in the associated peripheral, an event request is generated on the rising edge only. There is no corresponding CPU pending bit in the EXTI.

When the associated CPU interrupt is unmasked, the corresponding CPU sub-system is woken up. The CPU is woken up (interrupted) by the peripheral synchronous interrupt.

The CPU event has to be unmasked to generate an event. When the enabled edge(s) occur on the event input a CPU event pulse is generated. There is no event pending bit.

For the configurable event inputs an event request can be generated by software when writing a '1' in the software interrupt/event register EXTI_SWIER, allowing the generation of a rising edge on the event. The rising edge event pending bit is set in EXTI_RPR, irrespective of the setting in EXTI_RTSR.

17.5 EXTI event protection

The EXTI is able to protect event register bits from being modified by non-secure and unprivileged accesses. The protection can individually be activated per input event via the register bits in EXTI_SECCFGR and EXTI_PRIVCFGR. At EXTI level the protection consists in preventing unauthorized write access to:

• • Change the settings of the secure and/or privileged configurable events.
• • Change the masking of the secure and/or privileged input events.
• • Clear pending status of the secure and/or privileged input events.

Table 115. Register protection overview

1. Security is enabled with the individual Input event. EXTI_SECCFG registers.

2. Privilege is enabled with the individual Input event EXTI_PRIVCFGRn registers.

17.5.1 EXTI security protection

When security is enabled for an input event, the associated input event configuration and control bits can only be modified and read by a secure access, a non-secure write access is discarded and a read returns 0.

When input events are non-secure, the security is disabled. The associated input event configuration and control bits can be modified and read by a secure access and non-secure access.

The security configuration in registers EXTI_SECCFGR can be globally locked after reset by EXTI_LOCKR.LOCK.

17.5.2 EXTI privilege protection

When privilege is enabled for an input event, the associated input event configuration and control bits can only be modified and read by a privilege access, an unprivileged write access is discarded and a read returns 0.

When input events are unprivileged, the privilege is disabled. The associated input event configuration and control bits can be modified and read by a privilege access and unprivileged access.

The privilege configuration in registers EXTI_PRIVCFGRn can be globally locked after reset by EXTI_LOCKR.LOCK.

17.6 EXTI registers

The EXTI register map is divided in the following sections:

Table 116. EXTI register map sections

All the registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit) access.

17.6.1 EXTI rising trigger selection register (EXTI_RTSR1)

Address offset: 0x000

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 RT[22:21] : Rising trigger event configuration bit of configurable event input x ⁽¹⁾ (where x = 18 to 22)

When SECx is disabled, RTx can be accessed with non-secure and secure access.

When SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded, non-secure read returns 0.

When EXTI_PRIVCFGn.PRIVx is disabled, RTx can be accessed with unprivileged and privilege access.

When EXTI_PRIVCFGn.PRIVx is enabled, RTx can only be accessed with privilege access. Unprivileged write to this bit x is discarded, unprivileged read returns 0.

• 0: Rising trigger disabled (for event and Interrupt) for input line
• 1: Rising trigger enabled (for event and Interrupt) for input line

Bits 20:17 Reserved, must be kept at reset value.

Bits 16:0 RT[16:0] : Rising trigger event configuration bit of configurable event input x ⁽¹⁾ (where x = 0 to 16)

When EXTI_SECCFG SECx is disabled, RTx can be accessed with non-secure and secure access.

When EXTI_SECCFG SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded, non-secure read returns 0.

When EXTI_PRIVCFG PRIVx is disabled, RTx can be accessed with unprivileged and privilege access.

When EXTI_PRIVCFG PRIVx is enabled, RTx can only be accessed with privilege access. Unprivileged write to this bit x is discarded, unprivileged read returns 0.

• 0: Rising trigger disabled (for event and Interrupt) for input line
• 1: Rising trigger enabled (for event and Interrupt) for input line

1. 1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a rising edge on the configurable event input occurs during writing of the register, the associated pending bit is not set. Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

17.6.2 EXTI falling trigger selection register (EXTI_FTSR1)

Address offset: 0x004

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 FT[22:21] : Falling trigger event configuration bit of configurable event input x ⁽¹⁾ (where x = 18 to 22).

When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privilege access.

When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privilege access. Unprivileged write to this FTx is discarded, unprivileged read returns 0.

0: Falling trigger disabled (for event and Interrupt) for input line
1: Falling trigger enabled (for event and Interrupt) for input line.

Bit 20:17 Reserved, must be kept at reset value.

Bits 16:0 FT[16:0] : Falling trigger event configuration bit of configurable event input x ⁽¹⁾ (where x = 0 to 16).

When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privilege access.

When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privilege access. Unprivileged write to this FTx is discarded, unprivileged read returns 0.

0: Falling trigger disabled (for event and Interrupt) for input line
1: Falling trigger enabled (for event and Interrupt) for input line.

1. 1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs.
   If a falling edge on the configurable event input occurs during writing of the register, the associated pending bit is not set.
   Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

17.6.3 EXTI software interrupt event register (EXTI_SWIER1)

Address offset: 0x008

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 SWI[22:21] : Software interrupt on event x (where x = 18 to 22)

When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access.
When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access.
Non-secure write to this SWI x is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privilege access.
Unprivileged write to this SWIx is discarded, unprivileged read returns 0.

A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read.

• 0: Writing 0 has no effect.
• 1: Writing a 1 to this bit triggers a rising edge event on event x. This bit is auto cleared by HW.

Bit 20:17 Reserved, must be kept at reset value.

Bits 16:0 SWI[16:0] : Software interrupt on event x (where x = 18 to 22)

When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access.
When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access.
Non-secure write to this SWI x is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privilege access.
Unprivileged write to this SWIx is discarded, unprivileged read returns 0.

A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read.

• 0: Writing 0 has no effect.
• 1: Writing a 1 to this bit triggers a rising edge event on event x. This bit is auto cleared by HW.

17.6.4 EXTI rising edge pending register (EXTI_RPR1)

Address offset: 0x00C

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 RPIF[22:21] : configurable event inputs x rising edge pending bit (where x = 18 to 22).

When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access.
When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access.
Non-secure write to this RPIFx is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privilege access.
Unprivileged write to this RPIFx is discarded, unprivileged read returns 0.

• 0: No rising edge trigger request occurred
• 1: Rising edge trigger request occurred

This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing a 1 into the bit.

Bit 20:17 Reserved, must be kept at reset value.

Bits 16:0 RPIF[16:0] : configurable event inputs x rising edge pending bit (where x = 0 to 16).

When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access.
When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access.
Non-secure write to this RPIFx is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privilege access.
Unprivileged write to this RPIFx is discarded, unprivileged read returns 0.

• 0: No rising edge trigger request occurred
• 1: Rising edge trigger request occurred

This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing a 1 into the bit.

17.6.5 EXTI falling edge pending register (EXTI_FPR1)

Address offset: 0x010

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 FPIF[22:21] : configurable event inputs x falling edge pending bit (where x = 22 to 18)

When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access.

Non-secure write to this FPIFx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privilege access.

When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privilege access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0.

0: No falling edge trigger request occurred
1: Rising edge trigger request occurred

This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing a 1 into the bit.

Bit 20:17 Reserved, must be kept at reset value.

Bits 16:0 FPIF[16:0] : configurable event inputs x falling edge pending bit (where x = 0 to 16)

When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access.

Non-secure write to this FPIFx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privilege access.

When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privilege access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0.

0: No falling edge trigger request occurred
1: Rising edge trigger request occurred

This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing a 1 into the bit.

17.6.6 EXTI security configuration register (EXTI_SECCFGR1)

Address offset: 0x014

Reset value: 0x0000 0000

This register provides write access security, a non-secure write access is ignored and causes the generation of an illegal access event. A non-secure read returns the register data.

Contains only register bits for security capable input events.

Bits 31:0 SEC[31:0] : Security enable on event input x (where x = 0 to 31)

When EXTI_PRIVCFGn.PRIVx is disabled, SECx can be accessed with privilege and unprivileged access.

When EXTI_PRIVCFGn.PRIVx is enabled, SECx can only be written with privilege access. Unprivileged write to this SECx is discarded.

0: Event security disabled (non-secure)

1: Event security enabled (secure)

17.6.7 EXTI privilege configuration register (EXTI_PRIVCFG1)

Address offset: 0x018

Reset value: 0x0000 0000

This register provides privileged write access protection. An unprivileged read returns the register data.

Contains only register bits for security capable input events.

Bits 31:0 PRIV[31:0] : Security enable on event input x (where x = 0 to 31)

When EXTI_SECCFG.SECx is disabled, PRIVx can be accessed with secure and non-secure access.

When EXTI_SECCFG.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded.

0: Event privilege disabled (unprivileged)

1: Event privilege enabled (privileged)

17.6.8 EXTI rising trigger selection register (EXTI_RTSR2)

Address offset: 0x020

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:3 RT[38:35] : Rising trigger event configuration bit of configurable event input x ⁽¹⁾ (where x = 35 to 38).

When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this RTx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privilege access.

When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privilege access. Unprivileged write to this RTx is discarded, unprivileged read returns 0.

0: Rising trigger disabled (for event and interrupt) for input line

1: Rising trigger enabled (for event and interrupt) for input line

Bits 2:0 Reserved, must be kept at reset value.

1. 1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a falling edge on the configurable event input occurs during writing of the register, the associated pending bit is not set. Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

17.6.9 EXTI falling trigger selection register (EXTI_FTSR2)

Address offset: 0x024

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:3 FT[38:35] : Falling trigger event configuration bit of configurable event input x ⁽¹⁾ (where x = 35 to 38)

When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privilege access.

When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privilege access. Unprivileged write to this FTx is discarded, unprivileged read returns 0.

0: Falling trigger disabled (for event and interrupt) for input line

1: Falling trigger enabled (for event and interrupt) for input line

Bits 2:0 Reserved, must be kept at reset value.

1. 1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs.
   If a falling edge on the configurable event input occurs during writing of the register, the associated pending bit is not set.
   Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

17.6.10 EXTI software interrupt event register (EXTI_SWIER2)

Address offset: 0x028

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:3 SWI[38:35] : Software interrupt on event x (where x = 35 to 38)

When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access.

Non-secure write to this SWIx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privilege access.

When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privilege access.
Unprivileged write to this SWIx is discarded, unprivileged read returns 0.

A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always return 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit triggers a rising edge event on event x+32. This bit is auto cleared by HW.

Bits 2:0 Reserved, must be kept at reset value.

17.6.11 EXTI rising edge pending register (EXTI_RPR2)

Address offset: 0x02C

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:3 RPIF[38:35] : configurable event inputs x rising edge pending bit (where x = 35 to 38).

When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access.

Non-secure write to this RPIFx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, RPIF can be accessed with unprivileged and privilege access.

When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privilege access.

Unprivileged write to this RPIFx is discarded, unprivileged read returns 0.

0: No rising edge trigger request occurred

1: Rising edge trigger request occurred

This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing a 1 into the bit.

Bits 2:0 Reserved, must be kept at reset value.

17.6.12 EXTI falling edge pending register (EXTI_FPR2)

Address offset: 0x030

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:3 FPIF[38:35] : configurable event inputs x pending bit (where x = 35 to 38).

When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access.

Non-secure write to this FPIFx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privilege access.

When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privilege access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0.

0: No falling edge trigger request occurred

1: Rising edge trigger request occurred

This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing a 1 into the bit.

Bits 2:0 Reserved, must be kept at reset value.

17.6.13 EXTI security enable register (EXTI_SECCFGR2)

Address offset: 0x034

Reset value: 0x0000 0000

This register provides write access security, a non-secure write access is ignored and causes the generation of an illegal access event. A non-secure read returns the register data.

Contains only register bits for security capable Input events.

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:0 SEC[42:32] : Security enable on event input x (where x = 32 to 42)

When EXTI_PRIVCFGRn.PRIVx is disabled, SECx can be accessed with privilege and unprivileged access.

When EXTI_PRIVCFGRn.PRIVx is enabled, SECx can only be written with privilege access.

Unprivileged write to this SECx is discarded

0: Event security disabled (non-secure)

1: Event security enabled (secure)

17.6.14 EXTI privilege enable register (EXTI_PRIVCFGR2)

Address offset: 0x038

Reset value: 0x0000 0000

This register provides privileged write access protection, an unprivileged write access is discarded and causes the generation of an illegal access event. An unprivileged read returns the register data.

Contains only register bits for security capable Input events.

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:0 PRIV[42:32] : Privilege enable on event input x (where x = 32 to 42)

When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access.

When EXTI_SECCFGR.SECx is enabled, PRIVx can only be accessed with secure access. Non-secure write to this PRIVx is discarded.

0: Event privilege disabled (unprivileged)
1: Event security enabled (privileged)

17.6.15 EXTI external interrupt selection register (EXTI_EXTICRn)

Address offset: 0x060 (EXTI_EXTICR1) EXTI mux 0, 1, 2, 3 (m = 0)
Address offset: 0x064 (EXTI_EXTICR2) EXTI mux 4, 5, 6, 7 (m = 4)
Address offset: 0x068 (EXTI_EXTICR3) EXTI mux 8, 9, 10, 11 (m = 8)
Address offset: 0x06C (EXTI_EXTICR4) EXTI mux 12, 13, 14, 15 (m = 12)

Reset value: 0x0000 0000

EXTIm fields contain only the number of bits in line with the nb_ioport configuration.

Bits 31:24 EXTIm+3[7:0] : EXTIm+3 GPIO port selection (where m = 0, 4, 8, or 12 for respectively EXTI_EXTICR[1:4]).

These bits are written by software to select the source input for EXTIm+3 external interrupt.

When EXTI_SECCFGR.SEC(m+3) is disabled, EXTI(m+3) can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SEC(m+3) is enabled, EXTI(m+3) can only be accessed with secure access. Non-secure write is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV(m+3) is disabled, EXTI(m+3) can be accessed with privilege and unprivileged access.

When EXTI_PRIVCFGR.PRIV(m+3) is enabled, EXTI(m+3) can only be accessed with privilege access. Unprivileged write to this bit is discarded.

0x00: PA[m+3] pin

0x01: PB[m+3] pin

0x02: PC[m+3] pin

0x03: PD[m+3] pin

0x04: PE[m+3] pin

0x05: PF[m+3] pin

0x06: PG[m+3] pin

0x07: PH[m+3] pin

Others reserved

Bits 23:1 EXTIm+2[7:0] : EXTIm+2 GPIO port selection (where m = 0, 4, 8, or 12 for respectively EXTI_EXTICR[1:4])(where m = 0, 4, 8, or 12 for respectively EXTI_EXTICR[1:4]).

These bits are written by software to select the source input for EXTIm+2 external interrupt.

When EXTI_SECCFGR.SEC(m+2) is disabled, EXTI(m+2) can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SEC(m+2) is enabled, EXTI(m+2) can only be accessed with secure access. Non-secure write is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV(m+2) is disabled, EXTI(m+2) can be accessed with privilege and unprivileged access.

When EXTI_PRIVCFGR.PRIV(m+2) is enabled, EXTI(m+2) can only be accessed with privilege access. Unprivileged write to this bit is discarded.

0x00: PA[m+2] pin

0x01: PB[m+2] pin

0x02: PC[m+2] pin

0x03: PD[m+2] pin

0x04: PE[m+2] pin

0x05: PF[m+2] pin

0x06: PG[m+2] pin

0x07: PH[m+2] pin

Others reserved

Bits 15:8 EXTIm+1[7:0] : EXTIm+1 GPIO port selection (where m = 0, 4, 8, or 12 for respectively EXTI_EXTICR[1:4]).

These bits are written by software to select the source input for EXTIm+1 external interrupt.

When EXTI_SECCFGR.SEC(m+1) is disabled, EXTI(m+1) can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SEC(m+1) is enabled, EXTI(m+1) can only be accessed with secure access. Non-secure write is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVm+1 is disabled, EXTI(m+1) can be accessed with privilege and unprivileged access.

When EXTI_PRIVCFGR.PRIVm+1 is enabled, EXTI(m+1) can only be accessed with privilege access. Unprivileged write to this bit is discarded.

0x00: PA[m+1] pin

0x01: PB[m+1] pin

0x02: PC[m+1] pin

0x03: PD[m+1] pin

0x04: PE[m+1] pin

0x05: PF[m+1] pin

0x06: PG[m+1] pin

0x07: PH[m+1] pin

Others reserved

Bits 7:0 EXTIm[7:0] : EXTIm GPIO port selection (where m = 0, 4, 8, or 12 for respectively EXTIm_EXTICR[1:4]).

These bits are written by software to select the source input for EXTIm external interrupt.

When EXTI_SECCFGR.SEC(m) is disabled, EXTI(m) can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SEC(m) is enabled, EXTI(m) can only be accessed with secure access. Non-secure write is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV(m) is disabled, EXTI(m) can be accessed with privilege and unprivileged access.

When EXTI_PRIVCFGR.PRIV(m) is enabled, EXTI(m) can only be accessed with privilege access. Unprivileged write to this bit is discarded

0x00: PA[m] pin

0x01: PB[m] pin

0x02: PC[m] pin

0x03: PD[m] pin

0x04: PE[m] pin

0x05: PF[m] pin

0x06: PG[m] pin

0x07: PH[m] pin

Others reserved

17.6.16 EXTI lock register (EXTI_LOCKR)

Address offset: 0x070

Reset value: 0x0000 0000

This register provides both write access security, a non-secure write access is ignored and a read access returns zero data, and generate an illegal access event.

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 LOCK : Global security and privilege configuration registers EXTI_SECCFGR and EXTI_PRIVCFGR lock.

This register bit is write once after reset.

0: Security and privilege configuration open, can be modified.

1: Security and privilege configuration locked, can no longer be modified.

17.6.17 EXTI CPU wakeup with interrupt mask register (EXTI_IMR1)

Address offset: 0x080

Reset value: 0xFF9E 0000

Contains register bits for configurable events and direct events.

Bits 31:0 IM[31:0] : CPU wakeup with interrupt mask on event input x ⁽¹⁾ (where x = 0 to 31).

When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privilege and unprivileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privilege access. Unprivileged write to this bit is discarded.

0: Wakeup with interrupt request from input event x is masked

1: Wakeup with interrupt request from input event x is unmasked

1. 1. The reset value for configurable event inputs is set to '0' in order to disable the interrupt by default.

17.6.18 EXTI CPU wakeup with event mask register (EXTI_EMR1)

Address offset: 0x084

Reset value: 0x0000 0000

Bits 31:0 EM[31:0] : CPU wakeup with event generation mask on event input x (where x = 0 to 31).

When EXTI_SECCFGR.SECENx is disabled, EMx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECENx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privilege and unprivileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privilege access. Unprivileged write to this bit is discarded.

0: Wakeup with event generation from Line x is masked

1: Wakeup with event generation from Line x is unmasked

17.6.19 EXTI CPU wakeup with interrupt mask register (EXTI_IMR2)

Address offset: 0x090

Reset value: 0x0000 0787

Contains register bits for configurable events and direct events.

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:0 IM[42:40] : CPU wakeup with interrupt mask on event input x ⁽¹⁾ (where x = 40 to 42).

When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded, non-secure read returns 0..

When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privilege and unprivileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privilege access. Unprivileged write to this bit is discarded.

0: Wakeup with interrupt request from input event x is masked

1: Wakeup with interrupt request from input event x is unmasked

Bit 7 Reserved, must be kept at reset value.

Bits 6:0 IM[38:32] : CPU wakeup with interrupt mask on event input x ⁽¹⁾ (where x = 32 to 38).

When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privilege and unprivileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privilege access. Unprivileged write to this bit is discarded.

0: Wakeup with interrupt request from input event x is masked

1: Wakeup with interrupt request from input event x is unmasked

1. 1. The reset value for configurable event inputs is set to '0' in order to disable the interrupt by default.

17.6.20 EXTI CPU wakeup with event mask register (EXTI_EMR2)

Address offset: 0x094

Reset value: 0x0000 0000

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:0 EM[42:40] : CPU wakeup with event generation mask on event input ⁽¹⁾ (where x = 40 to 42).
When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access.
Non-secure write to this bit x is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privilege and unprivileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privilege access.
Unprivileged write to this bit is discarded.

0: Wakeup with event generation from line x is masked

1: Wakeup with event generation from line x is unmasked

Bit 7 Reserved, must be kept at reset value.

Bits 6:0 EM[38:32] : CPU wakeup with event generation mask on event input x ⁽¹⁾ (where x = 32 to 38).
When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access.
Non-secure write to this bit x is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privilege and unprivileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privilege access.
Unprivileged write to this bit is discarded.

0: Wakeup with event generation from line x is masked

1: Wakeup with event generation from line x is unmasked

1. The reset value for configurable event inputs is set to '0' in order to disable the interrupt by default.

17.6.21 EXTI register map

The following table gives the EXTI register map and the reset values.

Table 117. Extended interrupt/event controller register map and reset values

Table 117. Extended interrupt/event controller register map and reset values (continued)

Refer to Section 2.3 on page 86 for the register boundary addresses.