12. System configuration controller (SYSCFG)

12.1 SYSCFG main features

The STM32L552xx and STM32L552xx devices feature a set of configuration registers. The main purposes of the system configuration controller are the following:

• • Managing robustness feature
• • Setting SRAM2 write protection and software erase
• • Configuring FPU interrupts
• • Enabling/disabling the I2C fast-mode plus driving capability on some I/Os and voltage booster for I/Os analog switches
• • Configuring TrustZone security register access

12.2 SYSCFG TrustZone security and privilege

SYSCFG TrustZone security

When the TrustZone security is activated, the SYSCFG is able to secure registers from being modified by non-secure accesses.

The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.

A non-secure read/write access to a secured register is RAZ/WI and generates an illegal access event. An illegal access interrupt is generated if the SYSCFG illegal access event is enabled in the GTZC_TZIC_IER register.

Privileged/unprivileged mode

The SYSCFG registers can be read and written by privileged and unprivileged accesses except the SYSCFG registers for CPU configuration: SYSCFG_CSLCKR, SYSCFG_FPUIMR and SYSCFG_CNSLCKR registers.

An unprivileged access to a privileged register is RAZ/WI.

The table below shows the register security overview.

Table 92. TrustZone security and privilege register accesses

Table 92. TrustZone security and privilege register accesses (continued)

1. TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.

2. Refer to register description for register access.

12.3 SYSCFG registers

12.3.1 SYSCFG secure configuration register (SYSCFG_SECCFGR)

Address offset: 0x00

Reset value: 0x0000 0000

When the system is secure (TZEN = 1), this register provides write access security and can be written only when the access is secure. It can be globally write-protected, or each bit of this register can be individually write-protected. A non-secure write access is WI and generates an illegal access event. There are no read restrictions.

When the system is not secure (TZEN = 0), this register is RAZ/WI.

This register can be read and written by privileged and unprivileged access.

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 FPUSEC : FPU security

0: SYSCFG_FPUIMR register can be written by secure and non-secure access.

1: SYSCFG_FPUIMR register can be written by secure access only.

Bit 2 SRAM2SEC : SRAM2 security

0: SYSCFG_SKR, SYSCFG_SCR, and SYSCFG_SWPRx registers can be written by secure and non-secure access.

1: SYSCFG_SKR, SYSCFG_SCR, and SYSCFG_SWPRx register can be written by secure access only.

Bit 1 CLASSBSEC : ClassB security

0: SYSCFG_CFGR2 register can be written by secure and non-secure access.

1: SYSCFG_CFGR2 register can be written by secure access only.

Bit 0 SYSCFGSEC : SYSCFG clock control security

0: SYSCFG configuration clock in RCC registers can be written by secure and non-secure access.

1: SYSCFG configuration clock in RCC registers can be written by secure access only.

12.3.2 SYSCFG configuration register 1 (SYSCFG_CFGR1)

Address offset: 0x04

Reset value: 0x0000 0000

When the system is secure (TZEN = 1), this register can be a mix of secure and non-secure bits depending on I2Cx, ADC security configuration bit in TZSC_SECCFGR register and GPIO security bits. A non-secure read/write access on secured bits is RAZ/WI.

When the system is not secure (TZEN = 0), there is no access restriction.

This register can be read and written by privileged and unprivileged access.

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 I2C4_FMP : I2C4 fast-mode plus (Fm+) driving capability activation.

This bit enables the Fm+ driving mode on I2C4 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C4 pins selected through AF selection bits.

1: Fm+ mode is enabled on I2C4 pins selected through AF selection bits.

Bit 22 I2C3_FMP : I2C3 fast-mode plus driving capability activation

This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C3 pins selected through AF selection bits.

1: Fm+ mode is enabled on I2C3 pins selected through AF selection bits.

Bit 21 I2C2_FMP : I2C2 fast-mode plus driving capability activation

This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C2 pins selected through AF selection bits.

1: Fm+ mode is enabled on I2C2 pins selected through AF selection bits.

Bit 20 I2C1_FMP : I2C1 fast-mode plus driving capability activation

This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C1 pins selected through AF selection bits.

1: Fm+ mode is enabled on I2C1 pins selected through AF selection bits.

Bit 19 I2C_PB9_FMP : I2C1 fast-mode plus driving capability activation on PB9

This bit enables the Fm+ driving mode for PB9.

0: PB9 pin operates in standard mode.

1: Fm+ mode is enabled on PB9 pin, and the speed control is bypassed.

Bit 18 I2C_PB8_FMP : I2C1 fast-mode plus driving capability activation on PB8

This bit enables the Fm+ driving mode for PB8.

0: PB8 pin operates in standard mode.

1: Fm+ mode is enabled on PB8 pin, and the speed control is bypassed.

Bit 17 I2C_PB7_FMP : 12C1 fast-mode plus driving capability activation on PB7

This bit enables the Fm+ driving mode for PB7.

0: PB7 pin operates in standard mode.

1: Fm+ mode is enabled on PB7 pin, and the speed control is bypassed.

Bit 16 I2C_PB6_FMP : 12C1 fast-mode plus driving capability activation on PB6

This bit enables the Fm+ driving mode for PB6.

0: PB6 pin operates in standard mode.

1: Fm+ mode is enabled on PB6 pin, and the speed control is bypassed.

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 ANASWVDD : GPIO analog switch control voltage selection

0: I/O analog switches supplied by VDDA or booster when booster is on

1: I/O analog switches supplied by VDD.

Note: Refer to Table 93: BOOSTEN and ANASWVDD set/reset for bit 9 setting.

Bit 8 BOOSTEN : I/O analog switch voltage booster enable.

0: I/O analog switches are supplied by VDDA voltage. This is the recommended configuration when using the ADC in high VDDA voltage operation.

1: I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD). This is the recommended configuration when using the ADC in low VDDA voltage operation.

Note: Refer to Table 93: BOOSTEN and ANASWVDD set/reset for bit 8 setting.

Bits 7:0 Reserved, must be kept at reset value.

The table below describes when the bit 8 (BOOSTEN) and the bit 9 (ANASWVDD) must be set or reset depending on the voltage settings.

Table 93. BOOSTEN and ANASWVDD set/reset

12.3.3 FPU interrupt mask register (SYSCFG_FPUIMR)

Address offset: 0x08

Reset value: 0x0000 001F

When the system is secure (TZEN =1), this register can be protected against non-secure access by setting the FPUSEC bit in the SYSCFG_SECCFGR register. A non-secure read/write access is RAZ/WI and generates an illegal access event.

When the system is not secure (TZEN=0), there is no access restriction.

This register can be read and written by privileged access only. Unprivileged access is RAZ/WI.

Bits 31:6 Reserved, must be kept at reset value.

Bits 5:0 FPU_IE[5:0] : Floating point unit interrupts enable bits

FPU_IE[5]: Inexact interrupt enable (interrupt disable at reset)

FPU_IE[4]: Input abnormal interrupt enable

FPU_IE[3]: Overflow interrupt enable

FPU_IE[2]: Underflow interrupt enable

FPU_IE[1]: Divide-by-zero interrupt enable

FPU_IE[0]: Invalid operation Interrupt enable

12.3.4 SYSCFG CPU non-secure lock register (SYSCFG_CNSLCKR)

Address offset: 0x0C

Reset value: 0x0000 0000

This register is used to lock the configuration of non-secure MPU and VTOR_NS registers. This register can be read and written by privileged access only. Unprivileged access is RAZ/WI.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 LOCKNSMPU : Non-secure MPU registers lock

This bit is set by software and cleared only by a system reset. When is set, it disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers.

0: Non-secure MPU registers write is enabled.

1: Non-secure MPU registers write is disabled.

Bit 0 LOCKNSVTOR : VTOR_NS register lock

This bit is set by software and cleared only by a system reset.

0: VTOR_NS register write is enabled.

1: VTOR_NS register write is disabled.

12.3.5 SYSCFG CPU secure lock register (SYSCFG_CSLOCKR)

Address offset: 0x10

Reset value: 0x0000 0000

This register is used to lock the configuration of PRIS and BFHFNMINS bits in the AIRCR register, SAU, secure MPU and VTOR_S registers.

When the system is secure (TZEN = 1), this register can be written only when the access is secure. A non-secure read/write access is RAZ/WI and generates an illegal access event.

When the system is not secure (TZEN = 0), this register is RAZ/WI

This register can be read and written by privileged access only. Unprivileged access is RAZ/WI.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 LOCKSAU : SAU registers lock

This bit is set by software and cleared only by a system reset. When is set, it disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers.

0: SAU registers write is enabled.

1: SAU registers write is disabled.

Bit 1 LOCKSMPU : Secure MPU registers lock

This bit is set by software and cleared only by a system reset. When is set, it disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers.

0: Secure MPU registers writes is enabled.

1: Secure MPU registers writes is disabled.

Bit 0 LOCKSVTAIRCR : VTOR_S register and AIRCR register bits lock

This bit is set by software and cleared only by a system reset. When is set, it disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register.

0: VTOR_S register PRIS and BFHFNMINS bits in the AIRCR register write is enabled.

1: VTOR_S register PRIS and BFHFNMINS bits in the AIRCR register write is disabled.

12.3.6 SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x14

Reset value: 0x0000 0000

When the system is secure (TZEN = 1), this register can be protected against non-secure access by setting the CLASSBSEC bit in the SYSCFG_SECCFGR register. When CLASSBSEC bit is set, only secure access is allowed. A non-secure read/write access is RAZ/WI and generates an illegal access event.

When the system is not secure (TZEN = 0), there is no access restriction.

This register can be read and written by privileged and unprivileged access.

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SPF : SRAM2 parity error flag

This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing 1.

0: No SRAM2 parity error detected

1: SRAM2 parity error detected

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 ECCL : ECC lock

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the flash ECC error connection to TIM1/8/15/16/17 Break input.

0: ECC error disconnected from TIM1/8/15/16/17 break input

1: ECC error connected to TIM1/8/15/16/17 break input.

Bit 2 PVDL : PVD lock enable bit

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/8/15/16/17 break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.

0: PVD interrupt disconnected from TIM1/8/15/16/17 break input. PVDE and PLS[2:0] bits can be programmed by the application.

1: PVD interrupt connected to TIM1/8/15/16/17 break input, PVDE and PLS[2:0] bits are read only.

Bit 1 SPL : SRAM2 parity lock bit

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 break inputs.

0: SRAM2 parity error signal disconnected from TIM1/8/15/16/17 break inputs

1: SRAM2 parity error signal connected to TIM1/8/15/16/17 break inputs

Bit 0 CLL : Cortex-M33 LOCKUP (HardFault) output enable bit

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of Cortex-M33 LOCKUP (hardfault) output to TIM1/8/15/16/17 break input.

0: Cortex-M33 LOCKUP output disconnected from TIM1/8/15/16/17 break inputs

1: Cortex-M33 LOCKUP output connected to TIM1/8/15/16/17 break inputs

12.3.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR)

Address offset: 0x18

Reset value: 0x0000 0000

When the system is secure (TZEN =1), this register can be protected against non-secure access by setting the SRAM2SEC bit in the SYSCFG_SECCFGR register. When SRAM2SEC bit is set, only secure access is allowed. A non-secure read/write access is RAZ/WI and generates an illegal access event.

When the system is not secure (TZEN=0), here is no access restriction.

This register can be read and written by privileged and unprivileged access.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 SRAM2BSY : SRAM2 busy by erase operation

0: No SRAM2 erase operation ongoing

1: SRAM2 erase operation ongoing

Bit 0 SRAM2ER : SRAM2 erase

Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at the end of the SRAM2 erase operation

Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register.

12.3.8 SYSCFG SRAM2 key register (SYSCFG_SKR)

Address offset: 0x1C

Reset value: 0x0000 0000

When the system is secure (TZEN = 1), this register can be protected against non-secure access by setting the SRAM2SEC bit in the SYSCFG_SECCFGR register. When SRAM2SEC bit is set, only secure access is allowed. A non-secure read/write access is RAZ/WI and generates an illegal access event.

When the system is not secure (TZEN = 0), there is no access restriction.

This register can be read and written by privileged and unprivileged access.

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 KEY[7:0] : SRAM2 write protection key for software erase

The following steps are required to unlock the write protection of SRAM2ER in SYSCFG_CFGR2.
0: Write 0xCA into Key[7:0].
1: Write 0x53 into Key[7:0].
Writing a wrong key reactivates the write protection.

12.3.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR)

Address offset: 0x20

Reset value: 0x0000 0000

When the system is secure (TZEN = 1), this register can be protected against non-secure access by setting the SRAM2SEC bit in the SYSCFG_SECCFGR register. When SRAM2SEC bit is set, only secure access is allowed. A non-secure read/write access is RAZ/WI and generates an illegal access event.

When the system is not secure (TZEN=0), there is no access restriction.

This register can be read and written by privileged and unprivileged access.

Bits 31:0 PxWP : SRAM2 1 Kbyte page x write protection (x = 31 to 0)

These bits are set by software and cleared only by a system reset.

0: Write protection of SRAM2 1-Kbyte page x is disabled.

1: Write protection of SRAM2 1-Kbyte page x is enabled.

12.3.10 SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2)

Address offset: 0x24

Reset value: 0x0000 0000

When the system is secure (TZEN = 1), this register can be protected against non-secure access by setting the SRAM2SEC bit in the SYSCFG_SECCFGR register. When SRAM2SEC bit is set, only secure access is allowed. A non-secure read/write access is RAZ/WI and generates an illegal access event.

When the system is not secure (TZEN = 0), there is no access restriction.

This register can be read and written by privileged and unprivileged access.

Bits 31:0 PxWP : SRAM2 1 Kbyte page x write protection (x = 63 to 32)

These bits are set by software and cleared only by a system reset.

0: Write protection of SRAM2 1-Kbyte page x is disabled.

1: Write protection of SRAM2 1-Kbyte page x is enabled.

12.3.11 SYSCFG RSS command register (SYSCFG_RSSCMDR)

Address offset: 0x2C

Power-on reset value: 0x0000 0000

System reset: not affected

When the system is secure (TZEN = 1), this register can be read and written only when the APB access is secure. Otherwise it is RAZ/WI.

When the system is not secure (TZEN = 0), this register is RAZ/WI.

This register can be read and written by privileged and unprivileged access.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RSSCMD[15:0] : RSS commands

Defines a command to be executed by the RSS.

0x01C0: request boot from RSS with jump to bootloader when BOOT_LOCK bitfield from FLASH_SECBOOTADD0R option byte register and FLASH_OPTR_nBOOT0 bitfield from FLASH_OPTR option byte register are cleared.

12.3.12 SYSCFG register map

Table 94. SYSCFG register map and reset values

Table 94. SYSCFG register map and reset values (continued)

Refer to Section 2.3 for the register boundary addresses.