2. Memory and bus architecture

The STM32L552xx and STM32L562xx devices are ultra-low-power microcontrollers (STM32L5 Series) based on the high-performance Arm Cortex-M33 32-bit RISC core. They operate at frequencies up to 110 MHz.

The Cortex-M33 processor delivers a high computational performance with low-power consumption and an advanced response to interrupts. It features:

• • Arm TrustZone ^® technology, using the Armv8-M main extension supporting secure and non-secure states
• • Memory protection units (MPUs), supporting 8 regions for secure world and 8 regions for non-secure world.
• • Configurable security attribution unit (SAU) supporting up to 8 memory regions
• • Floating-point arithmetic functionality with support for single precision arithmetic

The Cortex-M33 processor supports the following bus interfaces:

• • System AHB bus: the system AHB (S-AHB) bus interface is used for any instruction fetch and data access to the memory-mapped SRAM, peripherals, external RAM and external devices, or Vendor_SYS regions of the Armv8-M memory map.
• • Code AHB bus: the Code AHB (C-AHB) bus interface is used for any instruction fetch and data access to the code region of the Armv8-M memory map.

2.1 System architecture

The main system consists of 32-bit multilayer AHB bus matrix that interconnects:

• • Up to six masters:
  • – Fast C-bus, connecting Cortex-M33 with TrustZone and FPU core C-bus to the internal memories through the ART (instruction cache)
  • – Slow C-bus, connecting Cortex-M33 with TrustZone and FPU core C-bus to the external memories through the ART (instruction cache)
  • – Cortex ^® -M33 with TrustZone and FPU core S-bus
  • – DMA1
  • – DMA2
  • – SDMMC1 bus
• • Up to seven slaves:
  • – Internal flash memory on the fast C-bus
  • – Internal SRAM1 (192 Kbytes)
  • – Internal SRAM2 (64 Kbytes)
  • – AHB1 peripherals including AHB to APB bridges and APB peripherals (connected to APB1 and APB2)
  • – AHB2 peripherals
  • – Flexible static memory controller (FSMC)
  • – OCTOSPI1 memory controller

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. This architecture is shown in the figure below:

Figure 1. System architecture

2.1.1 Fast C-bus

This bus connects the C-bus of the Cortex-M33 core to the BusMatrix via the instruction cache. This bus is used for instruction fetch and data access to the internal memories mapped in code region. The target of this bus are the internal flash and internal SRAMs.

2.1.2 Slow C-bus

This bus connects the C-bus of the Cortex-M33 core to the BusMatrix via the instruction cache. This bus is used for instruction fetch and data access to the external memories mapped in code region. The target of this bus are the external memories (FSMC and OCTOSPI).

2.1.3 S-bus

This bus connects the system bus of the Cortex-M33 core to the BusMatrix. This bus is used by the core to access data located in a peripheral or SRAM area. The targets of this bus are

the internal SRAMs, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the external memories through the OCTOSPI or the FSMC.

The SRAM2 is also accessible on this bus to allow continuous mapping with SRAM1.

2.1.4 DMA-bus

This bus connects the AHB master interface of the DMA to the BusMatrix. The targets of this bus are the SRAM1 and SRAM2, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the external memories through the OCTOSPI or the FSMC.

2.1.5 SDMMC controller DMA bus

This bus connects the SDMMC1 DMA master interface to the BusMatrix. This bus is used only by the SDMMC1 DMA to load/store data from/to memory. The targets of this bus are data memories: internal SRAMs (SRAM1, SRAM2), internal flash memory or external memories through FSMC or OCTOSPI.

2.1.6 BusMatrix

The BusMatrix manages the access arbitration between masters. The arbitration uses a Round Robin algorithm. The BusMatrix is composed of up to six masters (CPU AHB, system bus, Fast C-bus, Slow C-bus, DMA1, DMA2, SDMMC1) and up to seven slaves (FLASH, SRAM1, SRAM2, AHB1 (including APB1 and APB2), AHB2, OCTOSTPI1 and FSMC).

AHB/APB bridges

The two AHB/APB bridges provide full synchronous connections between the AHB and the two APB buses, allowing flexible selection of the peripheral frequency.

Refer to Section 2.3.2 for the address mapping of the peripherals connected to this bridge.

After each device reset, all peripheral clocks are disabled (except for the SRAM1/2 and flash memory interface). Before using a peripheral the user has to enable its clock in the RCC_AHBxENR and the RCC_APBxENR registers.

Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

2.2 TrustZone security architecture

The security architecture is based on Arm TrustZone with the Armv8-M main extension.

The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.

When the TrustZone is enabled, the SAU (security attribution unit) and IDAU (implementation defined attribution unit) define the memory access permissions based on secure or non-secure state of the processor.

• • SAU: Up to eight SAU configurable regions are available for security attribution.
• • IDAU: It provides a first memory partition between non-secure and non-secure-callable regions. The IDAU memory map partition is not configurable and fixed by hardware implementation (refer to Figure 2 ). It is then combined with the results from the SAU security attribution and the most secure level between the two is selected.

Based on IDAU security attribution, the flash, system SRAMs and peripherals memory space is aliased twice for secure and non-secure state. However, the external memories space is not aliased.

The table below shows an example of typical eight SAU regions mapping based on IDAU regions. The user can split and choose the secure, non-secure or NSC regions for external memories as needed.

Table 1. Example of memory map security attribution versus SAU regions configuration ⁽¹⁾

1. Different colors highlights the different configurations: pink = non-secure, blue= NSC (non-secure callable), and green = secure, non-secure, or NSC.

2.2.1 Default TrustZone security state

When the TrustZone security is activated by the TZEN option bit in the FLASH_OPTR, the default system security state is:

• • CPU:
  • – Cortex-M33 is in secure state after reset. The boot address must be in secure address (i.e. belonging to the secure part of the memory map).
• • Memory map:
  • – SAU: is fully secure after reset. Consequently, the memory map is fully secure. Up to 8 SAU configurable regions are available for security attribution.

• • Flash:
  • – Flash secure regions are defined by watermark user options.
  • – Flash interface blocks (pages) are all non-Secure after reset (but the watermark configuration supersedes the block-based one in case of overlap).
• • SRAMs:
  • – All SRAMs are secure after reset. MPCBB (memory protection block based controller) is configured as fully secure.
• • External memories:
  • – FSMC, and OCTOSPI banks are secure after reset. MPCWM (memory protection watermark based controller) is secure.
• • All peripherals (except GPIOs) are non secure after reset. For TrustZone-aware peripherals, their secure configuration registers are secure.

Note: Refer to Table 2 and Table 3 for a list of securable and TrustZone-aware peripherals.

• • All GPIO are secure after reset.
• • Interrupts:
  • – NVIC: All interrupts are secure after reset. NVIC is banked for secure and non-secure state.
  • – TZIC: All illegal access interrupts are disabled after reset.

2.2.2 TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either securable or TrustZone-aware type as defined below:

• • securable: a peripheral is protected by an AHB/APB firewall gate that is controlled from TZSC controller to define security properties.
• • TrustZone-aware: a peripheral connected directly to AHB or APB bus and implementing a specific TrustZone behavior such as a subset of registers being secure. TrustZone-aware AHB masters always drive HNONSEC signal according to their security mode (as CM33 core and DMA).

Refer to Section 5.2.1: GTZC TrustZone system architecture

Table 2 and Table 3 summarize the list of Securables and TrustZone aware peripherals within the system.

Table 2. Securables peripherals by TZSC

Table 2. Securable peripherals by TZSC (continued)

Table 2. Securable peripherals by TZSC (continued)

Table 3. TrustZone-aware peripherals

1. Always secure when TZEN = 1.

2.3 Memory organization

2.3.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

2.3.2 Memory map and register boundary addresses

Figure 2. Memory map based on IDAU mapping

All the memory map areas that are not allocated to memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to the following table.

The following table gives the boundary addresses of the peripherals available in the devices.

Table 4. STM32L552xx and STM32L562xx memory map and peripheral register boundary addresses

Table 4. STM32L552xx and STM32L562xx memory map and peripheral register boundary addresses (continued)

Table 4. STM32L552xx and STM32L562xx memory map and peripheral register boundary addresses (continued)

Table 4. STM32L552xx and STM32L562xx memory map and peripheral register boundary addresses (continued)

Table 4. STM32L552xx and STM32L562xx memory map and peripheral register boundary addresses (continued)

2.4 Embedded SRAM

The STM32L552xx and STM32L562xx devices feature up to 256 Kbytes SRAM:

• • 192 Kbytes SRAM1
• • 64 Kbytes SRAM2

These SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). These memories can be addressed at maximum system clock frequency without wait state and thus by both CPU and DMA.

The CPU can access the SRAM1 and SRAM2 through the system bus or through the C-bus depending on the selected address.

Either 64 Kbytes or upper 4 Kbytes of SRAM2 can be retained in Standby mode.

When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM can be programmed as non-secure with a block granularity, using MPCBB (memory protection controller block configuration based) in GTZC controller. The granularity of SRAM secure/non-secure block-based is a page of 256 bytes.

2.4.1 SRAM2 parity check

The user can enable the SRAM2 parity check using the option bit SRAM2_PE in the OPTTR user option register (refer to Section 6.4.1: Option bytes description ).

The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in order to increase memory robustness, as required for instance by Class B or SIL safety standards.

The parity bits are computed and stored when writing into the SRAM2. Then, they are automatically checked when reading. If one bit fails, an NMI is generated. The same error can also be linked to the BRK_IN Break input of TIM1/TIM8/TIM15/TIM16/TIM17 with the SPL control bit in the SYSCFG configuration register 2 (SYSCFG_CFGR2) . The SRAM2 Parity Error flag (SPF) is available in the SYSCFG configuration register 2 (SYSCFG_CFGR2) .

Note: When enabling the RAM parity check, it is advised to initialize by software the whole RAM memory at the beginning of the code, to avoid getting parity errors when reading non-initialized locations.

2.4.2 SRAM2 Write protection

The SRAM2 can be write protected with a page granularity of 1 Kbyte.

Table 5. SRAM2 organization

Table 5. SRAM2 organization (continued)

The write protection can be enabled in SYSCFG SRAM2 write protection register (SYSCFG_SWPR) in the SYSCFG block. This is a register with write '1' once mechanism, which means that writing '1' on a bit will setup the write protection for that page of SRAM and it can be removed/cleared by a system reset only.

2.4.3 SRAM2 Read protection

The SRAM2 is protected with the Read protection (RDP). Refer to Section 6.7.2: Readout protection (RDP) for more details.

2.4.4 SRAM2 Erase

The SRAM2 can be erased with a system reset using the option bit SRAM2_RST in the OPTR user option register (refer to Section 6.4.1: Option bytes description ).

The SRAM2 erase can also be requested by software by setting the bit SRAM2ER in the SYSCFG SRAM2 control and status register (SYSCFG_SCSR) .

The SRAM2 is also erased by a Backup domain reset.

2.5 Flash memory overview

The flash memory is composed of two distinct physical areas:

• • The main flash memory block. It contains the application program and user data if necessary.
• • The information block. It is composed of three parts:
  • – Option bytes for hardware and memory protection user configuration.
  • – System memory that contains the ST proprietary code.
  • – OTP (one-time programmable) area

The flash interface implements instruction access and data access based on the AHB protocol. It also implements the logic necessary to carry out the flash memory operations (program/erase) controlled through the flash registers plus security access control features. Refer to Section 6: Embedded flash memory (FLASH) for more details.

3 Boot configuration

At startup, a BOOT0 pin, nBOOT0 and NSBOOTADDx[24:0] / SECBOOTADD0[24:0] option bytes are used to select the boot memory address which includes:

• • Boot from any address in user flash
• • Boot from system memory bootloader
• • Boot from any address in embedded SRAM
• • Boot from Root Security service (RSS)

The BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed.

Refer to Table 6 and Table 7 for boot modes when TrustZone is disabled and enabled respectively.

Table 6. Boot modes when TrustZone is disabled (TZEN=0)

When TrustZone is enabled by setting the TZEN option bit, the boot space must be in secure area. The SECBOOTADD0[24:0] option bytes are used to select the boot secure memory address.

A unique boot entry option can be selected by setting the BOOT_LOCK option bit. All other boot options are ignored.

Table 7. Boot modes when TrustZone is enabled (TZEN=1)

The boot address option bytes enables the possibility to program any boot memory address. However, the allowed address space depends on flash read protection RDP level.

If the programmed boot memory address is out of the allowed memory mapped area when RDP level is 0.5 or more, the default boot fetch address is forced to:

• • 0x0800 0000 (when TZEN = 0)
• • RSS (when TZEN = 1)

Refer to the Table 8 .

Table 8. Boot space versus RDP protection

1. 1. In RDP level 2, the boot is done from the address programmed in NSBOOTADD0 or NSBOOTADD1 depending on the boot configuration before setting the RDP level 2 and if the programmed address is within the user flash memory.
   If the programmed NSBOOTADD0 or NSBOOTADD1 is not a valid address, the boot is forced at 0x800 0000.

The BOOT0 value (either coming from the pin or the option bit) is latched upon reset release. It is up to the user to set nBOOT0 or BOOT0 values to select the required boot mode.

The BOOT0 pin or user option bit (depending on the nSWBOOT0 bit value in the FLASH_OPTR register) is also re-sampled when exiting from Standby mode. Consequently, they must be kept in the required Boot mode configuration in Standby mode. After startup delay, the selection of the boot area is done before releasing the processor reset.

PH3/BOOT0 GPIO is configured in:

• • Input mode during the complete reset phase if the option bit nSWBOOT0 is set into the FLASH_OPTR register and then switches automatically in analog mode after reset is released (BOOT0 pin).
• • Input mode from the reset phase to the completion of the option byte loading if the bit nSWBOOT0 is cleared into the FLASH_OPTR register (BOOT0 value coming from the option bit). It switches then automatically to the analog mode even if the reset phase is not complete.

Embedded bootloader and RSS

The bootloader is located in the system memory. It is used to reprogram the flash memory by using USART, I2C, SPI, FDCAN or USB FS in device mode through the DFU (device firmware upgrade). It is programmed by ST during production. Refer to AN2606, STM32 microcontroller system memory boot mode .

The root secure services (RSS) are embedded in a flash memory area named secure information block, programmed during ST production.

The RSS enables for example the secure firmware installation (SFI) thanks to the RSS extension firmware (RSSe SFI).

This feature allows the customers to protect the confidentiality of the firmware to be provisioned into the STM32 device when the production is subcontracted to a third party.

The RSS is available on all devices, after enabling the TrustZone through the TZEN option bit.