RM0438-STM32L5

This reference manual targets application developers. It provides complete information on how to use the STM32L552xx and STM32L562xx microcontrollers memory and peripherals.

STM32L552xx and STM32L562xx belong to the STM32L5x2 line of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets.

For information on the Arm ® Cortex ® -M33 core, refer to the Cortex ® -M33 Technical Reference manual .

The STM32L552xx and STM32L562xx microprocessors include ST state-of-the-art patented technology.

Contents

4.3Secure install . . . . .101
4.4Secure boot . . . . .101
4.4.1Introduction . . . . .101
4.4.2Unique boot entry and BOOT_LOCK . . . . .102
4.4.3Immutable root of trust in system flash memory . . . . .102
4.5Secure update . . . . .102
4.6Resource isolation using TrustZone . . . . .103
4.6.1Introduction . . . . .103
4.6.2TrustZone security architecture . . . . .103
4.6.3Armv8-M security extension of Cortex-M33 . . . . .104
4.6.4Memory and peripheral allocation using IDAU/SAU . . . . .104
4.6.5Memory and peripheral allocation using GTZC . . . . .106
4.6.6Managing security in TrustZone-aware peripherals . . . . .109
4.6.7Activating TrustZone security . . . . .116
4.6.8De-activating TrustZone security . . . . .116
4.7Other resource isolations . . . . .117
4.7.1Temporal isolation using secure hide protection (HDP) . . . . .117
4.8Secure execution . . . . .118
4.8.1Introduction . . . . .118
4.8.2Memory protection unit (MPU) . . . . .118
4.8.3Embedded flash memory write protection . . . . .118
4.8.4Tamper detection and response . . . . .118
4.9Secure storage . . . . .120
4.9.1Introduction . . . . .120
4.9.2Unique ID . . . . .121
4.10Crypto engines . . . . .121
4.10.1Introduction . . . . .121
4.10.2Crypto engines features . . . . .121
4.10.3On-the-fly decryption engine (OTFDEC) . . . . .122
4.11Product lifecycle . . . . .123
4.11.1Lifecycle management with readout protection (RDP) . . . . .124
4.11.2Recommended option byte settings . . . . .125
4.12Access controlled debug . . . . .125
4.12.1Debug protection with readout protection (RDP) . . . . .125
4.13Software intellectual property protection and collaborative development126
4.13.1Software intellectual property protection with readout protection (RDP) . . . . .126
4.13.2Software intellectual property protection with OTFDEC . . . . .127
4.13.3Other software intellectual property protections . . . . .129
5Global TrustZone® controller (GTZC) . . . . .130
5.1GTZC introduction . . . . .130
5.2GTZC main features . . . . .130
5.2.1GTZC TrustZone system architecture . . . . .130
5.3GTZC functional description . . . . .132
5.3.1GTZC block diagram . . . . .132
5.3.2Illegal access definition . . . . .133
5.3.3TrustZone security controller (TZSC) . . . . .134
5.3.4Memory protection controller - block based (MPCBB) . . . . .134
5.3.5TrustZone illegal access controller (TZIC) . . . . .135
5.3.6Power-on/reset state . . . . .135
5.3.7DMA requests . . . . .135
5.4GTZC events . . . . .135
5.5GTZC_TZSC registers . . . . .136
5.5.1GTZC_TZSC control register (GTZC_TZSC_CR) . . . . .136
5.5.2GTZC_TZSC secure configuration register 1
(GTZC_TZSC_SECCFGR1) . . . . .		137
5.5.3GTZC_TZSC secure configuration register 2
(GTZC_TZSC_SECCFGR2) . . . . .		140
5.5.4GTZC_TZSC privilege configuration register 1
(GTZC_TZSC_PRIVCFGR1) . . . . .		142
5.5.5GTZC_TZSC privilege configuration register 2
(GTZC_TZSC_PRIVCFGR2) . . . . .		145
5.5.6GTZC_TZSC external memory x non-secure watermark register 1
(GTZC_TZSC_MPCWMxANSR) . . . . .		147
5.5.7GTZC_TZSC external memory x non-secure watermark register 2
(GTZC_TZSC_MPCWMxBNSR) . . . . .		147
5.5.8GTZC_TZSC register map and reset values . . . . .148
5.6GTZC_MPCBB registers . . . . .150
5.6.1GTZC_MPCBBx control register (GTZC_MPCBBx_CR) (x = 1 to 2) . . . . .150
5.6.2GTZC_MPCBB1 lock register 1(GTZC_MPCBB1_LCKVTR1) . . . . .151
5.6.3GTZC_MPCBB2 lock register 1
(GTZC_MPCBB2_LCKVTR1) . . . . .		151
5.6.4GTZC_MPCBBx vector register y (GTZC_MPCBBx_VCTRY) (x = 1 to 2) .....152
5.6.5GTZC_MPCBB1 register map and reset values .....153
5.6.6GTZC_MPCBB2 register map and reset values .....153
5.7GTZC_TZIC registers .....154
5.7.1GTZC_TZIC interrupt enable register 1 (GTZC_TZIC_IER1) .....154
5.7.2GTZC_TZIC interrupt enable register 2 (GTZC_TZIC_IER2) .....157
5.7.3GTZC_TZIC interrupt enable register 3 (GTZC_TZIC_IER3) .....159
5.7.4GTZC_TZIC status register 1 (GTZC_TZIC_SR1) .....160
5.7.5GTZC_TZIC status register 2 (GTZC_TZIC_SR2) .....163
5.7.6GTZC_TZIC status register 3 (GTZC_TZIC_SR3) .....165
5.7.7GTZC_TZIC flag clear register 1 (GTZC_TZIC_FCR1) .....166
5.7.8GTZC_TZIC flag clear register 2 (GTZC_TZIC_FCR2) .....169
5.7.9GTZC_TZIC flag clear register 3 (GTZC_TZIC_FCR3) .....171
5.7.10GTZC_TZIC register map and reset values .....172
6Embedded flash memory (FLASH) .....174
6.1Introduction .....174
6.2FLASH main features .....174
6.3Flash memory functional description .....175
6.3.1Flash memory organization .....175
6.3.2Error code correction (ECC) .....178
6.3.3Read access latency .....179
6.3.4Low-voltage read .....180
6.3.5Flash program and erase operations .....180
6.3.6Flash main memory erase sequences .....182
6.3.7Flash main memory programming sequences .....185
6.3.8Flash errors flags .....186
6.3.9Read-while-write (RWW) available only in dual-bank mode (DBANK = 1) .....188
6.4Flash memory option bytes .....190
6.4.1Option bytes description .....190
6.4.2Option bytes programming .....191
6.5Flash TrustZone security and privilege protections .....193
6.5.1TrustZone security protection .....193
6.5.2Secure watermark-based area protection .....195
6.5.3Secure hide protection (HDP) .....195
6.5.4Secure block-based area (SECB) protection . . . . .196
6.5.5Forcing boot from a secure memory address . . . . .197
6.5.6Flash security attribute state . . . . .197
6.5.7Flash registers privileged and unprivileged modes . . . . .198
6.6Secure system memory . . . . .198
6.6.1Introduction . . . . .198
6.6.2RSS allocates resource to bootloader . . . . .198
6.6.3RSSLIB functions . . . . .200
6.7FLASH memory protection . . . . .202
6.7.1Write protection (WRP) . . . . .202
6.7.2Readout protection (RDP) . . . . .204
6.8FLASH interrupts . . . . .212
6.9FLASH registers . . . . .213
6.9.1Flash access control register (FLASH_ACR) . . . . .213
6.9.2Flash power-down key register (FLASH_PDKEYR) . . . . .214
6.9.3Flash non-secure key register (FLASH_NSKEYR) . . . . .215
6.9.4Flash secure key register (FLASH_SECKEYR) . . . . .215
6.9.5Flash option key register (FLASH_OPTKEYR) . . . . .216
6.9.6Flash low voltage key register (FLASH_LVEKEYR) . . . . .216
6.9.7Flash status register (FLASH_NSSR) . . . . .217
6.9.8Flash status register (FLASH_SECSR) . . . . .218
6.9.9Flash non-secure control register (FLASH_NSCR) . . . . .220
6.9.10Flash secure control register (FLASH_SECCR) . . . . .222
6.9.11Flash ECC register (FLASH_ECCR) . . . . .223
6.9.12Flash option register (FLASH_OPTR) . . . . .225
6.9.13Flash non-secure boot address 0 register (FLASH_NSBOOTADD0R) . . . . .227
6.9.14Flash non-secure boot address 1 register (FLASH_NSBOOTADD1R) . . . . .228
6.9.15Flash secure boot address 0 register (FLASH_SECBOOTADD0R) . . . . .228
6.9.16Flash bank 1 secure watermak1 register (FLASH_SECWM1R1) . . . . .229
6.9.17Flash secure watermak1 register 2 (FLASH_SECWM1R2) . . . . .230
6.9.18Flash WPR1 area A address register (FLASH_WRP1AR) . . . . .231
6.9.19Flash WPR1 area B address register (FLASH_WRP1BR) . . . . .232
6.9.20Flash secure watermak2 register (FLASH_SECWM2R1) . . . . .233
6.9.21Flash secure watermak2 register 2 (FLASH_SECWM2R2) . . . . .234
6.9.22Flash WPR2 area A address register (FLASH_WRP2AR) . . . . .235
6.9.23Flash WPR2 area B address register (FLASH_WRP2BR) . . . . .236
6.9.24FLASH secure block based bank 1 register (FLASH_SECB1Rx) (where x=1..4) . . . . .237
6.9.25FLASH secure block based bank 2 register (FLASH_SECB2Rx) (where x=1..4) . . . . .237
6.9.26FLASH secure HDP control register (FLASH_SECHDPCR) . . . . .238
6.9.27FLASH privilege configuration register (FLASH_PRIVCFGR) . . . . .238
6.9.28FLASH register map and reset values . . . . .239
7Instruction cache (ICACHE) . . . . .242
7.1ICACHE introduction . . . . .242
7.2ICACHE main features . . . . .242
7.3ICACHE implementation . . . . .243
7.4ICACHE functional description . . . . .243
7.4.1ICACHE block diagram . . . . .244
7.4.2ICACHE reset and clocks . . . . .244
7.4.3ICACHE TAG memory . . . . .245
7.4.4Direct-mapped ICACHE (1-way cache) . . . . .246
7.4.5ICACHE enable . . . . .247
7.4.6Cacheable and noncacheable traffic . . . . .247
7.4.7Address remapping . . . . .248
7.4.8Cacheable accesses . . . . .250
7.4.9Dual-master cache . . . . .251
7.4.10ICACHE security . . . . .251
7.4.11ICACHE maintenance . . . . .251
7.4.12ICACHE performance monitoring . . . . .252
7.4.13ICACHE boot . . . . .252
7.5ICACHE low-power modes . . . . .252
7.6ICACHE error management and interrupts . . . . .253
7.7ICACHE registers . . . . .253
7.7.1ICACHE control register (ICACHE_CR) . . . . .253
7.7.2ICACHE status register (ICACHE_SR) . . . . .254
7.7.3ICACHE interrupt enable register (ICACHE_IER) . . . . .255
7.7.4ICACHE flag clear register (ICACHE_FCR) . . . . .255
7.7.5ICACHE hit monitor register (ICACHE_HMONR) . . . . .256
7.7.6ICACHE miss monitor register (ICACHE_MMONR) . . . . .256
7.7.7ICACHE region x configuration register (ICACHE_CRRx) . . . . .256
7.7.8ICACHE register map . . . . .258
8Power control (PWR) . . . . .259
8.1Power supplies and supply domains . . . . .259
8.1.1Independent analog peripherals supply . . . . .264
8.1.2Independent I/O supply rail . . . . .264
8.1.3Independent USB transceivers supply . . . . .264
8.1.4Battery backup domain . . . . .265
8.2System supply voltage regulation . . . . .266
8.2.1Voltage regulator . . . . .266
8.2.2Embedded SMPS step down converter . . . . .267
8.2.3SMPS step down converter power supply scheme . . . . .268
8.2.4SMPS step down converter versus low-power mode . . . . .269
8.2.5Dynamic voltage scaling management . . . . .270
8.2.6VDD12 domain and external SMPS . . . . .271
8.3Power supply supervision . . . . .273
8.3.1Power-on reset (POR) / power-down reset (PDR) /
brown-out reset (BOR) . . . . .		273
8.3.2Programmable voltage detector (PVD) . . . . .274
8.3.3Peripheral voltage monitoring (PVM) . . . . .275
8.3.4Upper voltage threshold monitoring . . . . .276
8.3.5Temperature threshold monitoring . . . . .276
8.4Power management . . . . .277
8.4.1Power modes . . . . .277
8.4.2Run mode . . . . .283
8.4.3Low-power run mode (LP run) . . . . .283
8.4.4Low-power modes . . . . .284
8.4.5Sleep mode . . . . .285
8.4.6Low-power sleep mode (LP sleep) . . . . .286
8.4.7Stop 0 mode . . . . .287
8.4.8Stop 1 mode . . . . .289
8.4.9Stop 2 mode . . . . .290
8.4.10Standby mode . . . . .292
8.4.11Shutdown mode . . . . .295
8.4.12Auto-wakeup from a low-power mode . . . . .296
8.5PWR TrustZone security . . . . .296
8.5.1PWR Privileged and Unprivileged modes . . . . .298
8.6PWR registers . . . . .298
8.6.1Power control register 1 (PWR_CR1) . . . . .299
8.6.2Power control register 2 (PWR_CR2) . . . . .300
8.6.3Power control register 3 (PWR_CR3) . . . . .301
8.6.4Power control register 4 (PWR_CR4) . . . . .303
8.6.5Power status register 1 (PWR_SR1) . . . . .304
8.6.6Power status register 2 (PWR_SR2) . . . . .306
8.6.7Power status clear register (PWR_SCR) . . . . .307
8.6.8Power Port A pull-up control register (PWR_PUCRA) . . . . .308
8.6.9Power Port A pull-down control register (PWR_PDCRA) . . . . .308
8.6.10Power Port B pull-up control register (PWR_PUCRB) . . . . .309
8.6.11Power Port B pull-down control register (PWR_PDCRB) . . . . .310
8.6.12Power Port C pull-up control register (PWR_PUCRC) . . . . .310
8.6.13Power Port C pull-down control register (PWR_PDCRC) . . . . .311
8.6.14Power Port D pull-up control register (PWR_PUCRD) . . . . .311
8.6.15Power Port D pull-down control register (PWR_PDCRD) . . . . .312
8.6.16Power Port E pull-up control register (PWR_PUCRE) . . . . .313
8.6.17Power Port E pull-down control register (PWR_PDCRE) . . . . .313
8.6.18Power Port F pull-up control register (PWR_PUCRF) . . . . .314
8.6.19Power Port F pull-down control register (PWR_PDCRF) . . . . .314
8.6.20Power Port G pull-up control register (PWR_PUCRG) . . . . .315
8.6.21Power Port G pull-down control register (PWR_PDCRG) . . . . .316
8.6.22Power Port H pull-up control register (PWR_PUCRH) . . . . .316
8.6.23Power Port H pull-down control register (PWR_PDCRH) . . . . .317
8.6.24Power secure configuration register (PWR_SECCFGR) . . . . .317
8.6.25Power privilege configuration register (PWR_PRIVCFGR) . . . . .319
8.6.26PWR register map and reset values . . . . .320
9Reset and clock control (RCC) . . . . .323
9.1Reset . . . . .323
9.1.1Power reset . . . . .323
9.1.2System reset . . . . .323
9.1.3Backup domain reset . . . . .325
9.2RCC pins and internal signals . . . . .325
9.3Clocks . . . . .325
9.3.1HSE clock . . . . .329
9.3.2HSI16 clock . . . . .330
9.3.3MSI clock . . . . .331
9.3.4HSI48 clock .....332
9.3.5PLL .....332
9.3.6LSE clock .....333
9.3.7LSE system clock .....333
9.3.8LSI clock .....334
9.3.9System clock (SYSCLK) selection .....334
9.3.10Clock source frequency versus voltage scaling .....335
9.3.11Clock security system (CSS) .....335
9.3.12Clock security system on LSE .....335
9.3.13ADC clock .....336
9.3.14RTC clock .....336
9.3.15Timer clock .....336
9.3.16Watchdog clock .....337
9.3.17Clock-out capability .....337
9.3.18Internal/external clock measurement with TIM15/TIM16/TIM17 .....337
9.3.19Peripheral clock enable registers
(RCC_AHBxENR, RCC_APBxENRy) .....		340
9.4Low-power modes .....340
9.5RCC TrustZone ® security .....341
9.6RCC Privileged and Unprivileged mode .....343
9.7RCC interrupts .....343
9.8RCC registers .....345
9.8.1RCC clock control register (RCC_CR) .....345
9.8.2RCC internal clock sources calibration register (RCC_ICSCR) .....348
9.8.3RCC clock configuration register (RCC_CFGR) .....349
9.8.4RCC PLL configuration register (RCC_PLLCFGR) .....352
9.8.5RCC PLLSAI1 configuration register (RCC_PLLSAI1CFGR) .....355
9.8.6RCC PLLSAI2 configuration register (RCC_PLLSAI2CFGR) .....358
9.8.7RCC clock interrupt enable register (RCC_CIER) .....360
9.8.8RCC clock interrupt flag register (RCC_CIFR) .....361
9.8.9RCC clock interrupt clear register (RCC_CICR) .....363
9.8.10RCC AHB1 peripheral reset register (RCC_AHB1RSTR) .....364
9.8.11RCC AHB2 peripheral reset register (RCC_AHB2RSTR) .....365
9.8.12RCC AHB3 peripheral reset register (RCC_AHB3RSTR) .....367
9.8.13RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) .....368
9.8.14RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) .....370
9.8.15RCC APB2 peripheral reset register (RCC_APB2RSTR) .....371
9.8.16RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .373
9.8.17RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .374
9.8.18RCC AHB3 peripheral clock enable register(RCC_AHB3ENR) . . . . .376
9.8.19RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . .377
9.8.20RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . .379
9.8.21RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .381
9.8.22RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR) . . . . .		382
9.8.23RCC AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR) . . . . .		384
9.8.24RCC AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR) . . . . .		386
9.8.25RCC APB1 peripheral clocks enable in Sleep and Stop modes
register 1 (RCC_APB1SMENR1) . . . . .		387
9.8.26RCC APB1 peripheral clocks enable in Sleep and Stop modes
register 2 (RCC_APB1SMENR2) . . . . .		390
9.8.27RCC APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR) . . . . .		391
9.8.28RCC peripherals independent clock configuration register 1
(RCC_CCIPR1) . . . . .		393
9.8.29RCC Backup domain control register (RCC_BDCR) . . . . .395
9.8.30RCC control/status register (RCC_CSR) . . . . .398
9.8.31RCC clock recovery RC register (RCC_CRRRCR) . . . . .400
9.8.32RCC peripherals independent clock configuration register 2
(RCC_CCIPR2) . . . . .		401
9.8.33OCTOSPI delay configuration register (RCC_DLYCFGR) . . . . .402
9.8.34RCC secure configuration register (RCC_SECCFGR) . . . . .403
9.8.35RCC secure status register (RCC_SECSR) . . . . .405
9.8.36RCC AHB1 security status register (RCC_AHB1SECSR) . . . . .407
9.8.37RCC AHB2 security status register (RCC_AHB2SECSR) . . . . .408
9.8.38RCC AHB3 security status register (RCC_AHB3SECSR) . . . . .410
9.8.39RCC APB1 security status register 1 (RCC_APB1SECSR1) . . . . .411
9.8.40RCC APB1 security status register 2 (RCC_APB1SECSR2) . . . . .414
9.8.41RCC APB2 security status register (RCC_APB2SECSR) . . . . .415
9.8.42RCC register map . . . . .417
10Clock recovery system (CRS) . . . . .424
10.1CRS introduction . . . . .424
10.2CRS main features . . . . .424
10.3CRS implementation . . . . .424
10.4CRS functional description . . . . .425
10.4.1CRS block diagram . . . . .425
10.4.2CRS internal signals . . . . .425
10.4.3Synchronization input . . . . .426
10.4.4Frequency error measurement . . . . .426
10.4.5Frequency error evaluation and automatic trimming . . . . .427
10.4.6CRS initialization and configuration . . . . .428
10.5CRS in low-power modes . . . . .429
10.6CRS interrupts . . . . .429
10.7CRS registers . . . . .429
10.7.1CRS control register (CRS_CR) . . . . .429
10.7.2CRS configuration register (CRS_CFGR) . . . . .430
10.7.3CRS interrupt and status register (CRS_ISR) . . . . .431
10.7.4CRS interrupt flag clear register (CRS_ICR) . . . . .433
10.7.5CRS register map . . . . .434
11General-purpose I/Os (GPIO) . . . . .435
11.1Introduction . . . . .435
11.2GPIO main features . . . . .435
11.3GPIO functional description . . . . .435
11.3.1General-purpose I/O (GPIO) . . . . .438
11.3.2I/O pin alternate function multiplexer and mapping . . . . .438
11.3.3I/O port control registers . . . . .439
11.3.4I/O port data registers . . . . .439
11.3.5I/O data bitwise handling . . . . .439
11.3.6GPIO locking mechanism . . . . .440
11.3.7I/O alternate function input/output . . . . .440
11.3.8External interrupt/wakeup lines . . . . .440
11.3.9Input configuration . . . . .441
11.3.10Output configuration . . . . .441
11.3.11Alternate function configuration . . . . .442
11.3.12Analog configuration . . . . .443
11.3.13Using the HSE or LSE oscillator pins as GPIOs . . . . .443
11.3.14Using the GPIO pins in the RTC supply domain . . . . .443
11.3.15Using PH3 as GPIO . . . . .444
11.4TrustZone security . . . . .444
11.5Privileged and Unprivileged modes . . . . .445
11.6GPIO registers . . . . .446
11.6.1GPIO port mode register (GPIOx_MODER)
(x =A to H) . . . . .		446
11.6.2GPIO port output type register (GPIOx_OTYPER)
(x = A to H) . . . . .		446
11.6.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to H) . . . . .		447
11.6.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to H) . . . . .		447
11.6.5GPIO port input data register (GPIOx_IDR)
(x = A to H) . . . . .		448
11.6.6GPIO port output data register (GPIOx_ODR)
(x = A to H) . . . . .		448
11.6.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to H) . . . . .		448
11.6.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to H) . . . . .		449
11.6.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to H) . . . . .		450
11.6.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to H) . . . . .		451
11.6.11GPIO port bit reset register (GPIOx_BRR) (x = A to H) . . . . .452
11.6.12GPIO secure configuration register (GPIOx_SECCFGR) (x = A to H) . . . . .452
11.6.13GPIO register map . . . . .454
12System configuration controller (SYSCFG) . . . . .456
12.1SYSCFG main features . . . . .456
12.2SYSCFG TrustZone security and privilege . . . . .456
12.3SYSCFG registers . . . . .458
12.3.1SYSCFG secure configuration register (SYSCFG_SECCFGR) . . . . .458
12.3.2SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .459
12.3.3FPU interrupt mask register (SYSCFG_FPUIMR) . . . . .461
12.3.4SYSCFG CPU non-secure lock register (SYSCFG_CNSLCKR) . . . . .461
12.3.5SYSCFG CPU secure lock register (SYSCFG_CSLOCKR) . . . . .462
12.3.6SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .463
12.3.7SYSCFG SRAM2 control and status register (SYSCFG_SCSR) . . . . .464
12.3.8SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . .465

13        Peripherals interconnect matrix . . . . . 469

14        Direct memory access controller (DMA) . . . . . 478

14.3.1DMA1 and DMA2 . . . . .479
14.3.2DMA request mapping . . . . .479
14.4DMA functional description . . . . .480
14.4.1DMA block diagram . . . . .480
14.4.2DMA pins and internal signals . . . . .481
14.4.3DMA transfers . . . . .481
14.4.4DMA arbitration . . . . .482
14.4.5DMA channels . . . . .483
14.4.6DMA data width, alignment and endianness . . . . .488
14.4.7DMA error management . . . . .489
14.5DMA interrupts . . . . .490
14.6DMA registers . . . . .490
14.6.1DMA interrupt status register (DMA_ISR) . . . . .490
14.6.2DMA interrupt flag clear register (DMA_IFCR) . . . . .494
14.6.3DMA channel x configuration register (DMA_CCRx) . . . . .495
14.6.4DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . .500
14.6.5DMA channel x peripheral address register (DMA_CPARx) . . . . .501
14.6.6DMA channel x memory 0 address register (DMA_CM0ARx) . . . . .501
14.6.7DMA channel x memory 1 address register (DMA_CM1ARx) . . . . .502
14.6.8DMA register map . . . . .502
15DMA request multiplexer (DMAMUX) . . . . .506
15.1Introduction . . . . .506
15.2DMAMUX main features . . . . .507
15.3DMAMUX implementation . . . . .507
15.3.1DMAMUX instantiation . . . . .507
15.3.2DMAMUX mapping . . . . .508
15.4DMAMUX functional description . . . . .511
15.4.1DMAMUX block diagram . . . . .511
15.4.2DMAMUX signals . . . . .512
15.4.3DMAMUX channels . . . . .512
15.4.4DMAMUX secure/non-secure channels . . . . .513
15.4.5DMAMUX privileged / unprivileged channels . . . . .513
15.4.6DMAMUX request line multiplexer . . . . .513
15.4.7DMAMUX request generator . . . . .516
15.5DMAMUX interrupts . . . . .517
15.6DMAMUX registers . . . . .519
15.6.1DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR) . . . . .519
15.6.2DMAMUX request line multiplexer interrupt channel status register (DMAMUX_CSR) . . . . .520
15.6.3DMAMUX request line multiplexer interrupt channel clear flag register (DMAMUX_CCFR) . . . . .520
15.6.4DMAMUX request generator channel x configuration register (DMAMUX_RGxCR) . . . . .521
15.6.5DMAMUX request generator interrupt status register (DMAMUX_RGSR) . . . . .522
15.6.6DMAMUX request generator interrupt clear flag register (DMAMUX_RGCFR) . . . . .523
15.6.7DMAMUX register map . . . . .524
16Nested vectored interrupt controller (NVIC) . . . . .528
16.1NVIC main features . . . . .528
16.2SysTick calibration value register . . . . .528
16.3Interrupt and exception vectors . . . . .529
17Extended interrupts and event controller (EXTI) . . . . .533
17.1EXTI main features . . . . .533
17.2EXTI block diagram . . . . .534
17.2.1EXTI connections between peripherals and CPU . . . . .535
17.2.2EXTI interrupt/event mapping . . . . .535
17.3EXTI functional description . . . . .537
17.3.1EXTI configurable event input wakeup . . . . .537
17.3.2EXTI direct event input wakeup . . . . .539
17.3.3EXTI mux selection . . . . .539
17.4EXTI functional behavior . . . . .540
17.5EXTI event protection . . . . .541
17.5.1EXTI security protection . . . . .541
17.5.2EXTI privilege protection . . . . .542
17.6EXTI registers . . . . .543
17.6.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .543
17.6.2EXTI falling trigger selection register (EXTI_FTSR1) . . . . .544
17.6.3EXTI software interrupt event register (EXTI_SWIER1) . . . . .545
17.6.4EXTI rising edge pending register (EXTI_RPR1) . . . . .546
17.6.5EXTI falling edge pending register (EXTI_FPR1) . . . . .547
17.6.6EXTI security configuration register (EXTI_SECCFGR1) . . . . .548
17.6.7EXTI privilege configuration register (EXTI_PRIVCFGR1) . . . . .549
17.6.8EXTI rising trigger selection register (EXTI_RTSR2) . . . . .549
17.6.9EXTI falling trigger selection register (EXTI_FTSR2) . . . . .550
17.6.10EXTI software interrupt event register (EXTI_SWIER2) . . . . .551
17.6.11EXTI rising edge pending register (EXTI_RPR2) . . . . .551
17.6.12EXTI falling edge pending register (EXTI_FPR2) . . . . .552
17.6.13EXTI security enable register (EXTI_SECCFGR2) . . . . .553
17.6.14EXTI privilege enable register (EXTI_PRIVCFGR2) . . . . .553
17.6.15EXTI external interrupt selection register (EXTI_EXTICRn) . . . . .554
17.6.16EXTI lock register (EXTI_LOCKR) . . . . .557
17.6.17EXTI CPU wakeup with interrupt mask register (EXTI_IMR1) . . . . .557
17.6.18EXTI CPU wakeup with event mask register (EXTI_EM1) . . . . .558
17.6.19EXTI CPU wakeup with interrupt mask register (EXTI_IMR2) . . . . .559
17.6.20EXTI CPU wakeup with event mask register (EXTI_EM2) . . . . .559
17.6.21EXTI register map . . . . .560
18Cyclic redundancy check calculation unit (CRC) . . . . .563
18.1CRC introduction . . . . .563
18.2CRC main features . . . . .563
18.3CRC functional description . . . . .564
18.3.1CRC block diagram . . . . .564
18.3.2CRC internal signals . . . . .564
18.3.3CRC operation . . . . .564
18.4CRC registers . . . . .566
18.4.1CRC data register (CRC_DR) . . . . .566
18.4.2CRC independent data register (CRC_IDR) . . . . .566
18.4.3CRC control register (CRC_CR) . . . . .567
18.4.4CRC initial value (CRC_INIT) . . . . .568
18.4.5CRC polynomial (CRC_POL) . . . . .568
18.4.6CRC register map . . . . .569
19Flexible static memory controller (FSMC) . . . . .570
19.1FMC introduction . . . . .570
19.2FMC main features . . . . .570
19.3FMC block diagram . . . . .571
19.4AHB interface . . . . .571
19.4.1Supported memories and transactions . . . . .572
19.5External device address mapping . . . . .573
19.5.1NOR/PSRAM address mapping . . . . .573
19.5.2NAND flash memory address mapping . . . . .574
19.6NOR flash/PSRAM controller . . . . .575
19.6.1External memory interface signals . . . . .576
19.6.2Supported memories and transactions . . . . .578
19.6.3General timing rules . . . . .580
19.6.4NOR flash/PSRAM controller asynchronous transactions . . . . .580
19.6.5Synchronous transactions . . . . .598
19.6.6NOR/PSRAM controller registers . . . . .605
19.7NAND flash controller . . . . .613
19.7.1External memory interface signals . . . . .613
19.7.2NAND flash supported memories and transactions . . . . .614
19.7.3Timing diagrams for NAND flash memory . . . . .615
19.7.4NAND flash operations . . . . .615
19.7.5NAND flash prewait functionality . . . . .616
19.7.6Computation of the error correction code (ECC)
in NAND flash memory . . . . .		617
19.7.7NAND flash controller registers . . . . .618
19.7.8FMC register map . . . . .624
20Octo-SPI interface (OCTOSPI) . . . . .626
20.1OCTOSPI introduction . . . . .626
20.2OCTOSPI main features . . . . .626
20.3OCTOSPI implementation . . . . .627
20.4OCTOSPI functional description . . . . .628
20.4.1OCTOSPI block diagram . . . . .628
20.4.2OCTOSPI pins and internal signals . . . . .629
20.4.3OCTOSPI interface to memory modes . . . . .630
20.4.4OCTOSPI regular-command protocol . . . . .630
20.4.5OCTOSPI regular-command protocol signal interface . . . . .634
20.4.6HyperBus protocol . . . . .637
20.4.7Specific features . . . . .641
20.4.8OCTOSPI operating mode introduction . . . . .642
20.4.9OCTOSPI indirect mode . . . . .642
20.4.10OCTOSPI automatic status-polling mode . . . . .644
20.4.11OCTOSPI memory-mapped mode . . . . .645
20.4.12OCTOSPI configuration introduction . . . . .646
20.4.13OCTOSPI system configuration . . . . .646
20.4.14OCTOSPI device configuration . . . . .646
20.4.15OCTOSPI regular-command mode configuration . . . . .649
20.4.16OCTOSPI HyperBus protocol configuration . . . . .651
20.4.17OCTOSPI error management . . . . .652
20.4.18OCTOSPI BUSY and ABORT . . . . .653
20.4.19OCTOSPI reconfiguration or deactivation . . . . .653
20.4.20NCS behavior . . . . .653
20.5Address alignment and data number . . . . .655
20.6OCTOSPI interrupts . . . . .656
20.7OCTOSPI registers . . . . .657
20.7.1OCTOSPI control register (OCTOSPI_CR) . . . . .657
20.7.2OCTOSPI device configuration register 1 (OCTOSPI_DCR1) . . . . .659
20.7.3OCTOSPI device configuration register 2 (OCTOSPI_DCR2) . . . . .661
20.7.4OCTOSPI device configuration register 3 (OCTOSPI_DCR3) . . . . .662
20.7.5OCTOSPI device configuration register 4 (OCTOSPI_DCR4) . . . . .662
20.7.6OCTOSPI status register (OCTOSPI_SR) . . . . .663
20.7.7OCTOSPI flag clear register (OCTOSPI_FCR) . . . . .664
20.7.8OCTOSPI data length register (OCTOSPI_DLR) . . . . .664
20.7.9OCTOSPI address register (OCTOSPI_AR) . . . . .665
20.7.10OCTOSPI data register (OCTOSPI_DR) . . . . .665
20.7.11OCTOSPI polling status mask register (OCTOSPI_PSMKR) . . . . .666
20.7.12OCTOSPI polling status match register (OCTOSPI_PSMAR) . . . . .667
20.7.13OCTOSPI polling interval register (OCTOSPI_PIR) . . . . .667
20.7.14OCTOSPI communication configuration register (OCTOSPI_CCR) . . . . .667
20.7.15OCTOSPI timing configuration register (OCTOSPI_TCR) . . . . .670
20.7.16OCTOSPI instruction register (OCTOSPI_IR) . . . . .670
20.7.17OCTOSPI alternate bytes register (OCTOSPI_ABR) . . . . .671
20.7.18OCTOSPI low-power timeout register (OCTOSPI_LPTR) . . . . .671
20.7.19OCTOSPI wrap communication configuration register
(OCTOSPI_WPCCR) . . . . .		672
20.7.20OCTOSPI wrap timing configuration register (OCTOSPI_WPTCR) . . . . .674
20.7.21OCTOSPI wrap instruction register (OCTOSPI_WPIR) . . . . .674
20.7.22OCTOSPI wrap alternate bytes register (OCTOSPI_WPABR) . . . . .675
20.7.23OCTOSPI write communication configuration register
(OCTOSPI_WCCR) . . . . .		675
20.7.24OCTOSPI write timing configuration register (OCTOSPI_WTCR) . . . . .677
20.7.25OCTOSPI write instruction register (OCTOSPI_WIR) . . . . .678
20.7.26OCTOSPI write alternate bytes register (OCTOSPI_WABR) . . . . .678
20.7.27OCTOSPI HyperBus latency configuration register
(OCTOSPI_HLCR) . . . . .		679
20.7.28OCTOSPI register map . . . . .679
21Analog-to-digital converters (ADC) . . . . .683
21.1ADC introduction . . . . .683
21.2ADC main features . . . . .684
21.3ADC implementation . . . . .685
21.4ADC functional description . . . . .686
21.4.1ADC block diagram . . . . .686
21.4.2ADC pins and internal signals . . . . .687
21.4.3ADC clocks . . . . .688
21.4.4ADC1/2 connectivity . . . . .690
21.4.5Slave AHB interface . . . . .692
21.4.6ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator
(ADVREGEN) . . . . .		692
21.4.7Single-ended and differential input channels . . . . .693
21.4.8Calibration (ADCAL, ADCALDIF, ADC_CALFACT) . . . . .693
21.4.9ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .696
21.4.10Constraints when writing the ADC control bits . . . . .697
21.4.11Channel selection (ADC_SQRy, ADC_JSQR) . . . . .698
21.4.12Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .699
21.4.13Single conversion mode (CONT = 0) . . . . .699
21.4.14Continuous conversion mode (CONT = 1) . . . . .700
21.4.15Starting conversions (ADSTART, JADSTART) . . . . .701
21.4.16ADC timing . . . . .702
21.4.17Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .702
21.4.18Conversion on external trigger and trigger polarity
(EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . .		704
21.4.19Injected channel management . . . . .706
21.4.20Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .708
21.4.21Queue of context for injected conversions . . . . .709
21.4.22Programmable resolution (RES) - Fast conversion mode . . . . .717
21.4.23End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . . . .718
21.4.24End of conversion sequence (EOS, JEOS) . . . . .718
21.4.25Timing diagrams example (single/continuous modes,
hardware/software triggers) . . . . .		719
21.4.26Data management . . . . .721
21.4.27Managing conversions using the DFSDM . . . . .726
21.4.28Dynamic low-power features . . . . .727
21.4.29Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,
AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . .		732
21.4.30Oversampler . . . . .736
21.4.31Dual ADC modes . . . . .742
21.4.32Temperature sensor . . . . .755
21.4.33VBAT supply monitoring . . . . .757
21.4.34Monitoring the internal voltage reference . . . . .758
21.5ADC in low-power mode . . . . .759
21.6ADC interrupts . . . . .760
21.7ADC registers (for each ADC) . . . . .761
21.7.1ADC interrupt and status register (ADC_ISR) . . . . .761
21.7.2ADC interrupt enable register (ADC_IER) . . . . .763
21.7.3ADC control register (ADC_CR) . . . . .765
21.7.4ADC configuration register (ADC_CFGR) . . . . .768
21.7.5ADC configuration register 2 (ADC_CFGR2) . . . . .772
21.7.6ADC sample time register 1 (ADC_SMPR1) . . . . .774
21.7.7ADC sample time register 2 (ADC_SMPR2) . . . . .775
21.7.8ADC watchdog threshold register 1 (ADC_TR1) . . . . .776
21.7.9ADC watchdog threshold register 2 (ADC_TR2) . . . . .776
21.7.10ADC watchdog threshold register 3 (ADC_TR3) . . . . .777
21.7.11ADC regular sequence register 1 (ADC_SQR1) . . . . .778
21.7.12ADC regular sequence register 2 (ADC_SQR2) . . . . .779
21.7.13ADC regular sequence register 3 (ADC_SQR3) . . . . .780
21.7.14ADC regular sequence register 4 (ADC_SQR4) . . . . .781
21.7.15ADC regular data register (ADC_DR) . . . . .781
21.7.16ADC injected sequence register (ADC_JSQR) . . . . .782
21.7.17ADC offset y register (ADC_OFRy) . . . . .784
21.7.18ADC injected channel y data register (ADC_JDRy) . . . . .785

22 Digital-to-analog converter (DAC) . . . . . 796

22.7.4DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . .821
22.7.5DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . .821
22.7.6DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . .822
22.7.7DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . .822
22.7.8DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . .823
22.7.9Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . .823
22.7.10Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . .824
22.7.11Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . .824
22.7.12DAC channel1 data output register (DAC_DOR1) . . . . .825
22.7.13DAC channel2 data output register (DAC_DOR2) . . . . .825
22.7.14DAC status register (DAC_SR) . . . . .825
22.7.15DAC calibration control register (DAC_CCR) . . . . .827
22.7.16DAC mode control register (DAC_MCR) . . . . .827
22.7.17DAC channel1 sample and hold sample time register (DAC_SHSR1) . . . . .829
22.7.18DAC channel2 sample and hold sample time register (DAC_SHSR2) . . . . .829
22.7.19DAC sample and hold time register (DAC_SHHR) . . . . .829
22.7.20DAC sample and hold refresh time register (DAC_SHRR) . . . . .830
22.7.21DAC register map . . . . .831
23Voltage reference buffer (VREFBUF) . . . . .833
23.1VREFBUF introduction . . . . .833
23.2VREFBUF functional description . . . . .833
23.3VREFBUF trimming . . . . .834
23.4VREFBUF registers . . . . .835
23.4.1VREFBUF control and status register (VREFBUF_CSR) . . . . .835
23.4.2VREFBUF calibration control register (VREFBUF_CCR) . . . . .836
23.4.3VREFBUF register map . . . . .836
24Comparator (COMP) . . . . .837
24.1Introduction . . . . .837

24.2 COMP main features . . . . . 837

24.3 COMP functional description . . . . . 838

24.3.1 COMP block diagram . . . . . 838

24.3.2 COMP pins and internal signals . . . . . 838

24.3.3 COMP reset and clocks . . . . . 839

24.3.4 Comparator LOCK mechanism . . . . . 839

24.3.5 Window comparator . . . . . 840

24.3.6 Hysteresis . . . . . 840

24.3.7 Comparator output blanking function . . . . . 841

24.3.8 COMP power and speed modes . . . . . 842

24.4 COMP low-power modes . . . . . 842

24.5 COMP interrupts . . . . . 842

24.6 COMP registers . . . . . 843

24.6.1 Comparator 1 control and status register (COMP1_CSR) . . . . . 843

24.6.2 Comparator 2 control and status register (COMP2_CSR) . . . . . 845

24.6.3 COMP register map . . . . . 848

25 Operational amplifiers (OPAMP) . . . . . 849

25.1 Introduction . . . . . 849

25.2 OPAMP main features . . . . . 849

25.3 OPAMP functional description . . . . . 849

25.3.1 OPAMP reset and clocks . . . . . 849

25.3.2 Initial configuration . . . . . 850

25.3.3 Signal routing . . . . . 850

25.3.4 OPAMP modes . . . . . 851

25.3.5 Calibration . . . . . 854

25.4 OPAMP low-power modes . . . . . 856

25.5 OPAMP registers . . . . . 857

25.5.1 OPAMP1 control/status register (OPAMP1_CSR) . . . . . 857

25.5.2 OPAMP1 offset trimming register in normal mode (OPAMP1_OTR) . . . . . 858

25.5.3 OPAMP1 offset trimming register in low-power mode
(OPAMP1_LPOTR) . . . . . 858

25.5.4 OPAMP2 control/status register (OPAMP2_CRS) . . . . . 859

25.5.5 OPAMP2 offset trimming register in normal mode (OPAMP2_OTR) . . . . . 860

25.5.6 OPAMP2 offset trimming register in low-power mode
(OPAMP2_LPOTR) . . . . . 860

25.5.7 OPAMP register map . . . . . 861

26Digital filter for sigma delta modulators (DFSDM) . . . . .862
26.1Introduction . . . . .862
26.2DFSDM main features . . . . .863
26.3DFSDM implementation . . . . .864
26.4DFSDM functional description . . . . .865
26.4.1DFSDM block diagram . . . . .865
26.4.2DFSDM pins and internal signals . . . . .866
26.4.3DFSDM reset and clocks . . . . .867
26.4.4Serial channel transceivers . . . . .868
26.4.5Configuring the input serial interface . . . . .878
26.4.6Parallel data inputs . . . . .878
26.4.7Channel selection . . . . .880
26.4.8Digital filter configuration . . . . .881
26.4.9Integrator unit . . . . .882
26.4.10Analog watchdog . . . . .883
26.4.11Short-circuit detector . . . . .885
26.4.12Extreme detector . . . . .886
26.4.13Data unit block . . . . .886
26.4.14Signed data format . . . . .887
26.4.15Launching conversions . . . . .888
26.4.16Continuous and fast continuous modes . . . . .888
26.4.17Request precedence . . . . .889
26.4.18Power optimization in run mode . . . . .890
26.5DFSDM interrupts . . . . .890
26.6DFSDM DMA transfer . . . . .892
26.7DFSDM channel y registers (y=0..3) . . . . .892
26.7.1DFSDM channel y configuration register (DFSDM_CHyCFGR1) . . . . .892
26.7.2DFSDM channel y configuration register (DFSDM_CHyCFGR2) . . . . .894
26.7.3DFSDM channel y analog watchdog and short-circuit detector register (DFSDM_CHyAWSCDR) . . . . .895
26.7.4DFSDM channel y watchdog filter data register (DFSDM_CHyWDATR) . . . . .896
26.7.5DFSDM channel y data input register (DFSDM_CHyDATINR) . . . . .896
26.7.6DFSDM channel y delay register (DFSDM_CHyDLYR) . . . . .897
26.8DFSDM filter x module registers (x=0..3) . . . . .898
26.8.1DFSDM filter x control register 1 (DFSDM_FLTxCR1) . . . . .898
26.8.2DFSDM filter x control register 2 (DFSDM_FLTxCR2) . . . . .901

26.8.3 DFSDM filter x interrupt and status register (DFSDM_FLTxISR) . . . . 902

26.8.4 DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) . . . . 904

26.8.5 DFSDM filter x injected channel group selection register
(DFSDM_FLTxJCHGR) . . . . . 905

26.8.6 DFSDM filter x control register (DFSDM_FLTxFCR) . . . . . 905

26.8.7 DFSDM filter x data register for injected group
(DFSDM_FLTxJDATAR) . . . . . 906

26.8.8 DFSDM filter x data register for the regular channel
(DFSDM_FLTxRDATAR) . . . . . 907

26.8.9 DFSDM filter x analog watchdog high threshold register
(DFSDM_FLTxAWHTR) . . . . . 908

26.8.10 DFSDM filter x analog watchdog low threshold register
(DFSDM_FLTxAWLTR) . . . . . 908

26.8.11 DFSDM filter x analog watchdog status register
(DFSDM_FLTxAWSR) . . . . . 909

26.8.12 DFSDM filter x analog watchdog clear flag register
(DFSDM_FLTxAWCFR) . . . . . 910

26.8.13 DFSDM filter x extremes detector maximum register
(DFSDM_FLTxEXMAX) . . . . . 910

26.8.14 DFSDM filter x extremes detector minimum register
(DFSDM_FLTxEXMIN) . . . . . 911

26.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . . 911

26.8.16 DFSDM register map . . . . . 912

27 Touch sensing controller (TSC) . . . . . 920

27.1 Introduction . . . . . 920

27.2 TSC main features . . . . . 920

27.3 TSC functional description . . . . . 921

27.3.1 TSC block diagram . . . . . 921

27.3.2 Surface charge transfer acquisition overview . . . . . 921

27.3.3 Reset and clocks . . . . . 924

27.3.4 Charge transfer acquisition sequence . . . . . 924

27.3.5 Spread spectrum feature . . . . . 925

27.3.6 Max count error . . . . . 926

27.3.7 Sampling capacitor I/O and channel I/O mode selection . . . . . 926

27.3.8 Acquisition mode . . . . . 927

27.3.9 I/O hysteresis and analog switch control . . . . . 927

27.4 TSC low-power modes . . . . . 928

27.5 TSC interrupts . . . . . 928

27.6TSC registers . . . . .928
27.6.1TSC control register (TSC_CR) . . . . .928
27.6.2TSC interrupt enable register (TSC_IER) . . . . .931
27.6.3TSC interrupt clear register (TSC_ICR) . . . . .932
27.6.4TSC interrupt status register (TSC_ISR) . . . . .932
27.6.5TSC I/O hysteresis control register (TSC_IOHCR) . . . . .933
27.6.6TSC I/O analog switch control register
(TSC_IOASCR) . . . . .		933
27.6.7TSC I/O sampling control register (TSC_IOSCR) . . . . .934
27.6.8TSC I/O channel control register (TSC_IOCCR) . . . . .934
27.6.9TSC I/O group control status register (TSC_IOGCSR) . . . . .935
27.6.10TSC I/O group x counter register (TSC_IOGxCR) . . . . .935
27.6.11TSC register map . . . . .936
28True random number generator (RNG) . . . . .938
28.1RNG introduction . . . . .938
28.2RNG main features . . . . .938
28.3RNG functional description . . . . .939
28.3.1RNG block diagram . . . . .939
28.3.2RNG internal signals . . . . .939
28.3.3Random number generation . . . . .939
28.3.4RNG initialization . . . . .942
28.3.5RNG operation . . . . .943
28.3.6RNG clocking . . . . .945
28.3.7Error management . . . . .945
28.3.8RNG low-power use . . . . .946
28.4RNG interrupts . . . . .946
28.5RNG processing time . . . . .947
28.6RNG entropy source validation . . . . .947
28.6.1Introduction . . . . .947
28.6.2Validation conditions . . . . .947
28.6.3Data collection . . . . .948
28.7RNG registers . . . . .948
28.7.1RNG control register (RNG_CR) . . . . .948
28.7.2RNG status register (RNG_SR) . . . . .950
28.7.3RNG data register (RNG_DR) . . . . .951
28.7.4RNG health test control register (RNG_HTCR) . . . . .952
28.7.5RNG register map .....952
29AES hardware accelerator (AES) .....953
29.1Introduction .....953
29.2AES main features .....953
29.3AES implementation .....953
29.4AES functional description .....954
29.4.1AES block diagram .....954
29.4.2AES internal signals .....954
29.4.3AES cryptographic core .....954
29.4.4AES procedure to perform a cipher operation .....960
29.4.5AES decryption round key preparation .....963
29.4.6AES ciphertext stealing and data padding .....963
29.4.7AES task suspend and resume .....964
29.4.8AES basic chaining modes (ECB, CBC) .....964
29.4.9AES counter (CTR) mode .....969
29.4.10AES Galois/counter mode (GCM) .....971
29.4.11AES Galois message authentication code (GMAC) .....976
29.4.12AES counter with CBC-MAC (CCM) .....978
29.4.13AES data registers and data swapping .....983
29.4.14AES key registers .....985
29.4.15AES initialization vector registers .....985
29.4.16AES DMA interface .....986
29.4.17AES error management .....987
29.5AES interrupts .....988
29.6AES processing latency .....988
29.7AES registers .....989
29.7.1AES control register (AES_CR) .....989
29.7.2AES status register (AES_SR) .....991
29.7.3AES data input register (AES_DINR) .....993
29.7.4AES data output register (AES_DOUTR) .....993
29.7.5AES key register 0 (AES_KEYR0) .....994
29.7.6AES key register 1 (AES_KEYR1) .....994
29.7.7AES key register 2 (AES_KEYR2) .....995
29.7.8AES key register 3 (AES_KEYR3) .....995
29.7.9AES initialization vector register 0 (AES_IVR0) .....995
29.7.10AES initialization vector register 1 (AES_IVR1) . . . . .996
29.7.11AES initialization vector register 2 (AES_IVR2) . . . . .996
29.7.12AES initialization vector register 3 (AES_IVR3) . . . . .996
29.7.13AES key register 4 (AES_KEYR4) . . . . .997
29.7.14AES key register 5 (AES_KEYR5) . . . . .997
29.7.15AES key register 6 (AES_KEYR6) . . . . .997
29.7.16AES key register 7 (AES_KEYR7) . . . . .998
29.7.17AES suspend registers (AES_SUSPxR) . . . . .998
29.7.18AES register map . . . . .999
30Hash processor (HASH) . . . . .1001
30.1Introduction . . . . .1001
30.2HASH main features . . . . .1001
30.3HASH implementation . . . . .1002
30.4HASH functional description . . . . .1002
30.4.1HASH block diagram . . . . .1002
30.4.2HASH internal signals . . . . .1003
30.4.3About secure hash algorithms . . . . .1003
30.4.4Message data feeding . . . . .1003
30.4.5Message digest computing . . . . .1005
30.4.6Message padding . . . . .1006
30.4.7HMAC operation . . . . .1008
30.4.8HASH suspend/resume operations . . . . .1010
30.4.9HASH DMA interface . . . . .1012
30.4.10HASH error management . . . . .1012
30.4.11HASH processing time . . . . .1012
30.5HASH interrupts . . . . .1013
30.6HASH registers . . . . .1014
30.6.1HASH control register (HASH_CR) . . . . .1014
30.6.2HASH data input register (HASH_DIN) . . . . .1016
30.6.3HASH start register (HASH_STR) . . . . .1017
30.6.4HASH digest registers . . . . .1018
30.6.5HASH interrupt enable register (HASH_IMR) . . . . .1019
30.6.6HASH status register (HASH_SR) . . . . .1020
30.6.7HASH context swap registers . . . . .1020
30.6.8HASH register map . . . . .1021

31 On-the-fly decryption engine (OTFDEC) . . . . . 1023

31.1 OTFDEC introduction . . . . . 1023

31.2 OTFDEC main features . . . . . 1023

31.3 OTFDEC functional description . . . . . 1024

31.3.1 OTFDEC block diagram . . . . . 1024

31.3.2 OTFDEC internal signals . . . . . 1024

31.3.3 OTFDEC on-the-fly decryption . . . . . 1025

31.3.4 OTFDEC usage of AES in counter mode decryption . . . . . 1026

31.3.5 Flow control management . . . . . 1027

31.3.6 OTFDEC error management . . . . . 1027

31.4 OTFDEC interrupts . . . . . 1028

31.5 OTFDEC application information . . . . . 1028

31.5.1 OTFDEC initialization process . . . . . 1028

31.5.2 OTFDEC and power management . . . . . 1030

31.5.3 Encrypting for OTFDEC . . . . . 1030

31.5.4 OTFDEC key CRC source code . . . . . 1031

31.6 OTFDEC registers . . . . . 1032

31.6.1 OTFDEC control register (OTFDEC_CR) . . . . . 1032

31.6.2 OTFDEC privileged access control configuration register (OTFDEC_PRIVCFGGR) . . . . . 1033

31.6.3 OTFDEC region x configuration register (OTFDEC_RxCFGGR) . . . . . 1033

31.6.4 OTFDEC region x start address register (OTFDEC_RxSTARTADDR) . . . . . 1035

31.6.5 OTFDEC region x end address register (OTFDEC_RxENDADDR) . . . . . 1035

31.6.6 OTFDEC region x nonce register 0 (OTFDEC_RxNONCER0) . . . . . 1036

31.6.7 OTFDEC region x nonce register 1 (OTFDEC_RxNONCER1) . . . . . 1037

31.6.8 OTFDEC region x key register 0 (OTFDEC_RxKEYR0) . . . . . 1037

31.6.9 OTFDEC region x key register 1 (OTFDEC_RxKEYR1) . . . . . 1038

31.6.10 OTFDEC region x key register 2 (OTFDEC_RxKEYR2) . . . . . 1038

31.6.11 OTFDEC region x key register 3 (OTFDEC_RxKEYR3) . . . . . 1039

31.6.12 OTFDEC interrupt status register (OTFDEC_ISR) . . . . . 1039

31.6.13 OTFDEC interrupt clear register (OTFDEC_ICR) . . . . . 1040

31.6.14 OTFDEC interrupt enable register (OTFDEC_IER) . . . . . 1041

31.6.15 OTFDEC register map . . . . . 1042

32 Public key accelerator (PKA) . . . . . 1046

32.1 Introduction . . . . . 1046

32.2PKA main features . . . . .1046
32.3PKA functional description . . . . .1046
32.3.1PKA block diagram . . . . .1046
32.3.2PKA internal signals . . . . .1047
32.3.3PKA reset and clocks . . . . .1047
32.3.4PKA public key acceleration . . . . .1047
32.3.5Typical applications for PKA . . . . .1049
32.3.6PKA procedure to perform an operation . . . . .1051
32.3.7PKA error management . . . . .1052
32.4PKA operating modes . . . . .1052
32.4.1Introduction . . . . .1052
32.4.2Montgomery parameter computation . . . . .1053
32.4.3Modular addition . . . . .1054
32.4.4Modular subtraction . . . . .1054
32.4.5Modular and Montgomery multiplication . . . . .1055
32.4.6Modular exponentiation . . . . .1056
32.4.7Modular inversion . . . . .1056
32.4.8Modular reduction . . . . .1057
32.4.9Arithmetic addition . . . . .1057
32.4.10Arithmetic subtraction . . . . .1057
32.4.11Arithmetic multiplication . . . . .1058
32.4.12Arithmetic comparison . . . . .1058
32.4.13RSA CRT exponentiation . . . . .1059
32.4.14Point on elliptic curve Fp check . . . . .1059
32.4.15ECC Fp scalar multiplication . . . . .1060
32.4.16ECDSA sign . . . . .1061
32.4.17ECDSA verification . . . . .1063
32.5Example of configurations and processing times . . . . .1064
32.5.1Supported elliptic curves . . . . .1064
32.5.2Computation times . . . . .1066
32.6PKA interrupts . . . . .1067
32.7PKA registers . . . . .1068
32.7.1PKA control register (PKA_CR) . . . . .1068
32.7.2PKA status register (PKA_SR) . . . . .1069
32.7.3PKA clear flag register (PKA_CLRFR) . . . . .1070
32.7.4PKA RAM . . . . .1070
32.7.5PKA register map . . . . .1071
33Advanced-control timers (TIM1/TIM8) . . . . .1072
33.1TIM1/TIM8 introduction . . . . .1072
33.2TIM1/TIM8 main features . . . . .1072
33.3TIM1/TIM8 functional description . . . . .1074
33.3.1Time-base unit . . . . .1074
33.3.2Counter modes . . . . .1076
33.3.3Repetition counter . . . . .1087
33.3.4External trigger input . . . . .1089
33.3.5Clock selection . . . . .1090
33.3.6Capture/compare channels . . . . .1094
33.3.7Input capture mode . . . . .1096
33.3.8PWM input mode . . . . .1097
33.3.9Forced output mode . . . . .1098
33.3.10Output compare mode . . . . .1099
33.3.11PWM mode . . . . .1100
33.3.12Asymmetric PWM mode . . . . .1103
33.3.13Combined PWM mode . . . . .1104
33.3.14Combined 3-phase PWM mode . . . . .1105
33.3.15Complementary outputs and dead-time insertion . . . . .1106
33.3.16Using the break function . . . . .1108
33.3.17Bidirectional break inputs . . . . .1114
33.3.18Clearing the OCxREF signal on an external event . . . . .1115
33.3.196-step PWM generation . . . . .1117
33.3.20One-pulse mode . . . . .1118
33.3.21Retriggerable one pulse mode . . . . .1119
33.3.22Encoder interface mode . . . . .1120
33.3.23UIF bit remapping . . . . .1122
33.3.24Timer input XOR function . . . . .1123
33.3.25Interfacing with Hall sensors . . . . .1123
33.3.26Timer synchronization . . . . .1126
33.3.27ADC synchronization . . . . .1130
33.3.28DMA burst mode . . . . .1130
33.3.29Debug mode . . . . .1131
33.4TIM1/TIM8 registers . . . . .1132
33.4.1TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . .1132
33.4.2TIMx control register 2 (TIMx_CR2)(x = 1, 8) .....1133
33.4.3TIMx slave mode control register
(TIMx_SMCR)(x = 1, 8) .....		1136
33.4.4TIMx DMA/interrupt enable register
(TIMx_DIER)(x = 1, 8) .....		1138
33.4.5TIMx status register (TIMx_SR)(x = 1, 8) .....1140
33.4.6TIMx event generation register (TIMx_EGR)(x = 1, 8) .....1142
33.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 1, 8) ..1143
33.4.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) .....		1144
33.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 1, 8) ..1147
33.4.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) .....		1148
33.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 1, 8) .....		1149
33.4.12TIMx counter (TIMx_CNT)(x = 1, 8) .....1153
33.4.13TIMx prescaler (TIMx_PSC)(x = 1, 8) .....1153
33.4.14TIMx auto-reload register (TIMx_ARR)(x = 1, 8) .....1153
33.4.15TIMx repetition counter register (TIMx_RCR)(x = 1, 8) .....1154
33.4.16TIMx capture/compare register 1
(TIMx_CCR1)(x = 1, 8) .....		1154
33.4.17TIMx capture/compare register 2
(TIMx_CCR2)(x = 1, 8) .....		1155
33.4.18TIMx capture/compare register 3
(TIMx_CCR3)(x = 1, 8) .....		1155
33.4.19TIMx capture/compare register 4
(TIMx_CCR4)(x = 1, 8) .....		1156
33.4.20TIMx break and dead-time register
(TIMx_BDTR)(x = 1, 8) .....		1156
33.4.21TIMx DMA control register
(TIMx_DCR)(x = 1, 8) .....		1160
33.4.22TIMx DMA address for full transfer
(TIMx_DMAR)(x = 1, 8) .....		1161
33.4.23TIM1 option register 1 (TIM1_OR1) .....1162
33.4.24TIM8 option register 1 (TIM8_OR1) .....1162
33.4.25TIMx capture/compare mode register 3
(TIMx_CCMR3)(x = 1, 8) .....		1163
33.4.26TIMx capture/compare register 5
(TIMx_CCR5)(x = 1, 8) .....		1164
33.4.27TIMx capture/compare register 6
(TIMx_CCR6)(x = 1, 8) .....		1165
33.4.28TIM1 option register 2 (TIM1_OR2) . . . . .1165
33.4.29TIM1 option register 3 (TIM1_OR3) . . . . .1167
33.4.30TIM8 option register 2 (TIM8_OR2) . . . . .1168
33.4.31TIM8 option register 3 (TIM8_OR3) . . . . .1170
33.4.32TIM1 register map . . . . .1172
33.4.33TIM8 register map . . . . .1174
34General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . .1177
34.1TIM2/TIM3/TIM4/TIM5 introduction . . . . .1177
34.2TIM2/TIM3/TIM4/TIM5 main features . . . . .1177
34.3TIM2/TIM3/TIM4/TIM5 functional description . . . . .1179
34.3.1Time-base unit . . . . .1179
34.3.2Counter modes . . . . .1181
34.3.3Clock selection . . . . .1191
34.3.4Capture/Compare channels . . . . .1195
34.3.5Input capture mode . . . . .1197
34.3.6PWM input mode . . . . .1198
34.3.7Forced output mode . . . . .1199
34.3.8Output compare mode . . . . .1200
34.3.9PWM mode . . . . .1201
34.3.10Asymmetric PWM mode . . . . .1204
34.3.11Combined PWM mode . . . . .1205
34.3.12Clearing the OCxREF signal on an external event . . . . .1206
34.3.13One-pulse mode . . . . .1208
34.3.14Retriggerable one pulse mode . . . . .1209
34.3.15Encoder interface mode . . . . .1210
34.3.16UIF bit remapping . . . . .1212
34.3.17Timer input XOR function . . . . .1212
34.3.18Timers and external trigger synchronization . . . . .1213
34.3.19Timer synchronization . . . . .1216
34.3.20DMA burst mode . . . . .1221
34.3.21Debug mode . . . . .1222
34.4TIM2/TIM3/TIM4/TIM5 registers . . . . .1223
34.4.1TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . .1223
34.4.2TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . .1224
34.4.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . .1226
34.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . .1229
34.4.5TIMx status register (TIMx_SR)(x = 2 to 5) . . . . .1230
34.4.6TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . .1231
34.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) . . . . .1232
34.4.8TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5) . . . . .		1234
34.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) . . . . .1236
34.4.10TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5) . . . . .		1237
34.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 5) . . . . .		1238
34.4.12TIMx counter (TIMx_CNT)(x = 2 to 5) . . . . .1239
34.4.13TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) . . . . .1240
34.4.14TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . .1240
34.4.15TIMx auto-reload register (TIMx_ARR)(x = 2 to 5) . . . . .1241
34.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) . . . . .1241
34.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) . . . . .1241
34.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) . . . . .1242
34.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) . . . . .1242
34.4.20TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . .1243
34.4.21TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . .1244
34.4.22TIM2 option register 1 (TIM2_OR1) . . . . .1244
34.4.23TIM3 option register 1 (TIM3_OR1) . . . . .1244
34.4.24TIM2 option register 2 (TIM2_OR2) . . . . .1245
34.4.25TIM3 option register 2 (TIM3_OR2) . . . . .1245
34.4.26TIMx register map . . . . .1247
35General-purpose timers (TIM15/TIM16/TIM17) . . . . .1250
35.1TIM15/TIM16/TIM17 introduction . . . . .1250
35.2TIM15 main features . . . . .1250
35.3TIM16/TIM17 main features . . . . .1251
35.4TIM15/TIM16/TIM17 functional description . . . . .1254
35.4.1Time-base unit . . . . .1254
35.4.2Counter modes . . . . .1256
35.4.3Repetition counter . . . . .1260
35.4.4Clock selection . . . . .1261
35.4.5Capture/compare channels . . . . .1263
35.4.6Input capture mode . . . . .1265
35.4.7PWM input mode (only for TIM15) . . . . .1266
35.4.8Forced output mode . . . . .1267
35.4.9Output compare mode . . . . .1268
35.4.10PWM mode . . . . .1269
35.4.11Combined PWM mode (TIM15 only) . . . . .1270
35.4.12Complementary outputs and dead-time insertion . . . . .1271
35.4.13Using the break function . . . . .1273
35.4.14Bidirectional break inputs . . . . .1278
35.4.156-step PWM generation . . . . .1279
35.4.16One-pulse mode . . . . .1281
35.4.17Retriggerable one pulse mode (TIM15 only) . . . . .1282
35.4.18UIF bit remapping . . . . .1283
35.4.19Timer input XOR function (TIM15 only) . . . . .1284
35.4.20External trigger synchronization (TIM15 only) . . . . .1285
35.4.21Slave mode – combined reset + trigger mode . . . . .1287
35.4.22DMA burst mode . . . . .1287
35.4.23Timer synchronization (TIM15) . . . . .1289
35.4.24Using timer output as trigger for other timers (TIM16/TIM17) . . . . .1289
35.4.25Debug mode . . . . .1289
35.5TIM15 registers . . . . .1290
35.5.1TIM15 control register 1 (TIM15_CR1) . . . . .1290
35.5.2TIM15 control register 2 (TIM15_CR2) . . . . .1291
35.5.3TIM15 slave mode control register (TIM15_SMCR) . . . . .1293
35.5.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .1294
35.5.5TIM15 status register (TIM15_SR) . . . . .1295
35.5.6TIM15 event generation register (TIM15_EGR) . . . . .1297
35.5.7TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .1298
35.5.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		1299
35.5.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .1302
35.5.10TIM15 counter (TIM15_CNT) . . . . .1305
35.5.11TIM15 prescaler (TIM15_PSC) . . . . .1305
35.5.12TIM15 auto-reload register (TIM15_ARR) . . . . .1305
35.5.13TIM15 repetition counter register (TIM15_RCR) . . . . .1306
35.5.14TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .1306
35.5.15TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .1307
35.5.16TIM15 break and dead-time register (TIM15_BDTR) . . . . .1307
35.5.17TIM15 DMA control register (TIM15_DCR) . . . . .1310
35.5.18TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .1310
35.5.19TIM15 option register 1 (TIM15_OR1) . . . . .1311
35.5.20TIM15 option register 2 (TIM15_OR2) . . . . .1311
35.5.21TIM15 register map . . . . .1313
35.6TIM16/TIM17 registers . . . . .1316
35.6.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .1316
35.6.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .1317
35.6.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .1318
35.6.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .1319
35.6.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .1320
35.6.6TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 16 to 17) . . . . .		1321
35.6.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . .		1322
35.6.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .1324
35.6.9TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .1326
35.6.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .1327
35.6.11TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . .1327
35.6.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .1328
35.6.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .1328
35.6.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .1329
35.6.15TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .1331
35.6.16TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . .1332
35.6.17TIM16 option register 1 (TIM16_OR1) . . . . .1332
35.6.18TIM16 option register 2 (TIM16_OR2) . . . . .1333
35.6.19TIM17 option register 1 (TIM17_OR1) . . . . .1334
35.6.20TIM17 option register 2 (TIM17_OR2) . . . . .1335
35.6.21TIM16/TIM17 register map . . . . .1337
36Basic timers (TIM6/TIM7) . . . . .1339
36.1TIM6/TIM7 introduction . . . . .1339
36.2TIM6/TIM7 main features . . . . .1339
36.3TIM6/TIM7 functional description . . . . .1340
36.3.1Time-base unit . . . . .1340
36.3.2Counting mode . . . . .1342
36.3.3UIF bit remapping . . . . .1345
36.3.4Clock source . . . . .1345
36.3.5Debug mode .....1346
36.4TIM6/TIM7 registers .....1346
36.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) .....1346
36.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) .....1348
36.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) .....1348
36.4.4TIMx status register (TIMx_SR)(x = 6 to 7) .....1349
36.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) .....1349
36.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) .....1349
36.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) .....1350
36.4.8TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) .....1350
36.4.9TIMx register map .....1351
37Low-power timer (LPTIM) .....1352
37.1LPTIM introduction .....1352
37.2LPTIM main features .....1352
37.3LPTIM implementation .....1352
37.4LPTIM functional description .....1353
37.4.1LPTIM block diagram .....1353
37.4.2LPTIM pins and internal signals .....1353
37.4.3LPTIM input and trigger mapping .....1354
37.4.4LPTIM reset and clocks .....1355
37.4.5Glitch filter .....1355
37.4.6Prescaler .....1356
37.4.7Trigger multiplexer .....1356
37.4.8Operating mode .....1357
37.4.9Timeout function .....1359
37.4.10Waveform generation .....1359
37.4.11Register update .....1360
37.4.12Counter mode .....1361
37.4.13Timer enable .....1362
37.4.14Timer counter reset .....1362
37.4.15Encoder mode .....1363
37.4.16Repetition counter .....1364
37.4.17Debug mode .....1365
37.5LPTIM low-power modes .....1366
37.6LPTIM interrupts .....1366
37.7LPTIM registers . . . . .1367
37.7.1LPTIM interrupt and status register (LPTIM_ISR) . . . . .1367
37.7.2LPTIM interrupt clear register (LPTIM_ICR) . . . . .1368
37.7.3LPTIM interrupt enable register (LPTIM_IER) . . . . .1369
37.7.4LPTIM configuration register (LPTIM_CFGR) . . . . .1370
37.7.5LPTIM control register (LPTIM_CR) . . . . .1373
37.7.6LPTIM compare register (LPTIM_CMP) . . . . .1374
37.7.7LPTIM autoreload register (LPTIM_ARR) . . . . .1374
37.7.8LPTIM counter register (LPTIM_CNT) . . . . .1375
37.7.9LPTIM1 option register (LPTIM1_OR) . . . . .1375
37.7.10LPTIM2 option register (LPTIM2_OR) . . . . .1376
37.7.11LPTIM3 option register (LPTIM3_OR) . . . . .1376
37.7.12LPTIM repetition register (LPTIM_RCR) . . . . .1377
37.7.13LPTIM register map . . . . .1377
38Infrared interface (IRTIM) . . . . .1379
39Independent watchdog (IWDG) . . . . .1380
39.1Introduction . . . . .1380
39.2IWDG main features . . . . .1380
39.3IWDG functional description . . . . .1380
39.3.1IWDG block diagram . . . . .1380
39.3.2Window option . . . . .1381
39.3.3Hardware watchdog . . . . .1382
39.3.4Low-power freeze . . . . .1382
39.3.5Register access protection . . . . .1382
39.3.6Debug mode . . . . .1382
39.4IWDG registers . . . . .1383
39.4.1IWDG key register (IWDG_KR) . . . . .1383
39.4.2IWDG prescaler register (IWDG_PR) . . . . .1384
39.4.3IWDG reload register (IWDG_RLR) . . . . .1385
39.4.4IWDG status register (IWDG_SR) . . . . .1386
39.4.5IWDG window register (IWDG_WINR) . . . . .1387
39.4.6IWDG register map . . . . .1388
40System window watchdog (WWDG) . . . . .1389
40.1WWDG introduction . . . . .1389
40.2WWDG main features . . . . .1389
40.3WWDG functional description . . . . .1389
40.3.1WWDG block diagram . . . . .1390
40.3.2Enabling the watchdog . . . . .1390
40.3.3Controlling the down-counter . . . . .1390
40.3.4How to program the watchdog timeout . . . . .1390
40.3.5Debug mode . . . . .1391
40.4WWDG interrupts . . . . .1392
40.5WWDG registers . . . . .1392
40.5.1WWDG control register (WWDG_CR) . . . . .1392
40.5.2WWDG configuration register (WWDG_CFR) . . . . .1393
40.5.3WWDG status register (WWDG_SR) . . . . .1393
40.5.4WWDG register map . . . . .1394
41Real-time clock (RTC) . . . . .1395
41.1Introduction . . . . .1395
41.2RTC main features . . . . .1395
41.3RTC functional description . . . . .1396
41.3.1RTC block diagram . . . . .1396
41.3.2RTC pins and internal signals . . . . .1398
41.3.3GPIOs controlled by the RTC and TAMP . . . . .1399
41.3.4RTC secure protection modes . . . . .1401
41.3.5RTC privilege protection modes . . . . .1403
41.3.6Clock and prescalers . . . . .1404
41.3.7Real-time clock and calendar . . . . .1405
41.3.8Calendar ultra-low power mode . . . . .1405
41.3.9Programmable alarms . . . . .1405
41.3.10Periodic auto-wake-up . . . . .1406
41.3.11RTC initialization and configuration . . . . .1407
41.3.12Reading the calendar . . . . .1409
41.3.13Resetting the RTC . . . . .1410
41.3.14RTC synchronization . . . . .1410
41.3.15RTC reference clock detection . . . . .1411
41.3.16RTC smooth digital calibration . . . . .1412
41.3.17Timestamp function . . . . .1414
41.3.18Calibration clock output . . . . .1414
41.3.19Tamper and alarm output . . . . .1415
41.4RTC low-power modes . . . . .1416
41.5RTC interrupts . . . . .1417
41.6RTC registers . . . . .1419
41.6.1RTC time register (RTC_TR) . . . . .1419
41.6.2RTC date register (RTC_DR) . . . . .1420
41.6.3RTC sub second register (RTC_SSR) . . . . .1421
41.6.4RTC initialization control and status register (RTC_ICSR) . . . . .1421
41.6.5RTC prescaler register (RTC_PRER) . . . . .1423
41.6.6RTC wake-up timer register (RTC_WUTR) . . . . .1424
41.6.7RTC control register (RTC_CR) . . . . .1424
41.6.8RTC privilege mode control register (RTC_PRIVCR) . . . . .1428
41.6.9RTC secure mode control register (RTC_SMCR) . . . . .1429
41.6.10RTC write protection register (RTC_WPR) . . . . .1431
41.6.11RTC calibration register (RTC_CALR) . . . . .1431
41.6.12RTC shift control register (RTC_SHIFTTR) . . . . .1433
41.6.13RTC timestamp time register (RTC_TSTR) . . . . .1434
41.6.14RTC timestamp date register (RTC_TSDR) . . . . .1435
41.6.15RTC timestamp sub second register (RTC_TSSSR) . . . . .1436
41.6.16RTC alarm A register (RTC_ALRMAR) . . . . .1436
41.6.17RTC alarm A sub second register (RTC_ALRMASSR) . . . . .1438
41.6.18RTC alarm B register (RTC_ALRMBR) . . . . .1439
41.6.19RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .1440
41.6.20RTC status register (RTC_SR) . . . . .1441
41.6.21RTC non-secure masked interrupt status register (RTC_MISR) . . . . .1442
41.6.22RTC secure masked interrupt status register (RTC_SMISR) . . . . .1443
41.6.23RTC status clear register (RTC_SCR) . . . . .1444
41.6.24RTC register map . . . . .1445
42Tamper and backup registers (TAMP) . . . . .1447
42.1Introduction . . . . .1447
42.2TAMP main features . . . . .1447
42.3TAMP functional description . . . . .1448
42.3.1TAMP block diagram . . . . .1448
42.3.2TAMP pins and internal signals . . . . .1449
42.3.3TAMP register write protection . . . . .1450
43.4.6I2C reset .....1491
43.4.7I2C data transfer .....1492
43.4.8I2C target mode .....1494
43.4.9I2C controller mode .....1503
43.4.10I2C_TIMINGR register configuration examples .....1514
43.4.11SMBus specific features .....1516
43.4.12SMBus initialization .....1519
43.4.13SMBus I2C_TIMEOUTR register configuration examples .....1521
43.4.14SMBus target mode .....1521
43.4.15SMBus controller mode .....1525
43.4.16Wake-up from Stop mode on address match .....1528
43.4.17Error conditions .....1529
43.5I2C in low-power modes .....1531
43.6I2C interrupts .....1531
43.7I2C DMA requests .....1532
43.7.1Transmission using DMA .....1532
43.7.2Reception using DMA .....1532
43.8I2C debug modes .....1533
43.9I2C registers .....1533
43.9.1I2C control register 1 (I2C_CR1) .....1533
43.9.2I2C control register 2 (I2C_CR2) .....1536
43.9.3I2C own address 1 register (I2C_OAR1) .....1538
43.9.4I2C own address 2 register (I2C_OAR2) .....1538
43.9.5I2C timing register (I2C_TIMINGR) .....1539
43.9.6I2C timeout register (I2C_TIMEOUTR) .....1540
43.9.7I2C interrupt and status register (I2C_ISR) .....1541
43.9.8I2C interrupt clear register (I2C_ICR) .....1544
43.9.9I2C PEC register (I2C_PECR) .....1545
43.9.10I2C receive data register (I2C_RXDR) .....1545
43.9.11I2C transmit data register (I2C_TXDR) .....1546
43.9.12I2C register map .....1547
44Universal synchronous/asynchronous receiver transmitter (USART/UART) .....1548
44.1USART introduction .....1548
44.2USART main features .....1549
44.8.10USART interrupt and status register [alternate] (USART_ISR) . . . . .1624
44.8.11USART interrupt flag clear register (USART_ICR) . . . . .1629
44.8.12USART receive data register (USART_RDR) . . . . .1631
44.8.13USART transmit data register (USART_TDR) . . . . .1631
44.8.14USART prescaler register (USART_PRESC) . . . . .1632
44.8.15USART register map . . . . .1633
45Low-power universal asynchronous receiver transmitter (LPUART) . . . . .1635
45.1LPUART introduction . . . . .1635
45.2LPUART main features . . . . .1636
45.3LPUART implementation . . . . .1637
45.4LPUART functional description . . . . .1638
45.4.1LPUART block diagram . . . . .1638
45.4.2LPUART signals . . . . .1639
45.4.3LPUART character description . . . . .1640
45.4.4LPUART FIFOs and thresholds . . . . .1641
45.4.5LPUART transmitter . . . . .1642
45.4.6LPUART receiver . . . . .1645
45.4.7LPUART baud rate generation . . . . .1649
45.4.8Tolerance of the LPUART receiver to clock deviation . . . . .1650
45.4.9LPUART multiprocessor communication . . . . .1651
45.4.10LPUART parity control . . . . .1653
45.4.11LPUART single-wire half-duplex communication . . . . .1654
45.4.12Continuous communication using DMA and LPUART . . . . .1654
45.4.13RS232 hardware flow control and RS485 Driver Enable . . . . .1657
45.4.14LPUART low-power management . . . . .1659
45.5LPUART in low-power modes . . . . .1662
45.6LPUART interrupts . . . . .1663
45.7LPUART registers . . . . .1664
45.7.1LPUART control register 1 (LPUART_CR1) . . . . .1664
45.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .1667
45.7.3LPUART control register 2 (LPUART_CR2) . . . . .1670
45.7.4LPUART control register 3 (LPUART_CR3) . . . . .1672
45.7.5LPUART baud rate register (LPUART_BRR) . . . . .1675
45.7.6LPUART request register (LPUART_RQR) . . . . .1675
45.7.7LPUART interrupt and status register (LPUART_ISR) . . . . .1676
45.7.8LPUART interrupt and status register [alternate] (LPUART_ISR) . . .1680
45.7.9LPUART interrupt flag clear register (LPUART_ICR) . . . . .1683
45.7.10LPUART receive data register (LPUART_RDR) . . . . .1684
45.7.11LPUART transmit data register (LPUART_TDR) . . . . .1684
45.7.12LPUART prescaler register (LPUART_PRESC) . . . . .1685
45.7.13LPUART register map . . . . .1686
46Serial peripheral interface (SPI) . . . . .1688
46.1Introduction . . . . .1688
46.2SPI main features . . . . .1688
46.3SPI implementation . . . . .1689
46.4SPI functional description . . . . .1689
46.4.1General description . . . . .1689
46.4.2Communications between one master and one slave . . . . .1690
46.4.3Standard multislave communication . . . . .1692
46.4.4Multimaster communication . . . . .1693
46.4.5Slave select (NSS) pin management . . . . .1694
46.4.6Communication formats . . . . .1695
46.4.7Configuration of SPI . . . . .1697
46.4.8Procedure for enabling SPI . . . . .1698
46.4.9Data transmission and reception procedures . . . . .1698
46.4.10SPI status flags . . . . .1708
46.4.11SPI error flags . . . . .1709
46.4.12NSS pulse mode . . . . .1710
46.4.13TI mode . . . . .1710
46.4.14CRC calculation . . . . .1711
46.5SPI interrupts . . . . .1713
46.6SPI registers . . . . .1714
46.6.1SPI control register 1 (SPIx_CR1) . . . . .1714
46.6.2SPI control register 2 (SPIx_CR2) . . . . .1716
46.6.3SPI status register (SPIx_SR) . . . . .1718
46.6.4SPI data register (SPIx_DR) . . . . .1719
46.6.5SPI CRC polynomial register (SPIx_CRCPR) . . . . .1720
46.6.6SPI Rx CRC register (SPIx_RXCRCR) . . . . .1720
46.6.7SPI Tx CRC register (SPIx_TXCRCR) . . . . .1720
46.6.8SPI register map .....1722
47Serial audio interface (SAI) .....1723
47.1SAI introduction .....1723
47.2SAI main features .....1723
47.3SAI implementation .....1724
47.4SAI functional description .....1725
47.4.1SAI block diagram .....1725
47.4.2SAI pins and internal signals .....1726
47.4.3Main SAI modes .....1727
47.4.4SAI synchronization mode .....1728
47.4.5Audio data size .....1729
47.4.6Frame synchronization .....1729
47.4.7Slot configuration .....1732
47.4.8SAI clock generator .....1734
47.4.9Internal FIFOs .....1737
47.4.10PDM interface .....1739
47.4.11AC'97 link controller .....1747
47.4.12SPDIF output .....1749
47.4.13Specific features .....1752
47.4.14Error flags .....1756
47.4.15Disabling the SAI .....1759
47.4.16SAI DMA interface .....1759
47.5SAI interrupts .....1760
47.6SAI registers .....1762
47.6.1SAI global configuration register (SAI_GCR) .....1762
47.6.2SAI configuration register 1 (SAI_ACR1) .....1762
47.6.3SAI configuration register 2 (SAI_ACR2) .....1765
47.6.4SAI frame configuration register (SAI_AFRCR) .....1767
47.6.5SAI slot register (SAI_ASLOTR) .....1768
47.6.6SAI interrupt mask register (SAI_AIM) .....1769
47.6.7SAI status register (SAI_ASR) .....1771
47.6.8SAI clear flag register (SAI_ACLRFR) .....1773
47.6.9SAI data register (SAI_ADR) .....1774
47.6.10SAI configuration register 1 (SAI_BCR1) .....1774
47.6.11SAI configuration register 2 (SAI_BCR2) .....1777
47.6.12SAI frame configuration register (SAI_BFRCR) . . . . .1779
47.6.13SAI slot register (SAI_BSLOTR) . . . . .1780
47.6.14SAI interrupt mask register (SAI_BIM) . . . . .1781
47.6.15SAI status register (SAI_BSR) . . . . .1782
47.6.16SAI clear flag register (SAI_BCLRFR) . . . . .1784
47.6.17SAI data register (SAI_BDR) . . . . .1785
47.6.18SAI PDM control register (SAI_PDMCR) . . . . .1786
47.6.19SAI PDM delay register (SAI_PDMDLY) . . . . .1787
47.6.20SAI register map . . . . .1789
48Secure digital input/output MultiMediaCard interface (SDMMC) . .1791
48.1SDMMC main features . . . . .1791
48.2SDMMC bus topology . . . . .1791
48.3SDMMC operation modes . . . . .1793
48.4SDMMC functional description . . . . .1794
48.4.1SDMMC block diagram . . . . .1794
48.4.2SDMMC pins and internal signals . . . . .1795
48.4.3General description . . . . .1795
48.4.4SDMMC adapter . . . . .1797
48.4.5SDMMC AHB slave interface . . . . .1819
48.4.6SDMMC AHB master interface . . . . .1819
48.4.7AHB and SDMMC_CK clock relation . . . . .1821
48.5Card functional description . . . . .1822
48.5.1SD I/O mode . . . . .1822
48.5.2CMD12 send timing . . . . .1830
48.5.3Sleep (CMD5) . . . . .1833
48.5.4Interrupt mode (Wait-IRQ) . . . . .1834
48.5.5Boot operation . . . . .1835
48.5.6Response R1b handling . . . . .1838
48.5.7Reset and card cycle power . . . . .1839
48.6Hardware flow control . . . . .1840
48.7Ultra-high-speed phase I (UHS-I) voltage switch . . . . .1840
48.8SDMMC interrupts . . . . .1843
48.9SDMMC registers . . . . .1845
48.9.1SDMMC power control register (SDMMC_POWER) . . . . .1845
48.9.2SDMMC clock control register (SDMMC_CLKCR) . . . . .1846
48.9.3SDMMC argument register (SDMMC_ARGR) . . . . .1848
48.9.4SDMMC command register (SDMMC_CMDR) . . . . .1848
48.9.5SDMMC command response register (SDMMC_RESPCMDR) . . . . .1850
48.9.6SDMMC response x register (SDMMC_RESPxR) . . . . .1851
48.9.7SDMMC data timer register (SDMMC_DTIMER) . . . . .1851
48.9.8SDMMC data length register (SDMMC_DLENR) . . . . .1852
48.9.9SDMMC data control register (SDMMC_DCTRL) . . . . .1853
48.9.10SDMMC data counter register (SDMMC_DCNTR) . . . . .1854
48.9.11SDMMC status register (SDMMC_STAR) . . . . .1855
48.9.12SDMMC interrupt clear register (SDMMC_ICR) . . . . .1858
48.9.13SDMMC mask register (SDMMC_MASKR) . . . . .1860
48.9.14SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . . . .1863
48.9.15SDMMC DMA control register (SDMMC_IDMACTRLR) . . . . .1863
48.9.16SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) . . . . .1864
48.9.17SDMMC IDMA buffer 0 base address register
(SDMMC_IDMABASE0R) . . . . .		1865
48.9.18SDMMC IDMA buffer 1 base address register
(SDMMC_IDMABASE1R) . . . . .		1865
48.9.19SDMMC data FIFO registers x (SDMMC_FIFORx) . . . . .1865
48.9.20SDMMC register map . . . . .1866
49FD controller area network (FDCAN) . . . . .1869
49.1FDCAN introduction . . . . .1869
49.2FDCAN main features . . . . .1871
49.3FDCAN functional description . . . . .1872
49.3.1FDCAN block diagram . . . . .1872
49.3.2FDCAN pins and internal signals . . . . .1873
49.3.3Bit timing . . . . .1874
49.3.4Operating modes . . . . .1875
49.3.5Error management . . . . .1884
49.3.6Message RAM . . . . .1885
49.3.7FIFO acknowledge handling . . . . .1894
49.3.8FDCAN Rx FIFO element . . . . .1894
49.3.9FDCAN Tx buffer element . . . . .1896
49.3.10FDCAN Tx event FIFO element . . . . .1898
49.3.11FDCAN standard message ID filter element . . . . .1899
49.3.12FDCAN extended message ID filter element . . . . .1900
49.4FDCAN registers . . . . .1902
49.4.1FDCAN core release register (FDCAN_CREL) . . . . .1902
49.4.2FDCAN endian register (FDCAN_ENDN) . . . . .1902
49.4.3FDCAN data bit timing and prescaler register (FDCAN_DBTP) . . . . .1902
49.4.4FDCAN test register (FDCAN_TEST) . . . . .1903
49.4.5FDCAN RAM watchdog register (FDCAN_RWD) . . . . .1904
49.4.6FDCAN CC control register (FDCAN_CCCR) . . . . .1905
49.4.7FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . . . . .1906
49.4.8FDCAN timestamp counter configuration register (FDCAN_TSCC) . . . . .1908
49.4.9FDCAN timestamp counter value register (FDCAN_TSCV) . . . . .1908
49.4.10FDCAN timeout counter configuration register (FDCAN_TOCC) . . . . .1909
49.4.11FDCAN timeout counter value register (FDCAN_TOCV) . . . . .1910
49.4.12FDCAN error counter register (FDCAN_ECR) . . . . .1910
49.4.13FDCAN protocol status register (FDCAN_PSR) . . . . .1911
49.4.14FDCAN transmitter delay compensation register (FDCAN_TDCR) . . . . .1913
49.4.15FDCAN interrupt register (FDCAN_IR) . . . . .1913
49.4.16FDCAN interrupt enable register (FDCAN_IE) . . . . .1916
49.4.17FDCAN interrupt line select register (FDCAN_ILS) . . . . .1918
49.4.18FDCAN interrupt line enable register (FDCAN_ILE) . . . . .1919
49.4.19FDCAN global filter configuration register (FDCAN_RXGFC) . . . . .1919
49.4.20FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . .1921
49.4.21FDCAN high-priority message status register (FDCAN_HPMS) . . . . .1921
49.4.22FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . .1922
49.4.23CAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . .1923
49.4.24FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . .1923
49.4.25FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . .1924
49.4.26FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . .1924
49.4.27FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . .1925
49.4.28FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . .1925
49.4.29FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . .1926
49.4.30FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . . . . .1927
49.4.31FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) . . . . .1927
49.4.32FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . . . . .1928
49.4.33FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE) . . . . .		1928
49.4.34FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_TXBCIE) . . . . .		1929
49.4.35FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . .1929
49.4.36FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . .1930
49.4.37FDCAN CFG clock divider register (FDCAN_CKDIV) . . . . .1930
49.4.38FDCAN register map . . . . .1931
50Universal serial bus full-speed device interface (USB) . . . . .1935
50.1Introduction . . . . .1935
50.2USB main features . . . . .1935
50.3USB implementation . . . . .1935
50.4USB functional description . . . . .1936
50.4.1Description of USB blocks . . . . .1937
50.5Programming considerations . . . . .1938
50.5.1Generic USB device programming . . . . .1938
50.5.2System and power-on reset . . . . .1939
50.5.3Double-buffered endpoints . . . . .1944
50.5.4Isochronous transfers . . . . .1946
50.5.5Suspend/Resume events . . . . .1947
50.6USB and USB SRAM registers . . . . .1950
50.6.1Common registers . . . . .1950
50.6.2Buffer descriptor table . . . . .1963
50.6.3USB register map . . . . .1966
51USB Type-C ® /USB Power Delivery interface (UCPD) . . . . .1968
51.1UCPD introduction . . . . .1968
51.2UCPD main features . . . . .1968
51.3UCPD implementation . . . . .1969
51.4UCPD functional description . . . . .1969
51.4.1UCPD block diagram . . . . .1970
51.4.2UCPD reset and clocks . . . . .1971
51.4.3Physical layer protocol . . . . .1972
51.4.4UCPD BMC transmitter . . . . .1978
51.4.5UCPD BMC receiver . . . . .1980
51.4.6UCPD Type-C pull-ups (Rp) and pull-downs (Rd) . . . . .1981
51.4.7UCPD Type-C voltage monitoring and de-bouncing . . . . .1982
51.4.8UCPD fast role swap (FRS) . . . . .1982
51.4.9UCPD DMA Interface . . . . .1982
51.4.10Wake-up from Stop mode . . . . .1982
52.2.9Serial-wire debug port . . . . .2013
52.2.10Debug port registers . . . . .2014
52.2.11Debug port register map and reset values . . . . .2022
52.3Access ports . . . . .2023
52.3.1Access port registers . . . . .2023
52.3.2Access port register map and reset values . . . . .2028
52.4ROM tables . . . . .2029
52.4.1MCU ROM table registers . . . . .2032
52.4.2MCU ROM table register map and reset values . . . . .2037
52.4.3Processor ROM table registers . . . . .2038
52.4.4Processor ROM table register map and reset values . . . . .2043
52.5Data watchpoint and trace unit (DWT) . . . . .2044
52.5.1DWT registers . . . . .2045
52.5.2DWT register map and reset values . . . . .2060
52.6Instrumentation trace macrocell (ITM) . . . . .2062
52.6.1ITM registers . . . . .2063
52.6.2ITM register map and reset values . . . . .2072
52.7Breakpoint unit (BPU) . . . . .2073
52.7.1BPU registers . . . . .2074
52.7.2BPU register map and reset values . . . . .2081
52.8Embedded Trace Macrocell™ (ETM) . . . . .2082
52.8.1ETM registers . . . . .2083
52.8.2ETM register map and reset values . . . . .2109
52.9Trace port interface unit (TPIU) . . . . .2113
52.9.1TPIU registers . . . . .2114
52.9.2TPIU register map and reset values . . . . .2125
52.10Cross-trigger interface (CTI) . . . . .2127
52.10.1CTI registers . . . . .2128
52.10.2CTI register map and reset values . . . . .2140
52.11Microcontroller debug unit (DBGMCU) . . . . .2142
52.11.1DBGMCU registers . . . . .2143
52.11.2DBGMCU register map . . . . .2148
52.12References . . . . .2149
53Device electronic signature . . . . .2150
53.1Unique device ID register (96 bits) . . . . .2151
53.2Flash size data register .....2152
53.3Package data register .....2153
54Important security notice .....2154
55Revision history .....2155

List of tables

Table 1.Example of memory map security attribution versus SAU regions configuration . . . . .82
Table 2.Securable peripherals by TZSC . . . . .83
Table 3.TrustZone-aware peripherals . . . . .85
Table 4.STM32L552xx and STM32L562xx memory map and peripheral register boundary addresses . . . . .88
Table 5.SRAM2 organization . . . . .94
Table 6.Boot modes when TrustZone is disabled (TZEN=0) . . . . .97
Table 7.Boot modes when TrustZone is enabled (TZEN=1) . . . . .98
Table 8.Boot space versus RDP protection . . . . .98
Table 9.Configuring security attributes with IDAU and SAU . . . . .106
Table 10.MPCWMx instances . . . . .108
Table 11.MPCBBx instances . . . . .108
Table 12.DMA channel use (security) . . . . .111
Table 13.DMA channel usage (privilege) . . . . .112
Table 14.Secure alternate function between peripherals and allocated I/Os . . . . .114
Table 15.Summary of the I/Os that cannot be connected to a non-secure peripheral when secure . . . . .114
Table 16.Summary of the I/Os that can be secured and connected to a non-secure peripheral . . . . .115
Table 17.Internal tampers in TAMP . . . . .119
Table 18.Effect of low-power modes on TAMP . . . . .120
Table 19.Accelerated cryptographic operations . . . . .122
Table 20.Main product lifecycle transitions . . . . .123
Table 21.Typical product lifecycle phases . . . . .124
Table 22.Debug protection with RDP . . . . .125
Table 23.Software intellectual property protection with RDP . . . . .127
Table 24.MPCWMx . . . . .134
Table 25.MPCBBx . . . . .135
Table 26.GTZC_TZSC register map and reset values . . . . .148
Table 27.GTZC_MPCBB1 register map and reset values . . . . .153
Table 28.GTZC_MPCBB2 register map and reset values . . . . .153
Table 29.GTZC_TZIC register map and reset values . . . . .172
Table 30.Flash module - 256 KB dual bank organization (64 bits read width) . . . . .176
Table 31.Flash module - 512 KB dual bank organization (64 bits read width) . . . . .176
Table 32.Flash module - 256 KB single bank organization (128 bits read width) . . . . .177
Table 33.Flash module - 512 KB single bank organization (128 bits read width) . . . . .177
Table 34.Number of wait states according to CPU clock (HCLK) frequency . . . . .179
Table 35.User option byte organization mapping . . . . .190
Table 36.Default secure option bytes after TZEN activation . . . . .194
Table 37.Secure watermark-based area . . . . .195
Table 38.Secure, HDP protections summary . . . . .196
Table 39.Flash security state . . . . .197
Table 40.User accesses via bootloader or JTAG . . . . .199
Table 41.Non-secure peripherals, IRQn and IOs for bootloader execution . . . . .200
Table 42.WRP protection . . . . .204
Table 43.Flash memory readout protection status (TZEN=0) . . . . .204
Table 44.Access status versus protection level and execution modes when TZEN=0 . . . . .205
Table 45.Flash memory readout protection status (TZEN=1) . . . . .206
Table 46.Access status versus protection level and execution modes when TZEN=1 . . . . .207
Table 47.Flash access versus RDP level when TrustZone is active (TZEN=1) . . . . .210
Table 48.Flash access versus RDP level when TrustZone is disabled (TZEN=0) . . . . .210
Table 49.Flash mass erase versus RDP level when TrustZone is active (TZEN = 1). . . . .211
Table 50.Flash system memory, RSS and OTP accesses . . . . .211
Table 51.Flash registers access . . . . .212
Table 52.Flash interrupt request . . . . .212
Table 53.Flash interface - register map and reset values . . . . .239
Table 54.ICACHE features . . . . .243
Table 55.TAG memory dimensioning parameters
for n-way set associative operating mode (default) . . . . .		245
Table 56.TAG memory dimensioning parameters for direct-mapped cache mode . . . . .246
Table 57.ICACHE cacheability for AHB transaction . . . . .248
Table 58.Memory configurations . . . . .248
Table 59.ICACHE remap region size, base address, and remap address . . . . .249
Table 60.ICACHE interrupts . . . . .253
Table 61.ICACHE register map and reset values . . . . .258
Table 62.SMPS modes summary . . . . .268
Table 63.SMPS step down converter operating mode . . . . .268
Table 64.SMPS step down converter versus low-power modes . . . . .269
Table 65.PVM features . . . . .275
Table 66.Low-power mode summary . . . . .279
Table 67.Functionalities depending on the working mode. . . . .280
Table 68.Low-power run . . . . .284
Table 69.Sleep mode. . . . .285
Table 70.Low-power sleep. . . . .287
Table 71.Stop 0 mode . . . . .289
Table 72.Stop 1 mode . . . . .290
Table 73.Stop 2 mode . . . . .292
Table 74.Standby mode. . . . .294
Table 75.Shutdown mode . . . . .296
Table 76.PWR Security configuration summary . . . . .297
Table 77.PWR register map and reset values . . . . .320
Table 78.RCC input/output signals connected to package pins or balls . . . . .325
Table 79.Clock source frequency . . . . .335
Table 80.RCC security configuration summary . . . . .342
Table 81.Interrupt sources and control . . . . .344
Table 82.RCC register map and reset values . . . . .417
Table 83.CRS features . . . . .424
Table 84.CRS internal input/output signals . . . . .425
Table 85.CRS interconnection. . . . .426
Table 86.Effect of low-power modes on CRS . . . . .429
Table 87.Interrupt control bits . . . . .429
Table 88.CRS register map and reset values . . . . .434
Table 89.Port bit configuration table . . . . .437
Table 90.GPIO secured bits . . . . .445
Table 91.GPIO register map and reset values . . . . .454
Table 92.TrustZone security and privilege register accesses . . . . .456
Table 93.BOOSTEN and ANASWVDD set/reset. . . . .460
Table 94.SYSCFG register map and reset values. . . . .467
Table 95.STM32L552xx and STM32L562xx peripherals interconnect matrix . . . . .469
Table 96.DMA1 and DMA2 implementation . . . . .479
Table 97.DMA internal input/output signals. . . . .481
Table 98.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .488
Table 99.DMA interrupt requests . . . . .490
Table 100.DMA register map and reset values . . . . .502
Table 101.DMAMUX instantiation . . . . .507
Table 102.DMAMUX: assignment of multiplexer inputs to resources . . . . .508
Table 103.DMAMUX: assignment of trigger inputs to resources . . . . .509
Table 104.DMAMUX: assignment of synchronization inputs to resources . . . . .510
Table 105.DMAMUX signals . . . . .512
Table 106.DMAMUX interrupts . . . . .517
Table 107.DMAMUX register map and reset values . . . . .524
Table 108.DMAMUX register map and reset values . . . . .525
Table 109.STM32L552xx and STM32L562xx vector table . . . . .529
Table 110.EXTI pin overview . . . . .534
Table 111.EVG pin overview . . . . .535
Table 112.EXTI line connections . . . . .535
Table 113.EXTI event input configurations and register control . . . . .537
Table 114.Masking functionality . . . . .540
Table 115.Register protection overview . . . . .541
Table 116.EXTI register map sections . . . . .543
Table 117.Extended interrupt/event controller register map and reset values . . . . .560
Table 118.CRC internal input/output signals . . . . .564
Table 119.CRC register map and reset values . . . . .569
Table 120.NOR/PSRAM bank selection . . . . .573
Table 121.NOR/PSRAM External memory address . . . . .574
Table 122.NAND memory mapping and timing registers . . . . .574
Table 123.NAND bank selection . . . . .574
Table 124.Programmable NOR/PSRAM access parameters . . . . .576
Table 125.Non-multiplexed I/O NOR flash memory . . . . .576
Table 126.16-bit multiplexed I/O NOR flash memory . . . . .577
Table 127.Non-multiplexed I/Os PSRAM/SRAM . . . . .577
Table 128.16-Bit multiplexed I/O PSRAM . . . . .578
Table 129.NOR flash/PSRAM: example of supported memories
and transactions . . . . .		579
Table 130.FMC_BCRx bitfields (mode 1) . . . . .582
Table 131.FMC_BTRx bitfields (mode 1) . . . . .582
Table 132.FMC_BCRx bitfields (mode A) . . . . .584
Table 133.FMC_BTRx bitfields (mode A) . . . . .584
Table 134.FMC_BWTRx bitfields (mode A) . . . . .585
Table 135.FMC_BCRx bitfields (mode 2/B) . . . . .587
Table 136.FMC_BTRx bitfields (mode 2/B) . . . . .587
Table 137.FMC_BWTRx bitfields (mode 2/B) . . . . .588
Table 138.FMC_BCRx bitfields (mode C) . . . . .589
Table 139.FMC_BTRx bitfields (mode C) . . . . .590
Table 140.FMC_BWTRx bitfields (mode C) . . . . .590
Table 141.FMC_BCRx bitfields (mode D) . . . . .592
Table 142.FMC_BTRx bitfields (mode D) . . . . .593
Table 143.FMC_BWTRx bitfields (mode D) . . . . .593
Table 144.FMC_BCRx bitfields (Muxed mode) . . . . .595
Table 145.FMC_BTRx bitfields (Muxed mode) . . . . .596
Table 146.FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .601
Table 147.FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .602
Table 148.FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .603
Table 149.FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .604
Table 150.Programmable NAND flash access parameters . . . . .613
Table 151.8-bit NAND flash . . . . .613
Table 152.16-bit NAND flash . . . . .614
Table 153.Supported memories and transactions . . . . .614
Table 154.ECC result relevant bits . . . . .623
Table 155.FMC register map and reset values . . . . .624
Table 156.OCTOSPI implementation . . . . .627
Table 157.OCTOSPI input/output pins . . . . .629
Table 158.OCTOSPI internal signals . . . . .629
Table 159.Command/address phase description . . . . .638
Table 160.OctaRAM command address bit assignment
(based on 64-Mbyte OctaRAM) . . . . .		648
Table 161.Address alignment cases . . . . .655
Table 162.OCTOSPI interrupt requests . . . . .656
Table 163.OCTOSPI register map and reset values . . . . .679
Table 164.ADC features . . . . .685
Table 165.ADC internal input/output signals . . . . .687
Table 166.ADC input/output pins . . . . .687
Table 167.Configuring the trigger polarity for regular external triggers . . . . .704
Table 168.Configuring the trigger polarity for injected external triggers . . . . .704
Table 169.ADC1/2 - External triggers for regular channels . . . . .705
Table 170.ADC1/2 - External trigger for injected channels . . . . .706
Table 171.TSAR timings depending on resolution . . . . .718
Table 172.Offset computation versus data resolution . . . . .721
Table 173.Analog watchdog channel selection . . . . .732
Table 174.Analog watchdog 1 comparison . . . . .733
Table 175.Analog watchdog 2 and 3 comparison . . . . .733
Table 176.Maximum output results versus N and M (gray cells indicate truncation) . . . . .737
Table 177.Oversampler operating modes summary . . . . .741
Table 178.Effect of low-power modes on the ADC . . . . .759
Table 179.ADC interrupts per each ADC . . . . .760
Table 180.DELAY bits versus ADC resolution . . . . .791
Table 181.ADC global register map . . . . .792
Table 182.ADC register map and reset values for each ADC (offset = 0x000
for master ADC, 0x100 for slave ADC) . . . . .		792
Table 183.ADC register map and reset values (master and slave ADC
common registers) offset = 0x300 . . . . .		795
Table 184.DAC features . . . . .797
Table 185.DAC input/output pins . . . . .799
Table 186.DAC trigger selection . . . . .802
Table 187.Sample and refresh timings . . . . .807
Table 188.Channel output modes summary . . . . .808
Table 189.Effect of low-power modes on DAC . . . . .815
Table 190.DAC interrupts . . . . .816
Table 191.DAC register map and reset values . . . . .831
Table 192.VREF buffer modes . . . . .833
Table 193.VREFBUF trimming data . . . . .834
Table 194.VREFBUF register map and reset values . . . . .836
Table 195.COMP1 input plus assignment . . . . .838
Table 196.COMP1 input minus assignment . . . . .839
Table 197.COMP2 input plus assignment . . . . .839
Table 198.COMP2 input minus assignment . . . . .839
Table 199.Comparator behavior in the low power modes . . . . .842
Table 200.Interrupt control bits . . . . .843
Table 201.COMP register map and reset values . . . . .848
Table 202.Operational amplifier possible connections . . . . .850
Table 203.Operating modes and calibration . . . . .855
Table 204.Effect of low-power modes on the OPAMP . . . . .856
Table 205.OPAMP register map and reset values . . . . .861
Table 206.DFSDM1 implementation . . . . .864
Table 207.DFSDM external pins . . . . .866
Table 208.DFSDM internal signals . . . . .866
Table 209.DFSDM triggers connection . . . . .866
Table 210.DFSDM break connection . . . . .867
Table 211.Filter maximum output resolution (peak data values from filter output)
for some FOSR values . . . . .		882
Table 212.Integrator maximum output resolution (peak data values from integrator
output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . . .		883
Table 213.DFSDM interrupt requests . . . . .891
Table 214.DFSDM register map and reset values . . . . .912
Table 215.Acquisition sequence summary . . . . .923
Table 216.Spread spectrum deviation versus AHB clock frequency . . . . .925
Table 217.I/O state depending on its mode and IODEF bit value . . . . .926
Table 218.Effect of low-power modes on TSC . . . . .928
Table 219.Interrupt control bits . . . . .928
Table 220.TSC register map and reset values . . . . .936
Table 221.RNG internal input/output signals . . . . .939
Table 222.RNG interrupt requests . . . . .946
Table 223.RNG configurations . . . . .947
Table 224.Configuration selection . . . . .948
Table 225.RNG register map and reset map . . . . .952
Table 226.AES internal input/output signals . . . . .954
Table 227.CTR mode initialization vector definition . . . . .970
Table 228.GCM last block definition . . . . .972
Table 229.Initialization of AES_IVRx registers in GCM mode . . . . .973
Table 230.Initialization of AES_IVRx registers in CCM mode . . . . .980
Table 231.Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .985
Table 232.AES interrupt requests . . . . .988
Table 233.Processing latency for ECB, CBC and CTR . . . . .988
Table 234.Processing latency for GCM and CCM (in clock cycles) . . . . .989
Table 235.AES register map and reset values . . . . .999
Table 236.HASH internal input/output signals . . . . .1003
Table 237.Hash processor outputs . . . . .1006
Table 238.Processing time (in clock cycle) . . . . .1012
Table 239.HASH interrupt requests . . . . .1013
Table 240.HASH register map and reset values . . . . .1021
Table 241.OTFDEC internal input/output signals . . . . .1024
Table 242.OTFDEC interrupt requests . . . . .1028
Table 243.OTFDEC register map and reset values . . . . .1042
Table 244.Internal input/output signals . . . . .1047
Table 245.PKA integer arithmetic functions list . . . . .1048
Table 246.PKA prime field (Fp) elliptic curve functions list . . . . .1048
Table 247.Montgomery parameter computation . . . . .1054
Table 248.Modular addition . . . . .1054
Table 249.Modular subtraction . . . . .1054
Table 250.Montgomery multiplication . . . . .1055
Table 251.Modular exponentiation (normal mode) . . . . .1056
Table 252.Modular exponentiation (fast mode) . . . . .1056
Table 253.Modular inversion . . . . .1057
Table 254.Modular reduction . . . . .1057
Table 255.Arithmetic addition . . . . .1057
Table 256.Arithmetic subtraction . . . . .1058
Table 257.Arithmetic multiplication . . . . .1058
Table 258.Arithmetic comparison . . . . .1058
Table 259.CRT exponentiation . . . . .1059
Table 260.Point on elliptic curve Fp check . . . . .1060
Table 261.ECC Fp scalar multiplication . . . . .1060
Table 262.ECC Fp scalar multiplication (Fast Mode) . . . . .1061
Table 263.ECDSA sign - Inputs . . . . .1062
Table 264.ECDSA sign - Outputs . . . . .1062
Table 265.Extended ECDSA sign (extra outputs) . . . . .1063
Table 266.ECDSA verification (inputs) . . . . .1063
Table 267.ECDSA verification (outputs) . . . . .1063
Table 268.Family of supported curves for ECC operations . . . . .1064
Table 269.Modular exponentiation computation times . . . . .1066
Table 270.ECC scalar multiplication computation times . . . . .1066
Table 271.ECDSA signature average computation times . . . . .1066
Table 272.ECDSA verification average computation times . . . . .1067
Table 273.Point on elliptic curve Fp check average computation times . . . . .1067
Table 274.Montgomery parameters average computation times . . . . .1067
Table 275.PKA interrupt requests . . . . .1067
Table 276.PKA register map and reset values . . . . .1071
Table 277.Behavior of timer outputs versus BRK/BRK2 inputs . . . . .1113
Table 278.Break protection disarming conditions . . . . .1115
Table 279.Counting direction versus encoder signals . . . . .1121
Table 280.TIMx internal trigger connection . . . . .1138
Table 281.Output control bits for complementary OCx and OCxN channels with break feature . . . . .1152
Table 282.TIM1 register map and reset values . . . . .1172
Table 283.TIM8 register map and reset values . . . . .1174
Table 284.Counting direction versus encoder signals . . . . .1211
Table 285.TIMx internal trigger connection . . . . .1228
Table 286.Output control bit for standard OCx channels . . . . .1239
Table 287.TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . .1247
Table 288.Break protection disarming conditions . . . . .1278
Table 289.TIMx Internal trigger connection . . . . .1294
Table 290.Output control bits for complementary OCx and OCxN channels with break feature
(TIM15) . . . . .		1304
Table 291.TIM15 register map and reset values . . . . .1313
Table 292.Output control bits for complementary OCx and OCxN channels with break feature
(TIM16/17) . . . . .		1326
Table 293.TIM16/TIM17 register map and reset values . . . . .1337
Table 294.TIMx register map and reset values . . . . .1351
Table 295.STM32L552xx and STM32L562xx LPTIM features . . . . .1352
Table 296.LPTIM input/output pins . . . . .1353
Table 297.LPTIM internal signals . . . . .1354
Table 298.LPTIM1 external trigger connections . . . . .1354
Table 299.LPTIM2 external trigger connections . . . . .1354
Table 300.LPTIM3 external trigger connections . . . . .1355
Table 301.Prescaler division ratios . . . . .1356
Table 302.Encoder counting scenarios . . . . .1363
Table 303.Effect of low-power modes on the LPTIM . . . . .1366
Table 304.Interrupt events . . . . .1366
Table 305.LPTIM register map and reset values . . . . .1377
Table 306.IWDG register map and reset values . . . . .1388
Table 307.WWDG register map and reset values . . . . .1394
Table 308.RTC input/output pins . . . . .1398
Table 309.RTC internal input/output signals . . . . .1398
Table 310.RTC interconnection . . . . .1399
Table 311.RTC pin PC13 configuration . . . . .1399
Table 312.RTC_OUT mapping . . . . .1401
Table 313.Effect of low-power modes on RTC . . . . .1416
Table 314.RTC pins functionality over modes . . . . .1416
Table 315.Non-secure interrupt requests . . . . .1417
Table 316.Secure interrupt requests . . . . .1418
Table 317.RTC register map and reset values . . . . .1445
Table 318.TAMP input/output pins . . . . .1449
Table 319.TAMP internal input/output signals . . . . .1449
Table 320.TAMP interconnection . . . . .1449
Table 321.Minimum ATPER value . . . . .1454
Table 322.Effect of low-power modes on TAMP . . . . .1455
Table 323.TAMP pins functionality over modes . . . . .1455
Table 324.Non-secure interrupt requests . . . . .1456
Table 325.Secure interrupt requests . . . . .1456
Table 326.TAMP register map and reset values . . . . .1481
Table 327.I2C implementation . . . . .1484
Table 328.I2C input/output pins . . . . .1485
Table 329.I2C internal input/output signals . . . . .1486
Table 330.Comparison of analog and digital filters . . . . .1488
Table 331.I 2 C-bus and SMBus specification data setup and hold times . . . . .1490
Table 332.I2C configuration . . . . .1494
Table 333.I 2 C-bus and SMBus specification clock timings . . . . .1505
Table 334.Timing settings for f I2CCLK of 8 MHz . . . . .1515
Table 335.Timing settings for f I2CCLK of 16 MHz . . . . .1515
Table 336.Timing settings for f I2CCLK of 48 MHz . . . . .1516
Table 337.SMBus timeout specifications . . . . .1518
Table 338.SMBus with PEC configuration . . . . .1520
Table 339.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms . . . . .1521
Table 340.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .1521
Table 341.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .1521
Table 342.Effect of low-power modes to I2C . . . . .1531
Table 343.I2C interrupt requests . . . . .1531
Table 344.I2C register map and reset values . . . . .1547
Table 345.Instance implementation on STM32L552xx and STM32L562xx . . . . .1550
Table 346.USART / LPUART features . . . . .1550
Table 347.USART/UART input/output pins . . . . .1554
Table 348.USART internal input/output signals . . . . .1554
Table 349.Noise detection from sampled data . . . . .1566
Table 350.Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .1569
Table 351.Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . .1570
Table 352.USART frame formats . . . . .1575
Table 353.Effect of low-power modes on the USART . . . . .1598
Table 354.USART interrupt requests. . . . .1599
Table 355.USART register map and reset values . . . . .1633
Table 356.Instance implementation on STM32L552xx and STM32L562xx . . . . .1637
Table 357.USART / LPUART features . . . . .1637
Table 358.LPUART input/output pins . . . . .1639
Table 359.LPUART internal input/output signals. . . . .1639
Table 360.Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz . . . . .1649
Table 361.Error calculation for programmed baud rates at fCK = 100 MHz . . . . .1650
Table 362.Tolerance of the LPUART receiver. . . . .1651
Table 364.Effect of low-power modes on the LPUART . . . . .1662
Table 365.LPUART interrupt requests. . . . .1663
Table 366.LPUART register map and reset values . . . . .1686
Table 367.STM32L552xx and STM32L562xx SPI implementation . . . . .1689
Table 368.SPI interrupt requests . . . . .1713
Table 369.SPI register map and reset values . . . . .1722
Table 370.SAI features . . . . .1724
Table 371.SAI internal input/output signals . . . . .1726
Table 372.SAI input/output pins. . . . .1726
Table 373.External synchronization selection . . . . .1729
Table 374.MCLK_x activation conditions. . . . .1734
Table 375.Clock generator programming examples . . . . .1737
Table 376.SAI_A configuration for TDM mode . . . . .1744
Table 377.TDM frame configuration examples . . . . .1746
Table 378.SOPD pattern . . . . .1750
Table 379.Parity bit calculation . . . . .1750
Table 380.Audio sampling frequency versus symbol rates . . . . .1751
Table 381.SAI interrupt sources . . . . .1760
Table 382.SAI register map and reset values . . . . .1789
Table 383.SDMMC operation modes SD and SDIO . . . . .1793
Table 384.SDMMC operation modes e•MMC . . . . .1794
Table 385.SDMMC internal input/output signals . . . . .1795
Table 386.SDMMC pins. . . . .1795
Table 387.SDMMC Command and data phase selection . . . . .1796
Table 388.Command token format . . . . .1802
Table 389.Short response with CRC token format . . . . .1803
Table 390.Short response without CRC token format . . . . .1803
Table 391.Long response with CRC token format. . . . .1803
Table 392.Specific Commands overview. . . . .1804
Table 393.Command path status flags . . . . .1805
Table 394.Command path error handling . . . . .1805
Table 395.Data token format. . . . .1813
Table 396.Data path status flags and clear bits. . . . .1813
Table 397.Data path error handling. . . . .1815
Table 398.Data FIFO access. . . . .1816
Table 399.Transmit FIFO status flags . . . . .1817
Table 400.Receive FIFO status flags . . . . .1818
Table 401.AHB and SDMMC_CK clock frequency relation. . . . .1821
Table 402.SDIO special operation control. . . . .1822
Table 403.4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . .1826
Table 404.CMD12 use cases . . . . .1830
Table 405.SDMMC interrupts . . . . .1844
Table 406.Response type and SDMMC_RESPxR registers . . . . .1851
Table 407.SDMMC register map . . . . .1866
Table 408.CAN subsystem I/O signals . . . . .1873
Table 409.CAN subsystem I/O pins. . . . .1873
Table 410.DLC coding in FDCAN . . . . .1877
Table 411.Possible configurations for frame transmission . . . . .1891
Table 412.Rx FIFO element . . . . .1894
Table 413.Rx FIFO element description . . . . .1894
Table 414.Tx buffer and FIFO element . . . . .1896
Table 415.Tx buffer element description . . . . .1896
Table 416.Tx event FIFO element. . . . .1898
Table 417.Tx event FIFO element description. . . . .1898
Table 418.Standard message ID filter element . . . . .1899
Table 419.Standard message ID filter element field description . . . . .1900
Table 420.Extended message ID filter element. . . . .1900
Table 421.Extended message ID filter element field description. . . . .1901
Table 422.FDCAN register map and reset values . . . . .1931
Table 423.STM32L552xx and STM32L562xx USB implementation . . . . .1935
Table 424.Double-buffering buffer flag definition. . . . .1945
Table 425.Bulk double-buffering memory buffers usage . . . . .1945
Table 426.Isochronous memory buffers usage . . . . .1947
Table 427.Resume event detection. . . . .1948
Table 428.Reception status encoding . . . . .1961
Table 429.Endpoint type encoding . . . . .1961
Table 430.Endpoint kind meaning . . . . .1961
Table 431.Transmission status encoding . . . . .1962
Table 432.Definition of allocated buffer memory . . . . .1965
Table 433.USB register map and reset values . . . . .1966
Table 434.UCPD implementation . . . . .1969
Table 435.UCPD signals on pins. . . . .1970
Table 436.UCPD internal signals. . . . .1971
Table 437.4b5b symbol encoding table . . . . .1972
Table 438.Ordered sets . . . . .1974
Table 439.Validation of ordered sets. . . . .1974
Table 440.Data size. . . . .1975
Table 441.Coding for ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx . . . . .1983
Table 442.Type-C sequence (source: 3A); cable/sink connected (Rd on CC1; Ra on CC2) . . . . .1985
Table 443.Effect of low power modes on the UCPD . . . . .1987
Table 444.UCPD interrupt requests. . . . .1988
Table 445.UCPD register map and reset values . . . . .2003
Table 446.JTAG/Serial-wire debug port pins. . . . .2007
Table 447.Trace port pins . . . . .2007
Table 448.Single Wire Trace port pins . . . . .2008
Table 449.Authentication signal states . . . . .2009
Table 450.JTAG-DP data registers . . . . .2012
Table 451.Packet request . . . . .2014
Table 452.ACK response. . . . .2014
Table 453.Data transfer. . . . .2014
Table 454.Debug port register map and reset values . . . . .2022
Table 455.Access port register map and reset values. . . . .2028
Table 456. MCU ROM table . . . . .2029
Table 457. Processor ROM table . . . . .2030
Table 458. MCU ROM table register map and reset values . . . . .2037
Table 459. CPU ROM table register map and reset values . . . . .2043
Table 460. DWT register map and reset values . . . . .2060
Table 461. CPU1 ITM register map and reset values . . . . .2072
Table 462. CPU1 BPU register map and reset values . . . . .2081
Table 463. ETM register map and reset values . . . . .2109
Table 464. CPU1 TPIU register map and reset values . . . . .2125
Table 465. CTI inputs . . . . .2127
Table 466. CTI outputs . . . . .2127
Table 467. CTI register map and reset values . . . . .2140
Table 468. DBGMCU register map and reset values . . . . .2148
Table 469. Document revision history . . . . .2155

List of figures

Figure 1.System architecture . . . . .80
Figure 2.Memory map based on IDAU mapping. . . . .87
Figure 3.Secure/non-secure partitioning using TrustZone® technology . . . . .103
Figure 4.Sharing memory map between CPU in secure and non-secure state . . . . .105
Figure 5.Secure world transition and memory partitioning . . . . .106
Figure 6.Global TrustZone framework and TrustZone awareness . . . . .107
Figure 7.Flash memory TrustZone® protections. . . . .110
Figure 8.Flash memory secure hide protection (HDP) area . . . . .117
Figure 9.Key management principle . . . . .121
Figure 10.Device lifecycle security . . . . .123
Figure 11.RDP level transition scheme. . . . .124
Figure 12.Collaborative development principle . . . . .126
Figure 13.External flash memory protection using SFI. . . . .128
Figure 14.GTZC in Armv8-M subsystem block diagram. . . . .132
Figure 15.GTZC block diagram. . . . .133
Figure 16.RDP level transition scheme when TrustZone is disabled (TZEN=0I) . . . . .209
Figure 17.RDP level transition scheme when TrustZone is enabled (TZEN=1) . . . . .209
Figure 18.ICACHE block diagram . . . . .244
Figure 19.ICACHE TAG and data memories functional view . . . . .246
Figure 20.ICACHE remapping address mechanism . . . . .249
Figure 21.STM32L552xx and STM32L562xx power supply overview . . . . .261
Figure 22.STM32L552xxxP and STM32L562xxxP power supply overview . . . . .262
Figure 23.STM32L552xxxQ and STM32L562xxxQ power supply overview. . . . .263
Figure 24.SMPS step down converter power supply scheme . . . . .269
Figure 25.Internal main regulator overview. . . . .272
Figure 26.Brown-out reset waveform . . . . .274
Figure 27.PVD thresholds . . . . .274
Figure 28.Low-power modes possible transitions. . . . .278
Figure 29.Simplified diagram of the reset circuit. . . . .324
Figure 30.Clock tree . . . . .328
Figure 31.HSE/ LSE clock sources. . . . .329
Figure 32.Frequency measurement with TIM15 in capture mode. . . . .338
Figure 33.Frequency measurement with TIM16 in capture mode. . . . .338
Figure 34.Frequency measurement with TIM17 in capture mode. . . . .339
Figure 35.CRS block diagram. . . . .425
Figure 36.CRS counter behavior . . . . .427
Figure 37.Basic structure of an I/O port bit . . . . .436
Figure 38.Basic structure of a 5-Volt tolerant I/O port bit . . . . .436
Figure 39.Input floating/pull up/pull down configurations . . . . .441
Figure 40.Output configuration . . . . .442
Figure 41.Alternate function configuration . . . . .442
Figure 42.High impedance-analog configuration . . . . .443
Figure 43.DMA block diagram . . . . .480
Figure 44.DMAMUX block diagram . . . . .511
Figure 45.Synchronization mode of the DMAMUX request line multiplexer channel . . . . .515
Figure 46.Event generation of the DMA request line multiplexer channel . . . . .515
Figure 47.EXTI block diagram . . . . .534
Figure 48.Configurable event trigger logic CPU wakeup . . . . .538
Figure 49.Direct event trigger logic CPU wakeup . . . . .539
Figure 50.EXTI mux GPIO selection. . . . .540
Figure 51.CRC calculation unit block diagram . . . . .564
Figure 52.FMC block diagram. . . . .571
Figure 53.FMC memory banks . . . . .573
Figure 54.Mode 1 read access waveforms . . . . .581
Figure 55.Mode 1 write access waveforms. . . . .581
Figure 56.Mode A read access waveforms. . . . .583
Figure 57.Mode A write access waveforms . . . . .583
Figure 58.Mode 2 and mode B read access waveforms. . . . .585
Figure 59.Mode 2 write access waveforms. . . . .586
Figure 60.Mode B write access waveforms . . . . .586
Figure 61.Mode C read access waveforms . . . . .588
Figure 62.Mode C write access waveforms . . . . .589
Figure 63.Mode D read access waveforms . . . . .591
Figure 64.Mode D write access waveforms . . . . .592
Figure 65.Muxed read access waveforms . . . . .594
Figure 66.Muxed write access waveforms . . . . .595
Figure 67.Asynchronous wait during a read access waveforms. . . . .597
Figure 68.Asynchronous wait during a write access waveforms. . . . .598
Figure 69.Wait configuration waveforms. . . . .600
Figure 70.Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM). . . . .601
Figure 71.Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . .603
Figure 72.NAND flash controller waveforms for common memory access. . . . .615
Figure 73.Access to non 'CE don't care' NAND-flash. . . . .617
Figure 74.OCTOSPI block diagram in octal configuration . . . . .628
Figure 75.OCTOSPI block diagram in quad configuration . . . . .628
Figure 76.OCTOSPI block diagram in dual-quad configuration . . . . .629
Figure 77.SDR read command in octal configuration . . . . .630
Figure 78.DTR read in octal-SPI mode with DQS (Macronix mode) example . . . . .633
Figure 79.SDR write command in octo-SPI mode example . . . . .635
Figure 80.DTR write in octal-SPI mode (Macronix mode) example . . . . .636
Figure 81.Example of HyperBus read operation. . . . .637
Figure 82.HyperBus write operation with initial latency . . . . .639
Figure 83.HyperBus read operation with additional latency . . . . .639
Figure 84.HyperBus write operation with additional latency . . . . .640
Figure 85.HyperBus write operation with no latency (register write). . . . .640
Figure 86.HyperBus read operation page crossing with latency. . . . .641
Figure 87.D0/D1 data ordering in octal-SPI DTR mode (Micron) - Read access . . . . .647
Figure 88.OctaRAM read operation with reverse data ordering D1/D0 . . . . .648
Figure 89.NCS when CKMODE = 0 (T = CLK period) . . . . .654
Figure 90.NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .654
Figure 91.NCS when CKMODE = 1 in DTR mode (T = CLK period) . . . . .654
Figure 92.NCS when CKMODE = 1 with an abort (T = CLK period). . . . .655
Figure 93.ADC block diagram . . . . .686
Figure 94.ADC clock scheme . . . . .689
Figure 95.ADC1 connectivity . . . . .690
Figure 96.ADC2 connectivity . . . . .691
Figure 97.ADC calibration. . . . .694
Figure 98.Updating the ADC calibration factor . . . . .695
Figure 99.Mixing single-ended and differential channels . . . . .696
Figure 100.Enabling / disabling the ADC . . . . .697
Figure 101. Analog-to-digital conversion time . . . . .702
Figure 102. Stopping ongoing regular conversions . . . . .703
Figure 103. Stopping ongoing regular and injected conversions . . . . .703
Figure 104. Triggers sharing between ADC master and ADC slave . . . . .705
Figure 105. Injected conversion latency . . . . .707
Figure 106. Example of ADC_JSQR queue of context (sequence change) . . . . .711
Figure 107. Example of ADC_JSQR queue of context (trigger change) . . . . .711
Figure 108. Example of ADC_JSQR queue of context with overflow before conversion. . . . .712
Figure 109. Example of ADC_JSQR queue of context with overflow during conversion . . . . .712
Figure 110. Example of ADC_JSQR queue of context with empty queue (case JQM = 0). . . . .713
Figure 111. Example of ADC_JSQR queue of context with empty queue (case JQM = 1). . . . .714
Figure 112. Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs during an ongoing conversion . . . . .		714
Figure 113. Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . .		715
Figure 114. Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs outside an ongoing conversion . . . . .		715
Figure 115. Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 1) . . . . .716
Figure 116. Flushing ADC_JSQR queue of context by setting ADDIS = 1 (JQM = 0). . . . .716
Figure 117. Flushing ADC_JSQR queue of context by setting ADDIS = 1 (JQM = 1). . . . .717
Figure 118. Single conversions of a sequence, software trigger . . . . .719
Figure 119. Continuous conversion of a sequence, software trigger. . . . .719
Figure 120. Single conversions of a sequence, hardware trigger . . . . .720
Figure 121. Continuous conversions of a sequence, hardware trigger . . . . .720
Figure 122. Right alignment (offset disabled, unsigned value) . . . . .722
Figure 123. Right alignment (offset enabled, signed value). . . . .723
Figure 124. Left alignment (offset disabled, unsigned value) . . . . .723
Figure 125. Left alignment (offset enabled, signed value). . . . .724
Figure 126. Example of overrun (OVR) . . . . .725
Figure 127. AUTODLY = 1, regular conversion in continuous mode, software trigger . . . . .728
Figure 128. AUTODLY = 1, regular HW conversions interrupted by injected conversions
(DISCEN = 0; JDISCEN = 0) . . . . .		729
Figure 129. AUTODLY = 1, regular HW conversions interrupted by injected conversions . . . . .
(DISCEN = 1, JDISCEN = 1) . . . . .		730
Figure 130. AUTODLY = 1, regular continuous conversions interrupted by injected conversions . . . . .731
Figure 131. AUTODLY = 1 in auto- injected mode (JAUTO = 1). . . . .731
Figure 132. Analog watchdog guarded area . . . . .732
Figure 133. ADC y _AWD x _OUT signal generation (on all regular channels). . . . .734
Figure 134. ADC y _AWD x _OUT signal generation (AWD x flag not cleared by software) . . . . .735
Figure 135. ADC y _AWD x _OUT signal generation (on a single regular channel) . . . . .735
Figure 136. ADC y _AWD x _OUT signal generation (on all injected channels) . . . . .735
Figure 137. 20-bit to 16-bit result truncation . . . . .736
Figure 138. Numerical example with 5-bit shift and rounding . . . . .736
Figure 139. Triggered regular oversampling mode (TROVS bit = 1). . . . .738
Figure 140. Regular oversampling modes (4x ratio) . . . . .739
Figure 141. Regular and injected oversampling modes used simultaneously . . . . .740
Figure 142. Triggered regular oversampling with injection . . . . .740
Figure 143. Oversampling in auto-injected mode . . . . .741
Figure 144. Dual ADC block diagram (1) . . . . .743
Figure 145. Injected simultaneous mode on 4 channels: dual ADC mode . . . . .744
Figure 146. Regular simultaneous mode on 16 channels: dual ADC mode . . . . .746
Figure 147. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . .747
Figure 148. Interleaved mode on 1 channel in single conversion mode: dual ADC mode. . . . .748
Figure 149. Interleaved conversion with injection . . . . .748
Figure 150. Alternate trigger: injected group of each ADC . . . . .749
Figure 151. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode. . . . .750
Figure 152. Alternate + regular simultaneous . . . . .751
Figure 153. Case of trigger occurring during injected conversion . . . . .751
Figure 154. Interleaved single channel CH0 with injected sequence CH11, CH12. . . . .752
Figure 155. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first. . . . .		752
Figure 156. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first. . . . .		752
Figure 157. DMA Requests in regular simultaneous mode when MDMA = 00 . . . . .753
Figure 158. DMA requests in regular simultaneous mode when MDMA = 10 . . . . .754
Figure 159. DMA requests in interleaved mode when MDMA = 10. . . . .754
Figure 160. Temperature sensor channel block diagram . . . . .756
Figure 161. VBAT channel block diagram . . . . .757
Figure 162. VREFINT channel block diagram . . . . .758
Figure 163. Dual-channel DAC block diagram . . . . .798
Figure 164. Data registers in single DAC channel mode. . . . .800
Figure 165. Data registers in dual DAC channel mode . . . . .800
Figure 166. Timing diagram for conversion with trigger disabled TEN = 0 . . . . .801
Figure 167. DAC LFSR register calculation algorithm . . . . .804
Figure 168. DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .804
Figure 169. DAC triangle wave generation . . . . .805
Figure 170. DAC conversion (SW trigger enabled) with triangle wave generation . . . . .805
Figure 171. DAC sample and hold mode phase diagram . . . . .808
Figure 172. Comparator block diagram . . . . .838
Figure 173. Window mode. . . . .840
Figure 174. Comparator hysteresis . . . . .841
Figure 175. Comparator output blanking . . . . .841
Figure 176. Standalone mode: external gain setting mode . . . . .851
Figure 177. Follower configuration. . . . .852
Figure 178. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . .853
Figure 179. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for
filtering . . . . .		854
Figure 180. Single DFSDM block diagram. . . . .865
Figure 181. Input channel pins redirection. . . . .869
Figure 182. Channel transceiver timing diagrams . . . . .872
Figure 183. Clock absence timing diagram for SPI . . . . .873
Figure 184. Clock absence timing diagram for Manchester coding. . . . .874
Figure 185. First conversion for Manchester coding (Manchester synchronization) . . . . .876
Figure 186. DFSDM_CHyDATINR registers operation modes and assignment . . . . .880
Figure 187. Example: Sinc3 filter response . . . . .882
Figure 188. TSC block diagram . . . . .921
Figure 189. Surface charge transfer analog I/O group structure . . . . .922
Figure 190. Sampling capacitor voltage variation . . . . .923
Figure 191. Charge transfer acquisition sequence . . . . .924
Figure 192. Spread spectrum variation principle . . . . .925
Figure 193. RNG block diagram . . . . .939
Figure 194. NIST SP800-90B entropy source model. . . . .940
Figure 195. RNG initialization overview. . . . .943
Figure 196. AES block diagram . . . . .954
Figure 197. ECB encryption and decryption principle . . . . .956
Figure 198. CBC encryption and decryption principle . . . . .957
Figure 199. CTR encryption and decryption principle . . . . .958
Figure 200. GCM encryption and authentication principle . . . . .959
Figure 201. GMAC authentication principle . . . . .959
Figure 202. CCM encryption and authentication principle . . . . .960
Figure 203. Example of suspend mode management . . . . .964
Figure 204. ECB encryption . . . . .965
Figure 205. ECB decryption . . . . .965
Figure 206. CBC encryption . . . . .966
Figure 207. CBC decryption . . . . .966
Figure 208. ECB/CBC encryption (Mode 1) . . . . .967
Figure 209. ECB/CBC decryption (Mode 3) . . . . .968
Figure 210. Message construction in CTR mode . . . . .969
Figure 211. CTR encryption . . . . .970
Figure 212. CTR decryption . . . . .970
Figure 213. Message construction in GCM . . . . .972
Figure 214. GCM authenticated encryption . . . . .973
Figure 215. Message construction in GMAC mode . . . . .977
Figure 216. GMAC authentication mode . . . . .977
Figure 217. Message construction in CCM mode . . . . .978
Figure 218. CCM mode authenticated encryption . . . . .980
Figure 219. 128-bit block construction with respect to data swap . . . . .984
Figure 220. DMA transfer of a 128-bit data block during input phase . . . . .986
Figure 221. DMA transfer of a 128-bit data block during output phase . . . . .987
Figure 222. HASH block diagram . . . . .1002
Figure 223. Message data swapping feature . . . . .1004
Figure 224. HASH suspend/resume mechanism . . . . .1010
Figure 225. OTFDEC block diagram . . . . .1024
Figure 226. Typical OTFDEC use in a SoC . . . . .1025
Figure 227. AES CTR decryption flow . . . . .1026
Figure 228. OTFDEC flow control overview (dual burst read request) . . . . .1027
Figure 229. PKA block diagram . . . . .1047
Figure 230. Advanced-control timer block diagram . . . . .1073
Figure 231. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1075
Figure 232. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1075
Figure 233. Counter timing diagram, internal clock divided by 1 . . . . .1077
Figure 234. Counter timing diagram, internal clock divided by 2 . . . . .1077
Figure 235. Counter timing diagram, internal clock divided by 4 . . . . .1078
Figure 236. Counter timing diagram, internal clock divided by N . . . . .1078
Figure 237. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .1079
Figure 238. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .1079
Figure 239. Counter timing diagram, internal clock divided by 1 . . . . .1081
Figure 240. Counter timing diagram, internal clock divided by 2 . . . . .1081
Figure 241. Counter timing diagram, internal clock divided by 4 . . . . .1082
Figure 242. Counter timing diagram, internal clock divided by N . . . . .1082
Figure 243. Counter timing diagram, update event when repetition counter is not used . . . . .1083
Figure 244. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .1084
Figure 245. Counter timing diagram, internal clock divided by 2 . . . . .1085
Figure 246. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .1085
Figure 247. Counter timing diagram, internal clock divided by N . . . . .1086
Figure 248. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .1086
Figure 249. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .1087
Figure 250. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1088
Figure 251. External trigger input block . . . . .1089
Figure 252. TIM1 ETR input circuitry . . . . .1089
Figure 253. TIM8 ETR input circuitry . . . . .1089
Figure 254. Control circuit in normal mode, internal clock divided by 1 . . . . .1090
Figure 255. TI2 external clock connection example. . . . .1091
Figure 256. Control circuit in external clock mode 1 . . . . .1092
Figure 257. External trigger input block . . . . .1092
Figure 258. Control circuit in external clock mode 2 . . . . .1093
Figure 259. Capture/compare channel (example: channel 1 input stage) . . . . .1094
Figure 260. Capture/compare channel 1 main circuit . . . . .1095
Figure 261. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .1095
Figure 262. Output stage of capture/compare channel (channel 4). . . . .1096
Figure 263. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .1096
Figure 264. PWM input mode timing . . . . .1098
Figure 265. Output compare mode, toggle on OC1 . . . . .1100
Figure 266. Edge-aligned PWM waveforms (ARR=8) . . . . .1101
Figure 267. Center-aligned PWM waveforms (ARR=8). . . . .1102
Figure 268. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1104
Figure 269. Combined PWM mode on channel 1 and 3 . . . . .1105
Figure 270. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .1106
Figure 271. Complementary output with dead-time insertion . . . . .1107
Figure 272. Dead-time waveforms with delay greater than the negative pulse . . . . .1107
Figure 273. Dead-time waveforms with delay greater than the positive pulse. . . . .1108
Figure 274. Break and Break2 circuitry overview . . . . .1110
Figure 275. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .1112
Figure 276. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .1113
Figure 277. PWM output state following BRK assertion (OSSI=0) . . . . .1114
Figure 278. Output redirection (BRK2 request not represented) . . . . .1115
Figure 279. Clearing TIMx OCxREF . . . . .1116
Figure 280. 6-step generation, COM example (OSSR=1) . . . . .1117
Figure 281. Example of one pulse mode. . . . .1118
Figure 282. Retriggerable one pulse mode . . . . .1120
Figure 283. Example of counter operation in encoder interface mode. . . . .1121
Figure 284. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .1122
Figure 285. Measuring time interval between edges on 3 signals . . . . .1123
Figure 286. Example of Hall sensor interface . . . . .1125
Figure 287. Control circuit in reset mode . . . . .1126
Figure 288. Control circuit in Gated mode . . . . .1127
Figure 289. Control circuit in trigger mode . . . . .1128
Figure 290. Control circuit in external clock mode 2 + trigger mode . . . . .1129
Figure 291. General-purpose timer block diagram . . . . .1178
Figure 292. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1180
Figure 293. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1180
Figure 294. Counter timing diagram, internal clock divided by 1 . . . . .1181
Figure 295. Counter timing diagram, internal clock divided by 2 . . . . .1182
Figure 296. Counter timing diagram, internal clock divided by 4 . . . . .1182
Figure 297. Counter timing diagram, internal clock divided by N. . . . .1183
Figure 298. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1183
Figure 299. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .1184
Figure 300. Counter timing diagram, internal clock divided by 1 . . . . .1185
Figure 301. Counter timing diagram, internal clock divided by 2 . . . . .1185
Figure 302. Counter timing diagram, internal clock divided by 4 . . . . .1186
Figure 303. Counter timing diagram, internal clock divided by N . . . . .1186
Figure 304. Counter timing diagram, Update event . . . . .1187
Figure 305. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .1188
Figure 306. Counter timing diagram, internal clock divided by 2 . . . . .1189
Figure 307. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .1189
Figure 308. Counter timing diagram, internal clock divided by N . . . . .1190
Figure 309. Counter timing diagram, Update event with ARPE=1 (counter underflow) . . . . .1190
Figure 310. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .1191
Figure 311. Control circuit in normal mode, internal clock divided by 1 . . . . .1192
Figure 312. TI2 external clock connection example . . . . .1192
Figure 313. Control circuit in external clock mode 1 . . . . .1193
Figure 314. External trigger input block . . . . .1194
Figure 315. Control circuit in external clock mode 2 . . . . .1195
Figure 316. Capture/Compare channel (example: channel 1 input stage) . . . . .1196
Figure 317. Capture/Compare channel 1 main circuit . . . . .1196
Figure 318. Output stage of Capture/Compare channel (channel 1) . . . . .1197
Figure 319. PWM input mode timing . . . . .1199
Figure 320. Output compare mode, toggle on OC1 . . . . .1201
Figure 321. Edge-aligned PWM waveforms (ARR=8) . . . . .1202
Figure 322. Center-aligned PWM waveforms (ARR=8) . . . . .1203
Figure 323. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1204
Figure 324. Combined PWM mode on channels 1 and 3 . . . . .1206
Figure 325. Clearing TIMx_OCxREF . . . . .1207
Figure 326. Example of one-pulse mode . . . . .1208
Figure 327. Retriggerable one-pulse mode . . . . .1210
Figure 328. Example of counter operation in encoder interface mode . . . . .1211
Figure 329. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .1212
Figure 330. Control circuit in reset mode . . . . .1213
Figure 331. Control circuit in gated mode . . . . .1214
Figure 332. Control circuit in trigger mode . . . . .1215
Figure 333. Control circuit in external clock mode 2 + trigger mode . . . . .1216
Figure 334. Master/Slave timer example . . . . .1217
Figure 335. Master/slave connection example with 1 channel only timers . . . . .1217
Figure 336. Gating TIM2 with OC1REF of TIM3 . . . . .1218
Figure 337. Gating TIM2 with Enable of TIM3 . . . . .1219
Figure 338. Triggering TIM2 with update of TIM3 . . . . .1220
Figure 339. Triggering TIM2 with Enable of TIM3 . . . . .1220
Figure 340. Triggering TIM3 and TIM2 with TIM3 TI1 input . . . . .1221
Figure 341. TIM15 block diagram . . . . .1252
Figure 342. TIM16/TIM17 block diagram . . . . .1253
Figure 343. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1255
Figure 344. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1255
Figure 345. Counter timing diagram, internal clock divided by 1 . . . . .1257
Figure 346. Counter timing diagram, internal clock divided by 2 . . . . .1257
Figure 347. Counter timing diagram, internal clock divided by 4 . . . . .1258
Figure 348. Counter timing diagram, internal clock divided by N . . . . .1258
Figure 349. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded) . . . . .		1259
Figure 350. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . .1259
Figure 351. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1261
Figure 352. Control circuit in normal mode, internal clock divided by 1 . . . . .1262
Figure 353. TI2 external clock connection example. . . . .1262
Figure 354. Control circuit in external clock mode 1 . . . . .1263
Figure 355. Capture/compare channel (example: channel 1 input stage) . . . . .1264
Figure 356. Capture/compare channel 1 main circuit . . . . .1264
Figure 357. Output stage of capture/compare channel (channel 1). . . . .1265
Figure 358. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .1265
Figure 359. PWM input mode timing . . . . .1267
Figure 360. Output compare mode, toggle on OC1 . . . . .1269
Figure 361. Edge-aligned PWM waveforms (ARR=8) . . . . .1270
Figure 362. Combined PWM mode on channel 1 and 2 . . . . .1271
Figure 363. Complementary output with dead-time insertion. . . . .1272
Figure 364. Dead-time waveforms with delay greater than the negative pulse. . . . .1272
Figure 365. Dead-time waveforms with delay greater than the positive pulse. . . . .1273
Figure 366. Break circuitry overview . . . . .1275
Figure 367. Output behavior in response to a break . . . . .1277
Figure 368. Output redirection . . . . .1279
Figure 369. 6-step generation, COM example (OSSR=1) . . . . .1280
Figure 370. Example of one pulse mode . . . . .1281
Figure 371. Retriggerable one pulse mode . . . . .1283
Figure 372. Measuring time interval between edges on 2 signals . . . . .1284
Figure 373. Control circuit in reset mode . . . . .1285
Figure 374. Control circuit in gated mode . . . . .1286
Figure 375. Control circuit in trigger mode . . . . .1287
Figure 376. Basic timer block diagram. . . . .1339
Figure 377. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1341
Figure 378. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1341
Figure 379. Counter timing diagram, internal clock divided by 1 . . . . .1342
Figure 380. Counter timing diagram, internal clock divided by 2 . . . . .1343
Figure 381. Counter timing diagram, internal clock divided by 4 . . . . .1343
Figure 382. Counter timing diagram, internal clock divided by N. . . . .1344
Figure 383. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . .		1344
Figure 384. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . .		1345
Figure 385. Control circuit in normal mode, internal clock divided by 1 . . . . .1346
Figure 386. Low-power timer block diagram . . . . .1353
Figure 387. Glitch filter timing diagram . . . . .1356
Figure 388. LPTIM output waveform, single-counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . .		1358
Figure 389. LPTIM output waveform, single-counting mode configuration
and Set-once mode activated (WAVE bit is set). . . . .		1358
Figure 390. LPTIM output waveform, Continuous counting mode configuration . . . . .1359
Figure 391. Waveform generation . . . . .1360
Figure 392. Encoder mode counting sequence . . . . .1364
Figure 393. Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1). . . . .		1365
Figure 394. IRTIM internal hardware connections with TIM16 and TIM17 . . . . .1379
Figure 395. Independent watchdog block diagram . . . . .1380
Figure 396. Watchdog block diagram . . . . .1390
Figure 397. Window watchdog timing diagram .....1391
Figure 398. RTC block diagram .....1397
Figure 399. TAMP block diagram .....1448
Figure 400. Backup registers secure protections .....1450
Figure 401. Block diagram .....1485
Figure 402. I 2 C-bus protocol .....1487
Figure 403. Setup and hold timings .....1489
Figure 404. I2C initialization flow .....1491
Figure 405. Data reception .....1492
Figure 406. Data transmission .....1493
Figure 407. Target initialization flow .....1496
Figure 408. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 .....1498
Figure 409. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 .....1499
Figure 410. Transfer bus diagrams for I2C target transmitter (mandatory events only) .....1500
Figure 411. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 .....1501
Figure 412. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 .....1502
Figure 413. Transfer bus diagrams for I2C target receiver
(mandatory events only) .....		1502
Figure 414. Controller clock generation .....1504
Figure 415. Controller initialization flow .....1506
Figure 416. 10-bit address read access with HEAD10R = 0 .....1506
Figure 417. 10-bit address read access with HEAD10R = 1 .....1507
Figure 418. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes .....1508
Figure 419. Transfer sequence flow for I2C controller transmitter, N > 255 bytes .....1509
Figure 420. Transfer bus diagrams for I2C controller transmitter
(mandatory events only) .....		1510
Figure 421. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes .....1512
Figure 422. Transfer sequence flow for I2C controller receiver, N > 255 bytes .....1513
Figure 423. Transfer bus diagrams for I2C controller receiver
(mandatory events only) .....		1514
Figure 424. Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) .....1518
Figure 425. Transfer sequence flow for SMBus target transmitter N bytes + PEC .....1522
Figure 426. Transfer bus diagram for SMBus target transmitter (SBC = 1) .....1522
Figure 427. Transfer sequence flow for SMBus target receiver N bytes + PEC .....1524
Figure 428. Bus transfer diagrams for SMBus target receiver (SBC = 1) .....1525
Figure 429. Bus transfer diagrams for SMBus controller transmitter .....1526
Figure 430. Bus transfer diagrams for SMBus controller receiver .....1528
Figure 431. USART block diagram .....1552
Figure 432. Word length programming .....1555
Figure 433. Configurable stop bits .....1557
Figure 434. TC/TXE behavior when transmitting .....1560
Figure 435. Start bit detection when oversampling by 16 or 8 .....1561
Figure 436. usart_ker_ck clock divider block diagram .....1564
Figure 437. Data sampling when oversampling by 16 .....1565
Figure 438. Data sampling when oversampling by 8 .....1566
Figure 439. Mute mode using Idle line detection .....1573
Figure 440. Mute mode using address mark detection .....1574
Figure 441. Break detection in LIN mode (11-bit break length - LBDL bit is set) .....1577
Figure 442. Break detection in LIN mode vs. Framing error detection .....1578
Figure 443. USART example of synchronous master transmission .....1579
Figure 444. USART data clock timing diagram in synchronous master mode
(M bits = 00) .....		1579
Figure 445. USART data clock timing diagram in synchronous master mode (M bits = 01) . . . . .1580
Figure 446. USART data clock timing diagram in synchronous slave mode (M bits = 00) . . . . .1581
Figure 447. ISO 7816-3 asynchronous protocol . . . . .1583
Figure 448. Parity error detection using the 1.5 stop bits . . . . .1585
Figure 449. IrDA SIR ENDEC block diagram. . . . .1589
Figure 450. IrDA data modulation (3/16) - normal mode . . . . .1589
Figure 451. Transmission using DMA . . . . .1591
Figure 452. Reception using DMA . . . . .1592
Figure 453. Hardware flow control between 2 USARTs . . . . .1592
Figure 454. RS232 RTS flow control . . . . .1593
Figure 455. RS232 CTS flow control . . . . .1594
Figure 456. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .1597
Figure 457. Wake-up event not verified (wake-up event = address match, FIFO disabled) . . . . .1597
Figure 458. LPUART block diagram . . . . .1638
Figure 459. LPUART word length programming . . . . .1641
Figure 460. Configurable stop bits . . . . .1643
Figure 461. TC/TXE behavior when transmitting . . . . .1645
Figure 462. lpuart_ker_ck clock divider block diagram . . . . .1648
Figure 463. Mute mode using Idle line detection . . . . .1652
Figure 464. Mute mode using address mark detection . . . . .1653
Figure 465. Transmission using DMA . . . . .1655
Figure 466. Reception using DMA . . . . .1656
Figure 467. Hardware flow control between 2 LPUARTs . . . . .1657
Figure 468. RS232 RTS flow control . . . . .1657
Figure 469. RS232 CTS flow control . . . . .1658
Figure 470. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .1661
Figure 471. Wake-up event not verified (wake-up event = address match, FIFO disabled) . . . . .1661
Figure 472. SPI block diagram. . . . .1689
Figure 473. Full-duplex single master/ single slave application. . . . .1690
Figure 474. Half-duplex single master/ single slave application . . . . .1691
Figure 475. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . .1692
Figure 476. Master and three independent slaves. . . . .1693
Figure 477. Multimaster application . . . . .1694
Figure 478. Hardware/software slave select management . . . . .1695
Figure 479. Data clock timing diagram . . . . .1696
Figure 480. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .1697
Figure 481. Packing data in FIFO for transmission and reception. . . . .1701
Figure 482. Master full-duplex communication . . . . .1704
Figure 483. Slave full-duplex communication . . . . .1705
Figure 484. Master full-duplex communication with CRC . . . . .1706
Figure 485. Master full-duplex communication in packed mode . . . . .1707
Figure 486. NSSP pulse generation in Motorola SPI master mode. . . . .1710
Figure 487. TI mode transfer . . . . .1711
Figure 488. SAI functional block diagram . . . . .1725
Figure 489. Audio frame . . . . .1729
Figure 490. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .1731
Figure 491. FS role is start of frame (FSDEF = 0) . . . . .1732
Figure 492. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .1733
Figure 493. First bit offset . . . . .1733
Figure 494. Audio block clock generator overview . . . . .1735
Figure 495. PDM typical connection and timing . . . . .1739
Figure 496. Detailed PDM interface block diagram . . . . .1740
Figure 497. Start-up sequence . . . . .1741
Figure 498. SAI_ADR format in TDM mode, 32-bit slot width . . . . .1742
Figure 499. SAI_ADR format in TDM mode, 16-bit slot width . . . . .1743
Figure 500. SAI_ADR format in TDM mode, 8-bit slot width . . . . .1744
Figure 501. AC'97 audio frame . . . . .1747
Figure 502. Example of typical AC'97 configuration on devices featuring at least
two embedded SAIs (three external AC'97 decoders) . . . . .		1748
Figure 503. SPDIF format . . . . .1749
Figure 504. SAI_xDR register ordering . . . . .1750
Figure 505. Data companding hardware in an audio block in the SAI . . . . .1753
Figure 506. Tristate strategy on SD output line on an inactive slot . . . . .1755
Figure 507. Tristate on output data line in a protocol like I2S . . . . .1756
Figure 508. Overrun detection error . . . . .1757
Figure 509. FIFO underrun event . . . . .1757
Figure 510. SDMMC “no response” and “no data” operations . . . . .1792
Figure 511. SDMMC (multiple) block read operation . . . . .1792
Figure 512. SDMMC (multiple) block write operation . . . . .1792
Figure 513. SDMMC (sequential) stream read operation . . . . .1793
Figure 514. SDMMC (sequential) stream write operation . . . . .1793
Figure 515. SDMMC block diagram . . . . .1794
Figure 516. SDMMC Command and data phase relation . . . . .1796
Figure 517. Control unit . . . . .1798
Figure 518. Command/response path . . . . .1799
Figure 519. Command path state machine (CPSM) . . . . .1800
Figure 520. Data path . . . . .1806
Figure 521. DDR mode data packet clocking . . . . .1807
Figure 522. DDR mode CRC status / boot acknowledgment clocking . . . . .1807
Figure 523. Data path state machine (DPSM) . . . . .1808
Figure 524. CLKMUX unit . . . . .1819
Figure 525. Asynchronous interrupt generation . . . . .1823
Figure 526. Synchronous interrupt period data read . . . . .1823
Figure 527. Synchronous interrupt period data write . . . . .1824
Figure 528. Asynchronous interrupt period data read . . . . .1825
Figure 529. Asynchronous interrupt period data write . . . . .1825
Figure 530. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25 . . . . .1828
Figure 531. Clock stop with SDMMC_CK for DDR50, SDR50 . . . . .1828
Figure 532. Read Wait with SDMMC_CK < 50 MHz . . . . .1829
Figure 533. Read Wait with SDMMC_CK > 50 MHz . . . . .1830
Figure 534. CMD12 stream timing . . . . .1832
Figure 535. CMD5 Sleep Awake procedure . . . . .1834
Figure 536. Normal boot mode operation . . . . .1836
Figure 537. Alternative boot mode operation . . . . .1837
Figure 538. Command response R1b busy signaling . . . . .1838
Figure 539. SDMMC state control . . . . .1839
Figure 540. Card cycle power / power up diagram . . . . .1840
Figure 541. CMD11 signal voltage switch sequence . . . . .1841
Figure 542. Voltage switch transceiver typical application. . . . .1843
Figure 543. CAN subsystem. . . . .1870
Figure 544. FDCAN block diagram . . . . .1872
Figure 545. Bit timing . . . . .1874
Figure 546. Transceiver delay measurement . . . . .1879
Figure 547. Pin control in bus monitoring mode . . . . .1880
Figure 548. Pin control in loop-back mode . . . . .1883
Figure 549. CAN error state diagram. . . . .1884
Figure 550. Message RAM configuration. . . . .1885
Figure 551. Standard message ID filter path . . . . .1888
Figure 552. Extended message ID filter path. . . . .1889
Figure 553. USB peripheral block diagram . . . . .1936
Figure 554. Packet buffer areas with examples of buffer description table locations . . . . .1940
Figure 555. UCPD block diagram . . . . .1970
Figure 556. Clock division and timing elements. . . . .1971
Figure 557. K-code transmission . . . . .1974
Figure 558. Transmit order for various sizes of data . . . . .1975
Figure 559. Packet format . . . . .1976
Figure 560. Line format of Hard Reset. . . . .1976
Figure 561. Line format of Cable Reset. . . . .1977
Figure 562. BIST test data frame. . . . .1978
Figure 563. BIST Carrier Mode 2 frame. . . . .1978
Figure 564. UCPD BMC transmitter architecture. . . . .1979
Figure 565. UCPD BMC receiver architecture . . . . .1980
Figure 566. Block diagram of debug support infrastructure. . . . .2007
Figure 567. JTAG TAP state machine . . . . .2011
Figure 568. CoreSight topology . . . . .2031
Figure 569. Trace port interface unit (TPIU) . . . . .2114
Figure 570. Embedded cross trigger . . . . .2127

Chapters