44. Revision history

Table 293. Document revision history

Date	Revision	Changes
15-Jan-2018	1	Initial release.
12-Apr-2018	2	Updated document title, Introduction and Related documents . Updated Figure 1: System architecture and Figure 2: Memory map . Updated Table 1: Memory map and peripheral register boundary addresses . Updated Section 2.1.4: S3: CPU2 (Cortex®-M0+) S-bus, CPU1 physical remap and Section 2.33: CPU2 boot , and added Section 2.34: CPU2 SRAM fetch disable . Updated Section 3.3.4: Read access latency , Section 3.3.8: Flash main memory programming sequences , Standard programming , Fast programming , Programming errors signaled by flags , PGSERR and PGAERR in a page-based row programming , User and read protection option bytes , Secure SRAM2 start address and CPU2 reset vector option bytes , Option byte loading , Section 3.5: FLASH UID64 , Changing the Read protection level , Section 3.6.4: CPU2 security (ESE) , CPU2 secure SRAM2 areas , Section 3.10.1: Flash memory access control register (FLASH_ACR) , Section 3.10.4: Flash memory status register (FLASH_SR) , Section 3.10.5: Flash memory control register (FLASH_CR) , Section 3.10.7: Flash memory option register (FLASH_OPTR) , Section 3.10.19: Flash memory secure SRAM2 start address and CPU2 reset vector register (FLASH_SRRVR) and Section 3.10.16: Flash memory CPU2 status register (FLASH_C2SR) . Added Programming errors causing a bus error and PGSERR and PGAERR in a page-based row programming . Updated Table 4: Number of wait states vs, Flash memory clock (HCLK4) frequency , Table 9: Option bytes organization , Table 13: RDP regression from Level 1 to Level 0 and memory erase and Table 18: Flash interface register map and reset values . Updated Section 25.4.2: CRC independent data register (CRC_IDR) and Section Table 20.: CRC register map and reset values Updated Section 6.1: Power supplies , Section 6.4: Low-power modes , Section : Entering Low-power run mode , Section 6.6.3: PWR control register 3 (PWR_CR3) , Section 6.6.5: PWR status register 1 (PWR_SR1) , Section 6.6.7: PWR status clear register (PWR_SCR) , Section 6.6.8: PWR control register 5 (PWR_CR5) , Section 6.6.21: PWR CPU2 control register 1 (PWR_C2CR1) and Section 6.6.22: PWR CPU2 control register 3 (PWR_C2CR3) . Updated Table 24: Low-power mode summary , Table 30: Stop0 mode , Table 31: Stop1 mode , Table 32: Stop2 mode , Table 33: Standby mode , Table 34: Shutdown mode and Table 35: PWR register map and reset values . Updated Figure 7: Power supply overview and Figure 8: Supply configurations . Updated Table 37: Peripherals interconnect matrix and Section 7.4.1: From timer (TIM1/TIM2/TIM17) to timer (TIM1/TIM2) .

Date

Revision

Changes

15-Jan-2018

Initial release.

12-Apr-2018

Updated document title, Introduction and Related documents .

Updated Figure 1: System architecture and Figure 2: Memory map .

Updated Table 1: Memory map and peripheral register boundary addresses .

Updated Section 2.1.4: S3: CPU2 (Cortex®-M0+) S-bus, CPU1 physical remap and Section 2.33: CPU2 boot , and added Section 2.34: CPU2 SRAM fetch disable .

Updated Section 3.3.4: Read access latency , Section 3.3.8: Flash main memory programming sequences , Standard programming , Fast programming , Programming errors signaled by flags , PGSERR and PGAERR in a page-based row programming , User and read protection option bytes , Secure SRAM2 start address and CPU2 reset vector option bytes , Option byte loading , Section 3.5: FLASH UID64 , Changing the Read protection level , Section 3.6.4: CPU2 security (ESE) , CPU2 secure SRAM2 areas , Section 3.10.1: Flash memory access control register (FLASH_ACR) , Section 3.10.4: Flash memory status register (FLASH_SR) , Section 3.10.5: Flash memory control register (FLASH_CR) , Section 3.10.7: Flash memory option register (FLASH_OPTR) , Section 3.10.19: Flash memory secure SRAM2 start address and CPU2 reset vector register (FLASH_SRRVR) and Section 3.10.16: Flash memory CPU2 status register (FLASH_C2SR) .

Added Programming errors causing a bus error and PGSERR and PGAERR in a page-based row programming .

Updated Table 4: Number of wait states vs, Flash memory clock (HCLK4) frequency , Table 9: Option bytes organization , Table 13: RDP regression from Level 1 to Level 0 and memory erase and Table 18: Flash interface register map and reset values .

Updated Section 25.4.2: CRC independent data register (CRC_IDR) and Section Table 20.: CRC register map and reset values

Updated Section 6.1: Power supplies , Section 6.4: Low-power modes , Section : Entering Low-power run mode , Section 6.6.3: PWR control register 3 (PWR_CR3) , Section 6.6.5: PWR status register 1 (PWR_SR1) , Section 6.6.7: PWR status clear register (PWR_SCR) , Section 6.6.8: PWR control register 5 (PWR_CR5) , Section 6.6.21: PWR CPU2 control register 1 (PWR_C2CR1) and Section 6.6.22: PWR CPU2 control register 3 (PWR_C2CR3) .

Updated Table 24: Low-power mode summary , Table 30: Stop0 mode , Table 31: Stop1 mode , Table 32: Stop2 mode , Table 33: Standby mode , Table 34: Shutdown mode and Table 35: PWR register map and reset values .

Updated Figure 7: Power supply overview and Figure 8: Supply configurations .

Updated Table 37: Peripherals interconnect matrix and Section 7.4.1: From timer (TIM1/TIM2/TIM17) to timer (TIM1/TIM2) .

Table 293. Document revision history (continued)

Date	Revision	Changes
12-Apr-2018	2 (cont'd)	Updated Figure 14: Clock tree . Updated Table 34: Maximum clock source frequency , Table 35: SMPS step-down converter clock source selection and division and Table 38: RCC register map and reset values . Updated Section 6.2.5: PLLs , Section 6.2.8: LSI2 clock , Section 6.2.9: System clock (SYSCLK) selection , Section 6.2.13: LSI source selection , Section 6.2.20: Clock-out capability , Section 6.2.22: Peripheral clocks enable , Section 6.3: Low-power modes , Section 6.4.1: RCC clock control register (RCC_CR) , Section 6.4.9: RCC SMPS step-down converter control register (RCC_SMPSCR) , Section 6.4.16: RCC APB3 peripheral reset register (RCC_APB3RSTR) , Section 6.4.19: RCC AHB3 and AHB4 peripheral clock enable register (RCC_AHB3ENR) , Section 6.4.22: RCC APB2 peripheral clock enable register (RCC_APB2ENR) , Section 6.4.29: RCC peripherals independent clock configuration register (RCC_CCIPR) , Section 6.4.31: RCC control/status register (RCC_CSR) , Section 6.4.34: RCC extended clock recovery register (RCC_EXTCFGR) , Section 6.4.35: RCC CPU2 AHB1 peripheral clock enable register (RCC_C2AHB1ENR) , Section 6.4.37: RCC CPU2 AHB3 and AHB4 peripheral clock enable register (RCC_C2AHB3ENR) , Section 6.4.41: RCC CPU2 APB3 peripheral clock enable register (RCC_C2APB3ENR) , Section 6.4.42: RCC CPU2 AHB1 peripheral clocks enable in Sleep modes register (RCC_C2AHB1SMENR) and Section 6.4.48: RCC CPU2 APB3 peripheral clock enable in Sleep mode register (RCC_C2APB3SMENR) . Updated Section 11.3.1: General-purpose I/O (GPIO) , Section 11.3.2: I/O pin alternate function multiplexer and mapping , Section 11.4.1: GPIO port mode register (GPIOx_MODER) ( x = A to H, J, K ) and sections from 11.4.4 to 8.4.11. Updated Section 11.1: SYSCFG main features , Section 10.2.7: SYSCFG SRAM2 control and status register (SYSCFG_SCSR) , Section 10.2.16: SYSCFG secure IP control register (SYSCFG_SIPCR) and Table 54: SYSCFG register map and reset values . Updated Table 72: CPU1 vector table , Table 73: CPU2 vector table and Table 74: Wake-up interrupt table . Updated title of Section 16: Extended interrupt and event controller (EXTI) , Section 16.4: EXTI functional description , sections 16.6.1 to 16.6.8, and replaced former sections 12.5.9 to 12.5.12 with new sections 16.6.9 to 16.6.16. Updated Table 81: EXTI register map and reset values and Table 74: Wake-up interrupt table . Removed former sections 14.5.13 to 14.5.18. Updated Section 18.1: Introduction , Section 18.2: QUADSPI main features , Section 18.3.2: QUADSPI pins , Section 18.3.8: QUADSPI flash memory configuration , Section 18.3.10: QUADSPI configuration , Section 18.3.15: NCS behavior , Section 18.5.1: QUADSPI control register (QUADSPI_CR) and Section 18.5.6: QUADSPI communication configuration register (QUADSPI_CCR) Updated Table 84: QUADSPI pins and Table 86: QUADSPI register map and reset values . Removed former Dual-flash mode and former sections 23.7.5 to 23.7.7.

Date

Revision

Changes

12-Apr-2018

2
(cont'd)

Updated Figure 14: Clock tree .

Updated Table 34: Maximum clock source frequency , Table 35: SMPS step-down converter clock source selection and division and Table 38: RCC register map and reset values .

Updated Section 6.2.5: PLLs , Section 6.2.8: LSI2 clock , Section 6.2.9: System clock (SYSCLK) selection , Section 6.2.13: LSI source selection , Section 6.2.20: Clock-out capability , Section 6.2.22: Peripheral clocks enable , Section 6.3: Low-power modes , Section 6.4.1: RCC clock control register (RCC_CR) , Section 6.4.9: RCC SMPS step-down converter control register (RCC_SMPSCR) , Section 6.4.16: RCC APB3 peripheral reset register (RCC_APB3RSTR) , Section 6.4.19: RCC AHB3 and AHB4 peripheral clock enable register (RCC_AHB3ENR) , Section 6.4.22: RCC APB2 peripheral clock enable register (RCC_APB2ENR) , Section 6.4.29: RCC peripherals independent clock configuration register (RCC_CCIPR) , Section 6.4.31: RCC control/status register (RCC_CSR) , Section 6.4.34: RCC extended clock recovery register (RCC_EXTCFGR) , Section 6.4.35: RCC CPU2 AHB1 peripheral clock enable register (RCC_C2AHB1ENR) , Section 6.4.37: RCC CPU2 AHB3 and AHB4 peripheral clock enable register (RCC_C2AHB3ENR) , Section 6.4.41: RCC CPU2 APB3 peripheral clock enable register (RCC_C2APB3ENR) , Section 6.4.42: RCC CPU2 AHB1 peripheral clocks enable in Sleep modes register (RCC_C2AHB1SMENR) and Section 6.4.48: RCC CPU2 APB3 peripheral clock enable in Sleep mode register (RCC_C2APB3SMENR) .

Updated Section 11.3.1: General-purpose I/O (GPIO) , Section 11.3.2: I/O pin alternate function multiplexer and mapping , Section 11.4.1: GPIO port mode register (GPIOx_MODER) ( x = A to H, J, K ) and sections from 11.4.4 to 8.4.11.

Updated Section 11.1: SYSCFG main features , Section 10.2.7: SYSCFG SRAM2 control and status register (SYSCFG_SCSR) , Section 10.2.16: SYSCFG secure IP control register (SYSCFG_SIPCR) and Table 54: SYSCFG register map and reset values .

Updated Table 72: CPU1 vector table , Table 73: CPU2 vector table and Table 74: Wake-up interrupt table .

Updated title of Section 16: Extended interrupt and event controller (EXTI) , Section 16.4: EXTI functional description , sections 16.6.1 to 16.6.8, and replaced former sections 12.5.9 to 12.5.12 with new sections 16.6.9 to 16.6.16.

Updated Table 81: EXTI register map and reset values and Table 74: Wake-up interrupt table .

Removed former sections 14.5.13 to 14.5.18.

Updated Section 18.1: Introduction , Section 18.2: QUADSPI main features , Section 18.3.2: QUADSPI pins , Section 18.3.8: QUADSPI flash memory configuration , Section 18.3.10: QUADSPI configuration , Section 18.3.15: NCS behavior , Section 18.5.1: QUADSPI control register (QUADSPI_CR) and Section 18.5.6: QUADSPI communication configuration register (QUADSPI_CCR)

Updated Table 84: QUADSPI pins and Table 86: QUADSPI register map and reset values .

Removed former Dual-flash mode and former sections 23.7.5 to 23.7.7.

Table 293. Document revision history (continued)

Date	Revision	Changes
12-Apr-2018	2 (cont'd)	Updated Section 21.7.5: ADC configuration register 2 (ADC_CFGR2) . Updated Figure 93: ADC block diagram and Figure 103: Stopping ongoing regular conversions . Updated RSA encryption/decryption principle and Table 276: PKA register map and reset values . Updated Section 201.3.29: Debug mode . Updated notes in Using one timer to start another timer and in TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5, 23, 24) . Updated Section 58.4.5: How to program the watchdog timeout , Section 58.6.2: WWDG configuration register (WWDG_CFR) and Table 709: WWDG register map and reset values . Updated Selecting the clock source and the appropriate oversampling method , Section 54.7.4: LPUART control register 3 (LPUART_CR3) , sections 54.7.7 to 54.7.12 and Table 178: USART interrupt requests . Updated Frame length , Section 66.4.8: SAI clock generator and its subsections , Wrong clock configuration in master mode (with NODIV = 0) , and made two different sections for similar registers in Section 66.6: SAI registers . Updated Table 801: Clock generator programming examples and Table 807: SAI interrupt sources . Updated Table 167: IPCC register map and reset values . Removed former sections 37.4.9 to 38.4.13. Updated Table 164: HSEM register map and reset values . Removed former sections 38.4.9 to 38.4.13. Removed former sections 38.4.9 to 38.4.13. Updated Figure 81: CRS block diagram . Updated Section 41.4.1: JTAG debug port , Section 41.5: Access ports , Section 41.8: Microcontroller debug unit (DBGMCU) , Section 41.8.1: DBGMCU identity code register (DBGMCU_IDCODE) and Section 41.8.2: DBGMCU configuration register (DBGMCU_CR) . Updated Table 278: DBGMCU register map and reset values .
08-Jan-2019	3	Updated Table 1: Memory map and peripheral register boundary addresses . Updated Secure system flash memory programming , Section 3.3.7: Flash main memory erase sequences , Flash memory mass erase , Section 3.3.8: Flash main memory programming sequences , User and read protection option bytes , Secure flash memory start address option bytes , Secure SRAM2 start address and CPU2 reset vector option bytes , Secure user options , WRP Area A address option bytes , WRP Area B address option bytes , Changing the CPU2 security mode, Level 2: No debug , Changing the Read protection level , Section 3.6.4: CPU2 security (ESE) , CPU2 secure SRAM2 areas , CPU2 debug access , Section 3.10.5: Flash memory control register (FLASH_CR) , Section 3.10.7: Flash memory option register (FLASH_OPTR) , Section 3.10.18: Secure flash memory start address register (FLASH_SFR) , Section 3.10.19: Flash memory secure SRAM2 start address and CPU2 reset vector register (FLASH_SRRVR) and Section 3.10.17: Flash memory CPU2 control register (FLASH_C2CR) . Added Section 3.9: Register access protection .

Table 293. Document revision history (continued)

Date	Revision	Changes
08-Jan-2019	3 (cont'd)	Updated Table 3: Flash memory - Single bank organization , Table 5: Page erase overview , Table 6: Mass erase overview , Table 8: Option bytes format , Table 9: Option bytes organization , Table 13: RDP regression from Level 1 to Level 0 and memory erase and Table 18: Flash interface register map and reset values . Updated titles of sections 25.4.1 to 25.4.5. Updated Section 6.1.1: Independent analog peripherals supply , Section 6.4: Low-power modes , Section 6.6.3: PWR control register 3 (PWR_CR3) , Section 6.6.5: PWR status register 1 (PWR_SR1) , sections 6.6.8 to 6.6.20, 6.6.22 and 6.6.23. Updated Table 23: Sub-system low power wake-up sources , Table 24: Low-power mode summary and Table 25: Functionalities depending on system operating mode . Updated Table 37: Peripherals interconnect matrix . Updated Section 8.2: Clocks , Section 8.2.8: LSI2 clock, LSI2 trimming parameter , Section 8.2.20: Clock-out capability , Section 8.3: Low-power modes , Section 8.4.1: RCC clock control register (RCC_CR) and Section 8.4.31: RCC control/status register (RCC_CSR) . Updated Table 40: Peripheral clock enable , Table 42: RCC register map and reset values and added Table 41: Single core Low power debug configurations . Updated Section 10.2.16: SYSCFG secure IP control register (SYSCFG_SIPCR) . Updated Section 17.4.3: DMAMUX channels , Section 17.4.3: DMAMUX channels, Synchronization overrun and interrupt, Trigger overrun and interrupt , Section 12.6.1: DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR) , Section 12.6.3: DMAMUX request line multiplexer interrupt clear flag register (DMAMUX_CFR) and Section 12.6.6: DMAMUX request generator interrupt clear flag register (DMAMUX_RGCFR) . Updated Figure 89: DMAMUX block diagram . Replaced AIEC with EXTI in Section 13: Nested vectored interrupt controller (NVIC) . and ID with CoreID in Section 14: Hardware semaphore (HSEM) . Updated Table 61: CPU1 vector table and Table 62: CPU2 vector table . Updated Section 12.2: QUADSPI main features, FIFO and data management , Section 12.3.10: QUADSPI configuration , Section 12.3.11: QUADSPI use , Section 12.5.1: QUADSPI control register (QUADSPI_CR) , Section 12.5.3: QUADSPI status register (QUADSPI_SR) and Section 12.5.6: QUADSPI communication configuration register (QUADSPI_CCR) . Updated Table 83: QUADSPI register map and reset values .

Date

Revision

Changes

08-Jan-2019

3
(cont'd)

Updated Table 3: Flash memory - Single bank organization , Table 5: Page erase overview , Table 6: Mass erase overview , Table 8: Option bytes format , Table 9: Option bytes organization , Table 13: RDP regression from Level 1 to Level 0 and memory erase and Table 18: Flash interface register map and reset values .

Updated titles of sections 25.4.1 to 25.4.5.

Updated Section 6.1.1: Independent analog peripherals supply , Section 6.4: Low-power modes , Section 6.6.3: PWR control register 3 (PWR_CR3) , Section 6.6.5: PWR status register 1 (PWR_SR1) , sections 6.6.8 to 6.6.20, 6.6.22 and 6.6.23.

Updated Table 23: Sub-system low power wake-up sources , Table 24: Low-power mode summary and Table 25: Functionalities depending on system operating mode .

Updated Table 37: Peripherals interconnect matrix .

Updated Section 8.2: Clocks , Section 8.2.8: LSI2 clock, LSI2 trimming parameter , Section 8.2.20: Clock-out capability , Section 8.3: Low-power modes , Section 8.4.1: RCC clock control register (RCC_CR) and Section 8.4.31: RCC control/status register (RCC_CSR) .

Updated Table 40: Peripheral clock enable , Table 42: RCC register map and reset values and added Table 41: Single core Low power debug configurations .

Updated Section 10.2.16: SYSCFG secure IP control register (SYSCFG_SIPCR) .

Updated Section 17.4.3: DMAMUX channels , Section 17.4.3: DMAMUX channels, Synchronization overrun and interrupt, Trigger overrun and interrupt , Section 12.6.1: DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR) , Section 12.6.3: DMAMUX request line multiplexer interrupt clear flag register (DMAMUX_CFR) and Section 12.6.6: DMAMUX request generator interrupt clear flag register (DMAMUX_RGCFR) .

Updated Figure 89: DMAMUX block diagram .

Replaced AIEC with EXTI in Section 13: Nested vectored interrupt controller (NVIC) . and ID with CoreID in Section 14: Hardware semaphore (HSEM) .

Updated Table 61: CPU1 vector table and Table 62: CPU2 vector table .

Updated Section 12.2: QUADSPI main features, FIFO and data management , Section 12.3.10: QUADSPI configuration , Section 12.3.11: QUADSPI use , Section 12.5.1: QUADSPI control register (QUADSPI_CR) , Section 12.5.3: QUADSPI status register (QUADSPI_SR) and Section 12.5.6: QUADSPI communication configuration register (QUADSPI_CCR) .

Updated Table 83: QUADSPI register map and reset values .

Table 293. Document revision history (continued)

Date	Revision	Changes
08-Jan-2019	3 (cont'd)	Updated Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN), Section 21.4.7: Single-ended and differential input channels, Section 21.4.8: Calibration (ADCAL, ADCALDIF, ADC_CALFACT), Section 21.4.10: Constraints when writing the ADC control bits, Section 21.4.11: Channel selection (ADC_SQRY, ADC_JSQR) and Section 21.4.12: Channel-wise programmable sampling time (SMPR1, SMPR2). Updated Table 165: ADC internal input/output signals and Figure 95: ADC1 connectivity. Updated Section 35.1: RNG introduction, Section 35.2: RNG main features and Health checks. Updated Montgomery space and fast mode operations, RSA encryption/decryption principle, Executing a PKA operation, Using precomputed Montgomery parameters (PKA fast mode), Section 32.3.7: PKA error management, Extended ECDSA support, Section 32.5.1: Supported elliptic curves, Section 32.7.1: PKA control register (PKA_CR), Section 32.7.2: PKA status register (PKA_SR), Section 32.7.3: PKA clear flag register (PKA_CLRFR) and Section 32.7.4: PKA RAM. Updated Table 248: Modular addition, Table 249: Modular subtraction, Table 250: Montgomery multiplication, Table 254: Modular reduction, Table 255: Arithmetic addition, Table 256: Arithmetic subtraction, Table 257: Arithmetic multiplication, Table 258: Arithmetic comparison, Table 175: ECC curves parameters, Table 269: Modular exponentiation computation times, Table 270: ECC scalar multiplication computation times, Table 271: ECDSA signature average computation times, Table 272: ECDSA verification average computation times and Table 276: PKA register map and reset values. Replaced BKEx, BKPx by BKE, BK2E, BKP, BK2P and split registers CCMR1 and CCMR2 in Section 201: Advanced-control timers (TIM1/TIM8). Updated Section 201.3.16: Using the break function. Updated Figure 201: Advanced-control timer block diagram and Figure 249: Output redirection. Updated Section 221.5.24: Debug mode and Section 221.7.6: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 16 to 17). Updated Table 1053: TIM16/TIM17 register map and reset values. Updated Figure 275: Output redirection. Updated Section 24.2: RTC main features and Section 24.7.20: RTC backup registers (RTC_BKPxR). Updated Table 81: RTC register map and reset values. Added Section 49.3.4: Low-power freeze. Updated Section 49.3.1: IWDG block diagram and Section 49.4.2: IWDG prescaler register (IWDG_PR). Removed former Section 49.3.6: Behavior in Stop and Standby modes. Updated Table 354: IWDG register map and reset values. Updated Section 14.3.8: Semaphore attributes and Sections 14.4.1 to 14.4.7. Added Table 244: Authorized AHB bus master IDs and updated Table 164: HSEM register map and reset values.

Date

Revision

Changes

08-Jan-2019

3
(cont'd)

Updated Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN), Section 21.4.7: Single-ended and differential input channels, Section 21.4.8: Calibration (ADCAL, ADCALDIF, ADC_CALFACT), Section 21.4.10: Constraints when writing the ADC control bits, Section 21.4.11: Channel selection (ADC_SQRY, ADC_JSQR) and Section 21.4.12: Channel-wise programmable sampling time (SMPR1, SMPR2).

Updated Table 165: ADC internal input/output signals and Figure 95: ADC1 connectivity.

Updated Section 35.1: RNG introduction, Section 35.2: RNG main features and Health checks.

Updated Montgomery space and fast mode operations, RSA encryption/decryption principle, Executing a PKA operation, Using precomputed Montgomery parameters (PKA fast mode), Section 32.3.7: PKA error management, Extended ECDSA support, Section 32.5.1: Supported elliptic curves, Section 32.7.1: PKA control register (PKA_CR), Section 32.7.2: PKA status register (PKA_SR), Section 32.7.3: PKA clear flag register (PKA_CLRFR) and Section 32.7.4: PKA RAM.

Updated Table 248: Modular addition, Table 249: Modular subtraction, Table 250: Montgomery multiplication, Table 254: Modular reduction, Table 255: Arithmetic addition, Table 256: Arithmetic subtraction, Table 257: Arithmetic multiplication, Table 258: Arithmetic comparison, Table 175: ECC curves parameters, Table 269: Modular exponentiation computation times, Table 270: ECC scalar multiplication computation times, Table 271: ECDSA signature average computation times, Table 272: ECDSA verification average computation times and Table 276: PKA register map and reset values.

Replaced BKEx, BKPx by BKE, BK2E, BKP, BK2P and split registers CCMR1 and CCMR2 in Section 201: Advanced-control timers (TIM1/TIM8).

Updated Section 201.3.16: Using the break function.

Updated Figure 201: Advanced-control timer block diagram and Figure 249: Output redirection.

Updated Section 221.5.24: Debug mode and Section 221.7.6: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 16 to 17).

Updated Table 1053: TIM16/TIM17 register map and reset values.

Updated Figure 275: Output redirection.

Updated Section 24.2: RTC main features and Section 24.7.20: RTC backup registers (RTC_BKPxR).

Updated Table 81: RTC register map and reset values.

Added Section 49.3.4: Low-power freeze.

Updated Section 49.3.1: IWDG block diagram and Section 49.4.2: IWDG prescaler register (IWDG_PR).

Removed former Section 49.3.6: Behavior in Stop and Standby modes.

Updated Table 354: IWDG register map and reset values.

Updated Section 14.3.8: Semaphore attributes and Sections 14.4.1 to 14.4.7.

Added Table 244: Authorized AHB bus master IDs and updated Table 164: HSEM register map and reset values.

Table 293. Document revision history (continued)

Date	Revision	Changes
08-Jan-2019	3 (cont'd)	Updated Section 41.1: Introduction , Section 41.4.8: DP target identification register (DP_TARGETIDR) , Section 41.7: Cross trigger interface registers , Section 41.8.1: DBGMCU identity code register (DBGMCU_IDCODE) , Section 41.10.14: DWT CoreSight peripheral identity register 1 (DWT_PIDR1) and Section 41.14.14: DWT CoreSight peripheral identity register 1 (DWT_PIDR1) . Updated Table 271: Debug port register map and reset values and Table 278: DBGMCU register map and reset values . Removed former Section 32.11: CPU2 Instrumentation Trace Macrocell (ITM) and its subsections. Updated Section 42.1: Unique device ID register (96 bits)
01-Mar-2019	4	Changed document classification, from ST restricted to Public. Updated Section 8.3: Low-power modes , Channel configuration procedure , Channel state and disabling a channel , Section 32.1: RNG introduction , Section 32.2: RNG main features , Section 32.3.3: Random number generation and its subsections , Section 32.3.4: RNG initialization , Section 32.3.5: RNG operation and its subsections , Section 32.3.6: RNG clocking , Section 32.3.7: Error management , Section 32.3.8: The RNG low-power use , Section 32.6.1: Introduction , Section 21.7: RNG registers , Section 32.7.2: RNG status register (RNG_SR) , Section 32.7.3: RNG data register (RNG_DR) , sections 39.4.7 to 210.4.24, 41.6.6 and 41.6.7, Section 49.5.4: USART FIFOs and thresholds , Section 54.4.4: LPUART FIFOs and thresholds and Section 50.4.14: SPDIF output . Updated Table 63: Wake-up interrupt table , Table 362: TIM2/TIM3/TIM4/TIM5 register map and reset values and Table 260: STM32WB55xx SPI implementation . Updated Figure 272: RNG block diagram , Figure 273: Entropy source model and Figure 577: Reception using DMA . Added Figure 274: RNG initialization overview and footnote to Figure 481: Packing data in FIFO for transmission and reception .
13-Feb-2020	5	Updated Section 2.1: System architecture , Section 3.5: FLASH UID64 , Section 3.6.4: CPU2 security (ESE) , Section 6.4.12: Auto wake-up from Low-power mode , Section 6.6.8: PWR control register 5 (PWR_CR5) , Section 7.4.7: From USB to timer (TIM2) , Software reset , Section 8.2: Clocks , External source , Section 8.2.2: HSI16 clock , Section 8.2.3: MSI clock , Section 8.2.5: PLLs , Section 8.2.8: LSI2 clock , Section 8.4.1: RCC clock control register (RCC_CR) , Section 8.4.4: RCC PLL configuration register (RCC_PLLCFGR) , Section 8.4.31: RCC control/status register (RCC_CSR) , Section 11.3: GPIO functional description , Section 11.3.2: I/O pin alternate function multiplexer and mapping , Section 11.3.7: I/O alternate function input/output , Section 10.2.15: SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2) , Section 13.1: NVIC main features , Section 21.4.32: Monitoring the internal voltage reference , Section 24.5: RTC low-power modes , Section 64.4.10: PDM interface , Section 12.7.2: CRS configuration register (CRS_CFGR) and Section 42.3: Package data register . Added note in Section 3.8: FLASH interrupts and Section 12.3: CRS implementation . Removed note from Section 25.2: LCD main features .

Date

Revision

Changes

08-Jan-2019

3
(cont'd)

Updated Section 41.1: Introduction , Section 41.4.8: DP target identification register (DP_TARGETIDR) , Section 41.7: Cross trigger interface registers , Section 41.8.1: DBGMCU identity code register (DBGMCU_IDCODE) , Section 41.10.14: DWT CoreSight peripheral identity register 1 (DWT_PIDR1) and Section 41.14.14: DWT CoreSight peripheral identity register 1 (DWT_PIDR1) .

Updated Table 271: Debug port register map and reset values and Table 278: DBGMCU register map and reset values .

Removed former Section 32.11: CPU2 Instrumentation Trace Macrocell (ITM) and its subsections.

Updated Section 42.1: Unique device ID register (96 bits)

01-Mar-2019

Changed document classification, from ST restricted to Public.

Updated Section 8.3: Low-power modes , Channel configuration procedure , Channel state and disabling a channel , Section 32.1: RNG introduction , Section 32.2: RNG main features , Section 32.3.3: Random number generation and its subsections , Section 32.3.4: RNG initialization , Section 32.3.5: RNG operation and its subsections , Section 32.3.6: RNG clocking , Section 32.3.7: Error management , Section 32.3.8: The RNG low-power use , Section 32.6.1: Introduction , Section 21.7: RNG registers , Section 32.7.2: RNG status register (RNG_SR) , Section 32.7.3: RNG data register (RNG_DR) , sections 39.4.7 to 210.4.24, 41.6.6 and 41.6.7, Section 49.5.4: USART FIFOs and thresholds , Section 54.4.4: LPUART FIFOs and thresholds and Section 50.4.14: SPDIF output .

Updated Table 63: Wake-up interrupt table , Table 362: TIM2/TIM3/TIM4/TIM5 register map and reset values and Table 260: STM32WB55xx SPI implementation .

Updated Figure 272: RNG block diagram , Figure 273: Entropy source model and Figure 577: Reception using DMA .

Added Figure 274: RNG initialization overview and footnote to Figure 481: Packing data in FIFO for transmission and reception .

13-Feb-2020

Updated Section 2.1: System architecture , Section 3.5: FLASH UID64 , Section 3.6.4: CPU2 security (ESE) , Section 6.4.12: Auto wake-up from Low-power mode , Section 6.6.8: PWR control register 5 (PWR_CR5) , Section 7.4.7: From USB to timer (TIM2) , Software reset , Section 8.2: Clocks , External source , Section 8.2.2: HSI16 clock , Section 8.2.3: MSI clock , Section 8.2.5: PLLs , Section 8.2.8: LSI2 clock , Section 8.4.1: RCC clock control register (RCC_CR) , Section 8.4.4: RCC PLL configuration register (RCC_PLLCFGR) , Section 8.4.31: RCC control/status register (RCC_CSR) , Section 11.3: GPIO functional description , Section 11.3.2: I/O pin alternate function multiplexer and mapping , Section 11.3.7: I/O alternate function input/output , Section 10.2.15: SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2) , Section 13.1: NVIC main features , Section 21.4.32: Monitoring the internal voltage reference , Section 24.5: RTC low-power modes , Section 64.4.10: PDM interface , Section 12.7.2: CRS configuration register (CRS_CFGR) and Section 42.3: Package data register .

Added note in Section 3.8: FLASH interrupts and Section 12.3: CRS implementation .

Removed note from Section 25.2: LCD main features .

Table 293. Document revision history (continued)

Date	Revision	Changes
13-Feb-2020	5 (cont'd)	Updated Table 1: Memory map and peripheral register boundary addresses , Table 2: Boot modes , Table 25: Functionalities depending on system operating mode , Table 42: RCC register map and reset values , Table 61: CPU1 vector table , Table 62: CPU2 vector table and Table 63: Wake-up interrupt table . Updated Figure 15: Clock tree , Figure 19: Three-volt or Five-volt tolerant GPIO structure (TT or FT) , Figure 75: Input floating / pull up / pull down configurations , Figure 76: Output configuration and Figure 77: Alternate function configuration , and removed former Figure 21: Basic structure of a 5-Volt tolerant I/O port bit .

Table 293. Document revision history (continued)

Date	Revision	Changes
11-Jul-2020	6	Introduced STM32WB35xx devices. Updated Introduction , Section 3.3.1: Flash memory organization, PCROP1A start address option bytes, PCROP1A end address option bytes, WRP Area A address option bytes, WRP Area B address option bytes, PCROP1B start address option bytes, PCROP1B end address option bytes , Section 3.5: FLASH UID64 , Section 3.10.5: Flash memory control register (FLASH_CR) , sections 3.10.8 to 3.10.13, Section 3.10.17: Flash memory CPU2 control register (FLASH_C2CR) , sections 6.6.2 to 6.6.4, Section 6.6.7: PWR status clear register (PWR_SCR) , sections 6.6.12 to 6.6.14 and 6.6.18 to 6.6.20, Section 6.6.22: PWR CPU2 control register 3 (PWR_C2CR3) , Section 7.4.8: From internal analog to ADC1 , sections 8.4.12 to 8.4.13, 8.4.17 to 8.4.18, Section 8.4.20: RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) , sections 8.4.23 to 8.4.24, Section 8.4.26: RCC APB1 peripheral clocks enable in Sleep mode register 1 (RCC_APB1SMENR1) , Section 8.4.45: RCC CPU2 APB1 peripheral clocks enable in Sleep mode register 1 (RCC_C2APB1SMENR1) , Section 8.4.48: RCC CPU2 APB3 peripheral clock enable in Sleep mode register (RCC_C2APB3SMENR) , Section 9.4.3: I/O port control registers , sections 10.2.3 to 10.2.7, Section 10.2.15: SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2) , Section 17.4.4: DMAMUX request line multiplexer , Calculating the actual V _REF+voltage using the internal reference voltage , Section 36.5.2: VREFBUF calibration control register (VREFBUF_CCR) . Section 24.6.1: Comparator 1 control and status register (COMP1_CSR) , Section 24.2: TSC main features , Section 24.3.4: Charge transfer acquisition sequence, Montgomery space and fast mode operations , Section 32.7.2: PKA status register (PKA_SR) , Section 21.4.7: Single-ended and differential input channels , Software procedure to enable the ADC , Section 201.4.1: TIMx control register 1 (TIMx_CR1)(x = 1, 8) , Section 201.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 1, 8) , Section 201.4.20: TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) , sections 24.4.27 to 24.4.28, Section 210.3.19: Timer synchronization , Section 210.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 5, 23, 24) , sections 224.7.1 to 224.7.2, Section 54.7.8: LPUART interrupt and status register [alternate] (LPUART_ISR) , Section 66.6.18: SAI PDM control register (SAI_PDMCR) , Section 41.1: Introduction , Section 41.8.2: DBGMCU configuration register (DBGMCU_CR) , Section 41.8.4: DBGMCU CPU2 APB1 peripheral freeze register 1 (DBGMCU_C2APB1FZR1) , Section 41.8.6: DBGMCU CPU2 APB1 peripheral freeze register 2 (DBGMCU_C2APB1FZR2) and Section 41.8.8: DBGMCU CPU2 APB2 peripheral freeze register (DBGMCU_C2APB2FZR) .

Date

Revision

Changes

11-Jul-2020

Introduced STM32WB35xx devices.

Updated Introduction , Section 3.3.1: Flash memory organization, PCROP1A start address option bytes, PCROP1A end address option bytes, WRP Area A address option bytes, WRP Area B address option bytes, PCROP1B start address option bytes, PCROP1B end address option bytes , Section 3.5: FLASH UID64 , Section 3.10.5: Flash memory control register (FLASH_CR) , sections 3.10.8 to 3.10.13, Section 3.10.17: Flash memory CPU2 control register (FLASH_C2CR) , sections 6.6.2 to 6.6.4, Section 6.6.7: PWR status clear register (PWR_SCR) , sections 6.6.12 to 6.6.14 and 6.6.18 to 6.6.20, Section 6.6.22: PWR CPU2 control register 3 (PWR_C2CR3) , Section 7.4.8: From internal analog to ADC1 , sections 8.4.12 to 8.4.13, 8.4.17 to 8.4.18, Section 8.4.20: RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) , sections 8.4.23 to 8.4.24, Section 8.4.26: RCC APB1 peripheral clocks enable in Sleep mode register 1 (RCC_APB1SMENR1) , Section 8.4.45: RCC CPU2 APB1 peripheral clocks enable in Sleep mode register 1 (RCC_C2APB1SMENR1) , Section 8.4.48: RCC CPU2 APB3 peripheral clock enable in Sleep mode register (RCC_C2APB3SMENR) , Section 9.4.3: I/O port control registers , sections 10.2.3 to 10.2.7, Section 10.2.15: SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2) , Section 17.4.4: DMAMUX request line multiplexer , Calculating the actual V _REF+voltage using the internal reference voltage , Section 36.5.2: VREFBUF calibration control register (VREFBUF_CCR) . Section 24.6.1: Comparator 1 control and status register (COMP1_CSR) , Section 24.2: TSC main features , Section 24.3.4: Charge transfer acquisition sequence, Montgomery space and fast mode operations , Section 32.7.2: PKA status register (PKA_SR) , Section 21.4.7: Single-ended and differential input channels , Software procedure to enable the ADC , Section 201.4.1: TIMx control register 1 (TIMx_CR1)(x = 1, 8) , Section 201.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 1, 8) , Section 201.4.20: TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) , sections 24.4.27 to 24.4.28, Section 210.3.19: Timer synchronization , Section 210.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 5, 23, 24) , sections 224.7.1 to 224.7.2, Section 54.7.8: LPUART interrupt and status register [alternate] (LPUART_ISR) , Section 66.6.18: SAI PDM control register (SAI_PDMCR) , Section 41.1: Introduction , Section 41.8.2: DBGMCU configuration register (DBGMCU_CR) , Section 41.8.4: DBGMCU CPU2 APB1 peripheral freeze register 1 (DBGMCU_C2APB1FZR1) , Section 41.8.6: DBGMCU CPU2 APB1 peripheral freeze register 2 (DBGMCU_C2APB1FZR2) and Section 41.8.8: DBGMCU CPU2 APB2 peripheral freeze register (DBGMCU_C2APB2FZR) .

Table 293. Document revision history (continued)

Date	Revision	Changes
11-Jul-2020	6 (cont'd)	Updated Table 3: Flash memory - Single bank organization , Table 195: COMP1 input plus assignment , Table 196: COMP1 input minus assignment , Table 269: Modular exponentiation computation times , Table 274: Montgomery parameters average computation times , Table 205: Output control bits for complementary OCx and OCxN channels with break feature , Table 565: Output control bit for standard OCx channels and Table 1050: Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . Updated Figure 224: Control circuit in normal mode, internal clock divided by 1 , Figure 230: Capture/compare channel 1 main circuit , Figure 664: General-purpose timer block diagram , Figure 690: Capture/Compare channel 1 main circuit , Figure 1198: TIM16/TIM17 block diagram and Figure 1212: Capture/compare channel 1 main circuit . Added Section 7.2: Interconnect matrix implementation , Note: to Section 8.4.3: RCC clock configuration register (RCC_CFGR) , Section 9.3: GPIO implementation , Section 13.2: NVIC implementation , Section 14.2: EXTI implementation , Section 21.3: ADC implementation , Section 36.2: VREFBUF implementation , Section 221.3.18: Using timer output as trigger for other timers (TIM16/TIM17) , Section 24.3: RTC implementation and Section 66.3: SAI implementation . Added Table 101: DMAMUX implementation , Table 273: Point on elliptic curve Fp check average computation times , Table 147: LPTIM implementation , Table 732: I2C implementation and footnote to Table 367: SPI implementation . Minor text edits across the whole document.
20-Apr-2021	7	Updated Figure 109: Surface charge transfer analog I/O group structure , Figure 565: RS232 RTS flow control , Figure 566: RS232 CTS flow control , Figure 1021: Detailed PDM interface block diagram and Figure 124: IPCC Simplex - Send procedure state diagram . Updated Table 178: Acquisition sequence summary , Table 268: Family of supported curves for ECC operations , Table 275: PKA interrupt requests , Table 405: Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz , Table 406: Error calculation for programmed baud rates at fCK = 100 MHz and Table 161: HSEM internal input/output signals Added Table 163: IPCC interface signals . Added footnotes to Table 250: Montgomery multiplication , Table 796: STM32WB55xx SAI features , Table 798: SAI input/output pins and to Figure 1013: SAI functional block diagram , Figure 1021: Detailed PDM interface block diagram . Added Section 53.6: USART in low-power modes and Section 54.5: LPUART in low-power modes . Added notes in Section 224.4.6: Trigger multiplexer and Section 24.3.2: Surface charge transfer acquisition overview .

Date

Revision

Changes

11-Jul-2020

6
(cont'd)

Updated Table 3: Flash memory - Single bank organization , Table 195: COMP1 input plus assignment , Table 196: COMP1 input minus assignment , Table 269: Modular exponentiation computation times , Table 274: Montgomery parameters average computation times , Table 205: Output control bits for complementary OCx and OCxN channels with break feature , Table 565: Output control bit for standard OCx channels and Table 1050: Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) .

Updated Figure 224: Control circuit in normal mode, internal clock divided by 1 , Figure 230: Capture/compare channel 1 main circuit , Figure 664: General-purpose timer block diagram , Figure 690: Capture/Compare channel 1 main circuit , Figure 1198: TIM16/TIM17 block diagram and Figure 1212: Capture/compare channel 1 main circuit .

Added Section 7.2: Interconnect matrix implementation , Note: to Section 8.4.3: RCC clock configuration register (RCC_CFGR) , Section 9.3: GPIO implementation , Section 13.2: NVIC implementation , Section 14.2: EXTI implementation , Section 21.3: ADC implementation , Section 36.2: VREFBUF implementation , Section 221.3.18: Using timer output as trigger for other timers (TIM16/TIM17) , Section 24.3: RTC implementation and Section 66.3: SAI implementation .

Added Table 101: DMAMUX implementation , Table 273: Point on elliptic curve Fp check average computation times , Table 147: LPTIM implementation , Table 732: I2C implementation and footnote to Table 367: SPI implementation .

Minor text edits across the whole document.

20-Apr-2021

Updated Figure 109: Surface charge transfer analog I/O group structure , Figure 565: RS232 RTS flow control , Figure 566: RS232 CTS flow control , Figure 1021: Detailed PDM interface block diagram and Figure 124: IPCC Simplex - Send procedure state diagram .

Updated Table 178: Acquisition sequence summary , Table 268: Family of supported curves for ECC operations , Table 275: PKA interrupt requests , Table 405: Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz , Table 406: Error calculation for programmed baud rates at fCK = 100 MHz and Table 161: HSEM internal input/output signals

Added Table 163: IPCC interface signals .

Added footnotes to Table 250: Montgomery multiplication , Table 796: STM32WB55xx SAI features , Table 798: SAI input/output pins and to Figure 1013: SAI functional block diagram , Figure 1021: Detailed PDM interface block diagram .

Added Section 53.6: USART in low-power modes and Section 54.5: LPUART in low-power modes .

Added notes in Section 224.4.6: Trigger multiplexer and Section 24.3.2: Surface charge transfer acquisition overview .

Table 293. Document revision history (continued)

Date	Revision	Changes
20-Apr-2021	7 (cont'd)	Updated Introduction , Related documents , ST production values in Section 3.4.1: Option bytes description, Section 3.10.6: Flash memory ECC register (FLASH_ECCR), Section 3.10.9: Flash memory PCROP zone A end address register (FLASH_PCROP1AER), Section 3.10.10: Flash memory WRP area A address register (FLASH_WRP1AR), Section 3.10.11: Flash memory WRP area B address register (FLASH_WRP1BR), Section 3.10.12: Flash memory PCROP zone B start address register (FLASH_PCROP1BSR), Section 3.10.13: Flash memory PCROP zone B end address register (FLASH_PCROP1BER), Section 3.10.14: Flash memory IPCC mailbox data buffer address register (FLASH_IPCCBR), Section 3.10.18: Secure flash memory start address register (FLASH_SFR), Section 3.10.19: Flash memory secure SRAM2 start address and CPU2 reset vector register (FLASH_SRRVR), Section 4.1: Introduction, Section 4.2: Main features, Section 25.2: CRC main features, Polynomial programmability, Section 25.4: CRC registers, Section 8.2: Clocks, Section 8.2.14: SMPS step-down converter clock, Section 8.4.1: RCC clock control register (RCC_CR), Section 8.4.3: RCC clock configuration register (RCC_CFGR), Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN), note in Triggered injection mode, Section 24.2: TSC main features, Section 32.3.4: PKA public key acceleration, Section 32.5.1: Supported elliptic curves, Section 66.4.10: PDM interface, Section 224.7.1: LPTIM interrupt and status register (LPTIM_ISR), Section 53.2: USART main features, Section 53.8.9: USART interrupt and status register (USART_ISR), Section 53.8.10: USART interrupt and status register [alternate] (USART_ISR), Section 54.4.14: LPUART low-power management, Section 66.4.10: PDM interface, Section 66.6.19: SAI PDM delay register (SAI_PDMPLY), Section 14.3.3: HSEM lock procedures, Section 14.3.5: HSEM unlock procedures, Section 14.3.6: HSEM LOCKID semaphore clear, Section 14.3.7: HSEM interrupts, Section 14.3.8: Semaphore attributes, Section 41.4.7: DP data link control register (DP_DLCR), Simplex communications, Section 41.5.1: AP control/status word register (AP_CSWR), Section 41.5.5: AP base address register (AP_BASER), Section 41.5.6: AP identification register (AP_IDR) and Section 41.8.2: DBGMCU configuration register (DBGMCU_CR). Minor text edits across the whole document.

Date

Revision

Changes

20-Apr-2021

7 (cont'd)

Updated Introduction , Related documents , ST production values in Section 3.4.1: Option bytes description, Section 3.10.6: Flash memory ECC register (FLASH_ECCR), Section 3.10.9: Flash memory PCROP zone A end address register (FLASH_PCROP1AER), Section 3.10.10: Flash memory WRP area A address register (FLASH_WRP1AR), Section 3.10.11: Flash memory WRP area B address register (FLASH_WRP1BR), Section 3.10.12: Flash memory PCROP zone B start address register (FLASH_PCROP1BSR), Section 3.10.13: Flash memory PCROP zone B end address register (FLASH_PCROP1BER), Section 3.10.14: Flash memory IPCC mailbox data buffer address register (FLASH_IPCCBR), Section 3.10.18: Secure flash memory start address register (FLASH_SFR), Section 3.10.19: Flash memory secure SRAM2 start address and CPU2 reset vector register (FLASH_SRRVR), Section 4.1: Introduction, Section 4.2: Main features, Section 25.2: CRC main features, Polynomial programmability, Section 25.4: CRC registers, Section 8.2: Clocks, Section 8.2.14: SMPS step-down converter clock, Section 8.4.1: RCC clock control register (RCC_CR), Section 8.4.3: RCC clock configuration register (RCC_CFGR), Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN), note in Triggered injection mode, Section 24.2: TSC main features, Section 32.3.4: PKA public key acceleration, Section 32.5.1: Supported elliptic curves, Section 66.4.10: PDM interface, Section 224.7.1: LPTIM interrupt and status register (LPTIM_ISR), Section 53.2: USART main features, Section 53.8.9: USART interrupt and status register (USART_ISR), Section 53.8.10: USART interrupt and status register [alternate] (USART_ISR), Section 54.4.14: LPUART low-power management, Section 66.4.10: PDM interface, Section 66.6.19: SAI PDM delay register (SAI_PDMPLY), Section 14.3.3: HSEM lock procedures, Section 14.3.5: HSEM unlock procedures, Section 14.3.6: HSEM LOCKID semaphore clear, Section 14.3.7: HSEM interrupts, Section 14.3.8: Semaphore attributes, Section 41.4.7: DP data link control register (DP_DLCR), Simplex communications, Section 41.5.1: AP control/status word register (AP_CSWR), Section 41.5.5: AP base address register (AP_BASER), Section 41.5.6: AP identification register (AP_IDR) and Section 41.8.2: DBGMCU configuration register (DBGMCU_CR).

Minor text edits across the whole document.

Table 293. Document revision history (continued)

Date	Revision	Changes
13-Aug-2021	8	Updated Section 3.5: FLASH UID64 , Section 25.2: CRC main features , Section 6.6.2: PWR control register 2 (PWR_CR2) , Section 8.2.8: LSI2 clock , Section 8.2.12: Clock security system on LSE (LSECSS) , Section 9.4.2: I/O pin alternate function multiplexer and mapping , Section 201.3.16: Using the break function , Section 201.4.8: TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) , Section 210.4.8: TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) , Section 221.3.11: Using the break function , Section 24.4.14: Calibration clock output , Section 53.8.3: USART control register 2 (USART_CR2) and Section 41.8.1: DBGMCU identity code register (DBGMCU_IDCODE) . Added Section 221.3.13: 6-step PWM generation . Changed SCLK into CK throughout Section 53: Universal synchronous/asynchronous receiver transmitter (USART/UART) . Minor text edits across the whole document. Added footnote 2 to Table 21: Supply configuration control . Updated Figure 802: TDM frame configuration examples and Table 278: DBGMCU register map and reset values . Updated Figure 201: Advanced-control timer block diagram , Figure 224: Control circuit in normal mode, internal clock divided by 1 , Figure 1208: Control circuit in normal mode, internal clock divided by 1 , Figure 545: TC/TXE behavior when transmitting , Figure 324: Start bit detection when oversampling by 16 or 8 , Figure 554: USART example of synchronous master transmission and footnotes of Figure 1021: Detailed PDM interface block diagram .
04-Oct-2021	9	Updated Section 3.5: FLASH UID64 , DMA operation in different operating modes , Section 53.5.20: RS232 hardware flow control and RS485 Driver Enable , Section 53.8.4: USART control register 3 (USART_CR3) , Section 54.4.13: RS232 hardware flow control and RS485 Driver Enable , Section 54.7.4: LPUART control register 3 (LPUART_CR3) and Section 41.8.1: DBGMCU identity code register (DBGMCU_IDCODE) . Updated Figure 215: GCM authenticated encryption . Added Section 42.4: Part number codification register . Minor text edits across the whole document.

Date

Revision

Changes

13-Aug-2021

Updated Section 3.5: FLASH UID64 , Section 25.2: CRC main features , Section 6.6.2: PWR control register 2 (PWR_CR2) , Section 8.2.8: LSI2 clock , Section 8.2.12: Clock security system on LSE (LSECSS) , Section 9.4.2: I/O pin alternate function multiplexer and mapping , Section 201.3.16: Using the break function , Section 201.4.8: TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) , Section 210.4.8: TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) , Section 221.3.11: Using the break function , Section 24.4.14: Calibration clock output , Section 53.8.3: USART control register 2 (USART_CR2) and Section 41.8.1: DBGMCU identity code register (DBGMCU_IDCODE) .

Added Section 221.3.13: 6-step PWM generation .

Changed SCLK into CK throughout Section 53: Universal synchronous/asynchronous receiver transmitter (USART/UART) .

Minor text edits across the whole document.

Added footnote 2 to Table 21: Supply configuration control .

Updated Figure 802: TDM frame configuration examples and Table 278: DBGMCU register map and reset values .

Updated Figure 201: Advanced-control timer block diagram , Figure 224: Control circuit in normal mode, internal clock divided by 1 , Figure 1208: Control circuit in normal mode, internal clock divided by 1 , Figure 545: TC/TXE behavior when transmitting , Figure 324: Start bit detection when oversampling by 16 or 8 , Figure 554: USART example of synchronous master transmission and footnotes of Figure 1021: Detailed PDM interface block diagram .

04-Oct-2021

Updated Section 3.5: FLASH UID64 , DMA operation in different operating modes , Section 53.5.20: RS232 hardware flow control and RS485 Driver Enable , Section 53.8.4: USART control register 3 (USART_CR3) , Section 54.4.13: RS232 hardware flow control and RS485 Driver Enable , Section 54.7.4: LPUART control register 3 (LPUART_CR3) and Section 41.8.1: DBGMCU identity code register (DBGMCU_IDCODE) .

Updated Figure 215: GCM authenticated encryption .

Added Section 42.4: Part number codification register .

Minor text edits across the whole document.

Table 293. Document revision history (continued)

Date	Revision	Changes
07-Jun-2022	10	Updated Introduction , Section 3.3.1: Flash memory organization , Section 3.4.1: Option bytes description , Section 4.1: Introduction , Section 4.2: Main features , Section 6.4.4: Exiting Low-power mode , Section 8.4.5: RCC PLLSA1 configuration register (RCC_PLLSA1CFGR) , Section 8.4.30: RCC backup domain control register (RCC_BDCR) , Section 8.4.31: RCC control/status register (RCC_CSR) , Section 8.4.33: RCC clock HSE register (RCC_HSECR) , Analog watchdog, Triggering the start of a command , Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) , Reading the temperature , Section 32.2: RNG main features , Section 41.7.3: CTI application trigger set register (CTI_APPSETR) , Section 41.7.15: CTI lock access register (CTI_LAR) , and Section 41.8.2: DBGMCU configuration register (DBGMCU_CR) . Added Section 21.5: ADC in low-power mode and Section 45: Important security notice . Updated Figure 110: Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0) Case when JADSTP occurs during an ongoing conversion , Figure 112: Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0) Case when JADSTP occurs outside an ongoing conversion , Figure 140: Triggered regular oversampling with injection , Figure 293: GCM authenticated encryption , Figure 406: Transfer bus diagrams for I2C target transmitter (mandatory events only) , Figure 409: Transfer bus diagrams for I2C target receiver (mandatory events only) , and Figure 416: Transfer bus diagrams for I2C controller transmitter (mandatory events only) . Updated Table 72: ADC input/output pins and Table 369: SPI register map and reset values . Minor text edits across the whole document.
01-Feb-2023	11	Added Empty check and Caution in Section 3.3.6: Flash memory program and erase operations . Updated Section 3.3.7: Flash main memory erase sequences , Section 3.3.8: Flash main memory programming sequences , note in Section 3.6.1: Read protection (RDP) , Section 3.10.4: Flash memory status register (FLASH_SR) , Section 3.10.5: Flash memory control register (FLASH_CR) , Section 3.10.19: Flash memory secure SRAM2 start address and CPU2 reset vector register (FLASH_SRRVR) , Section 6.1: Power supplies, Force SMPS step-down converter Bypass mode , Section 6.2.2: Programmable voltage detector (PVD) , Section 8.1.2: System reset , Section 8.2.14: SMPS step-down converter clock , Converting a supply-relative ADC measurement to an absolute voltage value , Section 14.15.4: ADC configuration register 1 (ADC_CFGR1) , Section 38.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 1, 8) , Section 39.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) , Section 56.5: WWDG interrupts , Section 56.6.2: WWDG configuration register (WWDG_CFR) , and Section 41.4.11: DP access port select register (DP_SELECTR) . Updated Figure 135: Surface charge transfer analog I/O group structure , Figure 136: Sampling capacitor voltage variation , and Figure 762: Watchdog block diagram . Updated Table 271: Debug port register map and reset values . Minor text edits across the whole document.

Date

Revision

Changes

07-Jun-2022

Updated Introduction , Section 3.3.1: Flash memory organization , Section 3.4.1: Option bytes description , Section 4.1: Introduction , Section 4.2: Main features , Section 6.4.4: Exiting Low-power mode , Section 8.4.5: RCC PLLSA1 configuration register (RCC_PLLSA1CFGR) , Section 8.4.30: RCC backup domain control register (RCC_BDCR) , Section 8.4.31: RCC control/status register (RCC_CSR) , Section 8.4.33: RCC clock HSE register (RCC_HSECR) , Analog watchdog, Triggering the start of a command , Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) , Reading the temperature , Section 32.2: RNG main features , Section 41.7.3: CTI application trigger set register (CTI_APPSETR) , Section 41.7.15: CTI lock access register (CTI_LAR) , and Section 41.8.2: DBGMCU configuration register (DBGMCU_CR) .

Added Section 21.5: ADC in low-power mode and Section 45: Important security notice .

Updated Figure 110: Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0) Case when JADSTP occurs during an ongoing conversion , Figure 112: Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0) Case when JADSTP occurs outside an ongoing conversion , Figure 140: Triggered regular oversampling with injection , Figure 293: GCM authenticated encryption , Figure 406: Transfer bus diagrams for I2C target transmitter (mandatory events only) , Figure 409: Transfer bus diagrams for I2C target receiver (mandatory events only) , and Figure 416: Transfer bus diagrams for I2C controller transmitter (mandatory events only) .

Updated Table 72: ADC input/output pins and Table 369: SPI register map and reset values .

Minor text edits across the whole document.

01-Feb-2023

Added Empty check and Caution in Section 3.3.6: Flash memory program and erase operations .

Updated Section 3.3.7: Flash main memory erase sequences , Section 3.3.8: Flash main memory programming sequences , note in Section 3.6.1: Read protection (RDP) , Section 3.10.4: Flash memory status register (FLASH_SR) , Section 3.10.5: Flash memory control register (FLASH_CR) , Section 3.10.19: Flash memory secure SRAM2 start address and CPU2 reset vector register (FLASH_SRRVR) , Section 6.1: Power supplies, Force SMPS step-down converter Bypass mode , Section 6.2.2: Programmable voltage detector (PVD) , Section 8.1.2: System reset , Section 8.2.14: SMPS step-down converter clock , Converting a supply-relative ADC measurement to an absolute voltage value , Section 14.15.4: ADC configuration register 1 (ADC_CFGR1) , Section 38.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 1, 8) , Section 39.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) , Section 56.5: WWDG interrupts , Section 56.6.2: WWDG configuration register (WWDG_CFR) , and Section 41.4.11: DP access port select register (DP_SELECTR) .

Updated Figure 135: Surface charge transfer analog I/O group structure , Figure 136: Sampling capacitor voltage variation , and Figure 762: Watchdog block diagram .

Updated Table 271: Debug port register map and reset values .

Minor text edits across the whole document.

Table 293. Document revision history (continued)

Date	Revision	Changes
04-Sep-2023	12	Updated Introduction , Section 3.5: FLASH UID64 , Section 3.10.16: Flash memory CPU2 status register (FLASH_C2SR) , Section 4.1: Introduction , Section 4.2: Main features , Entering Stop0 mode , Section 6.4.8: Stop1 mode , Entering Stop2 mode , Section 8.2.8: LSI2 clock , Section 8.2.20: Clock-out capability , Section 24.3.4: Charge transfer acquisition sequence , Section 24.6.1: Comparator 1 control and status register (COMP1_CSR) , Section 201.3.22: Encoder interface mode , and Section 210.3.15: Encoder interface mode . Updated Figure 2: Memory map , Figure 508: Independent watchdog block diagram , Figure 293: I2C initialization flow , and Figure 892: Target initialization flow . Minor text edits across the whole document.
04-Jan-2024	13	Updated Section 6.4.12: Auto wake-up from Low-power mode . Added Section 61.4.15: SMBus controller mode and removed former Section 32.4.17: DMA requests and Section 32.4.18: Debug mode . Added Table 393: USART/UART input/output pins , Table 394: USART internal input/output signals , Table 403: LPUART input/output pins , and Table 404: LPUART internal input/output signals . Updated Figure 569: LPUART block diagram . Reorganized register sections by address offset in Section 66: Serial audio interface (SAI) . Minor text edits across the whole document.
09-Jan-2025	14	Added Section 1.3: Register reset value , Section 12.4.2: DMA pins and internal signals , and Section 13.4.2: CRS internal signals . Updated User and read protection option bytes , CPU2 secure SRAM2 areas , Exiting Standby mode , Section 12.3.2: DMA request mapping , Section 21.4.12: Channel-wise programmable sampling time (SMPR1, SMPR2) , Section 21.4.16: ADC timing , Remapping capability for small packages , Section 35.6.2: Validation conditions , and Adjusting the bitstream clock rate . Replaced master/slave with controller/target in Section 61: Inter-integrated circuit interface (I2C) . Rearranged Section 13: Clock recovery system (CRS) . Updated Figure 100: Analog-to-digital conversion time , Figure 115: Flushing ADC_JSQR queue of context by setting ADDIS = 1 (JQM = 1) , Figure 546: Start bit detection when oversampling by 16 or 8 , Figure 562: Transmission using DMA , Figure 563: Reception using DMA , Figure 576: Transmission using DMA , Figure 577: Reception using DMA , and CRS block diagram . Added Table 320: RNG configurations . Updated Table 392: USART / LPUART features , Table 393: USART/UART input/output pins , and Table 402: USART / LPUART features . Minor text edits across the whole document.
09-Jan-2026	15	Updated Table 1: Memory map and peripheral register boundary addresses and sections order .
06-Mar-2026	16	Updated Section 6.4.29: RCC peripherals independent clock configuration register (RCC_CCIPR) .