20. Voltage reference buffer (VREFBUF)

20.1 VREFBUF introduction

The devices embed a voltage reference buffer which can be used as voltage reference for the on-chip ADC, and also as voltage reference for external components through the VREF+ pin. When the VREF+ pin is double-bonded with VDDA pin in a package, the voltage reference buffer is not available and must be kept disabled (refer to datasheet for packages pinout description).

20.2 VREFBUF implementation

Table 104. VREFBUF implementation

20.3 VREFBUF functional description

The internal voltage reference buffer supports two voltages ^(a) , which are configured with VRS bits in the VREFBUF_CSR register:

• • VRS = 0: V _{REF_OUT1} around 2.048 V
• • VRS = 1: V _{REF_OUT2} around 2.5 V

The internal voltage reference can be configured in four different modes depending on ENVR and HIZ bits configuration. These modes are provided in the table below:

Table 105. VREF buffer modes

a. The minimum V _DDA voltage depends on VRS setting, refer to the product datasheet.

After enabling the VREFBUF by setting ENVR bit and clearing HIZ bit in the VREFBUF_CSR register, the user must wait until VRR bit is set, meaning that the voltage reference output has reached its expected value.

20.4 VREFBUF trimming

The VREFBUF output voltage is factory-calibrated by ST. For the VRS = 1 setting, the calibration data is automatically loaded to the TRIM register at reset. For the VRS = 0 setting, the software must take care of copying the calibration data from the read-only system memory area (flash memory) to the TRIM register.

Optionally user can trim the output voltage by changing the TRIM register bits.

Table 106. VREFBUF trimming data

20.5 VREFBUF registers

20.5.1 VREFBUF control and status register (VREFBUF_CSR)

Address offset: 0x00

Reset value: 0x0000 0002

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 VRR : Voltage reference buffer ready

• 0: the voltage reference buffer output is not ready.
• 1: the voltage reference buffer output reached the requested level.

Bit 2 VRS : Voltage reference scale

This bit selects the value generated by the voltage reference buffer.

• 0: Voltage reference set to \( V_{REF\_OUT1} \) (around 2.048 V).
• 1: Voltage reference set to \( V_{REF\_OUT2} \) (around 2.5 V).

Bit 1 HIZ : High impedance mode

This bit controls the analog switch to connect or not the \( V_{REF+} \) pin.

• 0: \( V_{REF+} \) pin is internally connected to the voltage reference buffer output.
• 1: \( V_{REF+} \) pin is high impedance.

Refer to Table 105: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.

Bit 0 ENVR : Voltage reference buffer mode enable

This bit is used to enable the voltage reference buffer mode.

• 0: Internal voltage reference mode disable (external voltage reference mode).
• 1: Internal voltage reference mode (reference buffer enable or hold mode) enable.

20.5.2 VREFBUF calibration control register (VREFBUF_CCR)

Address offset: 0x04

Reset value: 0x0000 00XX

Bits 31:6 Reserved, must be kept at reset value.

Bits 5:0 TRIM[5:0] : Trimming code

For VRS = 1 (2.5 V), these bits are automatically initialized after reset with the trimming value stored in the flash memory during the production test.

For VRS = 0 (2.048V), the software must take care of copying the calibration data from the read-only system memory area (flash memory) to the TRIM[5:0] bitfield. Writing into these bits allows the tuning of the internal reference buffer voltage.

Note: If the user application performs the trimming, the trimming code should start from 000000 to 111111 in ascending order.

20.5.3 VREFBUF register map

The following table gives the VREFBUF register map and the reset values.

Table 107. VREFBUF register map and reset values

Refer to Section 2.2: Memory organization for the register boundary addresses.