12. Peripherals interconnect matrix

12.1 Introduction

Several peripherals have direct connections, enabling autonomous communication and/or synchronization between them. This saves CPU resources and, consequently, reduces power consumption. In addition, these hardware connections remove software latency and result in more predictable system design.

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes.

12.2 Interconnect matrix implementation

Table 55. Interconnect matrix implementation

12.3 Connection summary

Table 56. Peripherals interconnect matrix ^{(1) (2)}

1. Numbers in table are links to corresponding subsections of Section 12.4: Interconnection details .

2. The “-” symbol in grayed cells means no interconnect.

12.4 Interconnection details

12.4.1 From timer (TIM1/TIM2/TIM17) to timer (TIM1/TIM2)

Purpose

Some of the timers are linked together internally for synchronization or chaining.

When one timer is configured in Master Mode, it can reset, start, stop or clock the counter of another timer configured in Slave Mode. A description of the feature is provided in Section 27.3.26: Timer synchronization .

The modes of synchronization are detailed in:

• • Section 27.3.26: Timer synchronization for advanced-control timers (TIM1)
• • Section 28.3.18: Timers and external trigger synchronization for general-purpose timers (TIM2)

Triggering signals

The output (from Master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1) following a configurable timer event. The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3.

The input and output signals for TIM1 are shown in Figure 156: Advanced-control timer block diagram .

The possible master/slave connections are given in:

• • Table 176: TIM1 internal trigger connection
• • Table 180: TIM2 internal trigger connection

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep.

12.4.2 From timer (TIM1/TIM2) and EXTI to ADC (ADC1)

Purpose

General-purpose timer TIM2, advanced-control timer TIM1 and EXTI can be used to generate an ADC triggering event.

TIMx synchronization is described in Section 27.3.27: ADC synchronization .

ADC synchronization is described in Section 14.5: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) .

Triggering signals

The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.

The input (to ADC) is on signals EXT[15:0] and JEXT[15:0].

The connection between timers and ADC is provided in:

• • Table 92: ADC1 - External triggers for regular channels
• • Table 93: ADC1 - External trigger for injected channels

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep.

12.4.3 From ADC (ADC1) to timer (TIM1)

Purpose

ADC1 can provide trigger event through watchdog signals to advanced-control timers (TIM1).

A description of the ADC analog watchdog setting is provided in Section 19.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) .

Trigger settings on the timer are provided in Section 27.3.4: External trigger input .

Triggering signals

The output (from ADC) is on signals ADC_AWDx_OUT n = 1, 2, 3 (for ADC1) x = 1, 2, 3 (three watchdogs on ADC) and the input (to timer) on signal TIMx_ETR (external trigger).

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep.

12.4.4 From HSE, LSE, LSI, MSI, MCO, RTC to timers (TIM2/TIM16/TIM17)

Purpose

External clocks (HSE, LSE), internal clocks (LSI, MSI), microcontroller output clock (MCO), GPIO and RTC wakeup interrupt can be used as input to general-purpose timers (TIM16/17) channel 1.

This makes possible calibration of the HSI16/MSI system clocks (with TIM16 and LSE) or of the LSI (with TIM16 and HSE). This is also used to precisely measure LSI (with TIM16 and HSI16) or MSI (with TIM17 and HSI16) oscillator frequency.

When Low Speed External (LSE) oscillator is used, no additional hardware connections are required.

This feature is described in Section 6.2.21: Internal/external clock measurement with TIM16/TIM17 .

External clock LSE can be used as input to general-purpose timer (TIM2) on TIM2_ETR pin, see Section 6.2.21: Internal/external clock measurement with TIM16/TIM17 ..

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep.

12.4.5 From RTC, COMP1, COMP2 to low-power timers (LPTIM1/LPTIM2)

Purpose

RTC alarm A/B, RTC_TAMP1/2/3 input detection, COMP1/2_OUT can be used as trigger to start LPTIM counters (LPTIM1/2).

Triggering signals

This trigger feature is described in Section 30.4.6: Trigger multiplexer (and following sections).

The input selection is described in Table 188: LPTIM1 external trigger connection and Table 189: LPTIM2 external trigger connection .

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep, Stop 0, Stop 1, Stop 2 (LPTIM1 only).

12.4.6 From timer (TIM1/TIM2) to comparators (COMP1/COMP2)

Purpose

Advanced-control timer (TIM1) and general-purpose timer (TIM2) can be used as blanking window input to COMP1/COMP2.

The blanking function is described in Section 21.3.7: Comparator output blanking function .

The blanking sources are given in

• • Section 21.6.1: Comparator 1 control and status register (COMP1_CSR) bits 20:18 BLANKING[2:0]
• • Section 21.6.2: Comparator 2 control and status register (COMP2_CSR) bits 20:18 BLANKING[2:0]

Triggering signals

Timer output signal TIMx_Ocx are the inputs to blanking source of COMP1/COMP2.

Active power mode(s)

Run, Sleep, Low-power run, Low-power sleep.

12.4.7 From USB to timer (TIM2)

Purpose

USB (FS SOF) can generate a trigger to general-purpose timer (TIM2).

Connection of USB to TIM2 is described in Table 180: TIM2 internal trigger connection .

Triggering signals

Internal signal generated by USB_FS Start Of Frame.

Active power mode(s)

Run, Sleep.

12.4.8 From internal analog to ADC1

Purpose

Internal temperature sensor (VTS), internal reference voltage (VREFINT) and VBAT monitoring channel are connected to ADC1 input channel.

This is according to:

• • Section 19.2: ADC main features
• • Section 19.4.11: Channel selection (ADC_SQRY, ADC_JSQR)
• • Section 19.4.30: Temperature sensor
• • Section 19.4.31: VBAT supply monitoring

Active power mode(s)

Run, Sleep, low-power run, Low-power sleep.

12.4.9 From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM16/TIM17)

Purpose

Comparators (COMP1/COMP2) output values can be connected to timers TIM1/TIM2/TIM16/TIM17 input captures or TIMx_ETR signals.

The connection to ETR is described in Section 27.3.4: External trigger input .

Comparators (COMP1/COMP2) output values can also generate break input signals for timer TIM1 on input pins TIMx_BKIN or TIMx_BKIN2 through GPIO alternate function selection using open drain connection of I/Os.

The possible connections are given in:

• • Section 27.4.23: TIM1 option register 1 (TIM1_OR1)
• • Section 27.4.28: TIM1 Alternate function register 2 (TIM1_AF2)
• • Section 28.4.22: TIM2 option register 1 (TIM2_OR1)
• • Section 27.4.27: TIM1 alternate function option register 1 (TIM1_AF1)
• • Section 29.2: TIM16/TIM17 main features

Run, Sleep, Low-power run, Low-power sleep.

CSS, CPU hard fault, RAM parity error, FLASH ECC double error detection, PVD can generate system errors in the form of timer break toward timers TIM1/TIM16/TIM17.

The purpose of the break function is to protect power switches driven by PWM signals generated by the timers.

List(s) of possible break source(s) are described in:

• • Section 27.3.16: Using the break function (TIM1)
• • Section 29.3.11: Using the break function (TIM16/TIM17)
• • Figure 265: TIM16/TIM17 block diagram

Run, Sleep, Low-power run, Low-power sleep.

General-purpose timer (TIM16/TIM17) output channel TIMx_OC1 are used to generate the waveform of infrared signal output.

The functionality is described in Section 31: Infrared interface (IRTIM) .

Run, Sleep, Low-power run, Low-power sleep.