11. System configuration controller (SYSCFG)

11.1 SYSCFG main features

The devices feature a set of configuration registers. The main purposes of the system configuration controller are the following:

• • Remapping memory areas
• • Managing the external interrupt line connection to the GPIOs
• • Managing robustness feature
• • Setting SRAM2 and PKA RAM write protection and software erase
• • Configuring FPU interrupts
• • Enabling /disabling I ² C Fast-mode Plus driving capability on some I/Os and voltage booster for I/Os analog switches
• • Interrupt pre-masking

11.2 SYSCFG registers

11.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)

This register is used for specific configurations on memory remap.

Address offset: 0x000

Reset value: 0x0000 000X (X is the memory mode selected by the BOOT0 pin and BOOT1 option bit)

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 MEM_MODE[2:0] : Memory mapping selection

These bits control the memory internal mapping at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the BOOT mode setting. After reset these bits take the value selected by BOOT0 (pin or option bit depending on nSWBOOT0 option bit) and BOOT1 option bit.

000: Main Flash memory mapped at CPU1 0x00000000

001: System Flash memory mapped at CPU1 0x00000000

010: Reserved

011: SRAM1 mapped at CPU1 0x00000000

100: Reserved

101: Reserved

110: QUADSPI memory mapped at CPU1 0x00000000

111: Reserved

11.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1)

Address offset: 0x004

Reset value: 0x7C00 0001

Bits 31:26 FPU_IE[5:0] : CPU1 FPU interrupts enable bits

FPU_IE[5]: Inexact interrupt enable

FPU_IE[4]: Input denormal interrupt enable

FPU_IE[3]: Overflow interrupt enable

FPU_IE[2]: underflow interrupt enable

FPU_IE[1]: Divide-by-zero interrupt enable

FPU_IE[0]: Invalid operation interrupt enable

Bits 25:23 Reserved, must be kept at reset value.

Bit 22 I2C3_FMP : I2C3 Fast-mode Plus driving capability activation

This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C3 pins selected through AF selection bits

1: Fm+ mode is enabled on I2C3 pins selected through AF selection bits.

Bit 21 Reserved, must be kept at reset value.

Bit 20 I2C1_FMP : I2C1 Fast-mode Plus driving capability activation

This bit enables the Fm+ driving mode on I2C1 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C1 pins selected through AF selection bits

1: Fm+ mode is enabled on I2C1 pins selected through AF selection bits.

Bit 19 I2C_PB9_FMP : Fast-mode Plus (Fm+) driving capability activation on PB9

This bit enables the Fm+ driving mode for PB9.

0: PB9 pin operates in standard mode.

1: Fm+ mode enabled on PB9 pin, and the Speed control is bypassed.

Bit 18 I2C_PB8_FMP : Fast-mode Plus (Fm+) driving capability activation on PB8

This bit enables the Fm+ driving mode for PB8.

0: PB8 pin operates in standard mode.

1: Fm+ mode enabled on PB8 pin, and the Speed control is bypassed.

Bit 17 I2C_PB7_FMP : Fast-mode Plus (Fm+) driving capability activation on PB7

This bit enables the Fm+ driving mode for PB7.

0: PB7 pin operates in standard mode.

1: Fm+ mode enabled on PB7 pin, and the Speed control is bypassed.

Bit 16 I2C_PB6_FMP : Fast-mode Plus (Fm+) driving capability activation on PB6

This bit enables the Fm+ driving mode for PB6.

0: PB6 pin operates in standard mode.

1: Fm+ mode enabled on PB6 pin, and the Speed control is bypassed.

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 BOOSTEN : I/O analog switch voltage booster enable

0: I/O analog switches are supplied by \( V_{DDA} \) voltage. This is the recommended configuration when using the ADC in high \( V_{DDA} \) voltage operation.

1: I/O analog switches are supplied by a dedicated voltage booster (supplied by \( V_{DD} \) ). This is the recommended configuration when using the ADC in low \( V_{DDA} \) voltage operation.

Bits 7:0 Reserved, must be kept at reset value.

11.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)

Address offset: 0x008

Reset value: 0x0000 0000

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:12 EXTI3[2:0] : EXTI 3 configuration bits

These bits are written by software to select the source input for the EXTI3 external interrupt.

000: PA[3] pin

001: PB[3] pin

010: PC[3] pin (STM32WB55xx only)

011: PD[3] pin (STM32WB55xx only)

100: PE[3] pin (STM32WB55xx only)

101: Reserved

110: Reserved

111: PH[3] pin

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 EXTI2[2:0] : EXTI 2 configuration bits

These bits are written by software to select the source input for the EXTI2 external interrupt.

000: PA[2] pin

001: PB[2] pin

010: PC[2] pin (STM32WB55xx only)

011: PD[2] pin (STM32WB55xx only)

100: PE[2] pin (STM32WB55xx only)

101: Reserved

110: Reserved

111: Reserved

Bit 7 Reserved, must be kept at reset value.

These bits are written by software to select the source input for the EXTI1 external interrupt.

000: PA[1] pin
001: PB[1] pin
010: PC[1] pin (STM32WB55xx only)
011: PD[1] pin (STM32WB55xx only)
100: PE[1] pin (STM32WB55xx only)
101: Reserved
110: Reserved
111: PH[1] pin (STM32WB55xx only)

Bit 3 Reserved, must be kept at reset value.

These bits are written by software to select the source input for the EXTI0 external interrupt.

000: PA[0] pin
001: PB[0] pin
010: PC[0] pin (STM32WB55xx only)
011: PD[0] pin (STM32WB55xx only)
100: PE[0] pin (STM32WB55xx only)
101: Reserved
110: Reserved
111: PH[0] pin (STM32WB55xx only)

Note: Some of the I/O pins mentioned in this register may be not available on small packages.

11.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)

Address offset: 0x00C

Reset value: 0x0000 0000

Bits 31:15 Reserved, must be kept at reset value.

These bits are written by software to select the source input for the EXTI7 external interrupt.

000: PA[7] pin
001: PB[7] pin
010: PC[7] pin (STM32WB55xx only)
011: PD[7] pin (STM32WB55xx only)
100: Reserved
101: Reserved
110: Reserved
111: Reserved

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 EXTI6[2:0] : EXTI 6 configuration bits

These bits are written by software to select the source input for the EXTI6 external interrupt.

000: PA[6] pin

001: PB[6] pin

010: PC[6] pin (STM32WB55xx only)

011: PD[6] pin (STM32WB55xx only)

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 EXTI5[2:0] : EXTI 5 configuration bits

These bits are written by software to select the source input for the EXTI5 external interrupt.

000: PA[5] pin

001: PB[5] pin

010: PC[5] pin (STM32WB55xx only)

011: PD[5] pin (STM32WB55xx only)

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 EXTI4[2:0] : EXTI 4 configuration bits

These bits are written by software to select the source input for the EXTI4 external interrupt.

000: PA[4] pin

001: PB[4] pin

010: PC[4] pin (STM32WB55xx only)

011: PD[4] pin (STM32WB55xx only)

100: PE[4] pin

101: Reserved

110: Reserved

111: Reserved

Note: Some of the I/O pins mentioned in this register may be not available on small packages.

11.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)

Address offset: 0x010

Reset value: 0x0000 0000

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:12 EXTI11[2:0] : EXTI 11 configuration bits

These bits are written by software to select the source input for the EXTI11 external interrupt.

000: PA[11] pin
001: PB[11] pin (STM32WB55xx only)
010: PC[11] pin (STM32WB55xx only)
011: PD[11] pin (STM32WB55xx only)
100: Reserved
101: Reserved
110: Reserved
111: Reserved

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 EXTI10[2:0] : EXTI 10 configuration bits

These bits are written by software to select the source input for the EXTI10 external interrupt.

000: PA[10] pin
001: PB[10] pin (STM32WB55xx only)
010: PC[10] pin (STM32WB55xx only)
011: PD[10] pin (STM32WB55xx only)
100: Reserved
101: Reserved
110: Reserved
111: Reserved

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 EXTI9[2:0] : EXTI 9 configuration bits

These bits are written by software to select the source input for the EXTI9 external interrupt.

000: PA[9] pin
001: PB[9] pin
010: PC[9] pin (STM32WB55xx only)
011: PD[9] pin (STM32WB55xx only)
100: Reserved
101: Reserved
110: Reserved
111: Reserved

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 EXTI8[2:0] : EXTI 8 configuration bits

These bits are written by software to select the source input for the EXTI8 external interrupt.

000: PA[8] pin

001: PB[8] pin

010: PC[8] pin (STM32WB55xx only)

011: PD[8] pin (STM32WB55xx only)

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Note: Some of the I/O pins mentioned in this register may be not available on small packages.

11.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)

Address offset: 0x014

Reset value: 0x0000 0000

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:12 EXTI15[2:0] : EXTI15 configuration bits

These bits are written by software to select the source input for the EXTI15 external interrupt.

000: PA[15] pin

001: PB[15] pin (STM32WB55xx only)

010: PC[15] pin

011: PD[15] pin (STM32WB55xx only)

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 EXTI14[2:0] : EXTI14 configuration bits

These bits are written by software to select the source input for the EXTI14 external interrupt.

000: PA[14] pin

001: PB[14] pin (STM32WB55xx only)

010: PC[14] pin

011: PD[14] pin (STM32WB55xx only)

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 EXTI13[2:0] : EXTI13 configuration bits

These bits are written by software to select the source input for the EXTI13 external interrupt.

000: PA[13] pin

001: PB[13] pin (STM32WB55xx only)

010: PC[13] pin (STM32WB55xx only)

011: PD[13] pin (STM32WB55xx only)

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 EXTI12[2:0] : EXTI12 configuration bits

These bits are written by software to select the source input for the EXTI12 external interrupt.

000: PA[12] pin

001: PB[12] pin (STM32WB55xx only)

010: PC[12] pin (STM32WB55xx only)

011: PD[12] pin (STM32WB55xx only)

100: Reserved

101: Reserved

110: Reserved

111: Reserved

Note: Some of the I/O pins mentioned in this register may be not available on small packages.

11.2.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR)

Address offset: 0x18

System reset value: 0x0000 0000

Bit 31 C2RFD : CPU2 SRAM fetch (execution) disable.

This bit can be set by software and be reset by a hardware reset, including a reset after Standby. Software writing 'b0 has no effect.

0: CPU2 fetch from SRAM1, SRAM2a and SRAM2b enabled, allows CPU2 to fetch and execute code from SRAMs

1: CPU2 fetch from SRAM1, SRAM2a and SRAM2b disabled, Any CPU2 fetch from SRAMs generates a bus error.

Bits 30:2 Reserved, must be kept at reset value.

Bit 1 SRAM2BSY : SRAM2 and PKA RAM busy by erase operation

0: Nor SRAM2 neither PKA RAM erase operation is on going.

1: SRAM2 and/or PKA RAM erase operation is on going.

Bit 0 SRAM2ER : SRAM2 and PKA RAM Erase

Setting this bit starts a hardware SRAM2 and PKA RAM erase operation. This bit is automatically cleared at the end of the SRAM2 and PKA RAM erase operation.

Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register.

11.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x01C

System reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SPF : SRAM2 parity error flag

This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing '1'.

0: No SRAM2 parity error detected

1: SRAM2 parity error detected

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 ECCL : ECC Lock

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Flash ECC error connection to TIM1/16/17 Break input.

0: ECC error disconnected from TIM1/16/17 Break input.

1: ECC error connected to TIM1/16/17 Break input.

Bit 2 PVDL : PVD lock enable bit

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.

0: PVD interrupt disconnected from TIM1/16/17 Break input. PVDE and PLS[2:0] bits can be programmed by the application.

1: PVD interrupt connected to TIM1/16/17 Break input, PVDE and PLS[2:0] bits are read only.

Bit 1 SPL : SRAM2 parity lock bit

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/16/17 Break inputs.

0: SRAM2 parity error signal disconnected from TIM1/16/17 Break inputs

1: SRAM2 parity error signal connected to TIM1/16/17 Break inputs

Bit 0 CLL : CPU1 LOCKUP (Hardfault) output enable bit

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of CPU1 LOCKUP (Hardfault) output to TIM1/16/17 Break input

0: CPU1 LOCKUP output disconnected from TIM1/16/17 Break inputs

1: CPU1 LOCKUP output connected to TIM1/16/17 Break inputs

11.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR1)

Address offset: 0x020

System reset value: 0x0000 0000

Bits 31:0 PxWP (x= 0 to 31): SRAM2 1Kbyte page x write protection

These bits are set by software and cleared only by a system reset.

0: Write protection of SRAM2 1Kbyte page x is disabled.

1: Write protection of SRAM2 1Kbyte page x is enabled.

11.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR)

Address offset: 0x024

System reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 KEY[7:0] : SRAM2 write protection key for software erase

The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register.

1. 1. Write 0xCA into Key[7:0]

1. 2. Write 0x53 into Key[7:0]

Writing a wrong key reactivates the write protection.

11.2.11 SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2)

Address offset: 0x028

System reset value: 0x0000 0000

Bits 31:0 PxWP (x= 32 to 63): SRAM2 1 Kbyte page x write protection

These bits are set by software and cleared only by a system reset.

• 0: Write protection of SRAM2 1 Kbyte page x is disabled.
• 1: Write protection of SRAM2 1 Kbyte page x is enabled.

11.2.12 SYSCFG CPU1 interrupt mask register 1 (SYSCFG_IMR1)

Address offset: 0x100

System reset value: 0x0000 0000

Bits 31:21 xxxIM : Peripheral xxx interrupt mask to CPU1

• 0: Peripheral xxx interrupt forwarded to CPU1
• 1: Peripheral xxx interrupt to CPU1 masked.

Bits 20:16 Reserved, must be kept at reset value.

Bits 15:13 xxxIM : Peripheral xxx interrupt mask to CPU1

• 0: Peripheral xxx interrupt forwarded to CPU1
• 1: Peripheral xxx interrupt to CPU1 masked.

Bits 12:0 Reserved, must be kept at reset value.

11.2.13 SYSCFG CPU1 interrupt mask register 2 (SYSCFG_IMR2)

Address offset: 0x104

System reset value: 0x0000 0000

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 xxxIM : Peripheral xxx interrupt mask to CPU1

0: Peripheral xxx interrupt forwarded to CPU1

1. Peripheral xxx interrupt to CPU1 masked.

Bit 19 Reserved, must be kept at reset value.

Bit 18 xxxIM : Peripheral xxx interrupt mask to CPU1

0: Peripheral xxx interrupt forwarded to CPU1

1. Peripheral xxx interrupt to CPU1 masked.

Bit 17 Reserved, must be kept at reset value.

Bits 16 xxxIM : Peripheral xxx interrupt mask to CPU1

0: Peripheral xxx interrupt forwarded to CPU1

1. Peripheral xxx interrupt to CPU1 masked.

Bits 15:0 Reserved, must be kept at reset value.

11.2.14 SYSCFG CPU2 interrupt mask register 1 (SYSCFG_C2IMR1)

Address offset: 0x108

System reset value: 0x0000 0000

Bits 31:16 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1. Peripheral xxx interrupt to CPU2 masked.

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:8 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1. Peripheral xxx interrupt to CPU2 masked.

Bit 7 Reserved, must be kept at reset value.

Bits 6:3 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1. Peripheral xxx interrupt to CPU2 masked.

Bits 2:1 Reserved, must be kept at reset value.

Bit 0 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1. Peripheral xxx interrupt to CPU2 masked.

11.2.15 SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2)

Address offset: 0x10C

System reset value: 0x0000 0000

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:20 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1: Peripheral xxx interrupt to CPU2 masked.

Note that bits 22:21 are reserved in STM32WB35xx devices.

Bit 19 Reserved, must be kept at reset value.

Bit 18 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1: Peripheral xxx interrupt to CPU2 masked.

Bit 17 Reserved, must be kept at reset value.

Bits 16:8 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1: Peripheral xxx interrupt to CPU2 masked.

Bit 7 Reserved, must be kept at reset value.

Bits 6:0 xxxIM : Peripheral xxx interrupt mask to CPU2

0: Peripheral xxx interrupt forwarded to CPU2

1: Peripheral xxx interrupt to CPU2 masked.

11.2.16 SYSCFG secure IP control register (SYSCFG_SIPCR)

Address offset: 0x110

System reset value: 0x0000 0000

This register provides write access security and can only be written by the CPU2. A write access from the CPU1 is ignored and a bus error is generated. On any read access the register value is returned.

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 SRNG : Enable true RNG security

0: True RNG security disabled (RNG registers can be accessed by both CPU1 and CPU2)

1: True RNG security enabled (RNG registers can only be accessed by the CPU2. Write accesses by the CPU1 generate a bus error, read access return 0 value).

Bit 2 SPKA : Enable PKA security

0: PKA security disabled (PKA registers can be accessed by both CPU1 and CPU2)

1: PKA security enabled. PKA registers can only be accessed by the CPU2. Write accesses by the CPU1 generate a bus error, read access return 0 value. When this bit is set and a system reset occurs (including a reset due to wakeup from Standby) the PKA RAM is erased.

Bit 1 SAES2 : Enable AES2 security

0: AES2 security disabled (AES2 registers can be accessed by both CPU1 and CPU2)

1: AES2 security enabled. (AES2 registers can only be accessed by the CPU2. Write accesses by the CPU1 generate a bus error, read access return 0 value).

Bit 0 SAES1 : Enable AES1 KEY[7:0] security

0: AES1 KEY[7:0] security disabled (AES1 KEY[7:0] registers can be accessed by both CPU1 and CPU2)

1: AES1 KEY[7:0] security enabled (AES1 KEY[7:0] registers can only be accessed by the CPU2. Write accesses by the CPU1 generate a bus error, read access return zero value).

11.2.17 SYSCFG register map

The following table summarizes the SYSCFG register map and the reset values.

Table 54. SYSCFG register map and reset values

Table 54. SYSCFG register map and reset values (continued)

Refer to Section 2.2 on page 66 for the register boundary addresses.