RM0434-STM32WB55-35

Introduction

This document is addressed to application developers. It provides complete information on how to use the STM32WB55xx and STM32WB35xx microcontrollers.

These multiprotocol wireless and ultra-low-power devices embed a powerful ultra-low-power radio compliant with the Bluetooth ® Low Energy SIG specification 5.4 and with IEEE 802.15.4-2011. They contain a dedicated Arm ® Cortex ® -M0+ for performing the real-time low layer operation.

The STM32WB55xx and STM32WB35xx microcontrollers feature different memory sizes, packages and peripherals, and include ST state of the art patented technology.

Available from STMicroelectronics web site www.st.com :

For information on the Arm ® Cortex ® -M4 and Cortex ® -M0+ cores, refer, respectively, to the corresponding Technical Reference Manuals, available from the www.arm.com website.

For information on 802.15.4 refer to the IEEE website ( www.ieee.org ).

For information on Bluetooth ® refer to www.bluetooth.com .

Contents

3.3.6Flash memory program and erase operations . . . . .83
3.3.7Flash main memory erase sequences . . . . .84
3.3.8Flash main memory programming sequences . . . . .86
3.4FLASH option bytes . . . . .91
3.4.1Option bytes description . . . . .91
3.4.2Option bytes programming . . . . .98
3.5FLASH UID64 . . . . .101
3.6Flash memory protection . . . . .102
3.6.1Read protection (RDP) . . . . .102
3.6.2Proprietary code readout protection (PCROP) . . . . .106
3.6.3Write protection (WRP) . . . . .107
3.6.4CPU2 security (ESE) . . . . .108
3.7FLASH program/erase suspension . . . . .109
3.8FLASH interrupts . . . . .110
3.9Register access protection . . . . .110
3.10FLASH registers . . . . .111
3.10.1Flash memory access control register (FLASH_ACR) . . . . .111
3.10.2Flash memory key register (FLASH_KEYR) . . . . .112
3.10.3Flash memory option key register (FLASH_OPTKEYR) . . . . .112
3.10.4Flash memory status register (FLASH_SR) . . . . .113
3.10.5Flash memory control register (FLASH_CR) . . . . .114
3.10.6Flash memory ECC register (FLASH_ECCR) . . . . .116
3.10.7Flash memory option register (FLASH_OPTR) . . . . .117
3.10.8Flash memory PCROP zone A start address register
(FLASH_PCROP1ASR) . . . . .		119
3.10.9Flash memory PCROP zone A end address register
(FLASH_PCROP1AER) . . . . .		120
3.10.10Flash memory WRP area A address register (FLASH_WRP1AR) . . . . .120
3.10.11Flash memory WRP area B address register (FLASH_WRP1BR) . . . . .121
3.10.12Flash memory PCROP zone B start address register
(FLASH_PCROP1BSR) . . . . .		121
3.10.13Flash memory PCROP zone B end address register
(FLASH_PCROP1BER) . . . . .		122
3.10.14Flash memory IPCC mailbox data buffer address register
(FLASH_IPCCBR) . . . . .		122
3.10.15Flash memory CPU2 access control register (FLASH_C2ACR) . . . . .122
3.10.16Flash memory CPU2 status register (FLASH_C2SR) . . . . .123
3.10.17Flash memory CPU2 control register (FLASH_C2CR) . . . . .125
5.4.12Auto wake-up from Low-power mode .....165
5.5Real-time radio information .....166
5.6PWR registers .....167
5.6.1PWR control register 1 (PWR_CR1) .....167
5.6.2PWR control register 2 (PWR_CR2) .....168
5.6.3PWR control register 3 (PWR_CR3) .....169
5.6.4PWR control register 4 (PWR_CR4) .....171
5.6.5PWR status register 1 (PWR_SR1) .....172
5.6.6PWR status register 2 (PWR_SR2) .....173
5.6.7PWR status clear register (PWR_SCR) .....174
5.6.8PWR control register 5 (PWR_CR5) .....175
5.6.9PWR Port A pull-up control register (PWR_PUCRA) .....176
5.6.10PWR Port A pull-down control register (PWR_PDCRA) .....177
5.6.11PWR Port B pull-up control register (PWR_PUCRB) .....177
5.6.12PWR Port B pull-down control register (PWR_PDCRB) .....178
5.6.13PWR Port C pull-up control register (PWR_PUCRC) .....178
5.6.14PWR Port C pull-down control register (PWR_PDCRC) .....179
5.6.15PWR Port D pull-up control register (PWR_PUCRD)
(STM32WB55xx only) .....		179
5.6.16PWR Port D pull-down control register (PWR_PDCRD)
(STM32WB55xx only) .....		180
5.6.17PWR Port E pull-up control register (PWR_PUCRE) .....180
5.6.18PWR Port E pull-down control register (PWR_PDCRE) .....181
5.6.19PWR Port H pull-up control register (PWR_PUCRH) .....181
5.6.20PWR Port H pull-down control register (PWR_PDCRH) .....182
5.6.21PWR CPU2 control register 1 (PWR_C2CR1) .....182
5.6.22PWR CPU2 control register 3 (PWR_C2CR3) .....184
5.6.23PWR extended status and status clear register (PWR_EXTSCR) .....185
5.6.24PWR register map and reset value table .....187
6Reset and clock control (RCC) .....189
6.1Reset .....189
6.1.1Power reset .....189
6.1.2System reset .....189
6.1.3Backup domain reset .....191
6.2Clocks .....191
6.2.1HSE clock .....195
6.2.2HSI16 clock .....196
6.2.3MSI clock .....196
6.2.4HSI48 clock .....197
6.2.5PLLs .....198
6.2.6LSE clock .....198
6.2.7LSI1 clock .....199
6.2.8LSI2 clock .....200
6.2.9System clock (SYSCLK) selection .....200
6.2.10Clock source frequency versus voltage scaling .....200
6.2.11Clock security system (CSS) on HSE .....201
6.2.12Clock security system on LSE (LSECSS) .....201
6.2.13LSI source selection .....202
6.2.14SMPS step-down converter clock .....202
6.2.15ADC clock .....203
6.2.16RTC clock .....203
6.2.17Timer clock .....203
6.2.18Watchdog clock .....204
6.2.19True RNG clock .....204
6.2.20Clock-out capability .....204
6.2.21Internal/external clock measurement with TIM16/TIM17 .....205
6.2.22Peripheral clocks enable .....206
6.3Low-power modes .....208
6.4RCC registers .....210
6.4.1RCC clock control register (RCC_CR) .....210
6.4.2RCC internal clock sources calibration register (RCC_ICSCR) .....213
6.4.3RCC clock configuration register (RCC_CFGR) .....214
6.4.4RCC PLL configuration register (RCC_PLLCFGR) .....216
6.4.5RCC PLLSAI1 configuration register (RCC_PLLSAI1CFGR) .....220
6.4.6RCC clock interrupt enable register (RCC_CIER) .....222
6.4.7RCC clock interrupt flag register (RCC_CIFR) .....223
6.4.8RCC clock interrupt clear register (RCC_CICR) .....225
6.4.9RCC SMPS step-down converter control register (RCC_SMPSSCR) ..226
6.4.10RCC AHB1 peripheral reset register (RCC_AHB1RSTR) .....227
6.4.11RCC AHB2 peripheral reset register (RCC_AHB2RSTR) .....228
6.4.12RCC AHB3 and AHB4 peripheral reset register (RCC_AHB3RSTR) .229
6.4.13RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) .....230
6.4.14RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) .....232
6.4.15RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .232
6.4.16RCC APB3 peripheral reset register (RCC_APB3RSTR) . . . . .233
6.4.17RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .234
6.4.18RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .235
6.4.19RCC AHB3 and AHB4 peripheral clock enable register
(RCC_AHB3ENR) . . . . .		236
6.4.20RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . .237
6.4.21RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . .239
6.4.22RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .239
6.4.23RCC AHB1 peripheral clocks enable in Sleep modes register
(RCC_AHB1SMENR) . . . . .		240
6.4.24RCC AHB2 peripheral clocks enable in Sleep modes register
(RCC_AHB2SMENR) . . . . .		241
6.4.25RCC AHB3 and AHB4 peripheral clocks enable in Sleep and Stop
modes register (RCC_AHB3SMENR) . . . . .		243
6.4.26RCC APB1 peripheral clocks enable in Sleep mode register 1
(RCC_APB1SMENR1) . . . . .		244
6.4.27RCC APB1 peripheral clocks enable in Sleep mode register 2
(RCC_APB1SMENR2) . . . . .		246
6.4.28RCC APB2 peripheral clocks enable in Sleep mode register
(RCC_APB2SMENR) . . . . .		246
6.4.29RCC peripherals independent clock configuration register
(RCC_CCIPR) . . . . .		248
6.4.30RCC backup domain control register (RCC_BDCR) . . . . .249
6.4.31RCC control/status register (RCC_CSR) . . . . .251
6.4.32RCC clock recovery RC register (RCC_CRRRCR) . . . . .253
6.4.33RCC clock HSE register (RCC_HSECR) . . . . .254
6.4.34RCC extended clock recovery register (RCC_EXTCFGR) . . . . .255
6.4.35RCC CPU2 AHB1 peripheral clock enable register
(RCC_C2AHB1ENR) . . . . .		257
6.4.36RCC CPU2 AHB2 peripheral clock enable register
(RCC_C2AHB2ENR) . . . . .		258
6.4.37RCC CPU2 AHB3 and AHB4 peripheral clock enable register
(RCC_C2AHB3ENR) . . . . .		259
6.4.38RCC CPU2 APB1 peripheral clock enable register 1
(RCC_C2APB1ENR1) . . . . .		260
6.4.39RCC CPU2 APB1 peripheral clock enable register 2
(RCC_C2APB1ENR2) . . . . .		262
6.4.40RCC CPU2 APB2 peripheral clock enable register
(RCC_C2APB2ENR) . . . . .		262
6.4.41RCC CPU2 APB3 peripheral clock enable register (RCC_C2APB3ENR) .....263
6.4.42RCC CPU2 AHB1 peripheral clocks enable in Sleep modes register (RCC_C2AHB1SMENR) .....264
6.4.43RCC CPU2 AHB2 peripheral clocks enable in Sleep modes register (RCC_C2AHB2SMENR) .....265
6.4.44RCC CPU2 AHB3 and AHB4 peripheral clocks enable in Sleep mode register (RCC_C2AHB3SMENR) .....267
6.4.45RCC CPU2 APB1 peripheral clocks enable in Sleep mode register 1 (RCC_C2APB1SMENR1) .....268
6.4.46RCC CPU2 APB1 peripheral clocks enable in Sleep mode register 2 (RCC_C2APB1SMENR2) .....269
6.4.47RCC CPU2 APB2 peripheral clocks enable in Sleep mode register (RCC_C2APB2SMENR) .....270
6.4.48RCC CPU2 APB3 peripheral clock enable in Sleep mode register (RCC_C2APB3SMENR) .....271
6.4.49RCC register map .....272
7Clock recovery system (CRS) .....278
7.1CRS introduction .....278
7.2CRS main features .....278
7.3CRS implementation .....278
7.4CRS functional description .....279
7.4.1CRS block diagram .....279
7.4.2CRS internal signals .....279
7.4.3Synchronization input .....280
7.4.4Frequency error measurement .....280
7.4.5Frequency error evaluation and automatic trimming .....281
7.4.6CRS initialization and configuration .....282
7.5CRS in low-power modes .....283
7.6CRS interrupts .....283
7.7CRS registers .....283
7.7.1CRS control register (CRS_CR) .....283
7.7.2CRS configuration register (CRS_CFGR) .....285
7.7.3CRS interrupt and status register (CRS_ISR) .....286
7.7.4CRS interrupt flag clear register (CRS_ICR) .....288
7.7.5CRS register map .....288
8Hardware semaphore (HSEM) .....290
8.1HSEM introduction . . . . .290
8.2HSEM main features . . . . .290
8.3Functional description . . . . .291
8.3.1HSEM block diagram . . . . .291
8.3.2HSEM internal signals . . . . .291
8.3.3HSEM lock procedures . . . . .291
8.3.4HSEM write/read/read lock register address . . . . .293
8.3.5HSEM unlock procedures . . . . .293
8.3.6HSEM COREID semaphore clear . . . . .294
8.3.7HSEM interrupts . . . . .294
8.3.8AHB bus master ID verification . . . . .296
8.4HSEM registers . . . . .297
8.4.1HSEM register semaphore x (HSEM_Rx) . . . . .297
8.4.2HSEM read lock register semaphore x (HSEM_RLRx) . . . . .298
8.4.3HSEM interrupt enable register (HSEM_CnIER) . . . . .299
8.4.4HSEM interrupt clear register (HSEM_CnICR) . . . . .299
8.4.5HSEM interrupt status register (HSEM_CnISR) . . . . .299
8.4.6HSEM interrupt status register (HSEM_CnMISR) . . . . .300
8.4.7HSEM clear register (HSEM_CR) . . . . .300
8.4.8HSEM clear semaphore key register (HSEM_KEYR) . . . . .301
8.4.9HSEM register map . . . . .302
9Inter-processor communication controller (IPCC) . . . . .304
9.1Introduction . . . . .304
9.2IPCC main features . . . . .304
9.3IPCC functional description . . . . .304
9.3.1IPCC block diagram . . . . .305
9.3.2IPCC Simplex channel mode . . . . .305
9.3.3IPCC Half-duplex channel mode . . . . .308
9.3.4IPCC interrupts . . . . .311
9.4IPCC registers . . . . .312
9.4.1IPCC processor 1 control register (IPCC_C1CR) . . . . .312
9.4.2IPCC processor 1 mask register (IPCC_C1MR) . . . . .312
9.4.3IPCC processor 1 status set clear register (IPCC_C1SCR) . . . . .313
9.4.4IPCC processor 1 to processor 2 status register
(IPCC_C1TOC2SR) . . . . .		313
9.4.5IPCC processor 2 control register (IPCC_C2CR) . . . . .314
9.4.6IPCC processor 2 mask register (IPCC_C2MR) . . . . .314
9.4.7IPCC processor 2 status set clear register (IPCC_C2SCR) . . . . .315
9.4.8IPCC processor 2 to processor 1 status register
(IPCC_C2TOC1SR) . . . . .		316
9.4.9IPCC register map . . . . .317
10General-purpose I/Os (GPIO) . . . . .318
10.1Introduction . . . . .318
10.2GPIO main features . . . . .318
10.3GPIO implementation . . . . .318
10.4GPIO functional description . . . . .319
10.4.1General-purpose I/O (GPIO) . . . . .321
10.4.2I/O pin alternate function multiplexer and mapping . . . . .321
10.4.3I/O port control registers . . . . .322
10.4.4I/O port data registers . . . . .322
10.4.5I/O data bitwise handling . . . . .322
10.4.6GPIO locking mechanism . . . . .323
10.4.7I/O alternate function input/output . . . . .323
10.4.8External interrupt/wakeup lines . . . . .323
10.4.9Input configuration . . . . .323
10.4.10Output configuration . . . . .324
10.4.11Alternate function configuration . . . . .325
10.4.12Analog configuration . . . . .325
10.4.13Using the LSE oscillator pins as GPIOs . . . . .326
10.4.14Using the GPIO pins in the RTC supply domain . . . . .326
10.4.15Using PH3 as GPIO . . . . .326
10.5GPIO registers . . . . .327
10.5.1GPIO port mode register (GPIOx_MODER)
(x =A to E and H) . . . . .		327
10.5.2GPIO port output type register (GPIOx_OTYPER)
(x = A to E and H) . . . . .		328
10.5.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to E and H) . . . . .		328
10.5.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to E and H) . . . . .		329
10.5.5GPIO port input data register (GPIOx_IDR)
(x = A to E and H) . . . . .		329
10.5.6GPIO port output data register (GPIOx_ODR)
(x = A to E and H) . . . . .		330
10.5.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to E and H) . . . . .		330
10.5.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to E and H) . . . . .		331
10.5.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to E and H) . . . . .		332
10.5.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to E and H) . . . . .		333
10.5.11GPIO port bit reset register (GPIOx_BRR) (x = A to E and H) . . . . .334
10.5.12GPIO register map . . . . .335
11System configuration controller (SYSCFG) . . . . .338
11.1SYSCFG main features . . . . .338
11.2SYSCFG registers . . . . .338
11.2.1SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .338
11.2.2SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .339
11.2.3SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . .		340
11.2.4SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . .		341
11.2.5SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . .		342
11.2.6SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . .		344
11.2.7SYSCFG SRAM2 control and status register (SYSCFG_SCSR) . . . . .345
11.2.8SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .346
11.2.9SYSCFG SRAM2 write protection register (SYSCFG_SWPR1) . . . . .347
11.2.10SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . .347
11.2.11SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2) . . . . .347
11.2.12SYSCFG CPU1 interrupt mask register 1 (SYSCFG_IMR1) . . . . .348
11.2.13SYSCFG CPU1 interrupt mask register 2 (SYSCFG_IMR2) . . . . .348
11.2.14SYSCFG CPU2 interrupt mask register 1 (SYSCFG_C2IMR1) . . . . .349
11.2.15SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2) . . . . .350
11.2.16SYSCFG secure IP control register (SYSCFG_SIPCR) . . . . .350
11.2.17SYSCFG register map . . . . .352
12Peripherals interconnect matrix . . . . .354
12.1Introduction . . . . .354
12.2Interconnect matrix implementation . . . . .354
12.3Connection summary . . . . .354
12.4Interconnection details . . . . .355
12.4.1From timer (TIM1/TIM2/TIM17) to timer (TIM1/TIM2) . . . . .355
12.4.2From timer (TIM1/TIM2) and EXTI to ADC (ADC1) . . . . .356
12.4.3From ADC (ADC1) to timer (TIM1) . . . . .356
12.4.4From HSE, LSE, LSI, MSI, MCO, RTC to timers
(TIM2/TIM16/TIM17) . . . . .		356
12.4.5From RTC, COMP1, COMP2 to low-power timers (LPTIM1/LPTIM2) . . . . .357
12.4.6From timer (TIM1/TIM2) to comparators (COMP1/COMP2) . . . . .357
12.4.7From USB to timer (TIM2) . . . . .358
12.4.8From internal analog to ADC1 . . . . .358
12.4.9From comparators (COMP1/COMP2) to timers
(TIM1/TIM2/TIM16/TIM17) . . . . .		358
12.4.10From system errors to timers (TIM1/TIM16/TIM17) . . . . .359
12.4.11From timers (TIM16/TIM17) to IRTIM . . . . .359
13Direct memory access controller (DMA) . . . . .360
13.1Introduction . . . . .360
13.2DMA main features . . . . .360
13.3DMA implementation . . . . .361
13.3.1DMA1 and DMA2 . . . . .361
13.3.2DMA request mapping . . . . .361
13.4DMA functional description . . . . .362
13.4.1DMA block diagram . . . . .362
13.4.2DMA pins and internal signals . . . . .363
13.4.3DMA transfers . . . . .363
13.4.4DMA arbitration . . . . .364
13.4.5DMA channels . . . . .364
13.4.6DMA data width, alignment, and endianness . . . . .368
13.4.7DMA error management . . . . .369
13.5DMA interrupts . . . . .370
13.6DMA registers . . . . .370
13.6.1DMA interrupt status register (DMA_ISR) . . . . .370
13.6.2DMA interrupt flag clear register (DMA_IFCR) . . . . .372
13.6.3DMA channel x configuration register (DMA_CCRx) . . . . .374
13.6.4DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . .376
13.6.5DMA channel x peripheral address register (DMA_CPARx) . . . . .377
13.6.6DMA channel x memory address register (DMA_CMARx) . . . . .378
13.6.7DMA register map . . . . .378
14DMA request multiplexer (DMAMUX) . . . . .381
14.1Introduction . . . . .381
14.2DMAMUX main features . . . . .382
14.3DMAMUX implementation . . . . .382
14.3.1DMAMUX instantiation . . . . .382
14.3.2DMAMUX mapping . . . . .382
14.4DMAMUX functional description . . . . .385
14.4.1DMAMUX block diagram . . . . .385
14.4.2DMAMUX signals . . . . .386
14.4.3DMAMUX channels . . . . .386
14.4.4DMAMUX request line multiplexer . . . . .386
14.4.5DMAMUX request generator . . . . .389
14.5DMAMUX interrupts . . . . .390
14.6DMAMUX registers . . . . .391
14.6.1DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR) . . . . .		391
14.6.2DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR) . . . . .		392
14.6.3DMAMUX request line multiplexer interrupt clear flag register
(DMAMUX_CFR) . . . . .		392
14.6.4DMAMUX request generator channel x configuration register
(DMAMUX_RGxCR) . . . . .		393
14.6.5DMAMUX request generator interrupt status register
(DMAMUX_RGSR) . . . . .		394
14.6.6DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR) . . . . .		394
14.6.7DMAMUX register map . . . . .395
15Nested vectored interrupt controller (NVIC) . . . . .398
15.1NVIC main features . . . . .398
15.2NVIC implementation . . . . .398
15.3Interrupt block diagram . . . . .398
15.4Interrupt and exception vectors . . . . .399
15.5Interrupt list . . . . .405
16Extended interrupt and event controller (EXTI) . . . . .407
16.1EXTI main features . . . . .407
16.2EXTI implementation . . . . .407
16.3EXTI block diagram . . . . .408
16.3.1EXTI connections between peripherals and CPU . . . . .409
16.4EXTI functional description . . . . .410
16.4.1EXTI configurable event input wakeup . . . . .410
16.4.2EXTI direct event input wakeup . . . . .412
16.5EXTI functional behavior . . . . .412
16.6EXTI registers . . . . .414
16.6.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .414
16.6.2EXTI falling trigger selection register (EXTI_FTSR1) . . . . .415
16.6.3EXTI software interrupt event register (EXTI_SWIER1) . . . . .415
16.6.4EXTI pending register (EXTI_PR1) . . . . .416
16.6.5EXTI rising trigger selection register (EXTI_RTSR2) . . . . .416
16.6.6EXTI falling trigger selection register (EXTI_FTSR2) . . . . .417
16.6.7EXTI software interrupt event register (EXTI_SWIER2) . . . . .418
16.6.8EXTI pending register (EXTI_PR2) . . . . .419
16.6.9EXTI CPU wakeup with interrupt mask register (EXTI_IMR1) . . . . .419
16.6.10EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR1) . . . . .420
16.6.11EXTI CPU wakeup with event mask register (EXTI_EMR1) . . . . .420
16.6.12EXTI CPU2 wakeup with event mask register (EXTI_C2EMR1) . . . . .421
16.6.13EXTI CPU wakeup with interrupt mask register (EXTI_IMR2) . . . . .421
16.6.14EXTI CPU2 wakeup with interrupt mask register (EXTI_C2IMR2) . . . . .422
16.6.15EXTI CPU wakeup with event mask register (EXTI_EMR2) . . . . .422
16.6.16EXTI CPU2 wakeup with event mask register (EXTI_C2EMR2) . . . . .423
16.6.17EXTI register map . . . . .424
17Cyclic redundancy check calculation unit (CRC) . . . . .426
17.1CRC introduction . . . . .426
17.2CRC main features . . . . .426
17.3CRC functional description . . . . .427
17.3.1CRC block diagram . . . . .427
17.3.2CRC internal signals . . . . .427
17.3.3CRC operation . . . . .427
17.4CRC registers . . . . .429
17.4.1CRC data register (CRC_DR) .....429
17.4.2CRC independent data register (CRC_IDR) .....429
17.4.3CRC control register (CRC_CR) .....430
17.4.4CRC initial value (CRC_INIT) .....431
17.4.5CRC polynomial (CRC_POL) .....431
17.4.6CRC register map .....432
18Quad-SPI interface (QUADSPI) .....433
18.1Introduction .....433
18.2QUADSPI main features .....433
18.3QUADSPI functional description .....433
18.3.1QUADSPI block diagram .....433
18.3.2QUADSPI pins .....434
18.3.3QUADSPI command sequence .....434
18.3.4QUADSPI signal interface protocol modes .....436
18.3.5QUADSPI indirect mode .....438
18.3.6QUADSPI automatic status-polling mode .....439
18.3.7QUADSPI memory-mapped mode .....440
18.3.8QUADSPI flash memory configuration .....441
18.3.9QUADSPI delayed data sampling .....441
18.3.10QUADSPI configuration .....441
18.3.11QUADSPI use .....442
18.3.12Sending the instruction only once .....444
18.3.13QUADSPI error management .....444
18.3.14QUADSPI busy bit and abort functionality .....444
18.3.15NCS behavior .....444
18.4QUADSPI interrupts .....446
18.5QUADSPI registers .....447
18.5.1QUADSPI control register (QUADSPI_CR) .....447
18.5.2QUADSPI device configuration register (QUADSPI_DCR) .....449
18.5.3QUADSPI status register (QUADSPI_SR) .....450
18.5.4QUADSPI flag clear register (QUADSPI_FCR) .....451
18.5.5QUADSPI data length register (QUADSPI_DLR) .....451
18.5.6QUADSPI communication configuration register (QUADSPI_CCR) ..452
18.5.7QUADSPI address register (QUADSPI_AR) .....454
18.5.8QUADSPI alternate-byte register (QUADSPI_ABR) .....454
18.5.9QUADSPI data register (QUADSPI_DR) .....455

19        Analog-to-digital converter (ADC) . . . . . 459

19.4.25Timing diagrams example (single/continuous modes, hardware/software triggers) . . . . .492
19.4.26Data management . . . . .494
19.4.27Dynamic low-power features . . . . .499
19.4.28Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . .504
19.4.29Oversampler . . . . .508
19.4.30Temperature sensor . . . . .513
19.4.31VBAT supply monitoring . . . . .515
19.4.32Monitoring the internal voltage reference . . . . .515
19.5ADC in low-power mode . . . . .517
19.6ADC interrupts . . . . .518
19.7ADC registers . . . . .519
19.7.1ADC interrupt and status register (ADC_ISR) . . . . .519
19.7.2ADC interrupt enable register (ADC_IER) . . . . .521
19.7.3ADC control register (ADC_CR) . . . . .523
19.7.4ADC configuration register (ADC_CFGR) . . . . .526
19.7.5ADC configuration register 2 (ADC_CFGR2) . . . . .530
19.7.6ADC sample time register 1 (ADC_SMPR1) . . . . .531
19.7.7ADC sample time register 2 (ADC_SMPR2) . . . . .532
19.7.8ADC watchdog threshold register 1 (ADC_TR1) . . . . .533
19.7.9ADC watchdog threshold register 2 (ADC_TR2) . . . . .533
19.7.10ADC watchdog threshold register 3 (ADC_TR3) . . . . .534
19.7.11ADC regular sequence register 1 (ADC_SQR1) . . . . .535
19.7.12ADC regular sequence register 2 (ADC_SQR2) . . . . .536
19.7.13ADC regular sequence register 3 (ADC_SQR3) . . . . .537
19.7.14ADC regular sequence register 4 (ADC_SQR4) . . . . .538
19.7.15ADC regular data register (ADC_DR) . . . . .538
19.7.16ADC injected sequence register (ADC_JSQR) . . . . .539
19.7.17ADC offset y register (ADC_OF Ry) . . . . .541
19.7.18ADC injected channel y data register (ADC_JDRy) . . . . .542
19.7.19ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . .542
19.7.20ADC analog watchdog 3 configuration register (ADC_AWD3CR) . . . . .543
19.7.21ADC differential mode selection register (ADC_DIFSEL) . . . . .543
19.7.22ADC calibration factors (ADC_CALFACT) . . . . .544
19.8ADC common registers . . . . .544
19.8.1ADC common status register (ADC_CSR) . . . . .544
19.8.2ADC common control register (ADC_CCR) . . . . .545
19.9ADC register map . . . . .547
20Voltage reference buffer (VREFBUF) . . . . .550
20.1VREFBUF introduction . . . . .550
20.2VREFBUF implementation . . . . .550
20.3VREFBUF functional description . . . . .550
20.4VREFBUF trimming . . . . .551
20.5VREFBUF registers . . . . .552
20.5.1VREFBUF control and status register (VREFBUF_CSR) . . . . .552
20.5.2VREFBUF calibration control register (VREFBUF_CCR) . . . . .553
20.5.3VREFBUF register map . . . . .553
21Comparator (COMP) . . . . .554
21.1COMP introduction . . . . .554
21.2COMP main features . . . . .554
21.3COMP functional description . . . . .555
21.3.1COMP block diagram . . . . .555
21.3.2COMP pins and internal signals . . . . .555
21.3.3COMP reset and clocks . . . . .557
21.3.4Comparator LOCK mechanism . . . . .557
21.3.5Window comparator . . . . .557
21.3.6Hysteresis . . . . .558
21.3.7Comparator output blanking function . . . . .559
21.3.8COMP power and speed modes . . . . .559
21.4COMP low-power modes . . . . .560
21.5COMP interrupts . . . . .560
21.6COMP registers . . . . .561
21.6.1Comparator 1 control and status register (COMP1_CSR) . . . . .561
21.6.2Comparator 2 control and status register (COMP2_CSR) . . . . .563
21.6.3COMP register map . . . . .566
22Liquid crystal display controller (LCD) . . . . .567
22.1LCD introduction . . . . .567
22.2LCD main features . . . . .567
22.3LCD functional description . . . . .569
22.3.1General description .....569
22.3.2Frequency generator .....570
22.3.3Common driver .....571
22.3.4Segment driver .....574
22.3.5Voltage generator and contrast control .....578
22.3.6Double-buffer memory .....581
22.3.7COM and SEG multiplexing .....581
22.3.8Flowchart .....587
22.4LCD low-power modes .....588
22.5LCD interrupts .....588
22.6LCD registers .....589
22.6.1LCD control register (LCD_CR) .....589
22.6.2LCD frame control register (LCD_FCR) .....590
22.6.3LCD status register (LCD_SR) .....592
22.6.4LCD clear register (LCD_CLR) .....593
22.6.5LCD display memory (LCD_RAMx) .....594
22.6.6LCD display memory (LCD_RAMx) .....594
22.6.7LCD display memory (LCD_RAMx) .....595
22.6.8LCD register map .....595
23Touch sensing controller (TSC) .....598
23.1TSC introduction .....598
23.2TSC main features .....598
23.3TSC functional description .....598
23.3.1TSC block diagram .....598
23.3.2Surface charge transfer acquisition overview .....599
23.3.3Reset and clocks .....602
23.3.4Charge transfer acquisition sequence .....602
23.3.5Spread spectrum feature .....603
23.3.6Max count error .....604
23.3.7Sampling capacitor I/O and channel I/O mode selection .....604
23.3.8Acquisition mode .....605
23.3.9I/O hysteresis and analog switch control .....605
23.4TSC low-power modes .....606
23.5TSC interrupts .....606
23.6TSC registers .....606

23.6.1 TSC control register (TSC_CR) . . . . . 606

23.6.2 TSC interrupt enable register (TSC_IER) . . . . . 609

23.6.3 TSC interrupt clear register (TSC_ICR) . . . . . 609

23.6.4 TSC interrupt status register (TSC_ISR) . . . . . 610

23.6.5 TSC I/O hysteresis control register (TSC_IOHCR) . . . . . 610

23.6.6 TSC I/O analog switch control register
(TSC_IOASCR) . . . . . 611

23.6.7 TSC I/O sampling control register (TSC_IOSCR) . . . . . 611

23.6.8 TSC I/O channel control register (TSC_IOCCR) . . . . . 612

23.6.9 TSC I/O group control status register (TSC_IOGCSR) . . . . . 612

23.6.10 TSC I/O group x counter register (TSC_IOGxCR) . . . . . 613

23.6.11 TSC register map . . . . . 613

24 True random number generator (RNG) . . . . . 616

24.1 RNG introduction . . . . . 616

24.2 RNG main features . . . . . 616

24.3 RNG functional description . . . . . 617

24.3.1 RNG block diagram . . . . . 617

24.3.2 RNG internal signals . . . . . 617

24.3.3 Random number generation . . . . . 618

24.3.4 RNG initialization . . . . . 620

24.3.5 RNG operation . . . . . 621

24.3.6 RNG clocking . . . . . 622

24.3.7 Error management . . . . . 622

24.3.8 RNG low-power use . . . . . 623

24.4 RNG interrupts . . . . . 623

24.5 RNG processing time . . . . . 623

24.6 RNG entropy source validation . . . . . 624

24.6.1 Introduction . . . . . 624

24.6.2 Validation conditions . . . . . 624

24.7 RNG registers . . . . . 625

24.7.1 RNG control register (RNG_CR) . . . . . 625

24.7.2 RNG status register (RNG_SR) . . . . . 625

24.7.3 RNG data register (RNG_DR) . . . . . 626

24.7.4 RNG register map . . . . . 627

25 AES hardware accelerator (AES) . . . . . 628

25.1Introduction . . . . .628
25.2AES main features . . . . .628
25.3AES implementation . . . . .628
25.4AES functional description . . . . .629
25.4.1AES block diagram . . . . .629
25.4.2AES internal signals . . . . .629
25.4.3AES cryptographic core . . . . .629
25.4.4AES procedure to perform a cipher operation . . . . .635
25.4.5AES decryption round key preparation . . . . .638
25.4.6AES ciphertext stealing and data padding . . . . .639
25.4.7AES task suspend and resume . . . . .639
25.4.8AES basic chaining modes (ECB, CBC) . . . . .640
25.4.9AES counter (CTR) mode . . . . .645
25.4.10AES Galois/counter mode (GCM) . . . . .647
25.4.11AES Galois message authentication code (GMAC) . . . . .652
25.4.12AES counter with CBC-MAC (CCM) . . . . .654
25.4.13AES data registers and data swapping . . . . .659
25.4.14AES key registers . . . . .661
25.4.15AES initialization vector registers . . . . .661
25.4.16AES DMA interface . . . . .662
25.4.17AES error management . . . . .663
25.5AES interrupts . . . . .664
25.6AES processing latency . . . . .664
25.7AES registers . . . . .665
25.7.1AES control register (AES_CR) . . . . .665
25.7.2AES status register (AES_SR) . . . . .668
25.7.3AES data input register (AES_DINR) . . . . .669
25.7.4AES data output register (AES_DOUTR) . . . . .669
25.7.5AES key register 0 (AES_KEYR0) . . . . .670
25.7.6AES key register 1 (AES_KEYR1) . . . . .671
25.7.7AES key register 2 (AES_KEYR2) . . . . .671
25.7.8AES key register 3 (AES_KEYR3) . . . . .671
25.7.9AES initialization vector register 0 (AES_IVR0) . . . . .672
25.7.10AES initialization vector register 1 (AES_IVR1) . . . . .672
25.7.11AES initialization vector register 2 (AES_IVR2) . . . . .672
25.7.12AES initialization vector register 3 (AES_IVR3) . . . . .673

26 Public key accelerator (PKA) . . . . . 677

26.5.1Supported elliptic curves .....695
26.5.2Computation times .....697
26.6PKA interrupts .....698
26.7PKA registers .....699
26.7.1PKA control register (PKA_CR) .....699
26.7.2PKA status register (PKA_SR) .....700
26.7.3PKA clear flag register (PKA_CLRFR) .....701
26.7.4PKA RAM .....701
26.7.5PKA register map .....702
27Advanced-control timer (TIM1) .....703
27.1TIM1 introduction .....703
27.2TIM1 main features .....704
27.3TIM1 functional description .....706
27.3.1Time-base unit .....706
27.3.2Counter modes .....708
27.3.3Repetition counter .....719
27.3.4External trigger input .....721
27.3.5Clock selection .....722
27.3.6Capture/compare channels .....726
27.3.7Input capture mode .....728
27.3.8PWM input mode .....729
27.3.9Forced output mode .....730
27.3.10Output compare mode .....731
27.3.11PWM mode .....732
27.3.12Asymmetric PWM mode .....735
27.3.13Combined PWM mode .....736
27.3.14Combined 3-phase PWM mode .....737
27.3.15Complementary outputs and dead-time insertion .....738
27.3.16Using the break function .....740
27.3.17Bidirectional break inputs .....746
27.3.18Clearing the OCxREF signal on an external event .....748
27.3.196-step PWM generation .....749
27.3.20One-pulse mode .....750
27.3.21Retriggerable one pulse mode .....751
27.3.22Encoder interface mode .....752
27.3.23UIF bit remapping .....754
27.3.24Timer input XOR function . . . . .755
27.3.25Interfacing with Hall sensors . . . . .755
27.3.26Timer synchronization . . . . .758
27.3.27ADC synchronization . . . . .762
27.3.28DMA burst mode . . . . .762
27.3.29Debug mode . . . . .763
27.4TIM1 registers . . . . .764
27.4.1TIM1 control register 1 (TIM1_CR1) . . . . .764
27.4.2TIM1 control register 2 (TIM1_CR2) . . . . .765
27.4.3TIM1 slave mode control register
(TIM1_SMCR) . . . . .		768
27.4.4TIM1 DMA/interrupt enable register
(TIM1_DIER) . . . . .		770
27.4.5TIM1 status register (TIM1_SR) . . . . .772
27.4.6TIM1 event generation register (TIM1_EGR) . . . . .774
27.4.7TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . .775
27.4.8TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . .		776
27.4.9TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . .779
27.4.10TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . .		780
27.4.11TIM1 capture/compare enable register
(TIM1_CCER) . . . . .		781
27.4.12TIM1 counter (TIM1_CNT) . . . . .785
27.4.13TIM1 prescaler (TIM1_PSC) . . . . .785
27.4.14TIM1 auto-reload register (TIM1_ARR) . . . . .785
27.4.15TIM1 repetition counter register (TIM1_RCR) . . . . .786
27.4.16TIM1 capture/compare register 1
(TIM1_CCR1) . . . . .		786
27.4.17TIM1 capture/compare register 2
(TIM1_CCR2) . . . . .		787
27.4.18TIM1 capture/compare register 3
(TIM1_CCR3) . . . . .		787
27.4.19TIM1 capture/compare register 4
(TIM1_CCR4) . . . . .		788
27.4.20TIM1 break and dead-time register
(TIM1_BDTR) . . . . .		788
27.4.21TIM1 DMA control register
(TIM1_DCR) . . . . .		792
27.4.22TIM1 DMA address for full transfer (TIM1_DMAR) . . . . .793
27.4.23TIM1 option register 1 (TIM1_OR1) . . . . .794
27.4.24TIM1 capture/compare mode register 3 (TIM1_CCMR3) . . . . .794
27.4.25TIM1 capture/compare register 5 (TIM1_CCR5) . . . . .795
27.4.26TIM1 capture/compare register 6 (TIM1_CCR6) . . . . .796
27.4.27TIM1 alternate function option register 1 (TIM1_AF1) . . . . .797
27.4.28TIM1 Alternate function register 2 (TIM1_AF2) . . . . .798
27.4.29TIM1 timer input selection register (TIM1_TISEL) . . . . .800
27.4.30TIM1 register map . . . . .801
28General-purpose timer (TIM2) . . . . .804
28.1TIM2 introduction . . . . .804
28.2TIM2 main features . . . . .804
28.3TIM2 functional description . . . . .806
28.3.1Time-base unit . . . . .806
28.3.2Counter modes . . . . .808
28.3.3Clock selection . . . . .818
28.3.4Capture/Compare channels . . . . .822
28.3.5Input capture mode . . . . .824
28.3.6PWM input mode . . . . .825
28.3.7Forced output mode . . . . .826
28.3.8Output compare mode . . . . .826
28.3.9PWM mode . . . . .827
28.3.10Asymmetric PWM mode . . . . .831
28.3.11Combined PWM mode . . . . .831
28.3.12Clearing the OCxREF signal on an external event . . . . .832
28.3.13One-pulse mode . . . . .834
28.3.14Retriggerable one pulse mode . . . . .835
28.3.15Encoder interface mode . . . . .836
28.3.16UIF bit remapping . . . . .838
28.3.17Timer input XOR function . . . . .838
28.3.18Timers and external trigger synchronization . . . . .839
28.3.19Timer synchronization . . . . .842
28.3.20DMA burst mode . . . . .847
28.3.21Debug mode .....848
28.4TIM2 registers .....849
28.4.1TIM2 control register 1 (TIM2_CR1) .....849
28.4.2TIM2 control register 2 (TIM2_CR2) .....850
28.4.3TIM2 slave mode control register (TIM2_SMCR) .....852
28.4.4TIM2 DMA/Interrupt enable register (TIM2_DIER) .....855
28.4.5TIM2 status register (TIM2_SR) .....856
28.4.6TIM2 event generation register (TIM2_EGR) .....858
28.4.7TIM2 capture/compare mode register 1 (TIM2_CCMR1) .....859
28.4.8TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) ..860
28.4.9TIM2 capture/compare mode register 2 (TIM2_CCMR2) .....863
28.4.10TIM2 capture/compare mode register 2 [alternate] (TIM2_CCMR2) ..864
28.4.11TIM2 capture/compare enable register
(TIM2_CCER) .....		865
28.4.12TIM2 counter (TIM2_CNT) .....866
28.4.13TIM2 counter [alternate] (TIM2_CNT) .....867
28.4.14TIM2 prescaler (TIM2_PSC) .....867
28.4.15TIM2 auto-reload register (TIM2_ARR) .....867
28.4.16TIM2 capture/compare register 1 (TIM2_CCR1) .....868
28.4.17TIM2 capture/compare register 2 (TIM2_CCR2) .....868
28.4.18TIM2 capture/compare register 3 (TIM2_CCR3) .....869
28.4.19TIM2 capture/compare register 4 (TIM2_CCR4) .....869
28.4.20TIM2 DMA control register (TIM2_DCR) .....870
28.4.21TIM2 DMA address for full transfer (TIM2_DMAR) .....870
28.4.22TIM2 option register 1 (TIM2_OR1) .....871
28.4.23TIM2 alternate function option register 1 (TIM2_AF1) .....871
28.4.24TIM2 timer input selection register (TIM2_TISEL) .....872
28.4.25TIMx register map .....873
29General-purpose timers (TIM16/TIM17) .....876
29.1TIM16/TIM17 introduction .....876
29.2TIM16/TIM17 main features .....876
29.3TIM16/TIM17 functional description .....878
29.3.1Time-base unit .....878
29.3.2Counter modes .....880
29.3.3Repetition counter .....884
29.3.4Clock selection .....885
29.3.5Capture/compare channels .....887
29.3.6Input capture mode .....889
29.3.7Forced output mode .....890
29.3.8Output compare mode .....890
29.3.9PWM mode .....892
29.3.10Complementary outputs and dead-time insertion .....893
29.3.11Using the break function .....895
29.3.12Bidirectional break inputs .....898
29.3.136-step PWM generation .....899
29.3.14One-pulse mode .....901
29.3.15UIF bit remapping .....902
29.3.16Slave mode – combined reset + trigger mode .....902
29.3.17DMA burst mode .....902
29.3.18Using timer output as trigger for other timers (TIM16/TIM17) .....903
29.3.19Debug mode .....904
29.4TIM16/TIM17 registers .....905
29.4.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) .....905
29.4.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) .....906
29.4.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) .....907
29.4.4TIMx status register (TIMx_SR)(x = 16 to 17) .....908
29.4.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) .....909
29.4.6TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 16 to 17) .....		910
29.4.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) .....		911
29.4.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) ..913
29.4.9TIMx counter (TIMx_CNT)(x = 16 to 17) .....915
29.4.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) .....916
29.4.11TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) .....916
29.4.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) .....917
29.4.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) .....917
29.4.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) .....918
29.4.15TIMx DMA control register (TIMx_DCR)(x = 16 to 17) .....920
29.4.16TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) .....921
29.4.17TIM16 option register 1 (TIM16_OR1) .....922
29.4.18TIM16 alternate function register 1 (TIM16_AF1) .....922
29.4.19TIM16 input selection register (TIM16_TISEL) .....923
30.7.9LPTIM1 option register (LPTIM1_OR) . . . . .950
30.7.10LPTIM2 option register (LPTIM2_OR) . . . . .951
30.7.11LPTIM register map . . . . .952
31Infrared interface (IRTIM) . . . . .953
32Independent watchdog (IWDG) . . . . .954
32.1Introduction . . . . .954
32.2IWDG main features . . . . .954
32.3IWDG functional description . . . . .954
32.3.1IWDG block diagram . . . . .954
32.3.2Window option . . . . .955
32.3.3Hardware watchdog . . . . .956
32.3.4Low-power freeze . . . . .956
32.3.5Register access protection . . . . .956
32.3.6Debug mode . . . . .956
32.4IWDG registers . . . . .957
32.4.1IWDG key register (IWDG_KR) . . . . .957
32.4.2IWDG prescaler register (IWDG_PR) . . . . .958
32.4.3IWDG reload register (IWDG_RLR) . . . . .959
32.4.4IWDG status register (IWDG_SR) . . . . .960
32.4.5IWDG window register (IWDG_WINR) . . . . .961
32.4.6IWDG register map . . . . .962
33System window watchdog (WWDG) . . . . .963
33.1WWDG introduction . . . . .963
33.2WWDG main features . . . . .963
33.3WWDG functional description . . . . .963
33.3.1WWDG block diagram . . . . .964
33.3.2Enabling the watchdog . . . . .964
33.3.3Controlling the down-counter . . . . .964
33.3.4How to program the watchdog timeout . . . . .964
33.3.5Debug mode . . . . .966
33.4WWDG interrupts . . . . .966
33.5WWDG registers . . . . .966
33.5.1WWDG control register (WWDG_CR) . . . . .966
34.7.10RTC sub second register (RTC_SSR) . . . . .997
34.7.11RTC shift control register (RTC_SHIFTR) . . . . .998
34.7.12RTC timestamp time register (RTC_TSTR) . . . . .999
34.7.13RTC timestamp date register (RTC_TSDR) . . . . .1000
34.7.14RTC time-stamp sub second register (RTC_TSSSR) . . . . .1001
34.7.15RTC calibration register (RTC_CALR) . . . . .1002
34.7.16RTC tamper configuration register (RTC_TAMPCR) . . . . .1003
34.7.17RTC alarm A sub second register (RTC_ALRMASSR) . . . . .1006
34.7.18RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .1007
34.7.19RTC option register (RTC_OR) . . . . .1008
34.7.20RTC backup registers (RTC_BKPxR) . . . . .1008
34.7.21RTC register map . . . . .1009
35Inter-integrated circuit interface (I2C) . . . . .1011
35.1I2C introduction . . . . .1011
35.2I2C main features . . . . .1011
35.3I2C implementation . . . . .1012
35.4I2C functional description . . . . .1012
35.4.1I2C block diagram . . . . .1013
35.4.2I2C pins and internal signals . . . . .1013
35.4.3I2C clock requirements . . . . .1014
35.4.4I2C mode selection . . . . .1014
35.4.5I2C initialization . . . . .1015
35.4.6I2C reset . . . . .1019
35.4.7I2C data transfer . . . . .1020
35.4.8I2C target mode . . . . .1022
35.4.9I2C controller mode . . . . .1031
35.4.10I2C_TIMINGR register configuration examples . . . . .1042
35.4.11SMBus specific features . . . . .1044
35.4.12SMBus initialization . . . . .1046
35.4.13SMBus I2C_TIMEOUTR register configuration examples . . . . .1048
35.4.14SMBus target mode . . . . .1049
35.4.15SMBus controller mode . . . . .1052
35.4.16Wake-up from Stop mode on address match . . . . .1055
35.4.17Error conditions . . . . .1056
35.5I2C in low-power modes . . . . .1058

35.6 I2C interrupts . . . . . 1058

35.7 I2C DMA requests . . . . . 1059

35.7.1 Transmission using DMA . . . . . 1059

35.7.2 Reception using DMA . . . . . 1059

35.8 I2C debug modes . . . . . 1059

35.9 I2C registers . . . . . 1060

35.9.1 I2C control register 1 (I2C_CR1) . . . . . 1060

35.9.2 I2C control register 2 (I2C_CR2) . . . . . 1062

35.9.3 I2C own address 1 register (I2C_OAR1) . . . . . 1064

35.9.4 I2C own address 2 register (I2C_OAR2) . . . . . 1065

35.9.5 I2C timing register (I2C_TIMINGR) . . . . . 1066

35.9.6 I2C timeout register (I2C_TIMEOUTR) . . . . . 1067

35.9.7 I2C interrupt and status register (I2C_ISR) . . . . . 1068

35.9.8 I2C interrupt clear register (I2C_ICR) . . . . . 1070

35.9.9 I2C PEC register (I2C_PECR) . . . . . 1071

35.9.10 I2C receive data register (I2C_RXDR) . . . . . 1071

35.9.11 I2C transmit data register (I2C_TXDR) . . . . . 1072

35.9.12 I2C register map . . . . . 1073

36 Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . . 1074

36.1 USART introduction . . . . . 1074

36.2 USART main features . . . . . 1075

36.3 USART extended features . . . . . 1076

36.4 USART implementation . . . . . 1076

36.5 USART functional description . . . . . 1077

36.5.1 USART block diagram . . . . . 1077

36.5.2 USART signals . . . . . 1078

36.5.3 USART character description . . . . . 1079

36.5.4 USART FIFOs and thresholds . . . . . 1081

36.5.5 USART transmitter . . . . . 1081

36.5.6 USART receiver . . . . . 1085

36.5.7 USART baud rate generation . . . . . 1092

36.5.8 Tolerance of the USART receiver to clock deviation . . . . . 1093

36.5.9 USART auto baud rate detection . . . . . 1095

36.5.10 USART multiprocessor communication . . . . . 1097

36.5.11USART Modbus communication . . . . .1099
36.5.12USART parity control . . . . .1100
36.5.13USART LIN (local interconnection network) mode . . . . .1101
36.5.14USART synchronous mode . . . . .1103
36.5.15USART single-wire half-duplex communication . . . . .1107
36.5.16USART receiver timeout . . . . .1107
36.5.17USART smartcard mode . . . . .1108
36.5.18USART IrDA SIR ENDEC block . . . . .1112
36.5.19Continuous communication using USART and DMA . . . . .1115
36.5.20RS232 hardware flow control and RS485 Driver Enable . . . . .1117
36.5.21USART low-power management . . . . .1120
36.6USART in low-power modes . . . . .1123
36.7USART interrupts . . . . .1124
36.8USART registers . . . . .1125
36.8.1USART control register 1 (USART_CR1) . . . . .1125
36.8.2USART control register 1 [alternate] (USART_CR1) . . . . .1128
36.8.3USART control register 2 (USART_CR2) . . . . .1132
36.8.4USART control register 3 (USART_CR3) . . . . .1136
36.8.5USART baud rate register (USART_BRR) . . . . .1140
36.8.6USART guard time and prescaler register (USART_GTPR) . . . . .1140
36.8.7USART receiver timeout register (USART_RTOR) . . . . .1141
36.8.8USART request register (USART_RQR) . . . . .1142
36.8.9USART interrupt and status register (USART_ISR) . . . . .1143
36.8.10USART interrupt and status register [alternate] (USART_ISR) . . . . .1149
36.8.11USART interrupt flag clear register (USART_ICR) . . . . .1154
36.8.12USART receive data register (USART_RDR) . . . . .1156
36.8.13USART transmit data register (USART_TDR) . . . . .1156
36.8.14USART prescaler register (USART_PRESC) . . . . .1157
36.8.15USART register map . . . . .1158
37Low-power universal asynchronous receiver transmitter (LPUART) . . . . .1160
37.1LPUART introduction . . . . .1160
37.2LPUART main features . . . . .1161
37.3LPUART implementation . . . . .1162
37.4LPUART functional description . . . . .1163
37.4.1LPUART block diagram . . . . .1163
37.4.2LPUART signals . . . . .1164
37.4.3LPUART character description . . . . .1165
37.4.4LPUART FIFOs and thresholds . . . . .1166
37.4.5LPUART transmitter . . . . .1167
37.4.6LPUART receiver . . . . .1170
37.4.7LPUART baud rate generation . . . . .1174
37.4.8Tolerance of the LPUART receiver to clock deviation . . . . .1175
37.4.9LPUART multiprocessor communication . . . . .1176
37.4.10LPUART parity control . . . . .1178
37.4.11LPUART single-wire half-duplex communication . . . . .1179
37.4.12Continuous communication using DMA and LPUART . . . . .1179
37.4.13RS232 hardware flow control and RS485 Driver Enable . . . . .1182
37.4.14LPUART low-power management . . . . .1184
37.5LPUART in low-power modes . . . . .1187
37.6LPUART interrupts . . . . .1188
37.7LPUART registers . . . . .1189
37.7.1LPUART control register 1 (LPUART_CR1) . . . . .1189
37.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .1192
37.7.3LPUART control register 2 (LPUART_CR2) . . . . .1195
37.7.4LPUART control register 3 (LPUART_CR3) . . . . .1197
37.7.5LPUART baud rate register (LPUART_BRR) . . . . .1200
37.7.6LPUART request register (LPUART_RQR) . . . . .1200
37.7.7LPUART interrupt and status register (LPUART_ISR) . . . . .1201
37.7.8LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .1205
37.7.9LPUART interrupt flag clear register (LPUART_ICR) . . . . .1208
37.7.10LPUART receive data register (LPUART_RDR) . . . . .1209
37.7.11LPUART transmit data register (LPUART_TDR) . . . . .1209
37.7.12LPUART prescaler register (LPUART_PRESC) . . . . .1210
37.7.13LPUART register map . . . . .1211
38Serial peripheral interface (SPI) . . . . .1213
38.1Introduction . . . . .1213
38.2SPI main features . . . . .1213
38.3SPI implementation . . . . .1214
38.4SPI functional description . . . . .1214
38.4.1General description . . . . .1214
38.4.2Communications between one master and one slave . . . . .1215
38.4.3Standard multislave communication . . . . .1217
38.4.4Multimaster communication . . . . .1218
38.4.5Slave select (NSS) pin management . . . . .1219
38.4.6Communication formats . . . . .1220
38.4.7Configuration of SPI . . . . .1222
38.4.8Procedure for enabling SPI . . . . .1223
38.4.9Data transmission and reception procedures . . . . .1223
38.4.10SPI status flags . . . . .1233
38.4.11SPI error flags . . . . .1234
38.4.12NSS pulse mode . . . . .1235
38.4.13TI mode . . . . .1235
38.4.14CRC calculation . . . . .1236
38.5SPI interrupts . . . . .1238
38.6SPI registers . . . . .1239
38.6.1SPI control register 1 (SPIx_CR1) . . . . .1239
38.6.2SPI control register 2 (SPIx_CR2) . . . . .1241
38.6.3SPI status register (SPIx_SR) . . . . .1243
38.6.4SPI data register (SPIx_DR) . . . . .1244
38.6.5SPI CRC polynomial register (SPIx_CRCPR) . . . . .1245
38.6.6SPI Rx CRC register (SPIx_RXCRCR) . . . . .1245
38.6.7SPI Tx CRC register (SPIx_TXCRCR) . . . . .1245
38.6.8SPI register map . . . . .1247
39Serial audio interface (SAI) . . . . .1248
39.1SAI introduction . . . . .1248
39.2SAI main features . . . . .1248
39.3SAI implementation . . . . .1249
39.4SAI functional description . . . . .1250
39.4.1SAI block diagram . . . . .1250
39.4.2SAI pins and internal signals . . . . .1251
39.4.3Main SAI modes . . . . .1252
39.4.4SAI synchronization mode . . . . .1253
39.4.5Audio data size . . . . .1253
39.4.6Frame synchronization . . . . .1253
39.4.7Slot configuration . . . . .1257
39.4.8SAI clock generator . . . . .1259
39.4.9Internal FIFOs . . . . .1262
39.4.10PDM interface . . . . .1264
39.4.11AC'97 link controller . . . . .1272
39.4.12SPDIF output . . . . .1273
39.4.13Specific features . . . . .1276
39.4.14Error flags . . . . .1280
39.4.15Disabling the SAI . . . . .1283
39.4.16SAI DMA interface . . . . .1283
39.5SAI interrupts . . . . .1284
39.6SAI registers . . . . .1286
39.6.1SAI configuration register 1 (SAI_ACR1) . . . . .1286
39.6.2SAI configuration register 2 (SAI_ACR2) . . . . .1288
39.6.3SAI frame configuration register (SAI_AFRCR) . . . . .1290
39.6.4SAI slot register (SAI_ASLOTR) . . . . .1291
39.6.5SAI interrupt mask register (SAI_AIM) . . . . .1292
39.6.6SAI status register (SAI_ASR) . . . . .1294
39.6.7SAI clear flag register (SAI_ACLRFR) . . . . .1296
39.6.8SAI data register (SAI_ADR) . . . . .1297
39.6.9SAI configuration register 1 (SAI_BCR1) . . . . .1297
39.6.10SAI configuration register 2 (SAI_BCR2) . . . . .1300
39.6.11SAI frame configuration register (SAI_BFRCR) . . . . .1302
39.6.12SAI slot register (SAI_BSLOTR) . . . . .1303
39.6.13SAI interrupt mask register (SAI_BIM) . . . . .1304
39.6.14SAI status register (SAI_BSR) . . . . .1305
39.6.15SAI clear flag register (SAI_BCLRFR) . . . . .1307
39.6.16SAI data register (SAI_BDR) . . . . .1308
39.6.17SAI PDM control register (SAI_PDMCR) . . . . .1309
39.6.18SAI PDM delay register (SAI_PDMPLY) . . . . .1310
39.6.19SAI register map . . . . .1312
40Universal serial bus full-speed device interface (USB) . . . . .1314
40.1Introduction . . . . .1314
40.2USB main features . . . . .1314
40.3USB implementation . . . . .1314
40.4USB functional description . . . . .1315
40.4.1Description of USB blocks . . . . .1316
40.5Programming considerations . . . . .1317
40.5.1Generic USB device programming . . . . .1317
40.5.2System and power-on reset . . . . .1318
40.5.3Double-buffered endpoints . . . . .1323
40.5.4Isochronous transfers . . . . .1325
40.5.5Suspend/Resume events . . . . .1326
40.6USB and USB SRAM registers . . . . .1329
40.6.1Common registers . . . . .1329
40.6.2Buffer descriptor table . . . . .1342
40.6.3USB register map . . . . .1345
41Debug support (DBG) . . . . .1347
41.1Introduction . . . . .1347
41.2Debug use cases . . . . .1347
41.3DBG functional description . . . . .1349
41.3.1DBG block diagram . . . . .1349
41.3.2DBG pins and internal signals . . . . .1349
41.3.3DBG power domains . . . . .1350
41.3.4DBG clocks . . . . .1350
41.3.5Debug and low power modes . . . . .1351
41.3.6DBG reset . . . . .1351
41.4Serial wire and JTAG debug port (SWJ-DP) . . . . .1351
41.4.1JTAG debug port . . . . .1351
41.4.2SW debug port . . . . .1354
41.4.3Debug port registers . . . . .1355
41.4.4DP debug port identification register (DP_PIDR) . . . . .1356
41.4.5DP abort register (DP_ABORTR) . . . . .1356
41.4.6DP control and status register (DP_CTRL/STATR) . . . . .1357
41.4.7DP data link control register (DP_DLCR) . . . . .1359
41.4.8DP target identification register (DP_TARGETIDR) . . . . .1359
41.4.9DP data link protocol identification register (DP_DLPIDR) . . . . .1360
41.4.10DP resend register (DP_RESENR) . . . . .1360
41.4.11DP access port select register (DP_SELECTR) . . . . .1361
41.4.12DP read buffer register (DP_BUFFR) . . . . .1361
41.4.13DP target selection register (DP_TARGETSELR) . . . . .1362
41.4.14Debug port register map and reset values . . . . .1363
41.5Access ports . . . . .1364
41.5.1AP control/status word register (AP_CSWR) . . . . .1367
41.5.2AP transfer address register (AP_TAR) . . . . .1368
41.5.3AP data read/write register (AP_DRWR) . . . . .1368
41.5.4AP banked data registers (AP_BD0-3R) . . . . .1368
41.5.5AP base address register (AP_BASER) . . . . .1369
41.5.6AP identification register (AP_IDR) . . . . .1369
41.5.7Access port register map and reset values . . . . .1371
41.6Cross trigger interface (CTI) and matrix (CTM) . . . . .1372
41.7Cross trigger interface registers . . . . .1376
41.7.1CTI control register (CTI_CONTROLR) . . . . .1376
41.7.2CTI trigger acknowledge register (CTI_INTACKR) . . . . .1376
41.7.3CTI application trigger set register (CTI_APPSETR) . . . . .1376
41.7.4CTI application trigger clear register (CTI_APPCLEAR) . . . . .1377
41.7.5CTI application pulse register (CTI_APPPULSER) . . . . .1378
41.7.6CTI trigger In x enable register (CTI_INENRx) . . . . .1378
41.7.7CTI trigger out x enable register (CTI_OUTENRx) . . . . .1379
41.7.8CTI trigger in status register (CTI_TRGISTSR) . . . . .1379
41.7.9CTI trigger out status register (CTI_TRGOSTSR) . . . . .1380
41.7.10CTI channel in status register (CTI_CHINSTSR) . . . . .1380
41.7.11CTI channel out status register (CTI_CHOUTSTSR) . . . . .1380
41.7.12CTI channel gate register (CTI_GATER) . . . . .1381
41.7.13CTI claim tag set register (CTI_CLAIMSETR) . . . . .1381
41.7.14CTI claim tag clear register (CTI_CLAIMCLR) . . . . .1382
41.7.15CTI lock access register (CTI_LAR) . . . . .1382
41.7.16CTI lock status register (CTI_LSR) . . . . .1383
41.7.17CTI authentication status register (CTI_AUTHSTATR) . . . . .1383
41.7.18CTI device configuration register (CTI_DEVIDR) . . . . .1384
41.7.19CTI device type identifier register (CTI_DEVTYPE) . . . . .1384
41.7.20CTI CoreSight peripheral identity register 4 (CTI_PIDR4) . . . . .1385
41.7.21CTI CoreSight peripheral identity register 0 (CTI_PIDR0) . . . . .1385
41.7.22CTI CoreSight peripheral identity register 1 (CTI_PIDR1) . . . . .1385
41.7.23CTI CoreSight peripheral identity register 2 (CTI_PIDR2) . . . . .1386
41.7.24CTI CoreSight peripheral identity register 3 (CTI_PIDR3) . . . . .1386
41.7.25CTI CoreSight component identity register 0 (CTI_CIDR0) . . . . .1387
41.7.26CTI CoreSight peripheral identity register 1 (CTI_CIDR1) . . . . .1387
41.7.27CTI CoreSight component identity register 2 (CTI_CIDR2) . . . . .1388
41.7.28CTI CoreSight component identity register 3 (CTI_CIDR3) . . . . .1388
41.7.29CTI register map and reset values . . . . .1389
41.8Microcontroller debug unit (DBGMCU) . . . . .1392
41.8.1DBGMCU identity code register (DBGMCU_IDCODE) . . . . .1392
41.8.2DBGMCU configuration register (DBGMCU_CR) . . . . .1392
41.8.3DBGMCU CPU1 APB1 peripheral freeze register 1
(DBGMCU_APB1FZR1) . . . . .		1393
41.8.4DBGMCU CPU2 APB1 peripheral freeze register 1
(DBGMCU_C2APB1FZR1) . . . . .		1394
41.8.5DBGMCU CPU1 APB1 peripheral freeze register 2
(DBGMCU_APB1FZR2) . . . . .		1395
41.8.6DBGMCU CPU2 APB1 peripheral freeze register 2
(DBGMCU_C2APB1FZR2) . . . . .		1396
41.8.7DBGMCU CPU1 APB2 peripheral freeze register
(DBGMCU_APB2FZR) . . . . .		1396
41.8.8DBGMCU CPU2 APB2 peripheral freeze register
(DBGMCU_C2APB2FZR) . . . . .		1397
41.8.9DBGMCU register map and reset values . . . . .1399
41.9CPU2 ROM tables . . . . .1401
41.9.1CPU2 ROM1 memory type register (C2ROM1_MEMTYPER) . . . . .1403
41.9.2CPU2 ROM1 CoreSight peripheral identity register 4
(C2ROM1_PIDR4) . . . . .		1403
41.9.3CPU2 ROM1 CoreSight peripheral identity register 0
(C2ROM1_PIDR0) . . . . .		1403
41.9.4CPU2 ROM1 CoreSight peripheral identity register 1
(C2ROM1_PIDR1) . . . . .		1404
41.9.5CPU2 ROM1 CoreSight peripheral identity register 2
(C2ROM1_PIDR2) . . . . .		1404
41.9.6CPU2 ROM1 CoreSight peripheral identity register 3
(C2ROM1_PIDR3) . . . . .		1405
41.9.7CPU2 ROM1 CoreSight component identity register 0
(C2ROM1_CIDR0) . . . . .		1405
41.9.8CPU2 ROM1 CoreSight peripheral identity register 1
(C2ROM1_CIDR1) . . . . .		1406
41.9.9CPU2 ROM1 CoreSight component identity register 2
(C2ROM1_CIDR2) . . . . .		1406
41.9.10CPU2 ROM1 CoreSight component identity register 3
(C2ROM1_CIDR3) . . . . .		1406
41.9.11CPU2 processor ROM table registers and reset values . . . . .1408
41.9.12CPU2 ROM2 memory type register (C2ROM2_MEMTYPE) . . . . .1409
41.9.13CPU2 ROM2 CoreSight peripheral identity register 4
(C2ROM2_PIDR4) . . . . .		1409
41.9.14CPU2 ROM2 CoreSight peripheral identity register 0
(C2ROM2_PIDR0) . . . . .		1409
41.9.15CPU2 ROM2 CoreSight peripheral identity register 1
(C2ROM2_PIDR1) . . . . .		1410
41.9.16CPU2 ROM2 CoreSight peripheral identity register 2
(C2ROM2_PIDR2) . . . . .		1410
41.9.17CPU2 ROM2 CoreSight peripheral identity register 3
(C2ROM2_PIDR3) . . . . .		1411
41.9.18CPU2 ROM2 CoreSight component identity register 0
(C2ROM2_CIDR0) . . . . .		1411
41.9.19CPU2 ROM2 CoreSight peripheral identity register 1
(C2ROM2_CIDR1) . . . . .		1412
41.9.20CPU2 ROM2 CoreSight component identity register 2
(C2ROM2_CIDR2) . . . . .		1412
41.9.21CPU2 ROM2 CoreSight component identity register 3
(C2ROM2_CIDR3) . . . . .		1412
41.9.22CPU2 ROM table register map and reset values . . . . .1414
41.10CPU2 data watchpoint and trace unit (DWT) . . . . .1415
41.10.1DWT control register (DWT_CTRLR) . . . . .1415
41.10.2DWT cycle count register (DWT_CYCCNTR) . . . . .1417
41.10.3DWT CPI count register (DWT_CPICNTR) . . . . .1417
41.10.4DWT exception count register (DWT_EXCCNTR) . . . . .1418
41.10.5DWT sleep count register (DWT_SLPNCNTR) . . . . .1418
41.10.6DWT LSU count register (DWT_LSUCNTR) . . . . .1419
41.10.7DWT fold count register (DWT_FOLDCNTR) . . . . .1419
41.10.8DWT program counter sample register (DWT_PCSR) . . . . .1419
41.10.9DWT comparator register x (DWT_COMPxR) . . . . .1420
41.10.10DWT mask register x (DWT_MASKxR) . . . . .1420
41.10.11DWT function register x (DWT_FUNCTxR) . . . . .1420
41.10.12DWT CoreSight peripheral identity register 4 (DWT_PIDR4) . . . . .1421
41.10.13DWT CoreSight peripheral identity register 0 (DWT_PIDR0) . . . . .1422
41.10.14DWT CoreSight peripheral identity register 1 (DWT_PIDR1) . . . . .1422
41.10.15DWT CoreSight peripheral identity register 2 (DWT_PIDR2) . . . . .1423
41.10.16DWT CoreSight peripheral identity register 3 (DWT_PIDR3) . . . . .1423
41.10.17DWT CoreSight component identity register 0 (DWT_CIDR0) . . . . .1424
41.10.18DWT CoreSight peripheral identity register 1 (DWT_CIDR1) . . . . .1424
41.10.19DWT CoreSight component identity register 2 (DWT_CIDR2) . . . . .1424
41.10.20DWT CoreSight component identity register 3 (DWT_CIDR3) . . . . .1425
41.10.21CPU2 DWT registers . . . . .1426
41.11CPU2 breakpoint unit (PBU) . . . . .1429
41.11.1BPU control register (BPU_CTRLR) . . . . .1429
41.11.2BPU remap register (BPU_REMAPR) . . . . .1429
41.11.3BPU comparator registers (BPU_COMPxR) . . . . .1430
41.11.4BPU CoreSight peripheral identity register 4 (BPU_PIDR4) . . . . .1430
41.11.5BPU CoreSight peripheral identity register 0 (BPU_PIDR0) . . . . .1431
41.11.6BPU CoreSight peripheral identity register 1 (BPU_PIDR1) . . . . .1431
41.11.7BPU CoreSight peripheral identity register 2 (BPU_PIDR2) . . . . .1431
41.11.8BPU CoreSight peripheral identity register 3 (BPU_PIDR3) . . . . .1432
41.11.9BPU CoreSight component identity register 0 (BPU_CIDR0) . . . . .1432
41.11.10BPU CoreSight peripheral identity register 1 (BPU_CIDR1) . . . . .1433
41.11.11BPU CoreSight component identity register 2 (BPU_CIDR2) . . . . .1433
41.11.12BPU CoreSight component identity register 3 (BPU_CIDR3) . . . . .1434
41.11.13CPU2 BPU register map and reset values . . . . .1435
41.12CPU2 cross trigger interface (CTI) . . . . .1436
41.13CPU1 ROM table . . . . .1436
41.13.1CPU1 ROM memory type register (C1ROM_MEMTYPER) . . . . .1437
41.13.2CPU1 ROM CoreSight peripheral identity register 4
(C1ROM_PIDR4) . . . . .		1438
41.13.3CPU1 ROM CoreSight peripheral identity register 0
(C1ROM_PIDR0) . . . . .		1438
41.13.4CPU1 ROM CoreSight peripheral identity register 1
(C1ROM_PIDR1) . . . . .		1439
41.13.5CPU1 ROM CoreSight peripheral identity register 2
(C1ROM_PIDR2) . . . . .		1439
41.13.6CPU1 ROM CoreSight peripheral identity register 3
(C1ROM_PIDR3) . . . . .		1440
41.13.7CPU1 ROM CoreSight component identity register 0
(C1ROM_CIDR0) . . . . .		1440
41.13.8CPU1 ROM CoreSight peripheral identity register 1
(C1ROM_CIDR1) . . . . .		1440
41.13.9CPU1 ROM CoreSight component identity register 2
(C1ROM_CIDR2) . . . . .		1441
41.13.10CPU1 ROM CoreSight component identity register 3
(C1ROM_CIDR3) . . . . .		1441
41.13.11CPU1 ROM table register map and reset values . . . . .1443
41.14CPU1 data watchpoint and trace unit (DWT) . . . . .1444
41.14.1DWT control register (DWT_CTRLR) . . . . .1444
41.14.2DWT cycle count register (DWT_CYCCNTR) . . . . .1446
41.14.3DWT CPI count register (DWT_CPICNTR) . . . . .1446
41.14.4DWT exception count register (DWT_EXCCNTR) . . . . .1447
41.14.5DWT sleep count register (DWT_SLP CNTR) . . . . .1447
41.14.6DWT LSU count register (DWT_LSUCNTR) . . . . .1448
41.14.7DWT fold count register (DWT_FOLDCNTR) . . . . .1448
41.14.8DWT program counter sample register (DWT_PCSR) . . . . .1448
41.14.9DWT comparator register x (DWT_COMPxR) . . . . .1449
41.14.10DWT mask register x (DWT_MASKxR) . . . . .1449
41.14.11DWT function register x (DWT_FUNCTxR) . . . . .1449
41.14.12DWT CoreSight peripheral identity register 4 (DWT_PIDR4) . . . . .1450
41.14.13DWT CoreSight peripheral identity register 0 (DWT_PIDR0) . . . . .1451
41.14.14DWT CoreSight peripheral identity register 1 (DWT_PIDR1) . . . . .1451
41.14.15DWT CoreSight peripheral identity register 2 (DWT_PIDR2) . . . . .1452
41.14.16DWT CoreSight peripheral identity register 3 (DWT_PIDR3) . . . . .1452
41.14.17DWT CoreSight component identity register 0 (DWT_CIDR0) . . . . .1453
41.14.18DWT CoreSight peripheral identity register 1 (DWT_CIDR1) . . . . .1453
41.14.19DWT CoreSight component identity register 2 (DWT_CIDR2) . . . . .1453
41.14.20DWT CoreSight component identity register 3 (DWT_CIDR3) . . . . .1454
41.14.21CPU1 DWT register map and reset values . . . . .1455
41.15CPU1 instrumentation trace macrocell (ITM) . . . . .1457
41.15.1ITM stimulus register x (ITM_STIMRx) . . . . .1457
41.15.2ITM trace enable register (ITM_TER) . . . . .1457
41.15.3ITM trace privilege register (ITM_TPR) . . . . .1458
41.15.4ITM trace control register (ITM_TCR) . . . . .1458
41.15.5ITM CoreSight peripheral identity register 4 (ITM_PIDR4) . . . . .1459
41.15.6ITM CoreSight peripheral identity register 0 (ITM_PIDR0) . . . . .1460
41.15.7ITM CoreSight peripheral identity register 1 (ITM_PIDR1) . . . . .1460
41.15.8ITM CoreSight peripheral identity register 2 (ITM_PIDR2) . . . . .1461
41.15.9ITM CoreSight peripheral identity register 3 (ITM_PIDR3) . . . . .1461
41.15.10ITM CoreSight component identity register 0 (ITM_CIDR0) . . . . .1462
41.15.11ITM CoreSight peripheral identity register 1 (ITM_CIDR1) . . . . .1462
41.15.12ITM CoreSight component identity register 2 (ITM_CIDR2) . . . . .1462
41.15.13ITM CoreSight component identity register 3 (ITM_CIDR3) . . . . .1463
41.15.14ITM register map and reset values . . . . .1464
41.16CPU1 breakpoint unit (FPB) . . . . .1465
41.16.1FPB control register (FPB_CTRLR) . . . . .1465
41.16.2FPB remap register (FPB_REMAPR) . . . . .1465
41.16.3FPB comparator registers (FPB_COMPxR) . . . . .1466
41.16.4FPB CoreSight peripheral identity register 4 (FPB_PIDR4) . . . . .1466
41.16.5FPB CoreSight peripheral identity register 0 (FPB_PIDR0) . . . . .1467
41.16.6FPB CoreSight peripheral identity register 1 (FPB_PIDR1) . . . . .1467
41.16.7FPB CoreSight peripheral identity register 2 (FPB_PIDR2) . . . . .1468
41.16.8FPB CoreSight peripheral identity register 3 (FPB_PIDR3) . . . . .1468
41.16.9FPB CoreSight component identity register 0 (FPB_CIDR0) . . . . .1469
41.16.10FPB CoreSight peripheral identity register 1 (FPB_CIDR1) . . . . .1469
41.16.11FPB CoreSight component identity register 2 (FPB_CIDR2) . . . . .1469
41.16.12FPB CoreSight component identity register 3 (FPB_CIDR3) . . . . .1470
41.16.13FPB register map and reset values . . . . .1471
41.17CPU1 Embedded trace macrocell (ETM™),
only available on STM32WB55xx . . . . .		1472
41.17.1ETM control register (ETM_CR) . . . . .1472
41.17.2ETM configuration code register (ETM_CCR) . . . . .1473
41.17.3ETM trigger register (ETM_TRIGGER) . . . . .1474
41.17.4ETM status register (ETM_SR) . . . . .1475
41.17.5ETM status register (ETM_SCR) . . . . .1475
41.17.6ETM trace enable event register (ETM_TEEVR) . . . . .1476
41.17.7ETM trace enable control 1 register (ETM_TECR1) . . . . .1477
41.17.8ETM FIFOFULL level register (ETM_FFLR) . . . . .1477
41.17.9ETM counter reload value 1 register (ETM_CNTRLDVR1) . . . . .1478
41.17.10ETM synchronization frequency register (ETM_SYNCFR) . . . . .1478
41.17.11ETM ID register (ETM_IDR) . . . . .1479
41.17.12ETM configuration code extension register (ETM_CCER) . . . . .1479
41.17.13ETM trace enable start/stop EmbeddedICE control register
(ETM_TESSEICR) . . . . .		1480
41.17.14ETM timestamp event register (ETM_TSEVR) . . . . .1481
41.17.15ETM trace ID register (ETM_TRACEIDR) . . . . .1482
41.17.16ETM ID register 2(ETM_IDR2) . . . . .1482
41.17.17ETM device power down status register 2(ETM_PDSR) . . . . .1482
41.17.18ETM claim tag set register (ETM_CLAIMSETR) . . . . .1483
41.17.19ETM claim tag clear register (ETM_CLAIMCLR) . . . . .1483
41.17.20ETM lock access register (ETM_LAR) . . . . .1484
41.17.21ETM lock status register (ETM_LSR) . . . . .1484
41.17.22 ETM authentication status register (ETM_AUTHSTATR) . . . . .1485
41.17.23 ETM CoreSight device identity register (ETM_DEVTYPE) . . . . .1485
41.17.24 ETM CoreSight peripheral identity register 4 (ETM_PIDR4) . . . . .1486
41.17.25 ETM CoreSight peripheral identity register 0 (ETM_PIDR0) . . . . .1486
41.17.26 ETM CoreSight peripheral identity register 1 (ETM_PIDR1) . . . . .1486
41.17.27 ETM CoreSight peripheral identity register 2 (ETM_PIDR2) . . . . .1487
41.17.28 ETM CoreSight peripheral identity register 3 (ETM_PIDR3) . . . . .1487
41.17.29 ETM CoreSight component identity register 0 (ETM_CIDR0) . . . . .1488
41.17.30 ETM CoreSight peripheral identity register 1 (ETM_CIDR1) . . . . .1488
41.17.31 ETM CoreSight component identity register 2 (ETM_CIDR2) . . . . .1489
41.17.32 ETM CoreSight component identity register 3 (ETM_CIDR3) . . . . .1489
41.17.33 ETM register map and reset values . . . . .1490
41.18 CPU1 trace port interface unit (TPIU) . . . . .1493
41.18.1 TPIU supported port size register (TPIU_SSPSR) . . . . .1493
41.18.2 TPIU current port size register (TPIU_CSPSR) . . . . .1494
41.18.3 TPIU asynchronous clock prescaler register (TPIU_ACPR) . . . . .1494
41.18.4 TPIU selected pin protocol register (TPIU_SPPR) . . . . .1494
41.18.5 TPIU formatter and flush status register (TPIU_FFSR) . . . . .1495
41.18.6 TPIU formatter and flush control register (TPIU_FFCR) . . . . .1495
41.18.7 TPIU formatter synchronization counter register (TPIU_FSCR) . . . . .1496
41.18.8 TPIU claim tag set register (TPIU_CLAIMSETR) . . . . .1496
41.18.9 TPIU claim tag clear register (TPIU_CLAIMCLR) . . . . .1497
41.18.10 TPIU device configuration register (TPIU_DEVIDR) . . . . .1497
41.18.11 TPIU device type identifier register (TPIU_DEVTYPE) . . . . .1498
41.18.12 TPIU CoreSight peripheral identity register 4 (TPIU_PIDR4) . . . . .1498
41.18.13 TPIU CoreSight peripheral identity register 0 (TPIU_PIDR0) . . . . .1499
41.18.14 TPIU CoreSight peripheral identity register 1 (TPIU_PIDR1) . . . . .1499
41.18.15 TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) . . . . .1500
41.18.16 TPIU CoreSight peripheral identity register 3 (TPIU_PIDR3) . . . . .1500
41.18.17 TPIU CoreSight component identity register 0 (TPIU_CIDR0) . . . . .1501
41.18.18 TPIU CoreSight peripheral identity register 1 (TPIU_CIDR1) . . . . .1501
41.18.19 TPIU CoreSight component identity register 2 (TPIU_CIDR2) . . . . .1501
41.18.20 TPIU CoreSight component identity register 3 (TPIU_CIDR3) . . . . .1502
41.18.21 CPU1 TPIU register map and reset values . . . . .1503
41.19 CPU1 cross trigger interface (CTI) . . . . .1505
41.20 References . . . . .1505

42 Device electronic signature . . . . . 1506

42.1 Unique device ID register (96 bits) . . . . . 1506

42.2 Memory size data register . . . . . 1507

42.2.1 Flash size data register . . . . . 1507

42.3 Package data register . . . . . 1507

42.4 Part number codification register . . . . . 1508

43 Important security notice . . . . . 1509

44 Revision history . . . . . 1510

List of tables

Table 1.Memory map and peripheral register boundary addresses . . . . .68
Table 2.Boot modes. . . . .73
Table 3.Flash memory - Single bank organization . . . . .77
Table 4.Number of wait states vs, Flash memory clock (HCLK4) frequency. . . . .79
Table 5.Page erase overview . . . . .84
Table 6.Mass erase overview . . . . .85
Table 7.Errors in page-based row programming . . . . .90
Table 8.Option bytes format . . . . .91
Table 9.Option bytes organization. . . . .91
Table 10.Option loading control. . . . .100
Table 11.UID64 organization. . . . .101
Table 12.Flash memory read protection status . . . . .102
Table 13.RDP regression from Level 1 to Level 0 and memory erase . . . . .104
Table 14.Access status vs. protection level and execution modes . . . . .105
Table 17.Flash memory interrupt requests . . . . .110
Table 18.Flash interface register map and reset values . . . . .129
Table 19.Supply configuration control . . . . .136
Table 20.PVM features . . . . .143
Table 21.Sub-system low power wake-up sources . . . . .147
Table 22.Low-power mode summary . . . . .149
Table 23.Functionalities depending on system operating mode . . . . .150
Table 24.Low-power run . . . . .153
Table 25.CPU CSTOP wake-up vs. system operating mode . . . . .154
Table 26.Sleep mode. . . . .155
Table 27.Low-power sleep. . . . .156
Table 28.Stop0 mode . . . . .158
Table 29.Stop1 mode . . . . .159
Table 30.Stop2 mode . . . . .162
Table 31.Standby mode. . . . .163
Table 32.Shutdown mode . . . . .165
Table 33.PWR register map and reset values. . . . .187
Table 34.Maximum clock source frequency . . . . .201
Table 35.SMPS step-down converter clock source selection and division . . . . .203
Table 36.Peripheral clock enable . . . . .207
Table 37.Single core Low power debug configurations. . . . .208
Table 38.RCC register map and reset values . . . . .272
Table 39.CRS features . . . . .278
Table 40.CRS internal input/output signals . . . . .279
Table 41.CRS interconnection. . . . .280
Table 42.Effect of low-power modes on CRS . . . . .283
Table 43.Interrupt control bits . . . . .283
Table 44.CRS register map and reset values . . . . .288
Table 45.HSEM internal input/output signals. . . . .291
Table 46.Authorized AHB bus master IDs . . . . .296
Table 47.HSEM register map and reset values. . . . .302
Table 48.IPCC interface signals . . . . .305
Table 49.Bits used for the communication. . . . .306
Table 50.IPCC register map and reset values. . . . .317
Table 51.GPIO implementation . . . . .318
Table 52.Port bit configuration table . . . . .320
Table 53.GPIO register map and reset values . . . . .335
Table 54.SYSCFG register map and reset values . . . . .352
Table 55.Interconnect matrix implementation . . . . .354
Table 56.Peripherals interconnect matrix . . . . .354
Table 57.DMA1 and DMA2 implementation . . . . .361
Table 58.DMA internal input/output signals . . . . .363
Table 59.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .368
Table 60.DMA interrupt requests . . . . .370
Table 61.DMA register map and reset values . . . . .378
Table 62.DMAMUX implementation . . . . .382
Table 63.DMAMUX instantiation . . . . .382
Table 64.DMAMUX: assignment of multiplexer inputs to resources . . . . .383
Table 65.DMAMUX: assignment of trigger inputs to resources . . . . .383
Table 66.DMAMUX: assignment of synchronization inputs to resources . . . . .384
Table 67.DMAMUX signals . . . . .386
Table 68.DMAMUX interrupts . . . . .390
Table 69.DMAMUX register map and reset values . . . . .395
Table 70.DMAMUX register map and reset values . . . . .396
Table 71.NVIC implementation . . . . .398
Table 72.CPU1 vector table . . . . .400
Table 73.CPU2 vector table . . . . .403
Table 74.Wake-up interrupt table . . . . .405
Table 75.EXTI implementation . . . . .407
Table 76.EXTI pin overview . . . . .408
Table 77.EVG pin overview . . . . .409
Table 78.EXTI event input configurations and register control . . . . .410
Table 79.Masking functionality . . . . .413
Table 80.EXTI register map sections . . . . .414
Table 81.EXTI register map and reset values . . . . .424
Table 82.CRC internal input/output signals . . . . .427
Table 83.CRC register map and reset values . . . . .432
Table 84.QUADSPI pins . . . . .434
Table 85.QUADSPI interrupt requests . . . . .446
Table 86.QUADSPI register map and reset values . . . . .457
Table 87.ADC features . . . . .460
Table 88.ADC internal input/output signals . . . . .462
Table 89.ADC input/output pins . . . . .462
Table 90.Configuring the trigger polarity for regular external triggers . . . . .478
Table 91.Configuring the trigger polarity for injected external triggers . . . . .478
Table 92.ADC1 - External triggers for regular channels . . . . .479
Table 93.ADC1 - External trigger for injected channels . . . . .479
Table 94.TSAR timings depending on resolution . . . . .491
Table 95.Offset computation versus data resolution . . . . .494
Table 96.Analog watchdog channel selection . . . . .504
Table 97.Analog watchdog 1 comparison . . . . .505
Table 98.Analog watchdog 2 and 3 comparison . . . . .505
Table 99.Maximum output results versus N and M (gray cells indicate truncation) . . . . .509
Table 100.Effect of low-power modes on the ADC . . . . .517
Table 101.ADC interrupts . . . . .518
Table 102.ADC register map and reset values . . . . .547
Table 103.ADC register map and reset values (master and slave ADC common registers) offset = 0x300 . . . . .549
Table 104.VREFBUF implementation . . . . .550
Table 105.VREF buffer modes . . . . .550
Table 106.VREFBUF trimming data . . . . .551
Table 107.VREFBUF register map and reset values. . . . .553
Table 108.COMP1 input plus assignment . . . . .555
Table 109.COMP1 input minus assignment . . . . .556
Table 110.COMP2 input plus assignment . . . . .556
Table 111.COMP2 input minus assignment . . . . .556
Table 112.Comparator behavior in the low power modes . . . . .560
Table 113.Interrupt control bits . . . . .560
Table 114.COMP register map and reset values. . . . .566
Table 115.Example of frame rate calculation . . . . .570
Table 116.Blink frequency . . . . .578
Table 117.Remapping capability . . . . .582
Table 118.LCD interrupt requests . . . . .588
Table 119.LCD register map and reset values . . . . .595
Table 120.Acquisition sequence summary . . . . .601
Table 121.Spread spectrum deviation versus AHB clock frequency . . . . .603
Table 122.I/O state depending on its mode and IODEF bit value . . . . .604
Table 123.Effect of low-power modes on TSC . . . . .606
Table 124.Interrupt control bits . . . . .606
Table 125.TSC register map and reset values . . . . .613
Table 126.RNG internal input/output signals . . . . .617
Table 127.RNG interrupt requests . . . . .623
Table 128.RNG configurations . . . . .624
Table 129.RNG register map and reset map. . . . .627
Table 130.AES internal input/output signals . . . . .629
Table 131.CTR mode initialization vector definition. . . . .646
Table 132.GCM last block definition . . . . .648
Table 133.Initialization of AES_IVRx registers in GCM mode . . . . .649
Table 134.Initialization of AES_IVRx registers in CCM mode . . . . .656
Table 135.Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .661
Table 136.AES interrupt requests . . . . .664
Table 137.Processing latency for ECB, CBC and CTR. . . . .664
Table 138.Processing latency for GCM and CCM (in clock cycles). . . . .665
Table 139.AES register map and reset values . . . . .675
Table 140.Internal input/output signals . . . . .678
Table 141.PKA integer arithmetic functions list . . . . .679
Table 142.PKA prime field (Fp) elliptic curve functions list . . . . .679
Table 143.Montgomery parameter computation . . . . .684
Table 144.Modular addition . . . . .685
Table 145.Modular subtraction . . . . .685
Table 146.Montgomery multiplication . . . . .686
Table 147.Modular exponentiation (normal mode) . . . . .687
Table 148.Modular exponentiation (fast mode) . . . . .687
Table 149.Modular inversion . . . . .687
Table 150.Modular reduction . . . . .688
Table 151.Arithmetic addition . . . . .688
Table 152.Arithmetic subtraction . . . . .688
Table 153.Arithmetic multiplication . . . . .689
Table 154.Arithmetic comparison . . . . .689
Table 155.CRT exponentiation . . . . .690
Table 156.Point on elliptic curve Fp check . . . . .691
Table 157.ECC Fp scalar multiplication. . . . .691
Table 158.ECC Fp scalar multiplication (Fast Mode) . . . . .692
Table 159.ECDSA sign - Inputs . . . . .693
Table 160.ECDSA sign - Outputs . . . . .693
Table 161.Extended ECDSA sign (extra outputs) . . . . .694
Table 162.ECDSA verification (inputs) . . . . .694
Table 163.ECDSA verification (outputs) . . . . .694
Table 164.Family of supported curves for ECC operations . . . . .695
Table 165.Modular exponentiation computation times . . . . .697
Table 166.ECC scalar multiplication computation times . . . . .697
Table 167.ECDSA signature average computation times . . . . .697
Table 168.ECDSA verification average computation times . . . . .698
Table 169.Point on elliptic curve Fp check average computation times . . . . .698
Table 170.Montgomery parameters average computation times. . . . .698
Table 171.PKA interrupt requests . . . . .698
Table 172.PKA register map and reset values . . . . .702
Table 173.Behavior of timer outputs versus BRK/BRK2 inputs. . . . .745
Table 174.Break protection disarming conditions . . . . .747
Table 175.Counting direction versus encoder signals. . . . .753
Table 176.TIM1 internal trigger connection . . . . .770
Table 177.Output control bits for complementary OCx and OCxN channels with break feature. . . . .784
Table 178.TIM1 register map and reset values . . . . .801
Table 179.Counting direction versus encoder signals. . . . .837
Table 180.TIM2 internal trigger connection . . . . .855
Table 181.Output control bit for standard OCx channels. . . . .866
Table 182.TIM2 register map and reset values . . . . .873
Table 183.Break protection disarming conditions . . . . .898
Table 184.Output control bits for complementary OCx and OCxN channels with break feature
(TIM16/17) . . . . .		915
Table 185.TIM16/TIM17 register map and reset values . . . . .926
Table 186.LPTIM features . . . . .929
Table 187.LPTIM implementation . . . . .929
Table 188.LPTIM1 external trigger connection . . . . .930
Table 189.LPTIM2 external trigger connection . . . . .931
Table 190.Prescaler division ratios . . . . .932
Table 191.Encoder counting scenarios . . . . .939
Table 192.Effect of low-power modes on the LPTIM. . . . .940
Table 193.Interrupt events. . . . .941
Table 194.LPTIM register map and reset values. . . . .952
Table 195.IWDG register map and reset values . . . . .962
Table 196.WWDG register map and reset values . . . . .968
Table 197.RTC implementation. . . . .970
Table 198.Effect of low-power modes on RTC . . . . .984
Table 199.Interrupt control bits . . . . .984
Table 200.RTC register map and reset values . . . . .1009
Table 201.I2C implementation. . . . .1012
Table 202.I2C input/output pins. . . . .1013
Table 203.I2C internal input/output signals . . . . .1014
Table 204.Comparison of analog and digital filters . . . . .1016
Table 205.I 2 C-bus and SMBus specification data setup and hold times . . . . .1018
Table 206.I 2 C configuration. . . . .1022
Table 207.I 2 C-bus and SMBus specification clock timings . . . . .1033
Table 208.Timing settings for f I2CCLK of 8 MHz. . . . .1043
Table 209.Timing settings for f I2CCLK of 16 MHz. . . . .1043
Table 210.SMBus timeout specifications . . . . .1045
Table 211.SMBus with PEC configuration . . . . .1047
Table 212.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms. . . . .1048
Table 213.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .1048
Table 214.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .1048
Table 215.Effect of low-power modes to I 2 C. . . . .1058
Table 216.I 2 C interrupt requests . . . . .1058
Table 217.I 2 C register map and reset values . . . . .1073
Table 218.USART / LPUART features . . . . .1076
Table 219.USART/UART input/output pins . . . . .1079
Table 220.USART internal input/output signals . . . . .1079
Table 221.Noise detection from sampled data . . . . .1091
Table 222.Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .1094
Table 223.Tolerance of the USART receiver when BRR[3:0] is different from 0000. . . . .1095
Table 224.USART frame formats . . . . .1100
Table 225.Effect of low-power modes on the USART . . . . .1123
Table 226.USART interrupt requests. . . . .1124
Table 227.USART register map and reset values . . . . .1158
Table 228.USART / LPUART features . . . . .1162
Table 229.LPUART input/output pins . . . . .1164
Table 230.LPUART internal input/output signals. . . . .1164
Table 231.Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz. . . . .1174
Table 232.Error calculation for programmed baud rates at fCK = 100 MHz . . . . .1175
Table 233.Tolerance of the LPUART receiver. . . . .1176
Table 235.Effect of low-power modes on the LPUART . . . . .1187
Table 236.LPUART interrupt requests. . . . .1188
Table 237.LPUART register map and reset values . . . . .1211
Table 238.SPI implementation. . . . .1214
Table 239.SPI interrupt requests . . . . .1238
Table 240.SPI register map and reset values . . . . .1247
Table 241.STM32WB55xx SAI features . . . . .1249
Table 242.SAI internal input/output signals . . . . .1251
Table 243.SAI input/output pins. . . . .1251
Table 244.MCLK_x activation conditions. . . . .1259
Table 245.Clock generator programming examples . . . . .1262
Table 246.SAI_A configuration for TDM mode . . . . .1269
Table 247.TDM frame configuration examples . . . . .1271
Table 248.SOPD pattern . . . . .1274
Table 249.Parity bit calculation . . . . .1274
Table 250.Audio sampling frequency versus symbol rates . . . . .1275
Table 251.SAI interrupt sources . . . . .1284
Table 252.SAI register map and reset values . . . . .1312
Table 253.USB implementation . . . . .1314
Table 254.Double-buffering buffer flag definition. . . . .1324
Table 255.Bulk double-buffering memory buffers usage . . . . .1324
Table 256.Isochronous memory buffers usage . . . . .1326
Table 257.Resume event detection . . . . .1327
Table 258.Reception status encoding . . . . .1340
Table 259.Endpoint type encoding . . . . .1340
Table 260.Endpoint kind meaning . . . . .1340
Table 261.Transmission status encoding . . . . .1341
Table 262.Definition of allocated buffer memory . . . . .1344
Table 263.USB register map and reset values . . . . .1345
Table 264.JTAG/Serial-wire debug port pins . . . . .1349
Table 265.Trace port pins . . . . .1350
Table 266.Single Wire Trace port pins . . . . .1350
Table 267.Trigger pins . . . . .1350
Table 268.JTAG-DP data registers . . . . .1353
Table 269.Packet request . . . . .1354
Table 270.ACK response . . . . .1355
Table 271.Data transfer . . . . .1355
Table 272.Debug port register map and reset values . . . . .1363
Table 273.Access port register map and reset values . . . . .1371
Table 274.CPU2 CTI inputs . . . . .1372
Table 275.CPU2 CTI outputs . . . . .1373
Table 276.CPU1 CTI inputs . . . . .1373
Table 277.CPU1 CTI outputs . . . . .1373
Table 278.CTI register map and reset values . . . . .1389
Table 279.DBGMCU register map and reset values . . . . .1399
Table 280.CPU2 processor ROM table . . . . .1401
Table 281.CPU2 ROM table . . . . .1401
Table 282.CPU2 processor ROM table register map and reset values . . . . .1408
Table 283.CPU2 ROM table register map and reset values . . . . .1414
Table 284.CPU2 DWT register map and reset values . . . . .1426
Table 285.CPU2 BPU register map and reset values . . . . .1435
Table 286.CPU1 ROM table . . . . .1436
Table 287.CPU1 ROM table register map and reset values . . . . .1443
Table 288.CPU1 DWT register map and reset values . . . . .1455
Table 289.CPU1 ITM register map and reset values . . . . .1464
Table 290.CPU1 FPB register map and reset values . . . . .1471
Table 291.CPU1 ETM register map and reset values . . . . .1490
Table 292.CPU1 TPIU register map and reset values . . . . .1503
Table 293.Document revision history . . . . .1510

List of figures

Figure 1. System architecture . . . . . 64

Figure 2. Memory map . . . . . 67

Figure 3. Sequential 16-bit instructions execution . . . . . 81

Figure 4. Changing the Read protection (RDP) level. . . . . 105

Figure 5. Radio system block diagram. . . . . 132

Figure 6. Power supply overview . . . . . 135

Figure 7. Supply configurations . . . . . 135

Figure 8. Brown-out reset waveform . . . . . 142

Figure 9. PVD thresholds . . . . . 143

Figure 10. CPU2 boot options . . . . . 145

Figure 11. Low-power modes possible transitions. . . . . 148

Figure 12. Real-time radio activity flags. . . . . 166

Figure 13. Simplified diagram of the reset circuit. . . . . 190

Figure 14. Clock tree . . . . . 194

Figure 15. HSE clock sources . . . . . 195

Figure 16. LSE clock sources . . . . . 199

Figure 17. Frequency measurement with TIM16 in capture mode. . . . . 205

Figure 18. Frequency measurement with TIM17 in capture mode. . . . . 205

Figure 19. CRS block diagram. . . . . 279

Figure 20. CRS counter behavior . . . . . 281

Figure 21. HSEM block diagram . . . . . 291

Figure 22. Procedure state diagram . . . . . 292

Figure 23. Interrupt state diagram . . . . . 295

Figure 24. IPCC block diagram . . . . . 305

Figure 25. IPCC Simplex channel mode transfer timing . . . . . 306

Figure 26. IPCC Simplex - Send procedure state diagram . . . . . 307

Figure 27. IPCC Simplex - Receive procedure state diagram . . . . . 308

Figure 28. IPCC Half-duplex channel mode transfer timing. . . . . 309

Figure 29. IPCC Half-duplex - Send procedure state diagram . . . . . 309

Figure 30. IPCC Half-duplex - Receive procedure state diagram . . . . . 310

Figure 31. Three-volt or five-volt tolerant GPIO structure (TT or FT). . . . . 319

Figure 32. Input floating/pull up/pull down configurations . . . . . 324

Figure 33. Output configuration . . . . . 324

Figure 34. Alternate function configuration . . . . . 325

Figure 35. High impedance-analog configuration . . . . . 326

Figure 36. DMA block diagram . . . . . 362

Figure 37. DMAMUX block diagram . . . . . 385

Figure 38. Synchronization mode of the DMAMUX request line multiplexer channel . . . . . 388

Figure 39. Event generation of the DMA request line multiplexer channel . . . . . 388

Figure 40. Interrupt block diagram. . . . . 399

Figure 41. EXTI block diagram . . . . . 408

Figure 42. Configurable event trigger logic CPU wakeup . . . . . 411

Figure 43. Direct event trigger logic CPU wakeup . . . . . 412

Figure 44. CRC calculation unit block diagram . . . . . 427

Figure 45. QUADSPI block diagram . . . . . 433

Figure 46. Example of read command in quad-SPI mode. . . . . 434

Figure 47. Example of a DDR command in quad-SPI mode . . . . . 438

Figure 48. NCS when CKMODE = 0 (T = CLK period) . . . . . 445

Figure 49.NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .445
Figure 50.NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . .445
Figure 51.NCS when CKMODE = 1 with an abort (T = CLK period). . . . .446
Figure 52.ADC block diagram . . . . .461
Figure 53.ADC clock scheme . . . . .464
Figure 54.ADC1 connectivity . . . . .465
Figure 55.ADC calibration. . . . .468
Figure 56.Updating the ADC calibration factor . . . . .469
Figure 57.Mixing single-ended and differential channels . . . . .470
Figure 58.Enabling / disabling the ADC . . . . .471
Figure 59.Analog-to-digital conversion time . . . . .476
Figure 60.Stopping ongoing regular conversions . . . . .477
Figure 61.Stopping ongoing regular and injected conversions . . . . .477
Figure 62.Injected conversion latency . . . . .481
Figure 63.Example of ADC_JSQR queue of context (sequence change) . . . . .484
Figure 64.Example of ADC_JSQR queue of context (trigger change) . . . . .484
Figure 65.Example of ADC_JSQR queue of context with overflow before conversion. . . . .485
Figure 66.Example of ADC_JSQR queue of context with overflow during conversion . . . . .485
Figure 67.Example of ADC_JSQR queue of context with empty queue (case JQM = 0). . . . .486
Figure 68.Example of ADC_JSQR queue of context with empty queue (case JQM = 1). . . . .487
Figure 69.Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs during an ongoing conversion . . . . .		487
Figure 70.Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . .		488
Figure 71.Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs outside an ongoing conversion . . . . .		488
Figure 72.Flushing ADC_JSQR queue of context by setting JADSTP = 1 (JQM = 1) . . . . .489
Figure 73.Flushing ADC_JSQR queue of context by setting ADDIS = 1 (JQM = 0). . . . .489
Figure 74.Flushing ADC_JSQR queue of context by setting ADDIS = 1 (JQM = 1). . . . .490
Figure 75.Single conversions of a sequence, software trigger . . . . .492
Figure 76.Continuous conversion of a sequence, software trigger. . . . .492
Figure 77.Single conversions of a sequence, hardware trigger . . . . .493
Figure 78.Continuous conversions of a sequence, hardware trigger . . . . .493
Figure 79.Right alignment (offset disabled, unsigned value) . . . . .495
Figure 80.Right alignment (offset enabled, signed value). . . . .496
Figure 81.Left alignment (offset disabled, unsigned value) . . . . .496
Figure 82.Left alignment (offset enabled, signed value). . . . .497
Figure 83.Example of overrun (OVR) . . . . .498
Figure 84.AUTODLY = 1, regular conversion in continuous mode, software trigger . . . . .501
Figure 85.AUTODLY = 1, regular HW conversions interrupted by injected conversions
(DISCEN = 0; JDISCEN = 0) . . . . .		501
Figure 86.AUTODLY = 1, regular HW conversions interrupted by injected conversions . . . . .
(DISCEN = 1, JDISCEN = 1) . . . . .		502
Figure 87.AUTODLY = 1, regular continuous conversions interrupted by injected conversions . . . . .503
Figure 88.AUTODLY = 1 in auto- injected mode (JAUTO = 1). . . . .503
Figure 89.Analog watchdog guarded area . . . . .504
Figure 90.ADC y _AWD x _OUT signal generation (on all regular channels). . . . .506
Figure 91.ADC y _AWD x _OUT signal generation (AWD x flag not cleared by software) . . . . .507
Figure 92.ADC y _AWD x _OUT signal generation (on a single regular channel) . . . . .507
Figure 93.ADC y _AWD x _OUT signal generation (on all injected channels) . . . . .507
Figure 94.20-bit to 16-bit result truncation . . . . .508
Figure 95.Numerical example with 5-bit shift and rounding . . . . .508
Figure 96.Triggered regular oversampling mode (TROVS bit = 1) . . . . .510
Figure 97.Regular oversampling modes (4x ratio) . . . . .511
Figure 98.Regular and injected oversampling modes used simultaneously . . . . .512
Figure 99.Triggered regular oversampling with injection . . . . .512
Figure 100.Oversampling in auto-injected mode . . . . .513
Figure 101.Temperature sensor channel block diagram . . . . .514
Figure 102.VBAT channel block diagram . . . . .515
Figure 103.VREFINT channel block diagram . . . . .516
Figure 104.Comparator block diagram . . . . .555
Figure 105.Window mode . . . . .558
Figure 106.Comparator hysteresis . . . . .558
Figure 107.Comparator output blanking . . . . .559
Figure 108.LCD controller block diagram . . . . .569
Figure 109.1/3 bias, 1/4 duty . . . . .571
Figure 110.Static duty case 1 . . . . .572
Figure 111.Static duty case 2 . . . . .573
Figure 112.1/2 duty, 1/2 bias . . . . .574
Figure 113.1/3 duty, 1/3 bias . . . . .575
Figure 114.1/4 duty, 1/3 bias . . . . .576
Figure 115.1/8 duty, 1/4 bias . . . . .577
Figure 116.LCD voltage control . . . . .580
Figure 117.Dead time . . . . .581
Figure 118.SEG/COM mux feature example . . . . .586
Figure 119.Flowchart example . . . . .587
Figure 120.TSC block diagram . . . . .599
Figure 121.Surface charge transfer analog I/O group structure . . . . .600
Figure 122.Sampling capacitor voltage variation . . . . .601
Figure 123.Charge transfer acquisition sequence . . . . .602
Figure 124.Spread spectrum variation principle . . . . .603
Figure 125.RNG block diagram . . . . .617
Figure 126.Entropy source model . . . . .618
Figure 127.RNG initialization overview . . . . .620
Figure 128.AES block diagram . . . . .629
Figure 129.ECB encryption and decryption principle . . . . .631
Figure 130.CBC encryption and decryption principle . . . . .632
Figure 131.CTR encryption and decryption principle . . . . .633
Figure 132.GCM encryption and authentication principle . . . . .634
Figure 133.GMAC authentication principle . . . . .634
Figure 134.CCM encryption and authentication principle . . . . .635
Figure 135.Encryption key derivation for ECB/CBC decryption (Mode 2). . . . .638
Figure 136.Example of suspend mode management . . . . .639
Figure 137.ECB encryption . . . . .640
Figure 138.ECB decryption . . . . .640
Figure 139.CBC encryption . . . . .641
Figure 140.CBC decryption . . . . .641
Figure 141.ECB/CBC encryption (Mode 1) . . . . .642
Figure 142.ECB/CBC decryption (Mode 3) . . . . .643
Figure 143.Message construction in CTR mode . . . . .645
Figure 144.CTR encryption . . . . .646
Figure 145.CTR decryption . . . . .646
Figure 146.Message construction in GCM . . . . .648
Figure 147. GCM authenticated encryption . . . . .649
Figure 148. Message construction in GMAC mode . . . . .653
Figure 149. GMAC authentication mode . . . . .653
Figure 150. Message construction in CCM mode . . . . .654
Figure 151. CCM mode authenticated encryption . . . . .656
Figure 152. 128-bit block construction with respect to data swap . . . . .660
Figure 153. DMA transfer of a 128-bit data block during input phase . . . . .662
Figure 154. DMA transfer of a 128-bit data block during output phase . . . . .663
Figure 155. PKA block diagram . . . . .678
Figure 156. Advanced-control timer block diagram . . . . .705
Figure 157. Counter timing diagram with prescaler division change from 1 to 2 . . . . .707
Figure 158. Counter timing diagram with prescaler division change from 1 to 4 . . . . .707
Figure 159. Counter timing diagram, internal clock divided by 1 . . . . .709
Figure 160. Counter timing diagram, internal clock divided by 2 . . . . .709
Figure 161. Counter timing diagram, internal clock divided by 4 . . . . .710
Figure 162. Counter timing diagram, internal clock divided by N . . . . .710
Figure 163. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .711
Figure 164. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .711
Figure 165. Counter timing diagram, internal clock divided by 1 . . . . .713
Figure 166. Counter timing diagram, internal clock divided by 2 . . . . .713
Figure 167. Counter timing diagram, internal clock divided by 4 . . . . .714
Figure 168. Counter timing diagram, internal clock divided by N . . . . .714
Figure 169. Counter timing diagram, update event when repetition counter is not used . . . . .715
Figure 170. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .716
Figure 171. Counter timing diagram, internal clock divided by 2 . . . . .717
Figure 172. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .717
Figure 173. Counter timing diagram, internal clock divided by N . . . . .718
Figure 174. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .718
Figure 175. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .719
Figure 176. Update rate examples depending on mode and TIMx_RCR register settings . . . . .720
Figure 177. External trigger input block . . . . .721
Figure 178. TIM1 ETR input circuitry . . . . .721
Figure 179. Control circuit in normal mode, internal clock divided by 1 . . . . .722
Figure 180. TI2 external clock connection example . . . . .723
Figure 181. Control circuit in external clock mode 1 . . . . .724
Figure 182. External trigger input block . . . . .724
Figure 183. Control circuit in external clock mode 2 . . . . .725
Figure 184. Capture/compare channel (example: channel 1 input stage) . . . . .726
Figure 185. Capture/compare channel 1 main circuit . . . . .726
Figure 186. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .727
Figure 187. Output stage of capture/compare channel (channel 4) . . . . .727
Figure 188. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .728
Figure 189. PWM input mode timing . . . . .730
Figure 190. Output compare mode, toggle on OC1 . . . . .732
Figure 191. Edge-aligned PWM waveforms (ARR=8) . . . . .733
Figure 192. Center-aligned PWM waveforms (ARR=8) . . . . .734
Figure 193. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .736
Figure 194. Combined PWM mode on channel 1 and 3 . . . . .737
Figure 195. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .738
Figure 196. Complementary output with dead-time insertion . . . . .739
Figure 197. Dead-time waveforms with delay greater than the negative pulse . . . . .739
Figure 198. Dead-time waveforms with delay greater than the positive pulse . . . . .740
Figure 199. Break and Break2 circuitry overview . . . . .742
Figure 200. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .744
Figure 201. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .745
Figure 202. PWM output state following BRK assertion (OSSI=0) . . . . .746
Figure 203. Output redirection (BRK2 request not represented) . . . . .747
Figure 204. Clearing TIMx OCxREF . . . . .748
Figure 205. 6-step generation, COM example (OSSR=1) . . . . .749
Figure 206. Example of one pulse mode. . . . .750
Figure 207. Retriggerable one pulse mode . . . . .752
Figure 208. Example of counter operation in encoder interface mode. . . . .753
Figure 209. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .754
Figure 210. Measuring time interval between edges on 3 signals . . . . .755
Figure 211. Example of Hall sensor interface . . . . .757
Figure 212. Control circuit in reset mode . . . . .758
Figure 213. Control circuit in Gated mode . . . . .759
Figure 214. Control circuit in trigger mode . . . . .760
Figure 215. Control circuit in external clock mode 2 + trigger mode . . . . .761
Figure 216. General-purpose timer block diagram . . . . .805
Figure 217. Counter timing diagram with prescaler division change from 1 to 2 . . . . .807
Figure 218. Counter timing diagram with prescaler division change from 1 to 4 . . . . .807
Figure 219. Counter timing diagram, internal clock divided by 1 . . . . .808
Figure 220. Counter timing diagram, internal clock divided by 2 . . . . .809
Figure 221. Counter timing diagram, internal clock divided by 4 . . . . .809
Figure 222. Counter timing diagram, internal clock divided by N . . . . .810
Figure 223. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .810
Figure 224. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .811
Figure 225. Counter timing diagram, internal clock divided by 1 . . . . .812
Figure 226. Counter timing diagram, internal clock divided by 2 . . . . .812
Figure 227. Counter timing diagram, internal clock divided by 4 . . . . .813
Figure 228. Counter timing diagram, internal clock divided by N . . . . .813
Figure 229. Counter timing diagram, Update event . . . . .814
Figure 230. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .815
Figure 231. Counter timing diagram, internal clock divided by 2 . . . . .816
Figure 232. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .816
Figure 233. Counter timing diagram, internal clock divided by N . . . . .817
Figure 234. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .817
Figure 235. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .818
Figure 236. Control circuit in normal mode, internal clock divided by 1 . . . . .819
Figure 237. TI2 external clock connection example. . . . .819
Figure 238. Control circuit in external clock mode 1 . . . . .820
Figure 239. External trigger input block . . . . .821
Figure 240. Control circuit in external clock mode 2 . . . . .822
Figure 241. Capture/Compare channel (example: channel 1 input stage) . . . . .822
Figure 242. Capture/Compare channel 1 main circuit . . . . .823
Figure 243. Output stage of Capture/Compare channel (channel 1). . . . .823
Figure 244. PWM input mode timing . . . . .825
Figure 245. Output compare mode, toggle on OC1 . . . . .827
Figure 246. Edge-aligned PWM waveforms (ARR=8) . . . . .828
Figure 247. Center-aligned PWM waveforms (ARR=8). . . . .830
Figure 248. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .831
Figure 249. Combined PWM mode on channels 1 and 3 . . . . .832
Figure 250. Clearing TIMx OCxREF . . . . .833
Figure 251. Example of one-pulse mode. . . . .834
Figure 252. Retriggerable one-pulse mode . . . . .836
Figure 253. Example of counter operation in encoder interface mode . . . . .837
Figure 254. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .838
Figure 255. Control circuit in reset mode . . . . .839
Figure 256. Control circuit in gated mode . . . . .840
Figure 257. Control circuit in trigger mode . . . . .841
Figure 258. Control circuit in external clock mode 2 + trigger mode . . . . .842
Figure 259. Master/Slave timer example . . . . .843
Figure 260. Master/slave connection example with 1 channel only timers . . . . .843
Figure 261. Gating TIM2 with OC1REF of TIM1 . . . . .844
Figure 262. Gating TIM2 with Enable of TIM1 . . . . .845
Figure 263. Triggering TIM2 with update of TIM1 . . . . .846
Figure 264. Triggering TIM2 with Enable of TIM1 . . . . .846
Figure 265. TIM16/TIM17 block diagram . . . . .877
Figure 266. Counter timing diagram with prescaler division change from 1 to 2 . . . . .879
Figure 267. Counter timing diagram with prescaler division change from 1 to 4 . . . . .879
Figure 268. Counter timing diagram, internal clock divided by 1 . . . . .881
Figure 269. Counter timing diagram, internal clock divided by 2 . . . . .881
Figure 270. Counter timing diagram, internal clock divided by 4 . . . . .882
Figure 271. Counter timing diagram, internal clock divided by N . . . . .882
Figure 272. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .883
Figure 273. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .883
Figure 274. Update rate examples depending on mode and TIMx_RCR register settings . . . . .885
Figure 275. Control circuit in normal mode, internal clock divided by 1 . . . . .886
Figure 276. TI2 external clock connection example. . . . .886
Figure 277. Control circuit in external clock mode 1 . . . . .887
Figure 278. Capture/compare channel (example: channel 1 input stage) . . . . .888
Figure 279. Capture/compare channel 1 main circuit . . . . .888
Figure 280. Output stage of capture/compare channel (channel 1). . . . .889
Figure 281. Output compare mode, toggle on OC1 . . . . .892
Figure 282. Edge-aligned PWM waveforms (ARR=8) . . . . .893
Figure 283. Complementary output with dead-time insertion. . . . .894
Figure 284. Dead-time waveforms with delay greater than the negative pulse. . . . .894
Figure 285. Dead-time waveforms with delay greater than the positive pulse. . . . .895
Figure 286. Output behavior in response to a break . . . . .897
Figure 287. Output redirection . . . . .899
Figure 288. 6-step generation, COM example (OSSR=1) . . . . .900
Figure 289. Example of one pulse mode . . . . .901
Figure 290. Low-power timer block diagram . . . . .930
Figure 291. Glitch filter timing diagram . . . . .932
Figure 292. LPTIM output waveform, single counting mode configuration . . . . .934
Figure 293. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set). . . . .934
Figure 294. LPTIM output waveform, Continuous counting mode configuration . . . . .935
Figure 295. Waveform generation . . . . .936
Figure 296. Encoder mode counting sequence . . . . .940
Figure 297. IRTIM internal hardware connections with TIM16 and TIM17 . . . . .953
Figure 298. Independent watchdog block diagram . . . . .954
Figure 299. Watchdog block diagram . . . . .964
Figure 300. Window watchdog timing diagram . . . . .965
Figure 301. RTC block diagram . . . . .971
Figure 302. Block diagram . . . . .1013
Figure 303. I 2 C-bus protocol . . . . .1015
Figure 304. Setup and hold timings . . . . .1017
Figure 305. I2C initialization flow . . . . .1019
Figure 306. Data reception . . . . .1020
Figure 307. Data transmission . . . . .1021
Figure 308. Target initialization flow . . . . .1024
Figure 309. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .1026
Figure 310. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .1027
Figure 311. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .1028
Figure 312. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .1029
Figure 313. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .1030
Figure 314. Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . .		1030
Figure 315. Controller clock generation . . . . .1032
Figure 316. Controller initialization flow . . . . .1034
Figure 317. 10-bit address read access with HEAD10R = 0 . . . . .1034
Figure 318. 10-bit address read access with HEAD10R = 1 . . . . .1035
Figure 319. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .1036
Figure 320. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .1037
Figure 321. Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . .		1038
Figure 322. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .1040
Figure 323. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .1041
Figure 324. Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . .		1042
Figure 325. Timeout intervals for t LOW:SEXT , t LOW:MEXT . . . . .1046
Figure 326. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .1049
Figure 327. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .1050
Figure 328. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .1051
Figure 329. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .1052
Figure 330. Bus transfer diagrams for SMBus controller transmitter . . . . .1053
Figure 331. Bus transfer diagrams for SMBus controller receiver . . . . .1055
Figure 332. USART block diagram . . . . .1077
Figure 333. Word length programming . . . . .1080
Figure 334. Configurable stop bits . . . . .1082
Figure 335. TC/TXE behavior when transmitting . . . . .1085
Figure 336. Start bit detection when oversampling by 16 or 8. . . . .1086
Figure 337. usart_ker_ck clock divider block diagram . . . . .1089
Figure 338. Data sampling when oversampling by 16. . . . .1090
Figure 339. Data sampling when oversampling by 8. . . . .1091
Figure 340. Mute mode using Idle line detection . . . . .1098
Figure 341. Mute mode using address mark detection . . . . .1099
Figure 342. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .1102
Figure 343. Break detection in LIN mode vs. Framing error detection. . . . .1103
Figure 344. USART example of synchronous master transmission. . . . .1104
Figure 345. USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		1104
Figure 346. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		1105
Figure 347. USART data clock timing diagram in synchronous slave mode (M bits = 00) . . . . .1106
Figure 348. ISO 7816-3 asynchronous protocol . . . . .1108
Figure 349. Parity error detection using the 1.5 stop bits . . . . .1110
Figure 350. IrDA SIR ENDEC block diagram. . . . .1114
Figure 351. IrDA data modulation (3/16) - normal mode . . . . .1114
Figure 352. Transmission using DMA . . . . .1116
Figure 353. Reception using DMA . . . . .1117
Figure 354. Hardware flow control between 2 USARTs . . . . .1117
Figure 355. RS232 RTS flow control . . . . .1118
Figure 356. RS232 CTS flow control . . . . .1119
Figure 357. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .1122
Figure 358. Wake-up event not verified (wake-up event = address match, FIFO disabled) . . . . .1122
Figure 359. LPUART block diagram . . . . .1163
Figure 360. LPUART word length programming . . . . .1166
Figure 361. Configurable stop bits . . . . .1168
Figure 362. TC/TXE behavior when transmitting . . . . .1170
Figure 363. lpuart_ker_ck clock divider block diagram . . . . .1173
Figure 364. Mute mode using Idle line detection . . . . .1177
Figure 365. Mute mode using address mark detection . . . . .1178
Figure 366. Transmission using DMA . . . . .1180
Figure 367. Reception using DMA . . . . .1181
Figure 368. Hardware flow control between 2 LPUARTs . . . . .1182
Figure 369. RS232 RTS flow control . . . . .1182
Figure 370. RS232 CTS flow control . . . . .1183
Figure 371. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .1186
Figure 372. Wake-up event not verified (wake-up event = address match, FIFO disabled) . . . . .1186
Figure 373. SPI block diagram. . . . .1214
Figure 374. Full-duplex single master/ single slave application. . . . .1215
Figure 375. Half-duplex single master/ single slave application . . . . .1216
Figure 376. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . .1217
Figure 377. Master and three independent slaves. . . . .1218
Figure 378. Multimaster application . . . . .1219
Figure 379. Hardware/software slave select management . . . . .1220
Figure 380. Data clock timing diagram . . . . .1221
Figure 381. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .1222
Figure 382. Packing data in FIFO for transmission and reception. . . . .1226
Figure 383. Master full-duplex communication . . . . .1229
Figure 384. Slave full-duplex communication . . . . .1230
Figure 385. Master full-duplex communication with CRC . . . . .1231
Figure 386. Master full-duplex communication in packed mode . . . . .1232
Figure 387. NSSP pulse generation in Motorola SPI master mode. . . . .1235
Figure 388. TI mode transfer . . . . .1236
Figure 389. SAI functional block diagram . . . . .1250
Figure 390. Audio frame . . . . .1253
Figure 391. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .1256
Figure 392. FS role is start of frame (FSDEF = 0) . . . . .1257
Figure 393. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .1258
Figure 394. First bit offset . . . . .1258
Figure 395. Audio block clock generator overview . . . . .1260
Figure 396. PDM typical connection and timing . . . . .1264
Figure 397. Detailed PDM interface block diagram . . . . .1265
Figure 398. Start-up sequence . . . . .1266
Figure 399. SAI_ADR format in TDM mode, 32-bit slot width . . . . .1267
Figure 400. SAI_ADR format in TDM mode, 16-bit slot width . . . . .1268
Figure 401. SAI_ADR format in TDM mode, 8-bit slot width . . . . .1269
Figure 402. AC'97 audio frame . . . . .1272
Figure 403. SPDIF format . . . . .1273
Figure 404. SAI_xDR register ordering . . . . .1274
Figure 405. Data companding hardware in an audio block in the SAI . . . . .1277
Figure 406. Tristate strategy on SD output line on an inactive slot . . . . .1279
Figure 407. Tristate on output data line in a protocol like I2S . . . . .1280
Figure 408. Overrun detection error . . . . .1281
Figure 409. FIFO underrun event . . . . .1281
Figure 410. USB peripheral block diagram . . . . .1315
Figure 411. Packet buffer areas with examples of buffer description table locations . . . . .1319
Figure 412. Block diagram of debug support infrastructure . . . . .1349
Figure 413. JTAG TAP state machine . . . . .1352
Figure 414. Debug and access port connections . . . . .1364
Figure 415. Debugger connection to debug components . . . . .1366
Figure 416. Embedded cross trigger . . . . .1372
Figure 417. Mapping trigger inputs to outputs . . . . .1374
Figure 418. Cross trigger configuration example . . . . .1375
Figure 419. CPU2 CoreSight™ topology . . . . .1402
Figure 420. CPU1 CoreSight™ topology . . . . .1437
Figure 421. Trace port interface unit (TPIU) . . . . .1493

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