63. Revision history

Section 2 renamed Memory and bus architecture.
Updated Section : Embedded bootloader .

Section 3: Embedded Flash memory (FLASH)
Updated Section : Flash sector erase , Section : Standard Flash bank erase , Section : Flash bank erase with automatic protection removal and Section : Flash mass erase .
Added Section : Flash mass erase with automatic protection removal .
Updated Table 16: FLASH register map and reset value :
– FLASH_BOOT7_CURR/PRG (add offset = 0x140/0x144) available only on RM0399.
– Added FLASH_CRCEADD2R at add. offset = 0x158
– Added FLASH_CRCEADD2R at add offset = 0x15C

Section 6: Power control (PWR)
Updated Section 6.3.1: PWR pins and internal signals .
Updated VBAT in Section 6.4: Power supplies .
Updated Figure 13: Power supply overview and Figure 15: Device startup with VCORE supplied from voltage regulator .
Removed VCORE in Section 6.5: Power supply supervision .
Updated Figure 24: VCORE voltage scaling versus system power modes and Figure 25: Power control modes detailed state diagram .

Section 8: Reset and Clock Control (RCC)
Names of all clock source selection bits changed from XXSCR to XXSEL.
RC48 renamed HSI48.
VSWRST bit renamed BDRST in RCC_BDCR and bit description modified.
CAMITFEN renamed DCMIEN in RCC_AHB2ENR; and CAMITFLPEN renamed DCMILPEN in RCC_AHB2LPENR.
FLITFLPEN bit renamed FLASHLPEN in RCC_AHB3LPENR.
HDMICELPEN renamed CECLPEN in RCC_APB1LPENR.
Updated peripheral kernel clock names in the whole document.
Updated Figure 34: System reset circuit to remove VDDA.
Updated maximum frequency for ADC1, 2, 3 in Table 51: Kernel clock distribution overview .
Removed lsi_ck as USBxOTG clock in Section : Peripherals dedicated to control and data transfer .

Section 8: Reset and Clock Control (RCC) (continued)
Renamed USART7RST/EN/LPEN bits into UART7RST/EN/LPEN, and USART8RST/EN/LPEN bits into UART8RST/EN/LPEN in Section 8.7.31: RCC APB1 Peripheral Reset Register ( RCC_APB1LRSTR ), Section 8.7.43: RCC APB1 Clock Register ( RCC_APB1LENR ) and Section 8.7.52: RCC APB1 Low Sleep Clock Register ( RCC_APB1LLPENR ).

Section 10: Hardware semaphore (HSEM)
Renamed pclk into hsem_hclk in the whole document.
Updated COREID bit description in Section 10.4.1: HSEM register ( HSEM_R0 - HSEM_R31 ).

Section 11: General-purpose I/Os (GPIO)
Table 84: GPIO register map and reset values:
– updated GPIOx_MODER reset values
– changed index to A to K for GPIOx_AFRH.
– added GPIOC..K_PUPDR

Section 12: System configuration controller (SYSCFG)
Updated SYSCFG_UR3 register.

Section 13: Block interconnect
In Table 92: DMAMUX1, DMA1 and DMA2 connections , renamed dac1_dma and dac2_dma into dac_ch1_dma and dac_ch2_dma, respectively.
Updated several source and destination signals in Table 88: Peripherals interconnect matrix details and Table 89: EXTI wakeup inputs .

Section 17: DMA request multiplexer (DMAMUX)
Updated resources in Table 110: DMAMUX1: assignment of multiplexer inputs to resources to Table 112: DMAMUX1: assignment of synchronization inputs to resources .

Section 19: Nested Vectored Interrupt Controllers
Added LCD-TFT interrupts (ltc_it and ltc_err_it) in Table 130: NVIC .
Extended interrupt and event controller (EXTI)
Replaced DMA1 by BDMA for events 66 to 73 in Table 133: EXTI Event input mapping .

Section 22: Flexible memory controller (FMC)

• – Updated internal signals in Figure 86: FMC block diagram
• – HCLK renamed fmc_hclk
• – KCK_FMC renamed fmc_ker_ck

Updated Section 22.5: AXI interface to add 32-bit accesses. Read FIFO depth changed to 6x64 bits. AXI bus width correct (64 bits instead of 32 bits).

All waveforms made generic for what regards data bus and NBL bits.

In Section : SRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4) , modified DATAST example and updated BURSTURN description. In Section : SRAM/NOR-Flash write timing registers 1..4 (FMC_BWTR1..4) : updated BURSTURN description. Updated Section : SDRAM Control registers 1,2 (FMC_SDCR1,2) to add bitfield width.

Added missing FMC_SDCR2 bits in Table 181: FMC register map .

Section 23: Quad-SPI interface (QUADSPI)

Updated internal signals in Figure 115: QUADSPI block diagram when dual-flash mode is disabled and Figure 116: QUADSPI block diagram when dual-flash mode is enabled . Added Section 23.3.2: QUADSPI pins and internal signals . Modified error type for access by Cortex CPU in Section 23.3.7: QUADSPI memory-mapped mode .

Added Section 23.3.8: QUADSPI Free running clock mode as well as FRCM bit in Section 23.5.6: QUADSPI communication configuration register (QUADSPI_CCR) . Updated Section 23.5.1: QUADSPI control register (QUADSPI_CR) . In Table 185: QUADSPI register map and reset values , changed DMAEN bit to reserved for QUADSPI_CR register.

Section 24: Delay block (DLYB)

Added internal signals in Figure 123: DLYB block diagram and added Section 24.3.2: DLYB pins and internal signals .

Section 25: Analog-to-digital converters (ADC)

Number of ADCs changed to 3 in Section 25.1: Introduction .

Added internal signals in Section 25.3.1: ADC block diagram .

Changed ADCx_IN[19:0] into ADCx_INP[19:0] and ADCx_INN[19:0] in Figure 124: ADC block diagram and Table 190: ADC input/output pins . Changed ADC_CLK into adc_ker_ck.

Updated Figure 126: ADC1 connectivity , Figure 127: ADC2 connectivity and Figure 128: ADC3 connectivity and added note below figure. Updated Figure 175: Dual ADC block diagram(1) .

Updated notes in Section : Dual clock domain architecture .

Updated Section 25.3.11: Channel selection (SQRx, JSQRx) and Section 25.3.12: Channel preselection register (ADCx_PCSEL) .

Section 25: Analog-to-digital converters (ADC) (continued)

Examples given for 24 MHz instead of 72 MHz in Section 25.3.13: Channel-wise programmable sampling time (SMPR1, SMPR2) and Section 25.3.17: Timing .

6-bit resolution removed and updated Table 195: TSAR timings depending on resolution in Section 25.3.23: Programmable resolution (RES) - fast conversion mode .

Updated notes in Section : Combined regular/injected simultaneous mode and Section : Combined regular simultaneous + alternate trigger mode .

Added Section : DFSDM mode in dual ADC simultaneous mode .

Changed ADC3_IN18 into ADC3 VINP[18] in Section 25.3.33: Temperature sensor .

Changed ADC3_IN17 into ADC3 VINP[17] in Section 25.3.34: VBAT supply monitoring .

Changed ADC3_IN19 into ADC3 VINP[19] in Section 25.3.35: Monitoring the internal voltage reference .

Changed all bit access type to 'r' in Section 25.5.15: ADC x regular Data Register (ADCx_DR) (x=1 to 3).

Updated Table 206: ADC register map and reset values (master and slave ADC common registers) offset =0x300).

Section 26: Digital-to-analog converter (DAC)

Updated/added internal signals in Figure 194: DAC channel block diagram .

Added Section 26.3.2: DAC pins and internal signals .. APB1 clock and LSI clock replaced by dac_pclk and by lsi_ck in the whole document.

Section 28: Comparator (COMP)

Replaced COMP_IFCR by COMP_ICFR in Section 28.7.1: Comparator status register (COMP_SR) .

Section 29: Operational amplifiers (OPAMP)

Replaced all occurrences of DACx_int by dac_outx (x = 1, 2).

Updated VP_SEL bit description in Section 29.6.1: OPAMP1 control/status register (OPAMP1_CSR) register.

Section 31: Digital camera interface (DCMI)

Section DCMI pins merged with Section 31.4.4: DCMI physical interface .

External signals HSYNC, VSYNC and PIXCLK standardized to DCMI_HSYNC, DCMI_VSYNC and DCIM_PIXCLK in the whole document. Updated Figure 224: DCMI block diagram and Figure 225: Top level block diagram .

Section 32: LCD-TFT Display Controller (LTDC)

LCD-TFT pins and signal interface renamed LCD-TFT pins and external signal interface .

Internal signal names updated in Figure 233: LTDC block diagram . ck_axi_d1 renamed ltdc_aclk in the whole document.

Updated Section 32.3.4: LTDC reset and clocks .

Updated CFBP bitfield size in Section 32.7.23: LTDC Layerx Color Frame Buffer Length Register (LTDC_LxCFBLR) (where x=1..2).

Section 33: JPEG codec (JPEG)
Added Internal signal names in Figure 238: JPEG codec block diagram and added Section 33.3.2: JPEG internal signals .
Suppressed DMA feature.
Updated JPEG_CR, JPEG_SR and JPRG_CFR registers in Table 259: JPEG codec register map and reset values .

Section 37: High-Resolution Timer (HRTIM)
Renamed SCOUT into HRTIM_SCOUT in the whole section.
Renamed Tx into HRTIM_CHxy in all figures where it is referred to.
Updated internal signals in Figure 274: High-resolution timer block diagram .
Added hrtim_in_sync1 and hrtim_out_sync1 in Table 283: HRTIM Input/output summary .
Updated Section : Definition of terms .
Updated internal signal names in all the figures where they are mentioned and in HRTIM functional description
Added note related to hrtim_ker_ck in Table 283: HRTIM Input/output summary .
Modified ADC3TAPER bit description in Section 37.5.56: HRTIM ADC Trigger 3 Register (HRTIM_ADC3R) .
Modified ADC4TCRST, ADC4TAPER, ADC4TAC2, ADC4EEV6, ADC4MPER and DC4MC1 bit descriptions in and Section 37.5.57: HRTIM ADC Trigger 4 Register (HRTIM_ADC4R) .

Section 43: Low-power timer (LPTIM)
Added internal signals in Figure 515: Low-power timer block diagram (LPTIM1 and LPTIM2) , Figure 516: Low-power timer block diagram (LPTIM3) and Figure 517: Low-power timer block diagram (LPTIM4 and LPTIM5) . Added Section 43.4.2: LPTIM pins and internal signals .
Table 335: LPTIM1 external trigger connection to Table 339: LPTIM5 external trigger connection updated and moved under Section 43.4.3: LPTIM input and trigger mapping . Table 340: LPTIM1 Input 1 connection to Table 344: LPTIM3 Input 1 connection updated and moved under Section 43.4.3: LPTIM input and trigger mapping .
Updated TRIGSEL bitfield description in Section 43.6.4: LPTIM configuration register (LPTIM_CFGR) .

Section 43: Low-power timer (LPTIM) (continued)
Added caution note for COUNTRST bit in Section 43.6.5: LPTIM control register (LPTIM_CR) .
Updated IN1SEL and IN2SEL bitfield description and added caution note in Section 43.6.9: LPTIM configuration register 2 (LPTIM_CFGR2) .
Added caution note in Section 43.6.10: LPTIM3 configuration register 2 (LPTIM3_CFGR2) .

Section 46: Real-time clock (RTC)
Added Figure 527: RTC block overview .
Updated title of Figure 528: Detailed RTC block diagram .
Added Section 46.3.2: RTC pins and internal signals . Updated Table 353: RTC pins and internal signals .
Updated Section 46.3.3: GPIOs controlled by the RTC .
Updated Section 46.6.16: RTC tamper configuration register (RTC_TAMPCR) .

Section 47: Inter-integrated circuit (I2C) interface
Updated OA1[7:1] and OA2[7:1] bit description in Section 47.7.3: Own address 1 register (I2C_OAR1) and Section 47.7.4: Own address 2 register (I2C_OAR2) .
Replaced HSI16 by HSI or CSI or internal oscillator in Section 47.4.14: Wakeup from Stop mode on address match .

Section 48: Universal synchronous asynchronous receiver transmitter (USART)
Section 48.5.14: USART synchronous mode : removed Figure RX data setup/hold time , added reference to synchronous master mode in Figure 574: USART data clock timing diagram in synchronous master mode (M bits = '00') and Figure 575: USART data clock timing diagram in synchronous master mode (M bits = '01') and figure contents updated to mention two M bits instead of one.
Updated Figure 586: Wakeup event verified (wakeup event = address match, FIFO disabled) in Section 48.5.21: USART low-power management .

Section 51: Serial audio interface (SAI)
Updated SYNCIN bitfield description in Section 51.5.1: Global configuration register (SAI_GCR) .

Section 50: Serial peripheral interface (SPI)
Updated note in Section : Simplex communications .
Added note about the PCM long and short frame definition in Section : PCM standard . Added Section 50.9.3: Bits and fields usable in I2S/PCM mode description and Table 391: Bit fields usable in PCM/I2S mode .
Updated WSINV in Section 50.11.14: SPI/I2S configuration register (SPI_I2SCGFR) and Section 50.12: SPI register map and reset values .

Section 52: SPDIF receiver interface (SPDIFRX)
Added internal signals in Section Figure 658.: SPDIFRX block diagram and added Section 52.3.1: SPDIFRX pins and internal signals .

Section 55: Secure digital input/output MultiMediaCard interface (SDMMC)

• – Renamed internal signals in the whole section; updated Figure 694: SDMMC block diagram ; added Section 55.4.2:SDMMC pins and internal signals
• – Added Section 55.4.7: MDMA request generation
• – Removed SDMMC_VER, SDMMC_ID, SDMMC_SID
• – Updated SDMMC_STAR bit 12 and 13 in Table 449: SDMMC register map .

Section 56: FD Controller Area Network (FDCAN)

ASC (asynchronous serial communication) removed from the whole section.

Added F0OM bit (bit 31) and F1OM bit (bit 31) in FDCAN Rx FIFO 0 Configuration Register (FDCAN_RXF0C) and FDCAN Rx FIFO 1 Configuration Register (FDCAN_RXF1C) , respectively.

Section 57: USB on-the-go high-speed (OTG_HS)

Added Section 57.4.2: USB OTG pin and internal signals .

Section 60: Debug infrastructure

Updated Section 60.5.8: Microcontroller debug unit (DBGMCU) .

Replaced in all DBGMCU register names:

• – D1APB1 by APB3
• – D2APB1 by APB1
• – D2APB2 by APB2
• – D3APB4byAPB4

WDGLSD2 bit changed to reserved in Section : DBGMCU APB4 peripheral freeze register CPU (DBGMCU_APB4FZ1) DBGMCU_APB4FZ1.

Removed reserved registers in Table 578: DBGMCU register map and reset values .

Section 2.3: Embedded SRAM

Added Section : Error code correction (ECC) .

Section 12: System configuration controller (SYSCFG)

Changed 2.5 to 2.7 V in HSLV bit description of SYSCFG compensation cell control/status register (SYSCFG_CCCSR) and IO_HSLV of SYSCFG user register 17 (SYSCFG_UR17) .

Section 3: Embedded Flash memory (FLASH)

In Table 16: FLASH register map and reset value :

• – Updated FLASH_OPTSR_CUR at address offset 0x11C.
• – Updated FLASH_OPTSR_PRG at address offset 0x120.

Changed 2.5 to 2.7 V in IO_HSLV bit description of FLASH option status register (current value) (FLASH_OPTSR_CUR) and FLASH option status register (value to program) (FLASH_OPTSR_PRG) .

Section 6: Power control (PWR)
Replace AIEC by EXTI and wait VDD11 by Wait VCORE in Figure 27: Dynamic voltage scaling behavior with D1, D2 and system in Stop mode , Figure 28: Dynamic Voltage Scaling D1, D2, system Standby mode and Figure 29: Dynamic voltage scaling behavior with D1 and D2 in DStandby mode and D3 in autonomous mode .
Updated Section 6.4.7: USB regulator .
Updated Section : Entering Stop mode .

Section 7: Low-power D3 domain
Replaced VDD11 by VCORE.

Section 8: Reset and Clock Control (RCC)
Updated maximum frequency for ADC1, 2, 3 in Table 51: Kernel clock distribution overview .

Section 10: Hardware semaphore (HSEM)
Whole section updated to align with the product features.

Section 14: MDMA controller (MDMA)
Removed iterator in MDMA_CxISR and MDMA_CxIFCR bit names.

Section 19: Nested Vectored Interrupt Controllers
Changed usart4_gbl_it into uart4_gbl_it in Table 130: NVIC .

Section 21: Cyclic redundancy check calculation unit (CRC)
Updated first two features of Section 21.2: CRC main features .

Section 25: Analog-to-digital converters (ADC)
Section 25.2: ADC main features : suppressed ADC supply requirements.
Renamed VTS into VSENSE in the whole section.
Updated Figure 124: ADC block diagram , Figure 126: ADC1 connectivity , Figure 127: ADC2 connectivity and Figure 128: ADC3 connectivity .
VINN connected to ADC_INN instead of ADC_INN-1 in Table 190: ADC input/output pins .
Section : I/O analog switches voltage booster : voltage booster enable bit renamed BOOTSE (instead of BOOTSEN) and corresponding register renamed SYSCFG_PMCR (instead of SYSCFG_CFGR1).

Section 25: Analog-to-digital converters (ADC) (continued)

Added note related to software trigger selection in Section 25.3.16: Starting conversions (ADSTART, JADSTART) .

Updated Figure 136: Triggers are shared between ADC master and ADC slave , Figure 191: Temperature sensor channel block diagram , Figure 192: VBAT channel block diagram and Figure 193: VREFINT channel block diagram .

Updated Section : Analog watchdog .

Updated software notification by interrupt at end of conversion in Section : Interleaved mode with independent injected ; updated Figure 178: Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode and Figure 179: Interleaved mode on 1 channel in single conversion mode: dual ADC mode .

Removed temperature sensor precision and replaced ambient by junction temperature in Section 25.3.33: Temperature sensor .

Section 25.6.2: ADC x common control register (ADCx_CCR) (x=12 or 3):

• – VBATEN bit description made generic
• – TSEN renamed VSENSEEN and description made generic
• – Updated Table 203: DELAY bits versus ADC resolution .

ADCx_OR register suppressed since all bits are reserved.

Renamed ADCx_LHTR1 into ADCx_HTR1.

Changed ADCx_ISR bit access type to rc_w1.

Updated iterators for all ADC common registers

Section 26: Digital-to-analog converter (DAC)

Updated VREF+ range in Table 207: DAC input/output pins .

Updated Section 26.3.5: DAC conversion .

Added note related to ENx limitation when CENx is set in Section 26.3.12: DAC channel buffer calibration .

Added case of accesses to DHRxxxD for wave generation in Section 26.3.13: Dual DAC channel conversion (if available) .

Renamed DAC_M_ID into DAC_SIDR and M_ID bits into SID.

Section 26: Digital-to-analog converter (DAC) (continued)

Added Section 26.5: DAC interrupts

Section 26.6.1: DAC x control register (DACx_CR) (x=1 to 2) :

• – TEN2 bit: replaced DACx_DHRy by DACx_DHR2
• – TEN1 bit: replaced DACx_DHRy by DACx_DHR1.
• – TSELx bits: updated information on trigger selection/mapping

Section 26.6.16: DAC x mode control register (DACx_MCR) (x=1 to 2) : added note related to ENx bit for MODEx bit description.

Section 26.6.19: DAC x Sample and Hold hold time register (DACx_SHHR)(x=1 to 2) : added notes related to THOLDx modification when ENx=0.

Section 26.6.20: DAC x Sample and Hold refresh time register (DACx_SHRR)(x=1 to 2) : added note related to TREFRESHx modification when ENx=0.

Suppressed DAC_OR register.

Section 29: Operational amplifiers (OPAMP)
Updated OPAMP1_VINM internal connection in Table 225: Operational amplifier possible connections .

Section 37: High-Resolution Timer (HRTIM)
Updated Note 1. in Table 289: External events mapping and associated features .

Section 44: System window watchdog (WWDG)
Corrected math equations used to calculate the WWDG period.

Section 47: Inter-integrated circuit (I2C) interface
Updated NACKCF bit definition in Section 47.7.8: Interrupt clear register (I2C_ICR) register.

Section 51: Serial audio interface (SAI)
SAIXEN bit renamed SAIEN in SAI_xCR register.
Updated Figure 643: PDM typical connection and timing to make the block diagram independent from the number of data and clock lines.
Updated Figure 644: Detailed PDM interface block diagram to add “n” and “p” indexes (n being the number of data lines and p the number of microphone pairs).

Section 52: SPDIF receiver interface (SPDIFRX)
Updated Figure 658: SPDIFRX block diagram .

Section 59: HDMI-CEC controller (HDMI-CEC)
Updated
– Section 59.2: HDMI-CEC controller main features
– Updated Figure 798: HDMI-CEC block diagram

Section 61: Device electronic signature
Updated Unique device ID register base address in Section 61.1: Unique device ID register (96 bits) .
Updated Flash size base address in Section 61.2: Flash size .
Replaced package data register description by reference to SYSCFG_PKGR in Section 61.3: Package data register .

Section 2: Memory and bus architecture
Updated Figure 1: System architecture for STM32H743/53xx and STM32H750xB devices.
Updated Table 2: Bus-master-to-bus-slave interconnect.
Section 2.1.6: CPU buses: updated Cortex®-M7 and Cortex®-M7 DTCM, core with FPU replaced by CPU for I-bus, D_bus and S-bus.
Section 2.1.7: Bus master peripherals: updated MDMA controller, DMA1/2 controllers and BDMA controller.
Added Table 6: Memory map and default device memory area attributes in Section 2.3.2: Memory map and register boundary addresses. Updated Table 7: Register boundary addresses.

Major update of Section 4: Embedded Flash memory (FLASH).

Section 4: Secure memory management:
Modified title.

Section 5: Power control (PWR)
Changed RC48 to HSI48 in Figure 18: Power supply overview.

Section 7: Reset and Clock Control (RCC)
Removed USB_PHY2 in the whole section.
Updated maximum allowed clock frequency for ADC1, 2, 3 Table 58: Kernel clock distribution overview.
Updated Figure 52: Kernel clock distribution for USB (2).

In RCC_AHB1ENR/RCC_C1_AHB1ENR: renamed USB2OTGEN into USB2OTGHSEN, USB1ULPIEN into USB1OTGHSULPIEN, USB1OTGEN into USB1OTGHSEN.
In RCC_AHB1LPENR/RCC_C1_AHB1LPENR: renamed USB2OTGLPEN into USB2OTGHSLPEN, USB1ULPILPEN into USB1OTGHSULPILPEN, USB1OTGLPEN into USB1OTGHSLPEN.
Bits changed to reserved: TMPSENSRST of RCC_APB4RSTR register, TMPSENSEN of RCC_APB4ENR and TMPSENSLPEN of RCC_APB4LPENR.

Section 13: System configuration controller (SYSCFG)
Renamed SYSCFG_CMPCR into SYSCFG_CCCSR.
Added SYSCFG configuration register (SYSCFG_CFGR).
SYSCFG user register 2 (SYSCFG_UR2): changed High/medium/Low level to Level3/2/1.
SYSCFG user register 11 (SYSCFG_UR11): swapped IWDG1M configurations.
SYSCFG user register 12 (SYSCFG_UR12): swapped IWDG2M configurations.

Section 12: Block interconnect

In Table 92: Peripherals interconnect matrix details:

Changed EXTx into adc_ext_trgx and JEXTx into adc_jext_trgx for ADC3

Updated D2/USB1/2 SOF connection

Changed PRC0 to 3 into d3_pendclear_in[0] to d3_pendclear_in[3] in Table 94: EXTI pending requests clear inputs.

Added DSI signals in Table 95: MDMA.

Updated EXTI connection in Table 97: DMAMUX2 and BDMA connections: dmamux1_req_inx numbering changed to start from dmamux1_req_in1 instead of dmamux1_req_in0 in Table 96: DMAMUX1, DMA1 and DMA2 connections and Table 97: DMAMUX2 and BDMA connections

Section 16: Basic direct memory access controller (BDMA)

Major section update.

Section 12: DMA request multiplexer (DMAMUX)

Updated Section 12.2: DMAMUX main features.

Updated all tables from Table 115: DMAMUX1 and DMAMUX2 instantiation to Table 121: DMAMUX2: assignment of synchronization inputs to resources.

Updated Section : Synchronization mode and channel event generation.

Removed note from Section : Synchronization overrun and interrupt.

Updated Section 12.4.5: DMAMUX request generator, Section 16.6.1: DMAMUX1 request line multiplexer channel x configuration register (DMAMUX1_CxCR), Section 16.6.2: DMAMUX2 request line multiplexer channel x configuration register (DMAMUX2_CxCR), Section 16.6.7: DMAMUX1 request generator channel x configuration register (DMAMUX1_RGxCR) and Section 16.6.8: DMAMUX2 request generator channel x configuration register (DMAMUX2_RGxCR).

Removed Section 12.6.13: DMAMUX illegal access flag register (DMAMUX_IAFR), Section 12.6.14: DMAMUX illegal access flag clear status register (DMAMUX_IAFCR) and Section 12.6.15: DMAMUX illegal access interrupt enable register (DMAMUX_IAIER).

Section 18: Chrom-Art Accelerator™ controller (DMA2D)
Added Section 18.4.8: DMA2D output FIFO byte reordering.
Added Section : Memory-to-memory with PFC, blending and fixed color FG and Section : Memory-to-memory with PFC, blending and fixed color BG.
Updated Section 18.6.1: DMA2D control register (DMA2D_CR):
Updated MODE[2:0] to MODE[3:0] bit description.
Added bit 6 LOM
Updated Section 18.6.5: DMA2D foreground offset register (DMA2D_FGOR) LO[15:0] bit description. Updated Section 18.6.7: DMA2D background offset register (DMA2D_BGOR) LO[15:0] bit description. Updated Section 18.6.9: DMA2D foreground color register (DMA2D_FGCOLR). Updated Section 18.6.11: DMA2D background color register (DMA2D_BGCOLR). Updated Section 18.6.14: DMA2D output PFC control register (DMA2D_OPFCCR) adding SB bit 6 description. Updated Section 18.6.17: DMA2D output offset register (DMA2D_OOR) LO[15:0] bit description.
Added identification registers: DMA2D_VERR, DMA2D_IPIDR, DMA2D_SIDR.

Section 20: Nested Vectored Interrupt Controllers (NVIC1 and NVIC2)
Updated Table 138: NVIC and Section 20.1.1: SysTick calibration value register.

Section 21: Extended interrupt and event controller (EXTI)
Added note related to WKUP1 to 6 in Table 155: EXTI Event input mapping

Section 23: Flexible memory controller (FMC)
Updated Figure 106: FMC memory banks (default mapping) and Table 147: FMC bank mapping options to change Bank 4 to “not used by FMC”).
Updated Section : General transaction rules.

Section 15: Quad-SPI interface (QUADSPI)
Updated access types in Section 15.5.1: QUADSPI control register (QUADSPI_CR) and Section 15.5.4: QUADSPI flag clear register (QUADSPI_FCR).

Section 28: Analog-to-digital converters (ADC)
\( f_{ADC} \) and \( T_{ADC} \) replaced by \( f_{ADC\_ker\_ck} \) and \( t_{ADC\_ker\_ck} \) in the whole IP user specification. Added \( f_{ADC\_ker\_ck} \) in Figure 179: ADC clock scheme. \( FHCLK \) replaced by \( f_{ADC\_hclk} \) in Section : Clock ratio constraint between ADC clock and AHB clock.
Replaced EXTSEL by JEXTSEL and \( adc\_ext\_trg0/1 \) by \( adc\_jext\_trg0/1 \) in Table 202: ADC1, ADC2 and ADC3 - External triggers for injected channels.
Updated note for JEOIE in Section 28.6.2: ADC interrupt enable register (ADC_IER).

Section 28: Analog-to-digital converters (ADC) (continued)
Updated conditions for programming ADC_JSQR register in Section 28.4.10: Constraints when writing the ADC control bits, Section 28.4.11: Channel selection (SQRx, JSQRx), as well as in notes related to all Section 28.6.16: ADC injected sequence register (ADC_JSQR) bitfields (product errata sheets updated accordingly).
Updated note related to offset correction in Section : Single ADC operating modes support when oversampling.
Updated Section 28.6.8: ADC channel preselection register (ADC_PCSEL).
Removed calibration value in Section 28.6.26: ADC calibration factors register (ADC_CALFACT).

Section 30: Digital-to-analog converter (DAC)
Changed data register indexing scheme in the whole document.
Updated Figure 252: Dual-channel DAC block diagram.
Added Section 30.3: DAC implementation.
Section : Sample and Hold mode:
Replaced SAMx by TSAMPEx.
Replaced CL by CSH.
Replaced TSAMx by TSAMPLEx.
Replaced TREFx by TREFRESHx/
Replaced \( t_{\text{sampling}} \) by \( t_{\text{SAMP}} \) .
Replaced \( t_{\text{stab-BON}} \) and \( t_{\text{stab-BOFF}} \) by 7 µs and 3 µs, respectively.
Replace \( T_{\text{offtrimmax}} \) by \( t_{\text{TRIM}} \) .
DAC status register (DAC_SR): for DAC1RDY and DAC1RDYbits, replaced DAC_CH1 and DAC_CH2 by DAC channel 1 and DAC channel 2, respectively.

Section 32: Digital filter for sigma delta modulators (DFSDM)
Updated Section 32.4.3: DFSDM reset and clocks and Section 32.4.4: Serial channel transceivers.

Section 33: Digital camera interface (DCMI)
Added 10-12-14-bit progressive video format in Section 33.5.1: Data formats.

Section 21: True random number generator (RNG)
BYP removed in the register description and map register.

Section 37: Hash processor (HASH)
In the whole document:
Replaced SHA1, SHA224, SHA256 by SHA-1, SHA-224, SHA-256.
Replaced HASH_Hx by HASH_HRx
Updated Section 37.1: Introduction
Updated Section 37.2: HASH main features
Updated Section 37.3.3: About secure hash algorithms

Section 24: Advanced-control timers (TIM1)
Updated procedure in Section : External clock source mode 1, Section 24.3.7: Input capture mode, Section 24.3.8: PWM input mode and Section 24.3.20: One-pulse mode. Updated Section 24.3.16: Using the break function, including Figure 191: Break and Break2 circuitry overview.

Section 25: General-purpose timer (TIM2)
Added TIM4 timer input selection register (TIM4_TISEL)

Section 26: General-purpose timers (TIM16/TIM17)
TI1SEL[3:0] description updated for 0001 configuration in Section 26.4.22: TIM17 input selection register (TIM17_TISEL).

Section 27: Low-power timer (LPTIM)
Added Section 27.4.15: Debug mode.

Section 31: System window watchdog (WWDG)
Updated Figure 290: Watchdog block diagram and Figure 291: Window watchdog timing diagram. Updated Section 31.3.2: Enabling the watchdog and Section 31.3.6: Debug mode. Updated Table 174: WWDG register map and reset values.

Section 32: Inter-integrated circuit (I2C) interface
Updated Figure 292: I2C block diagram.
Updated Section 32.4.5: I2C initialization removing the reference to RCC and modified Figure 294: Setup and hold timings.
Updated Table 189: Effect of low-power modes on the I2C.
Updated Section 32.6: I2C interrupts.
Updated note in Section : Master communication initialization (address phase).
Updated START bit 13 description in Section 32.7.2: I2C control register 2 (I2C_CR2).

Section 33: Universal synchronous/asynchronous receiver transmitter (USART/UART)
Section title updated to include UART
Added DWU formula in Section 33.5.8: Tolerance of the USART receiver to clock deviation.
Updated Section 33.5.21: USART low-power management
Added Section : Determining the maximum USART baud rate that allows to correctly wake up the microcontroller from low-power mode.
Replaced undocumented w_r0 access type by w access type in Section 33.7.8: USART request register (USART_RQR). Updated notes related to reserved bit/bitfield depending on USART feature in USART control register 1 [alternate] (USART_CR1), USART control register 2 (USART_CR2), USART control register 3 (USART_CR3), USART interrupt and status register [alternate] (USART_ISR) and USART interrupt flag clear register (USART_ICR).

Section 34: Low-power universal asynchronous receiver transmitter (LPUART)

Updated Section : Determining the maximum LPUART baud rate that allows to correctly wake up the MCU from low-power mode.

Transmit data register (LPUART_TDR) and Receive data register (LPUART_RDR) reset value changed from undefined to 0x0000 0000.

Updated notes related to reserved bit/bitfield depending on LPUART feature in Control register 3 (LPUART_CR3) and Interrupt and status register [alternate] (LPUART_ISR).

Section 36: Serial audio interface (SAI)

Updated Section : Clock generator programming in SPDIF generator mode.

Section 54: SPDIF receiver interface (SPDIFRX)

Suppressed references to spdifrx_symb_ck in the whole section.

Removed SPDIRX_VERR/IDR/SIDR registers.

Section 57: FD controller area network (FDCAN)

Changed fdcan_ker_ck max value from 500 MHz to 100 MHz.

Major section update.

Section 57: USB on-the-go high-speed (OTG)

Major section update.

Section 61: Ethernet (ETH): Gigabit media access control (GMAC) with DMA controller

Updated Rx flow control sequence in Section : Receive flow control.

Removed column “Behavior of the sbd_perch_tx_intr_o[] and sbd_perch_rx_intr_o[]” in Table 523: Transfer complete interrupt behavior.

Remove all references to non-user internal signals in register descriptions.

Updated SARC[2:0] configurations in Operating mode configuration register (ETH_MACCR). Updated DZPQ bit description in Tx Queue 0 flow control register (ETH_MACQ0TXFCR). Changed bit 21 to reserved in LPI control status register (ETH_MACLCSR). Changed bits 1:2 to reserved in Interrupt enable register (ETH_MACIER). Changed bits 1, 2 and 15 to reserved in Interrupt status register (ETH_MACISR). Changed bit 28 to reserved in L3 and L4 control 1 register (ETH_MACL3L4C1R). Removed ETH_MTLRxQ1OMR register description and updated Rx queue i operating mode register (ETH_MTLRXQiOMR) to support both Queue 0 and 1. Changed bits 20:16 to reserved in MMC Rx interrupt mask register (ETH_MMC_RX_INTERRUPT_MASK).

Added STM32H742xx part numbers.
Added Table 1: Peripherals versus products.
Added STM32H742xx and STM32H750xx in Table 2: Availability of security features.
Added case of reset during half word write in Section : Error code correction (ECC).
Section 4: Embedded Flash memory (FLASH)
Updated Figure 8: Embedded Flash memory usage.
Section : Adjusting programming timing constraints: added note related to WRHIGHFREQ modification during Flash memory programming/erasing.
Section : Adjusting programming parallelism: added note related to PSIZE1/2 modification during Flash memory programming/erasing.
Secure DTCM size (ST_RAM_SIZE):
Removed Secure DTCM size (ST_RAM_SIZE) from Section : Changing security option bytes.
Updated ST_RAM_SIZE description and added ST_RAM_SIZE to the values programmed in the data protection option bytes in Section 4.4.6: Description of data protection option bytes.
Section : Definitions of RDP global protection level: updated description of RDP level 1 to 0 regression and RDP level 2.
Section : RDP protection transitions: user Flash memory can be partially or mass erased when doing a level regression from RDP level 1 to 0.
Section 5: Secure internal Flash memory (SIFM) (former Secure memory management section)
Removed Section Flash protections.
Updated Section 5.3.1: Associated features and Section 5.3.2: Boot state machine.
Added and added Note 2. below Figure 15: Flash memory areas and services in Standard and Secure access modes.
Updated Figure 16: Bootloader state machine in Secure access mode.
Updated Section 5.3.3: Secure access mode configuration.
Restructured Section 5.4: Root secure services (RSS):
Added Section 5.4.1: Secure area setting service and Section 5.4.2: Secure area exiting service
Renamed RSS services (removed RSS_ prefix).
Removed RSS_resetAndDestroyPCROPArea
Updated Section 5.5.1: Access rules and Section 5.5.2: Setting secure user memory areas. Remove sections Removing secure memory areas and Selecting secure user software.
Updated Figure 17: Core access to Flash memory areas

Section 6: Power control (PWR)
Added case of device startup with VCORE supplied in Bypass mode in Section 6.4.1: System supply startup.
Added VOS0 in Section 6.4.2: Core domain, Section 6.4.3: PWR external supply and Section 6.6.2: Voltage scaling. Added Section : VOS0 activation/deactivation sequence.
Updated Section 6.5.5: Battery voltage thresholds.
Updated Section 6.5.6: Temperature thresholds to indicate that the thresholds are available only when the backup regulator is enabled.
Added note related to VOS0i activation in Section : Entering Stop mode and Section : Entering Standby mode.
Added Section 6.7.11: Monitoring low-power modes.
Added note related to VBAT and temperature monitoring availability for MONEN bit of Section 6.8.3: PWR control register 2 (PWR_CR2).
SCUEN bit is no more read-only in Section 6.8.4: PWR control register 3 (PWR_CR3) register description.

Section 8: Reset and Clock Control (RCC)
Changed adc_ker_ck to adc_ker_ck_input in the whole section.
Updated Section : HSE oscillator, Section : LSE oscillator and Figure 46: HSE/LSE clock source.
Changed maximum frequency to 480 MHz in Figure 49: Core and bus clock generation.
Updated Table 58: Kernel clock distribution overview.
Specified that RCC Internal Clock Source Calibration Register (RCC_ICSCR) is available only on revision Y and added RCC HSI configuration register (RCC_HSICFGR).
Specified that RCC Clock Recovery RC Register (RCC_CRRRCR) is available only on revision Y and added RCC CSI configuration register (RCC_CSICFGR).
Updated DIVP1[6:0] in RCC PLL1 Dividers Configuration Register (RCC_PLL1DIVR).
Renamed BKPSRAMAMEN into BKPRAMAMEN in RCC D3 Autonomous mode Register (RCC_D3AMR).
Added USB2OTGHSULPIEN in RCC AHB1 Clock Register (RCC_AHB1ENR), and USB2OTGHSULPILPEN in RCC AHB1 Sleep Clock Register (RCC_AHB1LPENR).
Renamed HDMICECRST into CECRST in RCC APB1 Peripheral Reset Register (RCC_APB1LRSTR), and HDMICECEN to CECEN in RCC APB1 Clock Register (RCC_APB1LENR).
Changed CPURST bit to in RCC AHB3 Sleep Clock Register (RCC_AHB3LPENR).

Section 11: General-purpose I/Os (GPIO)
Updated Figure 76: Analog inputs connected to ADC inputs to specify that the analog switch status depends on PxySO reset value in SYSCFG_PMCR.
MODER reset state changed to analog mode in Section 11.4.1: GPIO port mode register (GPIOx_MODER) (x =A to K).

Section 12: System configuration controller (SYSCFG)
Added BOOSTVDDSEL bit in SYSCFG peripheral mode configuration register (SYSCFG_PMCR).
Added note related to CSI clock required for setting READY bit in SYSCFG configuration register (SYSCFG_CFGR). Added SYSCFG power control register (SYSCFG_PWRRCR).

Section 16: Basic direct memory access controller (BDMA)
Updated Section : Channel state and disabling a channel.

Section 17: DMA request multiplexer (DMAMUX)
Removed references to security and privileged/unprivileged access control in Section 17.6.4: DMAMUX2 request line multiplexer interrupt channel status register (DMAMUX2_CSR), Section 17.6.6: DMAMUX2 request line multiplexer interrupt clear flag register (DMAMUX2_CFR) and Section 17.6.8: DMAMUX2 request generator channel x configuration register (DMAMUX2_RGxCR).

Section 18: Chrom-Art Accelerator™ controller (DMA2D)
Replaced DMA2D_FGPFCCR by DMA2D_FGPFCCR in Section : Memory-to-memory with PFC, blending and fixed color FG. Replaced DMA2D_BGPFCCR by DMA2D_BGPFCCR in Section : Memory-to-memory with PFC, blending and fixed color BG.
Updated Section 18.6.9: DMA2D foreground color register (DMA2D_FGCOLR).
Added Section 18.6.21: DMA2D foreground CLUT (DMA2D_FGCLUT[y]) and Section 18.6.22: DMA2D background CLUT (DMA2D_BGCLUT[y]).
Table 141: DMA2D register map and reset values: changed APLHA[7:0] to reserved for DMA2D_FGCOLR and APLHA[7:0] to reserved for DMA2D_BGCOLR.

Section 22: Flexible memory controller (FMC)
Replaced BCH8 by Hamming in Section 22.8.6: Computation of the error correction code (ECC) in NAND Flash memory.
Updated Figure 109: Mode D write access waveforms.

Section 24: Delay block (DLYB)
Updated Section 24.1: Introduction to specify that the DLYB output clock can be used to clock the data received by Quad-SPI interface.

Section 25: Analog-to-digital converters (ADC)
Renamed adc_ker_ck into adc_ker_ck_input in the hole section.
Renamed OVSR into OVR, OSR into OSVR[9:0] and AUTODLY into AUTDLY.
Added Section 25.3: ADC implementation.
For all ADC internal channels connected to VBAT, VSENSE, VREFINT, and DAC internal channels, changed ADC channel name from ADCx_INPy/INMy to ADCx_VINPy/VINMy.
Updated Figure 136: ADC clock scheme to distinguish between revision Y (without Fadc_ker_ck_input divider and revision V without Fadc_ker_ck_input divider.
Updated Table 209: Offset computation versus data resolution, Section : 16-bit and 8-bit signed format management: RSHIFTx,SSATE and Table 213: Analog watchdog 1,2,3 comparison.
Removed reference to ALIGN bit in the note related to data alignment in Section : Single ADC operating modes support when oversampling.
Updated Section 25.6.3: ADC control register (ADC_CR) to distinguish between revision Y with one BOOST bit an revision V with two BOOST bits.
Updated Section 25.6.4: ADC configuration register (ADC_CFGR) to change RES[2:0] value corresponding to 8-bit format.

Section 29: Operational amplifiers (OPAMP)
Removed references to OPAMODE in Section 29.6.1: OPAMP1 control/status register (OPAMP1_CSR). Changed OPAMODE bitfield to reserved in Section 29.6.1: OPAMP1 control/status register (OPAMP1_CSR).

Section 32: LCD-TFT display controller (LTDC)
Section 32.4.1: LTDC global configuration parameters / Synchronous timing updated.

Section 33: JPEG codec (JPEG)
Table 273: JPEG codec register map and reset values:
JPEG_CR: added HPDIE (bit 6)
Renamed JPEG_HWCFR1/2 into JPEG_HWCFGR1/2

Section 34: True random number generator (RNG)
Updated Section 34.2: RNG main features, Section 34.4: RNG interrupts, Section 34.6: RNG entropy source validation and Table 274: RNG internal input/output signals.

Section 35: Cryptographic processor (CRYP)
Section 35.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR): renamed CRYP_CSGCMCCMxR[31:0] bitfield into CSGCMCCMx[31:0] and updated bitfield description.
Section 35.6.22: CRYP context swap GCM registers (CRYP_CSGCMxR): renamed CRYP_CSGCMx[31:0] bitfield into CSGCMx[31:0] and updated bitfield description.
Table 291: CRYP register map and reset values:
Added bitfield ranges for CRYP_K0LR/RR to CRYP_K3LR/RR.
Updated CRYP_IV0LR/RR to CRYP_IV1LR/RR.
Renamed CRYP_KxLR bitfields into Kx.

Section 36: Hash processor (HASH)
Changed CSrn into CSn for all HASH_CRSx registers in Table 296: HASH1 register map and reset values.

Section 38: Advanced-control timers (TIM1/TIM8)
Replaced BKEx, BKPx by BKE, BK2E, BKP, BK2P.
Updated Figure 345: Advanced-control timer block diagram and Figure 388: Break and Break2 circuitry overview.
Updated Figure 375: Output stage of capture/compare channel (channel 1, idem ch. 2 and 3), Figure 376: Output stage of capture/compare channel (channel 4) and Figure 377: Output stage of capture/compare channel (channel 5, idem ch. 6).
Updated TIM1_CCMR1, TIM1_CCMR2, TIM1_CCMR3, TIM1_CCR2, TIM1_CCR4.
Added 00010 configuration for TS[4:0] in TIMx_SMCR register.
Table 330: TIM8 register map and reset values: extended DMAB bitfield to 32 bits for TIM8_DMAR.

Section 39: General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Updated Figure 405: General-purpose timer block diagram.
Updated Section 39.3.3: Clock selection.
Removed all information related to BDTR register and MOE and OSSSI bits.

Section 40: General-purpose timers (TIM12/TIM13/TIM14)
Updated Figure 454: General-purpose timer block diagram (TIM12).

Section 41: General-purpose timers (TIM15/TIM16/TIM17)
Updated Figure 480: TIM15 block diagram.
Updated Figure 495: Capture/compare channel 1 main circuit? Figure 496: Output stage of capture/compare channel (channel 1) and Figure 497: Output stage of capture/compare channel (channel 2 for TIM15).
Updated Section 41.4.13: Using the break function.
Removed bit COMDE for TIM16/17.
Table 344: TIM16/TIM17 register map and reset values: changed TISEL[3:0] into TI1SEL[3:0] for TIM16_TISEL and TIM17_TISEL registers.

Section 43: Low-power timer (LPTIM)
Updated Section 43.4.9: Timeout function.
Updated WAVE bit description in Section 43.7.4: LPTIM configuration register (LPTIM_CFGR).

Section 47: Inter-integrated circuit (I2C) interface
Updated Section 47.3: I2C implementation.
Updated Section 47.7.2: I2C control register 2 (I2C_CR2), Section 47.7.3: I2C own address 1 register (I2C_OAR1), and Section 47.7.8: I2C interrupt clear register (I2C_ICR).

Section 48: Universal synchronous/asynchronous receiver transmitter (USART/UART)
Replaced DSI_NSS by DIS_NSS in USART_CR1.
Changed USART_TDR into USART_RDR in Figure 590: Reception using DMA.
Updated Section 48.5.4: USART FIFOs and thresholds.
Updated RTO bitfield description in Section 48.7.7: USART receiver timeout register (USART_RTOR).
Section 48.7.9: USART interrupt and status register [alternate] (USART_ISR):
Updated ABRF, IDLE bit descriptions
For FIFO disabled only: updated RXNE and ORE bit descriptions
Changed NFCF to NECF in Section 48.7.11: USART interrupt flag clear register (USART_ICR).
Table 399: USART register map and reset values:
USART_CR1: bit 12 changed to M0, bit 7 changed to TXEIE/TXFNIE, bit 5 changed to RXNEIE/RXFNEIE.
USART_ISR: changed TXE bit to TXE/TXNFN and RXNE into RXNE/RXFNE
Corrected USART_ISR/TCGBT reset value for FIFO disabled.

Section 49: Low-power universal asynchronous receiver transmitter (LPUART)
Changed LPUART_TDR into LPUART_RDR in Figure 604: Reception using DMA.
Updated Section 48.5.4: USART FIFOs and thresholds.
Updated Section 49.5.1: LPUART control register 1 [alternate] (LPUART_CR1).
Corrected WUS bitfield length and changed RXFTCFG to TXFTCFG (bit 31 to 29) in Section 49.5.4: LPUART control register 3 (LPUART_CR3).
Section 49.5.8: LPUART interrupt and status register [alternate] (LPUART_ISR):
Updated IDLE bit descriptions
FIFO enabled only: updated reset value
Changed NFCF to NECF in Section 49.5.9: LPUART interrupt flag clear register (LPUART_ICR).
Table 405: LPUART register map and reset values
LPUART_CR1: bit 12 changed to M0, bit 5 changed to RXNEIE/RXFNEIE.
LPUART_ISR: changed TXE bit to TXE/TXNFN
Corrected LPUART_ISR reset value and bits 7 and 5 names.

Section 50: Serial peripheral interface (SPI)
Table 413: SPI register map and reset values:
SPI2S_SR: Changed bit 7 to CRCE.
SPI2S_I2SCFGR: added DATFMT (bit 14)

Section 54: Management data input/output (MDIOS)
In Table 441: MDIOS register map and reset values, for MDIOS_CR register, changed bit 3 to EIE and added DPC (bit 7).

Section 55: Secure digital input/output MultiMediaCard interface (SDMMC)
Replaced HOLD by DHOLD in the whole document.
Updated Figure 702: SDMMC block diagram and Table 446: SDMMC pins.
Updated Figure 711: CLKMUX unit.
Updated Wait_S in Section : Data path and Table 456: Data path status flags and clear bits.
Updated Section 55.5.3: General description.
Updated Section : Stream operation and CMD12.
Added Section 55.8: SDMMC interrupts.
Updated Section 55.9.10: SDMMC data counter register (SDMMC_DCNTR), Section 55.9.11: SDMMC status register (SDMMC_STAR) and Section 55.9.15: SDMMC data FIFO registers x (SDMMC_FIFORx).
Updated Table 468: SDMMC register map.

Section 56: Controller area network with flexible data rate (FDCAN)
Updated Section 56.4.7: FDCAN nominal bit timing and prescaler register (FDCAN_NBTP), Section 56.4.12: FDCAN error counter register (FDCAN_ECR), Section 56.4.15: FDCAN interrupt register (FDCAN_IR), Section 56.4.37: FDCAN Tx buffer request pending register (FDCAN_TXBRP) and Section 56.4.64: FDCAN TT trigger select register (FDCAN_TTTS).
Updated Table 495: FDCAN register map and reset values.
Updated Table 495: FDCAN register map and reset values.

Section 58: Ethernet (ETH): media access control (MAC) with DMA controller
Added Figure 789: Supported PHY interfaces.
Removed reference to AV standard in Section 58.1: Ethernet introduction.

Section 60: Debug infrastructure
Changed ETF RAM size to 4 Kbytes in Section 60.5.5: Embedded trace FIFO (ETF) and Section : ETF RAM size register (ETF_RSZ).
Added revision V and updated reset value in Section : DBGMCU identity code register (DBGMCU_IDC).
Renamed WDGLSD1 into DBG_IWDG1 in Section : DBGMCU APB4 peripheral freeze register (DBGMCU_APB4FZ1).
Prefixed all bits names in Section : DBGMCU APB1L peripheral freeze register (DBGMCU_APB1LFZ1), Section : DBGMCU APB2 peripheral freeze register (DBGMCU_APB2FZ1) and Section : DBGMCU APB4 peripheral freeze register (DBGMCU_APB4FZ1) by 'DBG_'.

Added RAMECC1/2/3 boundary addresses in Section Table 12.: Register boundary addresses STM32H7-Shark . Updated Section : Error code correction (ECC) and Section : Embedded bootloader .
Added Section 3: RAM ECC monitoring (RAMECC)

Section 4: Embedded flash memory (FLASH)
Restricted Table 26 to STM32H745xl/747xl/755xl/757xl and added Table 28: Flash memory organization on STM32H745xG/STM32H747xG devices .
Added VOS0 range to Table 34: FLASH recommended number of wait states and programming delay .
Added VOS0 range to Table 34: FLASH recommended number of wait states and programming delay .
Added CRCRDERRIE1/2 in FLASH_CR1/2 registers, together with Section 4.7.10: CRC read error (CRCRDERR) .

Section 5: Secure memory management (SMM) (former Secure internal Flash memory)
Updated exitSecureArea in Section 5.4.2: Secure area exiting service .

Section 27: Power control (PWR)
Moved LSI from backup to VDD domain in Figure 169: Power supply overview .
Added Figure 181: Switching VCORE from VOS1 to VOS0 in Section : VOS0 activation/deactivation sequence .
Updated list of GPIOs which use is restricted in Section 15.4.4: Backup domain .
Updated ACTVOSRDY bit definition in Section 27.8.2: PWR control status register 1 (PWR_CSR1) . Updated VOSRDY bit definition in Section 27.8.6: PWR D3 domain control register (PWR_D3CR) .

Section 7: Low-power SRD domain application example
Replaced LINUART1 by LPUART1.
Updated Figure 41: Timing diagram of SRD SRAM-to-LPUART1 transfer with BDMA2 and SRD domain in Autonomous mode .
Updated section Section : EXTI programming .
Updated DMAMUX2_C0CR value for DMAMUX2_SYNC0 in Table 48: BDMA2 and DMAMUX2 initialization sequence (DMAMUX2_INIT) . Renamed Table 50 into “LPUART1 start programming.”

Section 49: Reset and Clock Control (RCC)
Renamed adc_ker_ck into adc_ker_ck_inputs.
Added note on RTC/AWU and updated USB1ULPI and ADC1/2/3 maximum allowed frequencies for VOS0/1/2/3 in Table 345: Kernel clock distribution overview .

Section 12: Clock recovery system (CRS)
Added Section 12.3: CRS implementation . Updated Section 12.7.1: CRS control register (CRS_CR) . Updated Table 125: CRS register map and reset values .

Section 8: General-purpose I/Os (GPIO)
In Section 8: General-purpose I/Os (GPIO) changed to analog the mode in which most of the I/O ports are configured during and just after reset.

Section 16: Direct memory access controller (DMA)
Change Bit 20 to TRBUFF instead of reserved in Section 16.5.5: DMA stream x configuration register (DMA_SxCR) .

Section 23: Flexible memory controller (FMC)
Updated Section : General transaction rules to clarify the behavior of the FMC when AXI transaction data size is different from the device data width and add the case of unaligned addresses.
Replaced FMC_CLK by fmc_ker_ck in the formulas of Section : WAIT management in asynchronous accesses .

Section 23: Quad-SPI interface (QUADSPI)
Updated Section 23.4.4: QUADSPI signal interface protocol modes .
Updated Section 23.4.11: QUADSPI configuration and Section 23.6.1: QUADSPI control register (QUADSPI_CR) adding 'when setting QUADSPI interface in DDR mode, the prescaler must be set with a division ratio of 2 or more' paragraph.
Updated FTHRES[4:0] bits description of Section 23.6.1: QUADSPI control register (QUADSPI_CR) for IP_XACT compliance.
Added note in Section 23.6.6: QUADSPI communication configuration register (QUADSPI_CCR) .
Updated Section 23.6.7: QUADSPI address register (QUADSPI_AR) .
Changed FLEVEL[6:0] by FLEVEL[5:0] in Section 23.6.18: QUADSPI register map .

Section 27: Analog-to-digital converters (ADC)
Removed note related to connection to DFSDM limited to ADC1 and ADC2, and added adc_sclk in Figure 155: ADC block diagram . Removed VREF+ and VREF- ranges, and added adc_sclk in Table 201: ADC input/output pins .
Updated Section 27.4.3: ADC clocks to distinguish between revision Y and V, and renamed adc_ker_ck into adc_ker_ck_inputs.
Updated Section 27.3: ADC implementation .
Updated Section : BOOST control .
Updated Section 27.4.3: ADC clocks to distinguish between revision Y and V.
Updated Section 27.4.12: Channel selection (SQRx, JSQRx) .
Updated Section : ADC overrun (OVR, OVRMOD) . Added case of FIFO overflow in Section : Managing a sequence of conversion without using the DMA .
Updated Section : Single ADC operating modes support when oversampling to remove the mention that the offset correction is not supported in oversampling mode.
Section 27.7.2: ADC x common control register (ADC_CCR)(ADCx_CCR) (x=1/2) (x=1/2 or 3):
– Reworded DUAL[4:0] to remove duplicate configurations
– Renamed VSENSEEN into TSEN
– Updated CKMODE[1:0] bitfield definition to distinguish between revision Y and V.
Updated Section 27.6.3: ADC control register (ADC_CR) to distinguish between revision Y and V (one or two BOOST bit(s,) respectively).

Section 27: Analog-to-digital converters (ADC) (continued)

Updated RES[2:0] bitfield definition in Section 27.6.4: ADC configuration register (ADC_CFGR).

Updated LSHIFT[3:0] corresponding to the “Shift left 14-bits” configuration in Section 27.6.5: ADC configuration register 2 (ADC_CFGR2).

Reworded JEXTEN[1:0] to remove duplicate 00 configuration for JEXTEN[1:0] in Section 27.6.16: ADC injected sequence register (ADC_JSQR).

Updated Section 27.6.26: ADC calibration factors register (ADC_CALFACT).

Removed ADC_CALCLKR register.

Section 35: Digital-to-analog converter (DAC)

Replaced sample and hold clock (lsi_ck and lse_ck when available) by dac_hold_ck.

Updated Section 35.3: DAC implementation.

Updated Figure 284: Dual-channel DAC block diagram.

Section 35.4.2: DAC pins and internal signals: added DAC interconnection table, changed dac_chx_trg[0:15] into dac_chx_trg[1:15] (trigger 0 corresponds to the SW trigger) in block diagram and Table 128: DAC internal input/output signals.

Updated Figure 287: Timing diagram for conversion with trigger disabled TEN = 0 to make it independent from the bus (AHB or APB).

Removed Tables Trigger selection from Section 35.4.8: DAC trigger selection

Updated Section : Sample and hold mode to indicate that the lsi_ck/lse_ck (when available) must not be stopped when Sample and hold mode enabled.

Updated supply voltages in Section 35.4.13: DAC channel buffer calibration.

Updated TSELx bitfield description in Section 35.7.1: DAC control register (DAC_CR) register to add the correspondence between TSELx configurations and dac_chx_trgy.

Updated CStop mode description for DAC1 in Section 35.5: DAC in low-power modes.

Updated Section 35.6: DAC interrupts.

Section 33: Comparator (COMP)

Removed condition on OR_CFG and changed OR bits to reserved in Section 33.7.3: Comparator option register (COMP_OR).

Section 28: Digital filter for sigma delta modulators (DFSDM)

Updated Table 206: DFSDM break connection.

Removed all “ADC1 and ADC2 only” notes and footnotes.

Updated Section 28.7: DFSDM channel y registers (y=0..3), Section 28.7.5: DFSDM channel y data input register (DFSDM_CHyDATINR) and Section 28.8: DFSDM filter x module registers (x=0..1).

Section 46: JPEG codec (JPEG)
Updated Section 46.5.5: JPEG codec configuration register x (JPEG_CONF Rx). bit 1 and bit 0 description.

Section 48: True random number generator (RNG)
Updated Section 48.1: Introduction and Section 48.2: RNG main features.
Updated Section 48.3.3: Random number generation and note in Section 48.3.5: RNG operation. Updated Section 48.5: RNG processing time and Section 48.6: RNG entropy source validation.
Updated Section 48.7.3: RNG data register (RNG_DR).

Section 33: Cryptographic processor (CRYP)
Updated number of clock cycles for TDES in Section 33.2: CRYP main features.n
Removed flowcharts (Nonuser) in Section 33.4.5: CRYP procedure to perform a cipher operation.
Updated Section 33.4.18: CRYP key registers.
Section 33.5: CRYP interrupts: removed Figure CRYP interrupt mapping diagram and updated Table 268: CRYP interrupt requests.
Section 33.6: CRYP processing time: updated Table 269: Processing latency for ECB, CBC and CTR and Table 270: Processing time (in clock cycle) for GCM and CCM per 128-bit block.

Section 51: Hash processor (HASH)
Message size changed to \( 2^{64}-1 \) in Section 51.1: Introduction and Section 51.4.3: About secure hash algorithms. Added Section 51.3: HASH implementation. Updated Figure 477: HASH block diagram.
Updated Figure 478: Message data swapping feature.
Updated Section 51.4.8: HASH suspend/resume operations.
Renamed HASH_HRx registers located at address offset 0x0C into Section : HASH aliased digest register x (HASH_HRAx). Updated ALGO description in Section 51.7.1: HASH control register (HASH_CR). Specified value returned by reading Section 51.7.2: HASH data input register (HASH_DIN).

Section 23: Advanced-control timers (TIM1)
Updated Figure 114: Advanced-control timer block diagram.
Updated Section 23.3.3: Repetition counter.
Updated Section 23.3.16: Using the break function.
Updated Section 23.4.2: TIM1 control register 2 (TIM1_CR2TIMx_CR2)N/A. Aligned TS[2:0] field in Section 23.4.3: TIM1 slave mode control register (TIM1_SM CRTIMx_SMCR)N/A. Updated Section 23.4.5: TIM1 status register (TIM1_SRTIMx_SR)N/A. Updated Section 23.4.6: TIM1 event generation register (TIM1_EGRTIMx_EGR)N/A. Updated Table 176: TIM1 register map and reset values and Table 177: TIM8 register map and reset values. Updated Section 23.3.29: Debug mode.

Section 24: General-purpose timer (TIM2)
Updated Section 24.4.12: TIM2 counter (TIM2_CNT). Updated Table 173: TIM2 register map and reset values.

Section 39: General-purpose timers (TIM12/TIM13/TIM14)
Updated Figure 412: General-purpose timer block diagram (TIM12) and Figure 426: Capture/compare channel 1 main circuit.
Updated Figure 427: Output stage of capture/compare channel (channel 1).
Updated Section 39.4.1: TIM12 control register 1 (TIM12_CR1), Section 39.4.5: TIM12 status register (TIM12_SR) and Section 39.5.5: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 13 to 14).

Section 25: General-purpose timers (TIM16/TIM17)
Updated Figure 223: TIM15 block diagram.
Updated Figure 237: Capture/compare channel 1 main circuit.
Updated: Section 25.5.2: TIM15 control register 2 (TIM15_CR2), Section 25.5.5: TIM15 status register (TIM15_SR), Section 25.5.9: TIM15 capture/compare enable register (TIM15_CCER), Section 25.4.2: TIMx control register 2 (TIMx_CR2)(x = 16 to 17), Section 25.4.4: TIMx status register (TIMx_SR)(x = 16 to 17), Section 25.4.6: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 16 to 17) and Section 25.4.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17). Replaced DT[7:0] by DTG[7:0] in Table 184: TIM15 register map and reset values and Table 183: TIM16/TIM17 register map and reset values.

Section 42: Low-power timer (LPTIM)
Updated Section 42.4.5: Glitch filter.

Section 62: System window watchdog (WWDG)
Updated Section 62.6.1: WWDG control register (WWDG_CR).

Section 29: Real-time clock (RTC)
Updated Figure 286: RTC block diagram and Figure 1327: Tamper detection,
Updated Section 29.5: RTC low-power modes.
Updated Section 29.6: RTC interrupts.

Section 33: Universal synchronous/asynchronous receiver transmitter (USART/UART)
Section 33.8.9: USART interrupt and status register (USART_ISR):
– FIFO enabled: changed reset value to 0x0X80 00C0 in and Table 235: USART register map and reset values.
– FIFO disabled: changed reset value to 0x0000 00C0 in Table 235: USART register map and reset values
Section 33.8.12: USART receive data register (USART_RDR): changed reset value to 0x0000 0000. Section 33.8.13: USART transmit data register (USART_TDR): changed reset value to 0x0000 0000. Updated Section 33.8: USART registers to indicate that USART and LPUART registers are accessed by words.

Section 34: Low-power universal asynchronous receiver transmitter (LPUART)
Added Section 34.3: LPUART implementation .
Section 34.7.8: LPUART interrupt and status register [alternate] (LPUART_ISR) :
– FIFO enabled: changed reset value to 0x0080 00C0 in Table 242: LPUART register map and reset values .
– FIFO disabled: changed reset value to 0x0000 00C0 in Table 242: LPUART register map and reset values .
Updated Section 34.7: LPUART registers to indicate that USART and LPUART registers are accessed by words.

Section 69: Serial audio interface (SAI)
Figure 833: SAI functional block diagram : number of Dn and CKn lines made generic, added note to indicate that all Dn and CKn might not be available on all SAI instances.
Added Section 69.3: SAI implementation .
Updated Figure 697: SAI input/output pins to indicate the number of Dn/CKn available on each SAI instance.
Updated Section 69.6: SAI registers to indicate that SAI registers are accessed by words.
Updated Figure 842: Start-up sequence .

Section 58: Single wire protocol master interface (SWPMI)
Updated Table 431: SWPMI input/output signals connected to package pins or balls .

Section 71: Controller area network with flexible data rate (FDCAN)
Updated Section 71.1: Introduction, Software initialization, CAN FD operation, Transceiver delay compensation, Acceptance filter, Section 71.4.4: Bit timing, Section 71.4.6: Application, Clock calibration active and Timing of interface signals .
Updated Table 701: Standard message ID filter element, Table 703: Extended message ID filter element, Table 706: Trigger memory element description .
Updated Table 936: Standard message ID filter path and Table 937: Extended message ID filter path .
Updated Section 71.5.6: FDCAN CC control register (FDCAN_CCCR), Section 71.5.15: FDCAN interrupt register (FDCAN_IR), Section 71.5.18: FDCAN interrupt line enable register (FDCAN_ILE), Section 71.5.21: FDCAN extended ID filter configuration register (FDCAN_XIDFC) and Section 71.6.6: FDCAN TT operation control register (FDCAN_TTOCN) .
Updated Table 709: CCU register map and reset values .

Section 72: USB on-the-go full-speed (OTG_FS)

Updated Section 72.2: OTG_FS main features, Section 72.15.2: OTG interrupt register (OTG_GOTGINT), Section 72.15.5: OTG reset register (OTG_GRSTCTL), Section 72.15.6: OTG core interrupt register (OTG_GINTSTS), , Section 72.15.18: OTG host periodic transmit FIFO size register (OTG_HPTXFSIZ), Section 72.15.22: OTG host frame interval register (OTG_HFIR), Section 72.15.31: OTG host channel x transfer size register (OTG_HCTSIZx), Section 72.15.33: OTG device configuration register (OTG_DCFG), Section 72.15.34: OTG device control register (OTG_DCTL), Section 72.15.35: OTG device status register (OTG_DSTS), Section 72.15.36: OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK), Section 72.15.37: OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK), Section 72.15.44: OTG device IN endpoint x control register (OTG_DIEPCTLx) and Section 72.15.50: OTG device OUT endpoint x interrupt register (OTG_DOEPINTx).

Updated Section 72.10: OTG_FS Dynamic update of the OTG_HFIR register.

Updated Section 72.16.3: Device initialization.

Section 75: Ethernet (ETH): gigabit media access control (GMAC) with DMA controller

Replaced ptp_pps_o internal signal by eth_ptp_pps_out, and ptp_aux_ts_trig_i by eth_ptp_trgx (where x = 0 to 3) and ptp_aux_trig_i[x] by eth_ptp_trgx.

Update ARPEN bit description in Section : Operating mode configuration register (ETH_MACCR).

Reintroduced EIPG enumerated values in Section : Extended operating mode configuration register (ETH_MACECR).

Removed sentence “This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input” from Section : System time nanoseconds register (ETH_MACSTNR), Section : System time seconds update register (ETH_MACSTSUR) and Section : System time nanoseconds update register (ETH_MACSTNUR) register description.

Section 60: Debug infrastructure

Updated Figure 859: Block diagram of debug infrastructure , Figure 860: Power domains of debug infrastructure and Figure 861: Clock domains of debug infrastructure .

Updated Clock domains .

Changed ID code for Instruction register = 1110 in Table 585: JTAG-DP data registers .

Updated notes in Table 586: Debug port registers .

Modified Debug port target identification register (DP_TARGETID) reset value as well as bit descriptions.

Modified Access port identification register (AP_IDR) reset value as well as description of REVISION bitfield.

Updated Table 588: System ROM table 1 .

Modified SYSROM CoreSight peripheral identity register 0 (SYSROM_PIDR0) , SYSROM CoreSight peripheral identity register 1 (SYSROM_PIDR1) and SYSROM CoreSight peripheral identity register 2 (SYSROM_PIDR2) .

Added Table 589: System ROM table 2 .

Modified CTI CoreSight peripheral identity register 0 (CTI_PIDR0) and CTI CoreSight peripheral identity register 2 (CTI_PIDR2) .

Updated bitfield description for CTI application trigger set register (CTI_APPSET) , CTI application trigger clear register (CTI_APPCLEAR) , CTI application pulse register (CTI_APPPULSE) , CTI trigger IN x enable register (CTI_INENx) , CTI trigger OUT x enable register (CTI_OUTENx) and CTI channel gate register (CTI_GATE) .

Updated ETF CoreSight peripheral identity register 2 (ETF_PIDR2) reset value.

Modified TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) , TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) and SWTF CoreSight peripheral identity register 2 (SWTF_PIDR2) .

Changed DBGSTBY_D3 and DBGSTOP_D3 to reserved in DBGMCU configuration register (DBGMCU_CR) .

Updated Table 606: Cortex-M7 processor ROM table .

Updated Processor ROM CoreSight peripheral identity register 0 (M7_CPUROM_PIDR0) , Processor ROM CoreSight peripheral identity register 1 (M7_CPUROM_PIDR1) and Processor ROM CoreSight peripheral identity register 2 (M7_CPUROM_PIDR2) .

Updated DWT CoreSight peripheral identity register 0 (M7_DWT_PIDR0) , DWT CoreSight peripheral identity register 1 (M7_DWT_PIDR1) , DWT CoreSight peripheral identity register 2 (M7_DWT_PIDR2) reset value.

Updated ITM CoreSight peripheral identity register 0 (M7_ITM_PIDR0) , ITM CoreSight peripheral identity register 1 (M7_ITM_PIDR1) , ITM CoreSight peripheral identity register 2 (M7_ITM_PIDR2) .

Updated Table 613: Cortex-M7 ETM register map and reset values .

Updated Introduction

Added errata sheet in the list of reference documents in Section : Related documents

Section 2: Memory and bus architecture

Updated Figure 1: System architecture for STM32H742xx, STM32H743/53xx and STM32H750xB devices .

Updated system memory address range in Table 7: Memory map and default device memory area attributes and Table 9: Boot modes of Section 2.6: Boot configuration .

Updated D2 domain information in Section 2.4: Embedded SRAM

Section 3: RAM ECC monitoring (RAMECC)

Added note to Section 3.1: Introduction

Section 4: Embedded flash memory (FLASH)

Section : Erase operation overview : added note related to the case where data cache is enabled after erase operations. removed the mention that Bank 2 can be erased with ST secure firmware.

Removed bootloader extension from Figure 8: Embedded flash memory usage .

Replaced 02 and 03 respectively with 10 and 11 in the description of BOR_LEV bits in Section 4.9.8: FLASH option status register (FLASH_OPTSR_CUR)

Added note providing non-secure Flash area start address in SEC_AREA_END1 of Section 4.9.13: FLASH secure address for bank 1 (FLASH_SCAR_CUR1) .

Added formula to deduce bank 1/2 fail address from FAIL_ECC_ADDR1/2 in Section 4.9.23: FLASH ECC fail address for bank 1 (FLASH_ECC_FA1R) and Section 4.9.37: FLASH ECC fail address for bank 2 (FLASH_ECC_FA2R) , respectively.

Replaced ST_RAM_SIZE=00 with ST_RAM_SIZE in Section 4.4.6: Description of data protection option bytes .

Updated Table 21: Option byte organization :

• – Modified ST_RAM_SIZE default factory
• – Modified FLASH_OPTSR[28:27] default factory values

Added area of option bytes (bank 1) in Table 15: Flash memory organization on STM32H742xl/743xl/753xl devices , Table 15: Flash memory organization on STM32H742xl/743xl/753xl devices and Table 16: Flash memory organization on STM32H742xG/743xG devices

Modified number of wait states in description of LATENCY bits in Section 4.9.1: FLASH access control register (FLASH_ACR)

Replaced 2.5V with 2.7V in bit 29 description in Section 4.9.8: FLASH option status register (FLASH_OPTSR_CUR) and Section 4.9.9: FLASH option status register (FLASH_OPTSR_PRG)

Section 5: Secure memory management (SMM)

Updated Section 5.4.2: Secure area exiting service (modified information on Prototype and Arguments for exitSecureArea section)

Section 6: Power control (PWR)

Updated case of VDD supplied in Bypass mode in Section 6.4.1: System supply startup .

Added note below Figure 22: Device startup with VCORE supplied in Bypass mode from external regulator

Distinguished reset values for device revision Y and V in PWR control register 3 (PWR_CR3) .

Updated Figure 22: Device startup with VCORE supplied in Bypass mode from external regulator

Replaced WKUPn+1 with WKUPn, WKUPCn+1 with WKUPCn and WKUPFn+1 with WKUPFn in Section 6.8.7: PWR wakeup clear register (PWR_WKUPCR) , Section 6.8.8: PWR wakeup flag register (PWR_WKUPFR) and Section 6.8.9: PWR wakeup enable and polarity register (PWR_WKUPEPR)

Section 8: Reset and Clock Control (RCC)

Updated ADC1,2, 3 maximum allowed frequency and TIM[8:1][17:12] (VOSO) in Table 60: Kernel clock distribution overview .

Modified Section : PLL initialization phase description and description of FRACN3[12:0] bits in Section 8.5.5: PLL description

Updated FRACN1[12:0] bits in Section 8.7.14: RCC PLL1 fractional divider register (RCC_PLL1FRACR)

Section 8.7.36: RCC APB4 peripheral reset register (RCC_APB4RSTR) and Section 8.7.48: RCC APB4 clock register (RCC_APB4ENR) : replaced VREF with VREFBUF

Replaced VOS2 with VOS3 in Table 60: Kernel clock distribution overview

Updated maximum VCO frequency in PLLxVCOSEL of RCC PLL configuration register (RCC_PLLCFGR) and Figure 47: PLL block diagram .

Modified Section 8.7.41: RCC AHB1 clock register (RCC_AHB1ENR) : modified position of USB2OTGHSULPIEN bit (bit 28 instead of bit 18)

Added note to USB2OTGHSULPILPEN in RCC AHB1 Sleep clock register (RCC_AHB1LPENR) .

Added Clock switching state after system reset in Section 8.5.10: Peripheral allocation

Modified maximum allowed frequency for ADC1, 2, 3 in Table 60: Kernel clock distribution overview

Updated Figure 58 (added information for rev V devices)

Section 9: Clock recovery system (CRS)
Updated Section 9.8.1: CRS control register (CRS_CR) .
Updated Section Figure 65.: CRS block diagram .

Section 10: Hardware semaphore (HSEM)
Updated Section 10.1: Introduction
Updated sections 10.3.3 HSEM lock procedures to 10.3.8 and sections 10.4.1 to 10.4.6 .
Updated Table 90: HSEM internal input/output signals and Table 92: HSEM register map and reset values .
Updated Figure 68: Procedure state diagram

Section 12: System configuration controller (SYSCFG)
In Section 12.3.1: SYSCFG peripheral mode configuration register (SYSCFG_PMCR) :
– Added note indicating that SYSCFG peripheral mode configuration register (SYSCFG_PMCR) depends on the package,
– Modified BOOSTVDDSEL bit description in ( \( V_{DDA} \) instead of \( V_{DD} \) ).
– Updated SYSCFG_PMCR, PA0SO and PA1SO reset value in Table 95: SYSCFG register map and reset values .
Added PI[x] pin in Section 12.3.5: SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)

Section 15: Direct memory access controller (DMA)
Slight update in the introduction
Formatting adjusted in Table 110: Packing/unpacking and endian behavior (bit PINC = MINC = 1)

Section 17: DMA request multiplexer (DMAMUX)
Restored CSOF3 to 6 in Section 17.6.5: DMAMUX1 request line multiplexer interrupt clear flag register (DMAMUX1_CFR)
Updated Section 17.4.4: DMAMUX request line multiplexer .

Section 18: Chrom-ART Accelerator controller (DMA2D)
Updated Section 18.3.2: DMA2D internal signals

Section 21: Cyclic redundancy check calculation unit (CRC)
Added note in Section : Polynomial programmability to clarify what are even and odd polynomials.
Restored REV_OUT and REV_IN[1:0] in CRC_CR register map table.
Added CRC register access granularity in Section 21.2: CRC main features and Section 21.4: CRC registers .
Updated Figure 96: CRC calculation unit block diagram .

Section 22: Flexible memory controller (FMC)
Corrected formula in TWR[3:0] bitfield of SDRAM Timing registers for SDRAM memory bank x (FMC_SDTRx)

Section 24: Delay block (DLYB)
Updated Section 24.3.4: Delay line length configuration procedure .
Updated Section 24.3.5: Output clock phase configuration procedure .

Section 23: Quad-SPI interface (QUADSPI)
Updated Section : Triggering the start of a command

Section 25: Analog-to-digital converters (ADC)
Updated Section : I/O analog switch voltage booster .
Updated note related to adc_sclk in Section 25.4.3: ADC clocks .
Updated formula to calculate the temperature in Section : Reading the temperature (Section 25.4.33: Temperature sensor)
Updated Section DMA one shot mode to remove the cross-reference to DMA sections and change the DMA interrupt name to transfer complete interrupt.
Updated Figure 202: DMA requests in regular simultaneous mode when DAMDF=0b10 .
Updated Figure 170: Example of overrun (OVRMOD = 0) (8-stage FIFO).
Added Section : Constraints between ADC clocks
Remove ADC supply requirements from Table 205: ADC input/output pins
Updated Figure 170: Example of overrun (OVRMOD = 0) , Figure 176: AUTLDLY=1 in auto-injected mode (JAUTO=1) , Figure 185: Regular and injected oversampling modes used simultaneously , and Figure 186: Triggered regular oversampling with injection .
Replaced ADCx_CCR with ADCx_CDR (typo, 2 occurrences) in Section : Regular simultaneous mode with independent injected

Section 26: Digital-to-analog converter (DAC)
In TSEL1/2 of DAC_CR register, changed internal trigger signal names from dac_ch1_trigx/dac_ch2_trigx to dac_ch1_trgx/dac_ch2_trgx.
Removed DAC acronym in Section 26.4.9: Noise generation and Section 26.4.10: Triangle-wave generation .
Updated the way to stop LSI clock in Section : Sample and hold mode .
In all block diagrams, added index 'x' for DAC output pin names. Replaced all occurrences of DAC_OUTx by DACx_OUTy. Replaced all occurrences of DAC_OUT1 by DACx_OUT1 when referring to the DAC output pin in a generic way
Changed IP base address to 0x0000 0000
Renamed Section 26.5 into DAC in low-power modes .
Updated Table 224: DAC features to indicate if VREF+ pin is available or not
Updated HFSEL bitfield description in DAC_MCR register.
Changed XXXb notation for binary values into 0bXXX
In Figure 207: Dual-channel DAC block diagram , change OTRIMx[5:0] into OTRIMx[4:0] (5 trimming bits only).

Section 27: Voltage reference buffer (VREFBUF)
Fixed VREFUBUF spelling issue in Section 27.2: VREFBUF functional description
Updated VRS in Section 27.3.1: VREFBUF control and status register (VREFBUF_CSR) .
Updated TRIM in Section 27.3.2: VREFBUF calibration control register (VREFBUF_CCR)
Reworded notes related to trimming performed by the user application in Section 27.3.2 .
Updated Hold mode in Section Table 233.: VREF buffer modes .

Section 28: Comparator (COMP)
Section 28.7.2: Comparator interrupt clear flag register (COMP_ICFR) : changed CC2IF/CC1IF access type to rc_w1 and updated address offset to 0x04.

Section 29: Operational amplifiers (OPAMP)
Updated Section 29.2: OPAMP main features

Section 30: Digital filter for sigma delta modulators (DFSDM)
Removed indication of ID registers support in Section 30.3: DFSDM implementation .

Section 32: LCD-TFT display controller (LTDC)
Updated Figure 245: LTDC block diagram , Section 32.3.2: LTDC pins and internal signals created and Figure 247: Layer window programmable parameters

Section 33: JPEG codec (JPEG)
Updated several registers, starting from Section 33.5.11: JPEG quantization memory x (JPEG_QMEMx_y)

Section 34: True random number generator (RNG)
Updated Section 34.3.7: Error management , Section 34.3.8: In this case application must clear the SEIS bit interrupt flag. RNG low-power use and Section 34.7.1: RNG control register (RNG_CR)

Section 35: Cryptographic processor (CRYP)
Removed reference to STM32 cryptographic library from Section 35.1: Introduction .
Support for single and burst transfers updated in Section 35.2: CRYP main features .
Added Section 35.3: CRYP implementation .
Extended cryp_out_dma, Section : DES/TDES keying and chaining modes and transfer size in Table 292: Cryptographic processor configuration for memory-to-peripheral DMA transfers and Table 293: Cryptographic processor configuration for peripheral-to-memory DMA transfers and CRYP_K0LR/K0RR, both to DES and TDES.
Updated Section 35.5: CRYP interrupts .
Changed DES to DES/TDES in CRYP_K1LR/K1RR, and DES to TDES in CRYP_K2LR/K2RR and CRYP_K3LR/K3RR

Section 38: Advanced-control timers (TIM1/TIM8)

Updated Figure 395: Retriggerable one pulse mode .

Updated OC1M[3:0] and OC1PE in Section 38.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 1, 8)

Updated Figure 367: Control circuit in normal mode, internal clock divided by 1 .

Updated Figure 344: Advanced-control timer block diagram .

Replaced “AFIO controller” by “GPIO alternate function registers”.

Updated TIM1_OR1 .

Updated Figure 366: TIM1/TIM8 ETR input circuitry .

Updated Figure 371: Control circuit in external clock mode 2 .

Updated Section 38.4.20: TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) .

Updated BKINP, BK2INP, BKCMP1P, BKCMP2P bit description.

Replaced ECC error by Double ECC error when applicable, including in Figure 387: Break and Break2 circuitry overview .

Updated Section 38.3.16: Using the break function .

Updated Section 38.3.18: Clearing the OCxREF signal on an external event .

Updated Section 38.3.26: Timer synchronization .

Updated Figure 373: Capture/compare channel 1 main circuit .

Updated Section 38.3.21: Retriggerable one pulse mode title .

Updated Section 38.4.1: TIMx control register 1 (TIMx_CR1)(x = 1, 8) .

Updated Section 38.4.2: TIMx control register 2 (TIMx_CR2)(x = 1, 8) .

Updated Section 38.4.3: TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) .

Updated Section 38.4.7: TIMx capture/compare mode register 1(TIMx_CCMR1)(x = 1, 8) .

Updated Section 38.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 1, 8) .

Updated Table 334: Output control bits for complementary OCx and OCxN channels with break feature .

Section 39: General-purpose timers (TIM2/TIM3/TIM4/TIM5)

Updated Figure 404: General-purpose timer block diagram .

Updated Figure 430: Capture/Compare channel 1 main circuit .

Updated Figure 431: Output stage of Capture/Compare channel (channel 1) .

Updated Section 39.3.14: Retriggerable one pulse mode title .

Updated Section 39.4.2: TIMx control register 2 (TIMx_CR2)(x = 2 to 5) .

Updated Section 39.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 5) ..

Updated Table 339: Output control bit for standard OCx channels

Updated Section 39.3.19: Timer synchronization .

Added Figure 448: Master/slave connection example with 1 channel only timers .

Updated note below Figure 448: Master/slave connection example with 1 channel only timers

Updated Figure 428: Control circuit in external clock mode 2

Replaced “GPIO and AFIO” by “GPIO control and alternate function registers”.

Deleted Note in bitfield OC1PE of Section 39.3.8: Output compare mode .

Updated title of Figure 417: Counter timing diagram, Update event .

Updated Section 39.3.12: Clearing the OCxREF signal on an external event .

Updated Figure 440: Retriggerable one-pulse mode .

Section 40: General-purpose timers (TIM12/TIM13/TIM14)

Updated Figure 455: General-purpose timer block diagram (TIM13/TIM14) .

Updated Figure 466: Control circuit in external clock mode 1 .

Updated Figure 468: Capture/compare channel 1 main circuit .

Updated Figure 469: Output stage of capture/compare channel (channel 1) .

Updated Section 40.3.6: PWM input mode (only for TIM12) .

updated Section 40.3.12: Retriggerable one pulse mode (TIM12 only) title.

Added Section 40.3.18: Using timer output as trigger for other timers (TIM13/TIM14) .

Updated Section 40.4.2: TIM12 control register 2 (TIM12_CR2) .

Updated Section 40.4.8: TIM12 capture/compare mode register 1 [alternate] (TIM12_CCMR1) .

Updated Table 342: Output control bit for standard OCx channels .

Updated Section 40.5.6: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 13 to 14) .

Updated Table 344: Output control bit for standard OCx channels .

Updated Figure 475: Retriggerable one pulse mode .

Section 41: General-purpose timers (TIM15/TIM16/TIM17)

Updated Figure 495: Capture/compare channel 1 main circuit .

Updated Figure 496: Output stage of capture/compare channel (channel 1) .

Updated Figure 509: Retriggerable one pulse mode .

Updated Figure 491: Control circuit in normal mode, internal clock divided by 1 .

Added Note in Section 41.4.13: Using the break function .

Added Section 41.4.14: 6-step PWM generation .

Suppressed CC2DE in Section 41.5.4: TIM15 DMA/interrupt enable register (TIM15_DIER)

Updated Section 41.5.8: TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) .

Updated Section 41.6.7: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17) .

Replace “AFIO” with reference to GPIO control and/or alternate function registers.

Updated Figure 481: TIM16/TIM17 block diagram .

Updated Figure 497: Output stage of capture/compare channel (channel 2 for TIM15) .

Updated Figure 347: Output control bits for complementary OCx and OCxN channels with break feature (TIM15) .

Updated Section 41.4.7: PWM input mode (only for TIM15) .

Updated Section 41.4.16: Retriggerable one pulse mode (TIM15 only) title .

Added Section 41.4.23: Using timer output as trigger for other timers (TIM16/TIM17) .

Updated Section 41.6.2: TIMx control register 2 (TIMx_CR2)(x = 16 to 17) .

Updated Section 41.5.7: TIM15 capture/compare mode register 1 (TIM15_CCMR1) .

Updated Table 350: TIM16/TIM17 register map and reset values

Section 43: Low-power timer (LPTIM)

Updated Section 43.7: LPTIM registers introduction .

Updated Section 43.7.4: LPTIM configuration register (LPTIM_CFGR) .

Updated Section 43.2: LPTIM main features .

Updated Section 43.4.4: LPTIM reset and clocks

Added note to Section 43.4.7: Trigger multiplexer .

Updated Section 43.4.15: Encoder mode .

Updated Section 43.7.1: LPTIM interrupt and status register (LPTIM_ISR) .

Updated Section 43.7.2: LPTIM interrupt clear register (LPTIM_ICR) .

Updated Section 43.7.4: LPTIM configuration register (LPTIM_CFGR) .

Section 44: System window watchdog (WWDG)

Updated Section 44.3: WWDG functional description , Section 44.3.4: Controlling the down-counter , Section 44.4: WWDG interrupts , and Section 44.3.4: Controlling the down-counter .

Updated Figure 533: Watchdog block diagram .

Section 46: Real-time clock (RTC)

Updated Section : Alarm output .

Updated RTC_TAFCR in Table 380: RTC register map and reset values .

Updated Section 46.6.4: RTC initialization and status register (RTC_ISR) .

Section 47: Inter-integrated circuit (I2C) interface

Updated Section 47.4.3: I2C clock requirements and I2C timings .

Updated Table 388: Examples of timing settings for fI2CCLK = 8 MHz , Table 389: Examples of timing settings for fI2CCLK = 16 MHz , and Table 390: Examples of timing settings for fI2CCLK = 48 MHz

Updated Figure 548: Transfer bus diagrams for I2C slave transmitter (mandatory events only) , Figure 551: Transfer bus diagrams for I2C slave receiver (mandatory events only) , Figure 558: Transfer bus diagrams for I2C master transmitter (mandatory events only) , and Figure 561: Transfer bus diagrams for I2C master receiver (mandatory events only) .

Corrected issue in Section 47.7.1: I2C control register 1 (I2C_CR1) .

Updated Hardware transfer management .

Section 48: Universal synchronous/asynchronous receiver transmitter (USART/UART)

Updated PSC bitfield description in USART_GTPR register (alternate descriptions).

Updated SBKF bit description in USART_ISR and LPUART_ISR (alternate description).

Updated decimal and hexadecimal notation for values in Section : How to derive USARTDIV from USART_BRR register values .

Updated Figure 593: RS232 RTS flow control and Figure 594: RS232 CTS flow control to replace RTS and CTS by nRTS and nCTS respectively.

Updated EOBF bit description of USART_ISR (EOBIE belongs to USART_CR1 instead of USART_CR2).

Added wakeup from Stop in Section 48.2: USART main features .

Added Section 48.4: USART implementation and Section 49.5: LPUART in low-power modes .

Updated Section 48.7: USART interrupts and Section 49.6: LPUART interrupts .

Updated ABRRQ bit description in USART_RQR register.

Updated ABRE bit description in USART_ISR and LPUART_ISR registers (ABRRQ bit belongs to USART_RQR instead of USART_CR3).

Replaced all occurrences of 32,768 KHz by 32.768 kHz and baud/s by baud.

Corrected baud to bit in Section : Selecting the clock source .

Replaced KBps by kbaud and Bps by baud.

Replaced a few occurrences of USART in LPUART section.

Updated Table 408: Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz

Replaced 88.36 Kaud by 88.36 kbaud in the example provided in Section : Determining the maximum LPUART baud rate that enables to correctly wake up the MCU from low-power mode .

Renamed SCLK pin to CK in the whole document.

Section 48.5.21: USART low-power management and Section 49.4.14: LPUART low-power management : removed mention that usart_wkup/lpuart_wkup interrupt is not mandatory when wakeup event is detected.

Updated ADD[7:0] bitfield descriptions in USART_CR2 and LPUART_CR2.

Replaced nCTS and nRTS by CTS and RTS in the whole document.

Changed YES and NO into Yes and No, respectively, for consistency with other IP user specifications.

Replaced LPUART_CR3 by USART_CR3 in ORE bit description of USART_ISR alternate register.

Added DIS_NSS bit description in USART_CR2.
Removed useless uppercase first letters in USART register descriptions.
Updated link to section explaining how to configure the DMA register in USART/LPUART character transmission/reception sections.

Section 51: Serial audio interface (SAI)
Changed table titles into SAI features in Section 51.3: SAI implementation
In Section 51.4.12: SPDIF output , replaced \( F_{\text{SAI\_CK\_x}} \) by \( F_{\text{sai\_x\_ker\_ck}} \) in the formula enabling to compute the bit rate.
Added reference to implementation section in Section 51.4.10: PDM interface .
Added note related to bitfield usage depending on Dx line availability in SAI_PDMPLY.
Added note 2 in Table 429: TDM frame configuration examples
Changed note (1) to (2) in Figure 654: Detailed PDM interface block diagram .

Section 52: SPDIF receiver interface (SPDIFRX)
Added note about RCC capabilities in:
– Section 52.2: SPDIFRX main features
– Table 438: Minimum spdifrx_ker_ck frequency versus audio sampling rate
Updated:
- Section 52.3: SPDIFRX functional description
- Figure 668: SPDIFRX block diagram
Figure 673: SPDIFRX decoder
Figure 674: Noise filtering and edge detection
- Section 52.5.1: SPDIFRX control register (SPDIFRX_CR)
Added SPDIFRX prefix on all register titles

Section 55: Secure digital input/output MultiMediaCard interface (SDMMC)
Updated Section : Data path .
Updated Section : Data FIFO .
Updated DBLOCKSIZE[3:0] in Section 55.10.9: SDMMC data control register (SDMMC_DCTRL) .
Updated Section : Stream operation and CMD12 .
Updated Section : Block operation and CMD12 .
Updated Section : Normal boot operation .
Updated Section : Alternative boot operation
Added footnote to Table 453: SDMMC operation modes e•MMC .

Section 56: Controller area network with flexible data rate (FDCAN)

Added Section 56.5.47: FDCAN register map and Section 56.6: TTCAN registers

Updated Section 56.5.7: FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) .

Corrected markers in Section 56.7: CCU registers .

Updated Table 506: FDCAN TT register map and reset values .

Updated Operating conditions, Clock calibration bypassed, Software calibration, Clock calibration active and Section 56.7.2: Calibration configuration register (FDCAN_CCU_CCFG) .

Replaced Host with user

Updated Table 505: FDCAN register map and reset values .

Updated Section 56.5.3: FDCAN data bit timing and prescaler register (FDCAN_DBTP) .

Section 58: Ethernet (ETH): media access control (MAC) with DMA controller

Table 522: Ethernet peripheral pins:

• – Added ETH_PPS_OUT output, ETH_REF_CLK input, and CRS_DV input.
• – Renamed ETH_RDX and ETH_TX port names into ETH_RXD and ETH_TXD, respectively

Added mac_speed_o[1:0], clk_ptp_ref_i and eth_ptp_trig[4:1] in Table 523: Ethernet internal input/output signals

Updated Section 58.1: Ethernet introduction, Section 58.2: Ethernet main features, Section 58.2.4: DMA block features, Section 58.2.5: Bus interface features

Added Section 58.2.1: Standard compliance, Section 58.2.3: Transaction layer (MTL) features .

Updated step 9 of DMA reception sequence in Section : DMA reception .

Added Section : Priority scheme for Tx DMA and Rx DMA .

Updated Section 58.5.3: Packet filtering, Section 58.5.4: IEEE 1588 timestamp support, and Section 58.5.5: Checksum offload engine .

Section 58.5.6: TCP segmentation offload:

• – Added Section : DMA operation with TSO feature
• – Renamed section Enabling the TSO feature into Section : Building the Descriptor and the packet for the TSO feature and section updated.

Updated Section 58.5.7: IPv4 ARP offload, Section 58.5.8: Loopback, Section 58.5.9: Flow control and Section 58.5.10: MAC management counters .

Added MDIO Clause 45 in Section : SMA functional overview .

Updated Figure 802: RMII block diagram

Updated Section : MII management write operations .

Section : Preamble suppression, Section : Trailing clocks and back-to-back transactions and Section : Interrupt for MDIO transaction completion .

Updated Section 58.6.2: Media independent interface (MII) and Section 58.6.3: Reduced media independent interface (RMII) .

Updated Section 58.7: Ethernet low-power modes .

Updated Section 58.9.3: MAC initialization and Section 58.9.5: Stopping and starting transmission . Added Section 58.9.6: Programming guidelines for switching to new descriptor list in RxDMA , Section 58.9.7: Programming guidelines for switching the AHB clock frequency , Section 58.9.10: Programming guidelines for PTP offload feature and Section 58.9.14: Programming guidelines to perform VLAN filtering on the receive . Updated Section 58.9.11: Programming guidelines for Energy Efficient Ethernet (EEE) and Section 58.9.13: Programming guidelines for TSO .

Updated Figure 813: Receive normal descriptor (read format) as well as Table 570: RDES0 normal descriptor (read format) and Table 573: RDES3 normal descriptor (read format) .

Updated Figure 814: Receive normal descriptor (write-back format) as well as Table 577: RDES3 normal descriptor (write-back format) .

Updated HL or B1L bit in Table 560: TDES2 normal descriptor (read format) , Table 561: TDES3 normal descriptor (read format) , Table 565: TDES3 normal descriptor (write-back format) and Table 569: TDES3 context descriptor . Updated Table 581: RDES3 context descriptor .

Section 58.11.2: Ethernet DMA registers

• – ETH_DMAMR: changed DA bit access type to rw.
• – ETH_DMACRXIWTR/ETH_DMAC0RXIWTR: added RWTU[1:0] bitfield.
• – ETH_DMAIER: removed MMCIE/MCRCISIPIS and GPIIS/GPIIE from Figure 816: Generation of ETH_DMAISR flags ; updated AIE bit description.
• – ETH_DMACCTXDLAR: updated TDESLA description.
• – ETH_DMAMR: changed PR[2:0] and TXPR access type to rw.
• – ETH_DMA(i)CCR: updated MSS[13:0] bitfield description.
• – ETH_DMA(i)TXCR: Updated TSE bit description.
• – ETH_DMACRXDLAR: updated RDESLA description.
• – ETH_DMACTXDTPR: updated TDT description.
• – ETH_DMACRXDTPR: updated RDT description.
• – ETH_DMACCTXRLR: updated TDRL description.
• – ETH_DMACRXRLR: updated RDRL description.
• – ETH_DMACSR: changed bit 15:10, 8:6 and 2: 0 access type to rc_w1; updated REB, TEB, AIS, CDE and TBU bit descriptions
• – ETH_DMARxCR: updated RPF and RBSZ[13:0] descriptions.
• – ETH_DMASBMR reset value updated.

Section 58.11.3: Ethernet MTL registers

• – ETH_MTLOMR: updated CNTPRST and RAA and DTXSTS bit descriptions
• – Updated ETH_MTLRXQOMR register
• – ETH_MTLTXQOMR: updated TXQEN[1:0], updated TQS[2:0] bitfield definition.
• – Updated ETH_MTLTXQUR and ETH_MTLRXQMPOCR bit access type.
• – ETH_MTLTXQ(i)DR: updated STXSTSF[2:0], PTXQ[2:0] and TXSTSFSTS bitfield descriptions.

Section 58.11.4: Ethernet MAC and MMC registers

• – ETH_MACTSCR: moved Table Timestamp snapshot dependency on register bits from ETH_MACTSCR to Section : Clock types ; updated TSUPDT and TSINIT bit descriptions.
• – Updated ETH_MACVR reset value.
• – Updated ETH_MACCR, ETH_MACHTOR/1R, ETH_MACVTCR, and ETH_MACVHTR, ETH_MACTSSR, ETH_MACTSCR, ETH_MACISR, ETH_MACRXTXSR, ETH_MACL3L4C0R, ETH_MACSSIR, ETH_MACTSAR, ETH_MACPOCR, ETH_MACSPI0R and ETH_MACSPI1R, ETH_MACSTSUR and ETH_MACSTNUR, ETH_MACETR, ETH_MAC1USTCR, ETH_MACL3L4C1R, ETH_MACSTSR, ETH_MACATSNR, ETH_MACTSEACR, and ETH_MACPPSIR, ETH_MACMDIOAR, and ETH_MACxHR.
• – ETH_MACLCSR: added LPITCSE bit.
• – ETH_MACACR: updated ATSENX and ATSFC bit descriptions
• – ETH_MACECR: updated GPSL[13:0].
• – ETH_MACPFR: updated DNTU bit description.
• – ETH_MACPFR: updated DNTU, IPFE, HPF, HMC and HUC.
• – ETH_MACIER: updated TSIE and LPIIE bit descriptions.
• – ETH_MACHWF1R/F2R: updated reset value.
• – ETH_MACRPAR: updated ARPPA[31:0] bitfield description.
• – Updated ETH_MACVIR and added alternate register
• – ETH_MACQTXFCR: updated PT bitfield
• – ETH_MACPCSR: updated RWKFILTRST, RWKPTR, RWKPFE
• – ETH_MACDR: updated TFCSTS bit description
• – Added ETH_MACHWF0R/3R registers
• – Updated ETH_MMC_RX_INTERRUPT, ETH_MMC_TX_INTERRUPT, ETH_MMC_RX_INTERRUPT_MASK and ETH_MMC_TX_INTERRUPT_MASK, ETH_MACTXTSSNR register access types.

Section 61: Device electronic signature
Updated Section 61.1: Unique device ID register (96 bits)

Added Section 62: Important security notice