28. Comparator (COMP)

28.1 Introduction

The device embeds two ultra-low-power comparator channels (COMP1 and COMP2). They can be used for a variety of functions including:

• • wake up from low-power mode triggered by an analog signal
• • analog signal conditioning
• • cycle-by-cycle current control loop when combined with a PWM output from a timer

28.2 COMP main features

• • Selectable inverting analog inputs:
  • – I/O pins (different for either channel)
  • – DAC Channel1 and Channel2 outputs
  • – internal reference voltage and three sub multiple values (1/4, 1/2, 3/4) provided by scaler (buffered voltage divider)
• • Two I/O pins per channel selectable as non-inverting analog inputs
• • Programmable hysteresis
• • Programmable speed / consumption
• • Mapping of outputs to I/Os
• • Redirection of outputs to timer inputs for triggering:
  • – capture events
  • – OCREF_CLR events (for cycle-by-cycle current control)
  • – break events for fast PWM shutdowns
• • Blanking of comparator outputs
• • Window comparator
• • Interrupt generation capability with wake up from Sleep and Stop modes (through the EXTI controller)
• • Direct interrupt output to the CPU

28.3 COMP functional description

28.3.1 COMP block diagram

The block diagram of the comparators is shown in Figure 216: Comparator functional block diagram .

Figure 216. Comparator functional block diagram

28.3.2 COMP pins and internal signals

The I/Os used as comparator inputs must be configured in analog mode in the GPIO registers.

The comparator outputs can be connected to the I/Os through their alternate functions. Refer to the product datasheet.

The outputs can also be internally redirected to a variety of timer inputs for the following purposes:

• • emergency shut-down of PWM signals, using BKIN and BKIN2 inputs
• • cycle-by-cycle current control, using ETR inputs of timers
• • input capture for timing measurements

The comparator output can be routed simultaneously internally and to the I/O pins.

Table 235. COMP input/output internal signals

Table 236. COMP input/output pins

28.3.3 COMP reset and clocks

The clock comp_pclk provided by the clock controller is synchronous with the APB clock.

Note: Important: The polarity selection logic and the output redirection to the port works independently from the APB clock. This allows the comparator to work even in Stop mode. The interrupt line, connected to the NVIC of CPU, requires the APB clock ( comp_pclk ) to work. In absence of the APB clock, the interrupt signal comp_it cannot be generated.

28.3.4 Comparator LOCK mechanism

The comparators can be used for safety purposes, such as over-current or thermal protection. For applications with specific functional safety requirements, the comparator configuration can be protected against undesired alteration that could happen, for example, at program counter corruption.

For this purpose, the comparator configuration registers can be write-protected (read-only).

Upon configuring a comparator channel, its LOCK bit is set to 1. This causes the whole register set of the comparator channel, as well as the common COMP_OR register, to become read-only, the LOCK bit inclusive.

The write protection can only be removed through the MCU reset.

The COMP_OR register is locked by the LOCK bit of COMP_CFGR1 OR COMP_CFGR2.

28.3.5 Window comparator

The purpose of the window comparator is to monitor the analog voltage and check that it is comprised within the specified voltage range defined by lower and upper thresholds.

The window comparator requires both COMP channels. The monitored analog voltage is connected to their non-inverting (plus) inputs and the upper and lower threshold voltages are connected to the inverting (minus) input of either comparator, respectively. The non-inverting input of the COMP channel 2 can be connected internally with the non-inverting input of the COMP channel 1 by enabling WINMODE bit. This can save the input pins of COMP channel 2 for other purposes. See Figure 216: Comparator functional block diagram .

28.3.6 Hysteresis

The comparator includes a programmable hysteresis to avoid spurious output transitions in case of noisy signals. The hysteresis can be disabled if it is not needed (for instance when exiting from low-power mode) to be able to force the hysteresis value using external components.

Figure 217. Comparator hysteresis

28.3.7 Comparator output blanking function

The purpose of the blanking function is to prevent the current regulation to trip upon short current spikes at the beginning of the PWM period (typically the recovery current in power switches anti parallel diodes). It uses a blanking window defined with a timer output compare signal. Refer to the register description for selectable blanking signals. The blanking signal gates the internal comparator output such as to clean the comp_out from spurious pulses due to current spikes, as depicted in Figure 218 (the COMP channel number is not represented).

Figure 218. Comparator output blanking

28.3.8 Comparator output on GPIOs

The COMP1_OUT and COMP2_OUT outputs of the comparator channels are mapped to GPIOs through the AFOP field of the COMP_OR register, bits [10:0], and through the GPIO alternate function.

Table 237. COMP1_OUT assignment to GPIOs

Table 238. COMP2_OUT assignment to GPIOs

The assignment to GPIOs for both comparator channel outputs must be done before locking registers of any channel, because the common COMP_OR register is locked when locking the registers of either comparator channel.

28.3.9 Comparator output redirection

The outputs of either COMP channel can be redirected to timer break inputs (TIMx_BKIN or TIMx_BKIN2), as shown in Figure 219 . For that end, the COMP channel output is connected to one of GPIOs programmable in alternate function as timer break input. See Table 237 and Table 238 . The selected GPIO(s) must be set in open drain mode. The COMP output passes through the GPIO to the timer break input. With a pull-up resistor, the selected GPIO can be used as timer break input logic OR-ed with the comparator output.

Figure 219. Output redirection

28.3.10 COMP power and speed modes

The power consumption of the COMP channels versus propagation delay can be adjusted to have the optimum trade-off for a given application.

The bits PWRMODE[1:0] in COMP_CFGRx registers can be programmed as follows:

• 00: High speed / full power
• 01: Medium speed / medium power
• 10: Medium speed / medium power
• 11: Very-low speed / ultra-low-power

28.4 COMP low-power modes

Table 239. Comparator behavior in the low-power modes

Note: The comparators cannot be used to exit the device from Sleep or Stop mode when the internal reference voltage is switched off.

28.5 COMP interrupts

There are two ways to use the comparator as interrupt source.

The comparator outputs are internally connected to the Extended interrupt and event controller. Each comparator has its own EXTI line and can generate either interrupts or events to make the device exit low-power modes.

The comparators also provide an interrupt line to the NVIC of CPU. This functionality is used when the CPU is active to handle low latency interrupt. It requires APB clock running.

28.5.1 Interrupt through EXTI block

Refer to Interrupt and events section for more details.

Sequence to enable the COMPx interrupt through EXTI block:

1. 1. Configure the EXTI line, receiving the comp_wkup signal, in interrupt mode, select the rising, falling or either-edge sensitivity and enable the EXTI line.
2. 2. Configure and enable the NVIC IRQ channel mapped to the corresponding EXTI lines.
3. 3. Enable the COMPx.

Table 240. Interrupt control bits

28.5.2 Interrupt through NVIC of the CPU

Sequence to enable the COMPx interrupt through NVIC of the CPU:

1. 1. Configure and enable the NVIC IRQ channel mapped to the comp_it line.
2. 2. Configure and enable the ITEN in COMP_CFGRx.
3. 3. Enable the COMPx.

Table 241. Interrupt control bits

Note: It is mandatory to enable APB clock to use this interrupt. If clock is not enabled, interrupt is not generated.

28.6 SCALER function

The scaler block is available to provide the different voltage reference levels to the comparator inputs. It is based on an amplifier driving a resistor bridge. The amplifier input is connected to the internal voltage reference.

The amplifier and the resistor bridge can be enabled separately. The amplifier is enabled by the SCALEN bits of the COMP_CFGRx registers. The resistor bridge is enabled by the BRGEN bits of the COMP_CFGRx registers.

When the resistor divided voltage is not used, the resistor bridge can be disconnected in order to reduce the consumption. When it is disconnected, the \( 1/4 V_{REF\_COMP} \) , \( 1/2 V_{REF\_COMP} \) and \( 3/4 V_{REF\_COMP} \) levels are equal to \( V_{REF\_COMP} \) .

Figure 220. Scaler block diagram

28.7 COMP registers

28.7.1 Comparator status register (COMP_SR)

The COMP_SR is the comparator status register.

Address offset: 0x00

System reset value: 0x0000 0000

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 C2IF : COMP channel 2 Interrupt Flag
This bit is set by hardware when the COMP channel 2 output is set
This bit is cleared by software writing 1 the CC2IF bit in the COMP_ICFR register.

Bit 16 C1IF : COMP channel 1 Interrupt Flag
This bit is set by hardware when the COMP channel 1 output is set
This bit is cleared by software writing 1 the CC1IF bit in the COMP_ICFR register.

Bits 15:2 Reserved, must be kept at reset value.

Bit 1 C2VAL : COMP channel 2 output status bit
This bit is read-only. It reflects the current COMP channel 2 output taking into account POLARITY and BLANKING bits effect.

Bit 0 C1VAL : COMP channel 1 output status bit
This bit is read-only. It reflects the current COMP channel 1 output taking into account POLARITY and BLANKING bits effect.

28.7.2 Comparator interrupt clear flag register (COMP_ICFR)

The COMP_ICFR is the Comparator interrupt clear flag register.

Address offset: 0x04

System reset value: 0x0000 0004

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 CC2IF : Clear COMP channel 2 Interrupt Flag

Writing 1 clears the C2IF flag in the COMP_SR register.

Bit 16 CC1IF : Clear COMP channel 1 Interrupt Flag

Writing 1 clears the C1IF flag in the COMP_SR register.

Bits 15:0 Reserved, must be kept at reset value.

28.7.3 Comparator option register (COMP_OR)

The COMP_OR is the Comparator option register.

Address offset: 0x08

System reset value: 0x0000 0000

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:0 AFOP[10:0] : Selection of source for alternate function of output ports

Bits of this field are set and cleared by software (only if LOCK not set).

Output port (GPIO) correspondence:

For each bit:

0: COMP1_OUT is selected for the alternate function of the corresponding GPIO

1: COMP2_OUT is selected for the alternate function of the corresponding GPIO

28.7.4 Comparator configuration register 1 (COMP_CFGR1)

The COMP_CFGR1 is the COMP channel 1 configuration register.

Address offset: 0x0C

System reset value: 0x0000 0000

This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP channel 1 configuration register COMP_CFGR1[31:0], and COMP_OR register

0: COMP_CFGR1[31:0] register is read/write

1: COMP_CFGR1[31:0] and COMP_OR registers are read-only

Bits 30:28 Reserved, must be kept at reset value.

Bits of this field are set and cleared by software (only if LOCK not set).

The field selects the input source for COMP channel 1 output blanking:

0000: No blanking

0001: comp_blk1

0010: comp_blk2

0011: comp_blk3

0100: comp_blk4

0101: comp_blk5

0110: comp_blk6

All other values: reserved

Bits 23:21 Reserved, must be kept at reset value.

This bit is set and cleared by software (only if LOCK not set).

0: COMP1_INP1 (PB0)

1: COMP1_INP2 (PB2)

Bit 19 Reserved, must be kept at reset value.

These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of COMP channel 1.

000 = 1/4 V _{REF_COMP}

001 = 1/2 V _{REF_COMP}

010 = 3/4 V _{REF_COMP}

011 = V _{REF_COMP}

100 = comp_inm1 (DAC channel 1 output)

101 = comp_inm2 (DAC channel 2 output)

110 = COMP1_INM1 (PB1)

111 = COMP1_INM2 (PC4)

Bits 15:14 Reserved, must be kept at reset value.

These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the COMP channel 1.

00: High speed / full power

01: Medium speed / medium power

10: Medium speed / medium power

11: Ultra low power / ultra-low-power

Bits 11:10 Reserved, must be kept at reset value.

Bits 9:8 HYST[1:0] : COMP channel 1 hysteresis selection bits

These bits are set and cleared by software (only if LOCK not set). They select the Hysteresis voltage of the COMP channel 1.

• 00: No hysteresis
• 01: Low hysteresis
• 10: Medium hysteresis
• 11: High hysteresis

Bit 7 Reserved, must be kept at reset value.

Bit 6 ITEN : COMP channel 1 interrupt enable

This bit is set and cleared by software (only if LOCK not set). This bit enable the interrupt generation of the COMP channel 1.

• 0: Interrupt generation disabled for COMP channel 1
• 1: Interrupt generation enabled for COMP channel 1

Bits 5:4 Reserved, must be kept at reset value.

Bit 3 POLARITY : COMP channel 1 polarity selection bit

This bit is set and cleared by software (only if LOCK not set). It inverts COMP channel 1 polarity.

• 0: COMP channel 1 output is not inverted
• 1: COMP channel 1 output is inverted

Bit 2 SCALEN : Voltage scaler enable bit

This bit is set and cleared by software (only if LOCK not set). This bit enables the V _REFINT scaler for the COMP channels.

• 0: V _REFINT scaler disabled (if SCALEN bit of COMP_CFGR2 register is also low)
• 1: V _REFINT scaler enabled

Bit 1 BRGEN : Scaler bridge enable

This bit is set and cleared by software (only if LOCK not set). This bit enables the bridge of the scaler.

• 0: Scaler resistor bridge disabled (if BRGEN bit of COMP_CFGR2 register is also low)
• 1: Scaler resistor bridge enabled

If SCALEN is set and BRGEN is reset, all four scaler outputs provide the same level V _{REF_COMP} (similar to V _REFINT ).

If SCALEN and BRGEN are set, the four scaler outputs provide V _{REF_COMP} , 3/4 V _{REF_COMP} , 1/2 V _{REF_COMP} and 1/4 V _{REF_COMP} levels, respectively.

Bit 0 EN : COMP channel 1 enable bit

This bit is set and cleared by software (only if LOCK not set). It enables the COMP channel 1.

• 0: Disable
• 1: Enable

28.7.5 Comparator configuration register 2 (COMP_CFGR2)

The COMP_CFGR2 is the COMP channel 2 configuration register.

Address offset: 0x10

System reset value: 0x0000 0000

Bit 31 LOCK : Lock bit

This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP channel 2 configuration register COMP_CFGR2[31:0], and COMP_OR register

0: COMP_CFGR2[31:0] register is read/write

1: COMP_CFGR2[31:0] and COMP_OR registers are read-only

Bits 30:28 Reserved, must be kept at reset value.

Bits 27:24 BLANKING[3:0] : COMP channel 2 blanking source selection bits

These bits are set and cleared by software (only if LOCK not set). These bits select which timer output controls the COMP channel 2 output blanking.

0000: No blanking

0001: TIM1_OC5 selected as blanking source

0010: TIM2_OC3 selected as blanking source

0011: TIM3_OC3 selected as blanking source

0100: TIM3_OC4 selected as blanking source

0101: TIM8_OC5 selected as blanking source

0110: TIM15_OC1 selected as blanking source

All other values: reserved

Bits 23:21 Reserved, must be kept at reset value.

Bit 20 INPSEL : COMP channel 2 non-inverting input selection bit

This bit is set and cleared by software (only if LOCK not set).

0: COMP2_INP1 (PE9)

1: COMP2_INP2 (PE11)

Bit 19 Reserved, must be kept at reset value.

Bits 18:16 INMSEL[2:0] : COMP channel 2 inverting input selection field

These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of COMP channel 2.

000 = 1/4 V _{REF_COMP}

001 = 1/2 V _{REF_COMP}

010 = 3/4 V _{REF_COMP}

011 = V _{REF_COMP}

100 = comp_inm1 (DAC channel 1 output)

101 = comp_inm2 (DAC channel 2 output)

110 = COMP2_INM1 (PE10)

111 = COMP2_INM2 (PE7)

Bits 15:14 Reserved, must be kept at reset value.

Bits 13:12 PWRMODE[1:0] : Power Mode of the COMP channel 2

These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the COMP channel 2.

00: High speed / full power

01: Medium speed / medium power

10: Medium speed / medium power

11: Ultra low power / ultra-low-power

Bits 11:10 Reserved, must be kept at reset value.

Bits 9:8 HYST[1:0] : COMP channel 2 hysteresis selection bits

These bits are set and cleared by software (only if LOCK not set). They select the Hysteresis voltage of the COMP channel 2.

• 00: No hysteresis
• 01: Low hysteresis
• 10: Medium hysteresis
• 11: High hysteresis

Bit 7 Reserved, must be kept at reset value.

Bit 6 ITEN : COMP channel 2 interrupt enable

This bit is set and cleared by software (only if LOCK not set). This bit enable the interrupt generation of the COMP channel 2.

• 0: Interrupt generation disabled for COMP channel 2
• 1: Interrupt generation enabled for COMP channel 2

Bit 5 Reserved, must be kept at reset value.

Bit 4 WINMODE : Window comparator mode selection bit

This bit is set and cleared by software (only if LOCK not set). This bit selects the window mode of the comparators. If set, the non-inverting input of COMP channel 2 is connected to the non-inverting input of the COMP channel 1.

Depending on the bit value, the non-inverting input of COMP channel 2 is connected to:

• 0: COMP2_INP input selector
• 1: Non-inverting input comp1_inp of COMP channel 1

Bit 3 POLARITY : COMP channel 2 polarity selection bit

This bit is set and cleared by software (only if LOCK not set). It inverts COMP channel 2 polarity.

• 0: COMP channel 2 output is not inverted
• 1: COMP channel 2 output is inverted

Bit 2 SCALEN : Voltage scaler enable bit

This bit is set and cleared by software (only if LOCK not set). This bit enables the \( V_{REFINT} \) scaler for the COMP channels.

• 0: \( V_{REFINT} \) scaler disabled (if SCALEN bit of COMP_CFGR1 register is also low)
• 1: \( V_{REFINT} \) scaler enabled

Bit 1 BRGEN : Scaler bridge enable

This bit is set and cleared by software (only if LOCK not set). This bit enables the bridge of the scaler.

• 0: Scaler resistor bridge disabled (if BRGEN bit of COMP_CFGR1 register is also low)
• 1: Scaler resistor bridge enabled

If SCALEN is set and BRGEN is reset, all four scaler outputs provide the same level \( V_{REF\_COMP} \) (similar to \( V_{REFINT} \) ).

If SCALEN and BRGEN are set, the four scaler outputs provide \( V_{REF\_COMP} \) , \( 3/4 V_{REF\_COMP} \) , \( 1/2 V_{REF\_COMP} \) and \( 1/4 V_{REF\_COMP} \) levels, respectively.

Bit 0 EN : COMP channel 2 enable bit

This bit is set and cleared by software (only if LOCK not set). It enables the COMP channel 2.

• 0: Disable
• 1: Enable

28.7.6 COMP register map

The following table summarizes the comparator registers.

Table 242. COMP register map and reset values

Refer to Section 2.3 on page 129 for the register boundary addresses.