RM0433-STM32H742-743-753-750

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32H742xx, STM32H743/53xx and STM32H750xB microcontroller memory and peripherals.

The STM32H742, STM32H743/753 and STM32H750 are lines of microcontrollers with different memory sizes, packages and peripherals.

The devices include ST state-of-the-art patented technology.

For ordering information, mechanical, and electrical device characteristics refer to the corresponding datasheets.

For information on the Arm ® Cortex ® -M7 with FPU core, refer to the corresponding Arm Technical Reference Manuals .

Contents

3.3.2RAMECC internal signals .....142
3.3.3RAMECC monitor mapping .....142
3.4RAMECC registers .....143
3.4.1RAMECC interrupt enable register (RAMECC_IER) .....143
3.4.2RAMECC monitor x configuration register (RAMECC_MxCR) .....144
3.4.3RAMECC monitor x status register (RAMECC_MxSR) .....144
3.4.4RAMECC monitor x failing address register (RAMECC_MxFAR) .....145
3.4.5RAMECC monitor x failing data low register (RAMECC_MxFDRL) ..145
3.4.6RAMECC monitor x failing data high register (RAMECC_MxFDRH) .146
3.4.7RAMECC monitor x failing ECC error code register
RAMECC_MxFECR) .....		146
3.4.8RAMECC register map .....147
4Embedded flash memory (FLASH) .....148
4.1Introduction .....148
4.2FLASH main features .....148
4.3FLASH functional description .....149
4.3.1FLASH block diagram .....149
4.3.2FLASH internal signals .....150
4.3.3FLASH architecture and integration in the system .....150
4.3.4Flash memory architecture and usage .....152
4.3.5FLASH system performance enhancements .....156
4.3.6FLASH data protection schemes .....156
4.3.7Overview of FLASH operations .....157
4.3.8FLASH read operations .....158
4.3.9FLASH program operations .....161
4.3.10FLASH erase operations .....165
4.3.11FLASH parallel operations (STM32H742/743/753 devices only) .....168
4.3.12Flash memory error protections .....168
4.3.13Flash bank and register swapping (STM32H742/743/753 devices only) . .170
4.3.14FLASH reset and clocks .....173
4.4FLASH option bytes .....173
4.4.1About option bytes .....173
4.4.2Option byte loading .....174
4.4.3Option byte modification .....174
4.4.4Option bytes overview .....177
4.4.5Description of user and system option bytes . . . . .179
4.4.6Description of data protection option bytes . . . . .180
4.4.7Description of boot address option bytes . . . . .181
4.5FLASH protection mechanisms . . . . .182
4.5.1FLASH configuration protection . . . . .182
4.5.2Write protection . . . . .183
4.5.3Readout protection (RDP) . . . . .184
4.5.4Proprietary code readout protection (PCROP) . . . . .189
4.5.5Secure access mode . . . . .190
4.6FLASH low-power modes . . . . .191
4.6.1Introduction . . . . .191
4.6.2Managing the FLASH domain switching to DStop or DStandby . . . . .192
4.7FLASH error management . . . . .193
4.7.1Introduction . . . . .193
4.7.2Write protection error (WRPERR) . . . . .193
4.7.3Programming sequence error (PGSERR) . . . . .194
4.7.4Strobe error (STRBERR) . . . . .195
4.7.5Inconsistency error (INCERR) . . . . .195
4.7.6Operation error (OPERR) . . . . .196
4.7.7Error correction code error (SNECCERR/DBECCERR) . . . . .196
4.7.8Read protection error (RDPERR) . . . . .197
4.7.9Read secure error (RDSERR) . . . . .197
4.7.10CRC read error (CRCRDERR) . . . . .197
4.7.11Option byte change error (OPTCHANGEERR) . . . . .198
4.7.12Miscellaneous HardFault errors . . . . .198
4.8FLASH interrupts . . . . .198
4.9FLASH registers . . . . .201
4.9.1FLASH access control register (FLASH_ACR) . . . . .201
4.9.2FLASH key register for bank 1 (FLASH_KEYR1) . . . . .201
4.9.3FLASH option key register (FLASH_OPTKEYR) . . . . .202
4.9.4FLASH control register for bank 1 (FLASH_CR1) . . . . .202
4.9.5FLASH status register for bank 1 (FLASH_SR1) . . . . .207
4.9.6FLASH clear control register for bank 1 (FLASH_CCR1) . . . . .210
4.9.7FLASH option control register (FLASH_OPTCR) . . . . .211
4.9.8FLASH option status register (FLASH_OPTSR_CUR) . . . . .212
4.9.9FLASH option status register (FLASH_OPTSR_PRG) . . . . .215
4.9.10FLASH option clear control register (FLASH_OPTCCR) . . . . .217
4.9.11FLASH protection address for bank 1 (FLASH_PRAR_CUR1) . . . . .217
4.9.12FLASH protection address for bank 1 (FLASH_PRAR_PRG1) . . . . .218
4.9.13FLASH secure address for bank 1 (FLASH_SCAR_CUR1) . . . . .219
4.9.14FLASH secure address for bank 1 (FLASH_SCAR_PRG1) . . . . .219
4.9.15FLASH write sector protection for bank 1
(FLASH_WPSN_CUR1R) . . . . .		220
4.9.16FLASH write sector protection for bank 1
(FLASH_WPSN_PRG1R) . . . . .		221
4.9.17FLASH register boot address (FLASH_BOOT_CURR) . . . . .221
4.9.18FLASH register boot address (FLASH_BOOT_PRGR) . . . . .221
4.9.19FLASH CRC control register for bank 1 (FLASH_CRCCR1) . . . . .222
4.9.20FLASH CRC start address register for bank 1
(FLASH_CRCADD1R) . . . . .		223
4.9.21FLASH CRC end address register for bank 1
(FLASH_CRCEADD1R) . . . . .		224
4.9.22FLASH CRC data register (FLASH_CRCDATAR) . . . . .224
4.9.23FLASH ECC fail address for bank 1 (FLASH_ECC_FA1R) . . . . .225
4.9.24FLASH key register for bank 2 (FLASH_KEYR2) . . . . .225
4.9.25FLASH control register for bank 2 (FLASH_CR2) . . . . .226
4.9.26FLASH status register for bank 2 (FLASH_SR2) . . . . .230
4.9.27FLASH clear control register for bank 2 (FLASH_CCR2) . . . . .233
4.9.28FLASH protection address for bank 2 (FLASH_PRAR_CUR2) . . . . .234
4.9.29FLASH protection address for bank 2 (FLASH_PRAR_PRG2) . . . . .234
4.9.30FLASH secure address for bank 2 (FLASH_SCAR_CUR2) . . . . .235
4.9.31FLASH secure address for bank 2 (FLASH_SCAR_PRG2) . . . . .236
4.9.32FLASH write sector protection for bank 2
(FLASH_WPSN_CUR2R) . . . . .		237
4.9.33FLASH write sector protection for bank 2
(FLASH_WPSN_PRG2R) . . . . .		237
4.9.34FLASH CRC control register for bank 2 (FLASH_CRCCR2) . . . . .238
4.9.35FLASH CRC start address register for bank 2
(FLASH_CRCADD2R) . . . . .		239
4.9.36FLASH CRC end address register for bank 2
(FLASH_CRCEADD2R) . . . . .		240
4.9.37FLASH ECC fail address for bank 2 (FLASH_ECC_FA2R) . . . . .240
4.9.38FLASH register map and reset values . . . . .241
5Secure memory management (SMM) . . . . .246

5.1 Introduction . . . . . 246

5.2 Glossary . . . . . 246

5.3 Secure access mode . . . . . 247

5.3.1 Associated features . . . . . 248

5.3.2 Boot state machine . . . . . 248

5.3.3 Secure access mode configuration . . . . . 249

5.4 Root secure services (RSS) . . . . . 250

5.4.1 Secure area setting service . . . . . 250

5.4.2 Secure area exiting service . . . . . 250

5.5 Secure user software . . . . . 251

5.5.1 Access rules . . . . . 251

5.5.2 Setting secure user memory areas . . . . . 251

5.6 Summary of flash protection mechanisms . . . . . 252

6 Power control (PWR) . . . . . 254

6.1 Introduction . . . . . 254

6.2 PWR main features . . . . . 254

6.3 PWR block diagram . . . . . 255

6.3.1 PWR pins and internal signals . . . . . 256

6.4 Power supplies . . . . . 258

6.4.1 System supply startup . . . . . 261

6.4.2 Core domain . . . . . 263

6.4.3 PWR external supply . . . . . 264

6.4.4 Backup domain . . . . . 265

6.4.5 VBAT battery charging . . . . . 267

6.4.6 Analog supply . . . . . 267

6.4.7 USB regulator . . . . . 268

6.5 Power supply supervision . . . . . 268

6.5.1 Power-on reset (POR)/power-down reset (PDR) . . . . . 269

6.5.2 Brownout reset (BOR) . . . . . 269

6.5.3 Programmable voltage detector (PVD) . . . . . 270

6.5.4 Analog voltage detector (AVD) . . . . . 272

6.5.5 Battery voltage thresholds . . . . . 273

6.5.6 Temperature thresholds . . . . . 274

6.6 Power management . . . . . 275

6.6.1 Operating modes . . . . . 276

6.6.2Voltage scaling . . . . .279
6.6.3Power control modes . . . . .281
6.6.4Power management examples . . . . .285
6.7Low-power modes . . . . .291
6.7.1Slowing down system clocks . . . . .291
6.7.2Controlling peripheral clocks . . . . .291
6.7.3Entering low-power modes . . . . .291
6.7.4Exiting from low-power modes . . . . .292
6.7.5CSleep mode . . . . .293
6.7.6CStop mode . . . . .294
6.7.7DStop mode . . . . .295
6.7.8Stop mode . . . . .296
6.7.9DStandby mode . . . . .298
6.7.10Standby mode . . . . .300
6.7.11Monitoring low-power modes . . . . .302
6.8PWR register description . . . . .303
6.8.1PWR control register 1 (PWR_CR1) . . . . .303
6.8.2PWR control status register 1 (PWR_CSR1) . . . . .304
6.8.3PWR control register 2 (PWR_CR2) . . . . .305
6.8.4PWR control register 3 (PWR_CR3) . . . . .306
6.8.5PWR CPU control register (PWR_CPUCR) . . . . .308
6.8.6PWR D3 domain control register (PWR_D3CR) . . . . .309
6.8.7PWR wakeup clear register (PWR_WKUPCR) . . . . .310
6.8.8PWR wakeup flag register (PWR_WKUPFR) . . . . .310
6.8.9PWR wakeup enable and polarity register (PWR_WKUPEPR) . . . . .311
6.8.10PWR register map . . . . .312
7Low-power D3 domain application example . . . . .313
7.1Introduction . . . . .313
7.2EXTI, RCC and PWR interconnections . . . . .313
7.2.1Interrupts and wakeup . . . . .315
7.2.2Block interactions . . . . .315
7.2.3Role of DMAMUX2 in D3 domain . . . . .316
7.3Low-power application example based on
LPUART1 transmission . . . . .		317
7.3.1Memory retention . . . . .317
7.3.2Memory-to-peripheral transfer using LPUART1 interface . . . . .317
8.7.5RCC clock recovery RC register (RCC_CRRCR) . . . . .388
8.7.6RCC CSI configuration register (RCC_CSICFGR) . . . . .389
8.7.7RCC clock configuration register (RCC_CFGR) . . . . .390
8.7.8RCC domain 1 clock configuration register (RCC_D1CFGR) . . . . .393
8.7.9RCC domain 2 clock configuration register (RCC_D2CFGR) . . . . .395
8.7.10RCC domain 3 clock configuration register (RCC_D3CFGR) . . . . .396
8.7.11RCC PLL clock source selection register (RCC_PLLCKSELR) . . . . .397
8.7.12RCC PLL configuration register (RCC_PLLCFGR) . . . . .399
8.7.13RCC PLL1 dividers configuration register (RCC_PLL1DIVR) . . . . .402
8.7.14RCC PLL1 fractional divider register (RCC_PLL1FRACR) . . . . .404
8.7.15RCC PLL2 divider configuration register (RCC_PLL2DIVR) . . . . .405
8.7.16RCC PLL2 fractional divider register (RCC_PLL2FRACR) . . . . .407
8.7.17RCC PLL3 divider configuration register (RCC_PLL3DIVR) . . . . .408
8.7.18RCC PLL3 fractional divider register (RCC_PLL3FRACR) . . . . .410
8.7.19RCC domain 1 kernel clock configuration register
(RCC_D1CCIPR) . . . . .		411
8.7.20RCC domain 2 kernel clock configuration register
(RCC_D2CCIP1R) . . . . .		412
8.7.21RCC domain 2 kernel clock configuration register
(RCC_D2CCIP2R) . . . . .		415
8.7.22RCC domain 3 kernel clock configuration register
(RCC_D3CCIPR) . . . . .		417
8.7.23RCC clock source interrupt enable register (RCC_CIER) . . . . .420
8.7.24RCC clock source Interrupt flag register (RCC_CIFR) . . . . .422
8.7.25RCC clock source interrupt clear register (RCC_CICR) . . . . .424
8.7.26RCC backup domain control register (RCC_BDCR) . . . . .426
8.7.27RCC clock control and status register (RCC_CSR) . . . . .428
8.7.28RCC AHB3 reset register (RCC_AHB3RSTR) . . . . .429
8.7.29RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .431
8.7.30RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .433
8.7.31RCC AHB4 peripheral reset register (RCC_AHB4RSTR) . . . . .434
8.7.32RCC APB3 peripheral reset register (RCC_APB3RSTR) . . . . .436
8.7.33RCC APB1 peripheral reset register (RCC_APB1LRSTR) . . . . .437
8.7.34RCC APB1 peripheral reset register (RCC_APB1HRSTR) . . . . .440
8.7.35RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .441
8.7.36RCC APB4 peripheral reset register (RCC_APB4RSTR) . . . . .443
8.7.37RCC global control register (RCC_GCR) . . . . .445
8.7.38RCC D3 Autonomous mode register (RCC_D3AMR) . . . . .446
9.8.2CRS configuration register (CRS_CFGR) . . . . .512
9.8.3CRS interrupt and status register (CRS_ISR) . . . . .513
9.8.4CRS interrupt flag clear register (CRS_ICR) . . . . .515
9.8.5CRS register map . . . . .515
10Hardware semaphore (HSEM) . . . . .517
10.1Introduction . . . . .517
10.2Main features . . . . .517
10.3Functional description . . . . .518
10.3.1HSEM block diagram . . . . .518
10.3.2HSEM internal signals . . . . .518
10.3.3HSEM lock procedures . . . . .518
10.3.4HSEM write/read/read lock register address . . . . .520
10.3.5HSEM unlock procedures . . . . .520
10.3.6HSEM MASTERID semaphore clear . . . . .521
10.3.7HSEM interrupts . . . . .521
10.3.8AHB bus master ID verification . . . . .523
10.4HSEM registers . . . . .524
10.4.1HSEM register semaphore x (HSEM_Rx) . . . . .524
10.4.2HSEM read lock register semaphore x (HSEM_RLRx) . . . . .525
10.4.3HSEM interrupt enable register (HSEM_IER) . . . . .526
10.4.4HSEM interrupt clear register (HSEM_ICR) . . . . .526
10.4.5HSEM interrupt status register (HSEM_ISR) . . . . .526
10.4.6HSEM interrupt status register (HSEM_MISR) . . . . .527
10.4.7HSEM clear register (HSEM_CR) . . . . .527
10.4.8HSEM clear semaphore key register (HSEM_KEYR) . . . . .528
10.4.9HSEM register map . . . . .529
11General-purpose I/Os (GPIO) . . . . .530
11.1Introduction . . . . .530
11.2GPIO main features . . . . .530
11.3GPIO functional description . . . . .530
11.3.1General-purpose I/O (GPIO) . . . . .533
11.3.2I/O pin alternate function multiplexer and mapping . . . . .533
11.3.3I/O port control registers . . . . .534
11.3.4I/O port data registers . . . . .534
11.3.5I/O data bitwise handling . . . . .534
11.3.6GPIO locking mechanism . . . . .535
11.3.7I/O alternate function input/output . . . . .535
11.3.8External interrupt/wake-up lines . . . . .535
11.3.9Input configuration . . . . .536
11.3.10Output configuration . . . . .536
11.3.11I/O compensation cell . . . . .537
11.3.12Alternate function configuration . . . . .537
11.3.13Analog configuration . . . . .538
11.3.14Using the HSE or LSE oscillator pins as GPIOs . . . . .539
11.3.15Using the GPIO pins in the backup supply domain . . . . .539
11.4GPIO registers . . . . .540
11.4.1GPIO port mode register (GPIOx_MODER)
(x = A to K) . . . . .		540
11.4.2GPIO port output type register (GPIOx_OTYPER)
(x = A to K) . . . . .		540
11.4.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to K) . . . . .		541
11.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to K) . . . . .		541
11.4.5GPIO port input data register (GPIOx_IDR)
(x = A to K) . . . . .		542
11.4.6GPIO port output data register (GPIOx_ODR)
(x = A to K) . . . . .		542
11.4.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to K) . . . . .		543
11.4.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to K) . . . . .		543
11.4.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to K) . . . . .		544
11.4.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to J) . . . . .		545
11.4.11GPIO register map . . . . .546
12System configuration controller (SYSCFG) . . . . .548
12.1Introduction . . . . .548
12.2SYSCFG main features . . . . .548
12.3SYSCFG registers . . . . .548
12.3.1SYSCFG peripheral mode configuration register (SYSCFG_PMCR) . . . . .548
12.3.2SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) .....551
12.3.3SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) .....551
12.3.4SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) .....553
12.3.5SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) .....554
12.3.6SYSCFG configuration register (SYSCFG_CFGR) .....555
12.3.7SYSCFG compensation cell control/status register (SYSCFG_CCCSR) .....558
12.3.8SYSCFG compensation cell value register (SYSCFG_CCV) .....559
12.3.9SYSCFG compensation cell code register (SYSCFG_CCCR) .....559
12.3.10SYSCFG power control register (SYSCFG_PWR) .....560
12.3.11SYSCFG package register (SYSCFG_PKG) .....560
12.3.12SYSCFG user register 0 (SYSCFG_UR0) .....562
12.3.13SYSCFG user register 2 (SYSCFG_UR2) .....562
12.3.14SYSCFG user register 3 (SYSCFG_UR3) .....563
12.3.15SYSCFG user register 4 (SYSCFG_UR4) .....563
12.3.16SYSCFG user register 5 (SYSCFG_UR5) .....564
12.3.17SYSCFG user register 6 (SYSCFG_UR6) .....564
12.3.18SYSCFG user register 7 (SYSCFG_UR7) .....565
12.3.19SYSCFG user register 8 (SYSCFG_UR8) .....565
12.3.20SYSCFG user register 9 (SYSCFG_UR9) .....566
12.3.21SYSCFG user register 10 (SYSCFG_UR10) .....566
12.3.22SYSCFG user register 11 (SYSCFG_UR11) .....567
12.3.23SYSCFG user register 12 (SYSCFG_UR12) .....567
12.3.24SYSCFG user register 13 (SYSCFG_UR13) .....568
12.3.25SYSCFG user register 14 (SYSCFG_UR14) .....569
12.3.26SYSCFG user register 15 (SYSCFG_UR15) .....570
12.3.27SYSCFG user register 16 (SYSCFG_UR16) .....571
12.3.28SYSCFG user register 17 (SYSCFG_UR17) .....571
12.3.29SYSCFG register maps .....572
13Block interconnect .....575
13.1Peripheral interconnect .....575
13.1.1Introduction .....575
13.1.2Connection overview .....575
13.2Wakeup from low power modes . . . . .594
13.3DMA . . . . .599
13.3.1MDMA (D1 domain) . . . . .600
13.3.2DMAMUX1, DMA1 and DMA2 (D2 domain) . . . . .602
13.3.3DMAMUX2, BDMA (D3 domain) . . . . .607
14MDMA controller (MDMA) . . . . .610
14.1MDMA introduction . . . . .610
14.2MDMA main features . . . . .610
14.3MDMA functional description . . . . .612
14.3.1MDMA block diagram . . . . .612
14.3.2MDMA internal signals . . . . .612
14.3.3MDMA overview . . . . .612
14.3.4MDMA channel . . . . .614
14.3.5Source, destination and transfer modes . . . . .614
14.3.6Pointer update . . . . .614
14.3.7MDMA buffer transfer . . . . .615
14.3.8Request arbitration . . . . .616
14.3.9FIFO . . . . .616
14.3.10Block transfer . . . . .616
14.3.11Block repeat mode . . . . .617
14.3.12Linked-list mode . . . . .617
14.3.13MDMA transfer completion . . . . .617
14.3.14MDMA transfer suspension . . . . .617
14.3.15Error management . . . . .618
14.4MDMA interrupts . . . . .618
14.5MDMA registers . . . . .619
14.5.1MDMA global interrupt status register (MDMA_GISR0) . . . . .619
14.5.2MDMA channel x interrupt status register (MDMA_CxISR) . . . . .619
14.5.3MDMA channel x interrupt flag clear register (MDMA_CxIFCR) . . . . .621
14.5.4MDMA channel x error status register (MDMA_CxESR) . . . . .621
14.5.5MDMA channel x control register (MDMA_CxCR) . . . . .622
14.5.6MDMA channel x transfer configuration register (MDMA_CxTCR) . . . . .624
14.5.7MDMA channel x block number of data register (MDMA_CxBNDTR) . . . . .628
14.5.8MDMA channel x source address register (MDMA_CxSAR) . . . . .629
14.5.9MDMA channel x destination address register (MDMA_CxDAR) . . . . .630
14.5.10MDMA channel x block repeat address update register (MDMA_CxBRUR) . . . . .630
14.5.11MDMA channel x link address register (MDMA_CxLAR) . . . . .631
14.5.12MDMA channel x trigger and bus selection register (MDMA_CxTBR) . . . . .632
14.5.13MDMA channel x mask address register (MDMA_CxMAR) . . . . .633
14.5.14MDMA channel x mask data register (MDMA_CxMDR) . . . . .633
14.5.15MDMA register map . . . . .634
15Direct memory access controller (DMA) . . . . .635
15.1DMA introduction . . . . .635
15.2DMA main features . . . . .635
15.3DMA functional description . . . . .637
15.3.1DMA block diagram . . . . .637
15.3.2DMA internal signals . . . . .637
15.3.3DMA overview . . . . .637
15.3.4DMA transactions . . . . .638
15.3.5DMA request mapping . . . . .638
15.3.6Arbiter . . . . .639
15.3.7DMA streams . . . . .639
15.3.8Source, destination and transfer modes . . . . .639
15.3.9Pointer incrementation . . . . .643
15.3.10Circular mode . . . . .644
15.3.11Double-buffer mode . . . . .644
15.3.12Programmable data width, packing/unpacking, endianness . . . . .645
15.3.13Single and burst transfers . . . . .646
15.3.14FIFO . . . . .647
15.3.15DMA transfer completion . . . . .650
15.3.16DMA transfer suspension . . . . .651
15.3.17Flow controller . . . . .652
15.3.18Summary of the possible DMA configurations . . . . .653
15.3.19Stream configuration procedure . . . . .653
15.3.20Error management . . . . .654
15.4DMA interrupts . . . . .655
15.5DMA registers . . . . .656
15.5.1DMA low interrupt status register (DMA_LISR) . . . . .656
15.5.2DMA high interrupt status register (DMA_HISR) . . . . .657
15.5.3DMA low interrupt flag clear register (DMA_LIFCR)658
15.5.4DMA high interrupt flag clear register (DMA_HIFCR)658
15.5.5DMA stream x configuration register (DMA_SxCR)659
15.5.6DMA stream x number of data register (DMA_SxNDTR)662
15.5.7DMA stream x peripheral address register (DMA_SxPAR)662
15.5.8DMA stream x memory 0 address register
(DMA_SxM0AR)		663
15.5.9DMA stream x memory 1 address register
(DMA_SxM1AR)		663
15.5.10DMA stream x FIFO control register (DMA_SxFCR)664
15.5.11DMA register map665
16Basic direct memory access controller (BDMA)669
16.1Introduction669
16.2BDMA main features669
16.3BDMA implementation670
16.3.1BDMA670
16.3.2BDMA request mapping670
16.4BDMA functional description670
16.4.1BDMA block diagram670
16.4.2BDMA pins and internal signals671
16.4.3BDMA transfers671
16.4.4BDMA arbitration672
16.4.5BDMA channels672
16.4.6BDMA data width, alignment and endianness677
16.4.7BDMA error management678
16.5BDMA interrupts679
16.6BDMA registers679
16.6.1BDMA interrupt status register (BDMA_ISR)679
16.6.2BDMA interrupt flag clear register (BDMA_IFCR)682
16.6.3BDMA channel x configuration register (BDMA_CCRx)683
16.6.4BDMA channel x number of data to transfer register
(BDMA_CNDTRx)		687
16.6.5BDMA channel x peripheral address register (BDMA_CPARx)687
16.6.6BDMA channel x memory 0 address register (BDMA_CM0ARx)688
16.6.7BDMA channel x memory 1 address register (BDMA_CM1ARx)689
16.6.8BDMA register map689
17DMA request multiplexer (DMAMUX)692
17.1Introduction692
17.2DMAMUX main features693
17.3DMAMUX implementation693
17.3.1DMAMUX1 and DMAMUX2 instantiation693
17.3.2DMAMUX1 mapping693
17.3.3DMAMUX2 mapping696
17.4DMAMUX functional description699
17.4.1DMAMUX block diagram699
17.4.2DMAMUX signals700
17.4.3DMAMUX channels700
17.4.4DMAMUX request line multiplexer700
17.4.5DMAMUX request generator703
17.5DMAMUX interrupts704
17.6DMAMUX registers705
17.6.1DMAMUX1 request line multiplexer channel x configuration register (DMAMUX1_CxCR)705
17.6.2DMAMUX2 request line multiplexer channel x configuration register (DMAMUX2_CxCR)706
17.6.3DMAMUX1 request line multiplexer interrupt channel status register (DMAMUX1_CSR)707
17.6.4DMAMUX2 request line multiplexer interrupt channel status register (DMAMUX2_CSR)707
17.6.5DMAMUX1 request line multiplexer interrupt clear flag register (DMAMUX1_CFR)708
17.6.6DMAMUX2 request line multiplexer interrupt clear flag register (DMAMUX2_CFR)708
17.6.7DMAMUX1 request generator channel x configuration register (DMAMUX1_RGxCR)709
17.6.8DMAMUX2 request generator channel x configuration register (DMAMUX2_RGxCR)709
17.6.9DMAMUX1 request generator interrupt status register (DMAMUX1_RGSR)710
17.6.10DMAMUX2 request generator interrupt status register (DMAMUX2_RGSR)711
17.6.11DMAMUX1 request generator interrupt clear flag register (DMAMUX1_RGCFR)711
17.6.12DMAMUX2 request generator interrupt clear flag register (DMAMUX2_RGCFR)712
17.6.13DMAMUX register map713
18.5.13DMA2D background CLUT memory address register (DMA2D_BGC MAR) . . . . .740
18.5.14DMA2D output PFC control register (DMA2D_OPFCCR) . . . . .741
18.5.15DMA2D output color register (DMA2D_OCOLR) . . . . .742
18.5.16DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .742
18.5.17DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .743
18.5.18DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .743
18.5.19DMA2D output memory address register (DMA2D_OMAR) . . . . .744
18.5.20DMA2D output offset register (DMA2D_OOR) . . . . .744
18.5.21DMA2D number of line register (DMA2D_NLR) . . . . .745
18.5.22DMA2D line watermark register (DMA2D_LWR) . . . . .745
18.5.23DMA2D AXI master timer configuration register (DMA2D_AMTCR) . . . . .746
18.5.24DMA2D foreground CLUT (DMA2D_FGCLUTx) . . . . .746
18.5.25DMA2D background CLUT (DMA2D_BGCLUTx) . . . . .747
18.5.26DMA2D register map . . . . .747
19Nested vectored interrupt controller (NVIC) . . . . .749
19.1NVIC features . . . . .749
19.1.1SysTick calibration value register . . . . .749
19.1.2Interrupt and exception vectors . . . . .750
20Extended interrupt and event controller (EXTI) . . . . .758
20.1EXTI main features . . . . .758
20.2EXTI block diagram . . . . .758
20.2.1EXTI connections between peripherals, CPU, and D3 domain . . . . .759
20.3EXTI functional description . . . . .760
20.3.1EXTI Configurable event input CPU wakeup . . . . .761
20.3.2EXTI configurable event input Any wakeup . . . . .762
20.3.3EXTI direct event input CPU wakeup . . . . .764
20.3.4EXTI direct event input Any wakeup . . . . .765
20.3.5EXTI D3 pending request clear selection . . . . .766
20.4EXTI event input mapping . . . . .766
20.5EXTI functional behavior . . . . .769
20.5.1EXTI CPU interrupt procedure . . . . .770
20.5.2EXTI CPU event procedure . . . . .770
20.5.3EXTI CPU wakeup procedure . . . . .771
20.5.4EXTI D3 domain wakeup for autonomous Run mode procedure . . . . .771
20.5.5EXTI software interrupt/event trigger procedure . . . . .771
20.6EXTI registers . . . . .772
20.6.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .772
20.6.2EXTI falling trigger selection register (EXTI_FTSR1) . . . . .772
20.6.3EXTI software interrupt event register (EXTI_SWIER1) . . . . .773
20.6.4EXTI D3 pending mask register (EXTI_D3PMR1) . . . . .773
20.6.5EXTI D3 pending clear selection register low (EXTI_D3PCR1L) . . . . .774
20.6.6EXTI D3 pending clear selection register high (EXTI_D3PCR1H) . . . . .774
20.6.7EXTI rising trigger selection register (EXTI_RTSR2) . . . . .775
20.6.8EXTI falling trigger selection register (EXTI_FTSR2) . . . . .776
20.6.9EXTI software interrupt event register (EXTI_SWIER2) . . . . .776
20.6.10EXTI D3 pending mask register (EXTI_D3PMR2) . . . . .777
20.6.11EXTI D3 pending clear selection register low (EXTI_D3PCR2L) . . . . .778
20.6.12EXTI D3 pending clear selection register high (EXTI_D3PCR2H) . . . . .778
20.6.13EXTI rising trigger selection register (EXTI_RTSR3) . . . . .779
20.6.14EXTI falling trigger selection register (EXTI_FTSR3) . . . . .779
20.6.15EXTI software interrupt event register (EXTI_SWIER3) . . . . .780
20.6.16EXTI D3 pending mask register (EXTI_D3PMR3) . . . . .780
20.6.17EXTI D3 pending clear selection register low (EXTI_D3PCR3L) . . . . .781
20.6.18EXTI D3 pending clear selection register high (EXTI_D3PCR3H) . . . . .781
20.6.19EXTI interrupt mask register (EXTI_CPUIMR1) . . . . .782
20.6.20EXTI event mask register (EXTI_CPUEMR1) . . . . .782
20.6.21EXTI pending register (EXTI_CPUPR1) . . . . .783
20.6.22EXTI interrupt mask register (EXTI_CPUIMR2) . . . . .783
20.6.23EXTI event mask register (EXTI_CPUEMR2) . . . . .784
20.6.24EXTI pending register (EXTI_CPUPR2) . . . . .784
20.6.25EXTI interrupt mask register (EXTI_CPUIMR3) . . . . .785
20.6.26EXTI event mask register (EXTI_CPUEMR3) . . . . .786
20.6.27EXTI pending register (EXTI_CPUPR3) . . . . .786
20.6.28EXTI register map . . . . .787
21Cyclic redundancy check calculation unit (CRC) . . . . .790
21.1Introduction . . . . .790
21.2CRC main features . . . . .790
21.3CRC functional description . . . . .791
21.3.1CRC block diagram . . . . .791
21.3.2CRC internal signals . . . . .791
21.3.3CRC operation . . . . .791
21.4CRC registers . . . . .793
21.4.1CRC data register (CRC_DR) . . . . .793
21.4.2CRC independent data register (CRC_IDR) . . . . .793
21.4.3CRC control register (CRC_CR) . . . . .794
21.4.4CRC initial value (CRC_INIT) . . . . .795
21.4.5CRC polynomial (CRC_POL) . . . . .795
21.4.6CRC register map . . . . .796
22Flexible memory controller (FMC) . . . . .797
22.1FMC main features . . . . .797
22.2FMC block diagram . . . . .798
22.3FMC internal signals . . . . .800
22.4AHB interface . . . . .800
22.5AXI interface . . . . .800
22.5.1Supported memories and transactions . . . . .801
22.6External device address mapping . . . . .802
22.6.1NOR/PSRAM address mapping . . . . .803
22.6.2NAND flash memory address mapping . . . . .804
22.6.3SDRAM address mapping . . . . .804
22.7NOR flash/PSRAM controller . . . . .808
22.7.1External memory interface signals . . . . .809
22.7.2Supported memories and transactions . . . . .811
22.7.3General timing rules . . . . .812
22.7.4NOR flash/PSRAM controller asynchronous transactions . . . . .813
22.7.5Synchronous transactions . . . . .832
22.7.6NOR/PSRAM controller registers . . . . .838
22.8NAND flash controller . . . . .847
22.8.1External memory interface signals . . . . .847
22.8.2NAND flash supported memories and transactions . . . . .848
22.8.3Timing diagrams for NAND flash memories . . . . .849
22.8.4NAND flash operations . . . . .850
22.8.5NAND flash prewait feature . . . . .851
22.8.6Computation of the error correction code (ECC)
in NAND flash memory . . . . .		852
22.8.7NAND flash controller registers . . . . .853
22.9SDRAM controller . . . . .859
22.9.1SDRAM controller main features . . . . .859
22.9.2SDRAM External memory interface signals . . . . .859
22.9.3SDRAM controller functional description . . . . .860
22.9.4Low-power modes . . . . .867
22.9.5SDRAM controller registers . . . . .870
22.9.6FMC register map . . . . .876
23Quad-SPI interface (QUADSPI) . . . . .879
23.1Introduction . . . . .879
23.2QUADSPI main features . . . . .879
23.3QUADSPI functional description . . . . .879
23.3.1QUADSPI block diagram . . . . .879
23.3.2QUADSPI pins and internal signals . . . . .880
23.3.3QUADSPI command sequence . . . . .881
23.3.4QUADSPI signal interface protocol modes . . . . .883
23.3.5QUADSPI indirect mode . . . . .885
23.3.6QUADSPI automatic status-polling mode . . . . .887
23.3.7QUADSPI memory-mapped mode . . . . .887
23.3.8QUADSPI free-running clock mode . . . . .888
23.3.9QUADSPI flash memory configuration . . . . .888
23.3.10QUADSPI delayed data sampling . . . . .889
23.3.11QUADSPI configuration . . . . .889
23.3.12QUADSPI use . . . . .889
23.3.13Sending the instruction only once . . . . .891
23.3.14QUADSPI error management . . . . .892
23.3.15QUADSPI busy bit and abort functionality . . . . .892
23.3.16NCS behavior . . . . .892
23.4QUADSPI interrupts . . . . .894
23.5QUADSPI registers . . . . .895
23.5.1QUADSPI control register (QUADSPI_CR) . . . . .895
23.5.2QUADSPI device configuration register (QUADSPI_DCR) . . . . .897
23.5.3QUADSPI status register (QUADSPI_SR) . . . . .898
23.5.4QUADSPI flag clear register (QUADSPI_FCR) . . . . .899
23.5.5QUADSPI data length register (QUADSPI_DLR) . . . . .900
23.5.6QUADSPI communication configuration register (QUADSPI_CCR) . . . . .900
23.5.7QUADSPI address register (QUADSPI_AR) . . . . .902
23.5.8QUADSPI alternate-byte register (QUADSPI_ABR) . . . . .903
23.5.9QUADSPI data register (QUADSPI_DR) . . . . .903
23.5.10QUADSPI polling status mask register (QUADSPI_PSMKR) . . . . .904
23.5.11QUADSPI polling status match register (QUADSPI_PSMAR) . . . . .904
23.5.12QUADSPI polling interval register (QUADSPI_PIR) . . . . .905
23.5.13QUADSPI low-power timeout register (QUADSPI_LPTR) . . . . .905
23.5.14QUADSPI register map . . . . .906
24Delay block (DLYB) . . . . .907
24.1Introduction . . . . .907
24.2DLYB main features . . . . .907
24.3DLYB functional description . . . . .907
24.3.1DLYB diagram . . . . .907
24.3.2DLYB pins and internal signals . . . . .908
24.3.3General description . . . . .908
24.3.4Delay line length configuration procedure . . . . .909
24.3.5Output clock phase configuration procedure . . . . .909
24.4DLYB registers . . . . .910
24.4.1DLYB control register (DLYB_CR) . . . . .910
24.4.2DLYB configuration register (DLYB_CFGR) . . . . .910
24.4.3DLYB register map . . . . .911
25Analog-to-digital converters (ADC) . . . . .912
25.1Introduction . . . . .912
25.2ADC main features . . . . .913
25.3ADC implementation . . . . .914
25.4ADC functional description . . . . .915
25.4.1ADC block diagram . . . . .915
25.4.2ADC pins and internal signals . . . . .916
25.4.3ADC clocks . . . . .917
25.4.4ADC1/2/3 connectivity . . . . .920
25.4.5Slave AHB interface . . . . .923
25.4.6ADC deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) . . . . .923
25.4.7Single-ended and differential input channels . . . . .924
25.4.8Calibration (ADCAL, ADCALDIF, ADCALLIN, ADC_CALFACT) . . . . .924
25.4.9ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .930
25.4.10Constraints when writing the ADC control bits . . . . .931
25.4.11Channel selection (SQRx, JSQRx) . . . . .931
25.4.12Channel preselection register (ADC_PCSEL) . . . . .932
25.4.13Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .933
25.4.14Single conversion mode (CONT=0) . . . . .934
25.4.15Continuous conversion mode (CONT=1) . . . . .934
25.4.16Starting conversions (ADSTART, JADSTART) . . . . .935
25.4.17Timing . . . . .936
25.4.18Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .936
25.4.19Conversion on external trigger and trigger polarity (EXTSEL, EXTEN,
JEXTSEL, JEXTEN) . . . . .		938
25.4.20Injected channel management . . . . .941
25.4.21Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .943
25.4.22Queue of context for injected conversions . . . . .944
25.4.23Programmable resolution (RES) - fast conversion mode . . . . .952
25.4.24End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . . . .952
25.4.25End of conversion sequence (EOS, JEOS) . . . . .952
25.4.26Timing diagrams example (single/continuous modes,
hardware/software triggers) . . . . .		953
25.4.27Data management . . . . .954
25.4.28Managing conversions using the DFSDM . . . . .962
25.4.29Dynamic low-power features . . . . .962
25.4.30Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,
AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) . . . . .		967
25.4.31Oversampler . . . . .970
25.4.32Dual ADC modes . . . . .976
25.4.33Temperature sensor . . . . .991
25.4.34VBAT supply monitoring . . . . .992
25.4.35Monitoring the internal voltage reference . . . . .993
25.5ADC interrupts . . . . .995
25.6ADC registers (for each ADC) . . . . .996
25.6.1ADC interrupt and status register (ADC_ISR) . . . . .996
25.6.2ADC interrupt enable register (ADC_IER) . . . . .999
25.6.3ADC control register (ADC_CR) . . . . .1001
25.6.4ADC configuration register (ADC_CFGR) . . . . .1010
25.6.5ADC configuration register 2 (ADC_CFGR2) . . . . .1014
25.6.6ADC sample time register 1 (ADC_SMPR1) . . . . .1016
25.6.7ADC sample time register 2 (ADC_SMPR2) . . . . .1017
25.6.8ADC channel preselection register (ADC_PCSEL) . . . . .1018
25.6.9ADC watchdog threshold register 1 (ADC_LTR1) . . . . .1018
25.6.10ADC watchdog threshold register 1 (ADC_HTR1) . . . . .1019
25.6.11ADC regular sequence register 1 (ADC_SQR1) . . . . .1020
25.6.12ADC regular sequence register 2 (ADC_SQR2) . . . . .1021
25.6.13ADC regular sequence register 3 (ADC_SQR3) . . . . .1022
25.6.14ADC regular sequence register 4 (ADC_SQR4) . . . . .1023
25.6.15ADC regular Data Register (ADC_DR) . . . . .1024
25.6.16ADC injected sequence register (ADC_JSQR) . . . . .1025
25.6.17ADC injected channel y offset register (ADC_OF Ry) . . . . .1027
25.6.18ADC injected channel y data register (ADC_JDRy) . . . . .1028
25.6.19ADC analog watchdog 2 configuration register
(ADC_AWD2CR) . . . . .		1028
25.6.20ADC analog watchdog 3 configuration register
(ADC_AWD3CR) . . . . .		1029
25.6.21ADC watchdog lower threshold register 2 (ADC_LTR2) . . . . .1029
25.6.22ADC watchdog higher threshold register 2 (ADC_HTR2) . . . . .1030
25.6.23ADC watchdog lower threshold register 3 (ADC_LTR3) . . . . .1030
25.6.24ADC watchdog higher threshold register 3 (ADC_HTR3) . . . . .1031
25.6.25ADC differential mode selection register (ADC_DIFSEL) . . . . .1031
25.6.26ADC calibration factors register (ADC_CALFACT) . . . . .1032
25.6.27ADC calibration factor register 2 (ADC_CALFACT2) . . . . .1032
25.7ADC common registers . . . . .1033
25.7.1ADC x common status register (ADCx_CSR) (x=1/2 or 3) . . . . .1033
25.7.2ADC x common control register (ADCx_CCR) (x=1/2 or 3) . . . . .1035
25.7.3ADC x common regular data register for dual mode
(ADCx_CDR) (x=1/2 or 3) . . . . .		1039
25.7.4ADC x common regular data register for 32-bit dual mode
(ADCx_CDR2) (x=1/2 or 3) . . . . .		1039
25.8ADC register map . . . . .1040
26Digital-to-analog converter (DAC) . . . . .1044
26.1Introduction . . . . .1044
26.2DAC main features . . . . .1044
26.3DAC implementation . . . . .1045
26.4DAC functional description . . . . .1046
26.4.1DAC block diagram . . . . .1046
26.4.2DAC pins and internal signals . . . . .1047
26.4.3DAC channel enable . . . . .1048
26.4.4DAC data format . . . . .1048
26.4.5DAC conversion . . . . .1050
26.4.6DAC output voltage . . . . .1050
26.4.7DAC trigger selection . . . . .1050
26.4.8DMA requests . . . . .1051
26.4.9Noise generation . . . . .1051
26.4.10Triangle-wave generation . . . . .1053
26.4.11DAC channel modes . . . . .1054
26.4.12DAC channel buffer calibration . . . . .1057
26.4.13Dual DAC channel conversion modes (if dual channels are available) . . . . .1058
26.5DAC in low-power modes . . . . .1062
26.6DAC interrupts . . . . .1063
26.7DAC registers . . . . .1064
26.7.1DAC control register (DAC_CR) . . . . .1064
26.7.2DAC software trigger register (DAC_SWTRGR) . . . . .1067
26.7.3DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . .1068
26.7.4DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . .1068
26.7.5DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . .1069
26.7.6DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . .1069
26.7.7DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . .1070
26.7.8DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . .1070
26.7.9Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . .1071
26.7.10Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . .1071
26.7.11Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . .1072
26.7.12DAC channel1 data output register (DAC_DOR1) . . . . .1072
26.7.13DAC channel2 data output register (DAC_DOR2) . . . . .1073
26.7.14DAC status register (DAC_SR) . . . . .1073
26.7.15DAC calibration control register (DAC_CCR) . . . . .1075
26.7.16DAC mode control register (DAC_MCR) . . . . .1075
26.7.17DAC channel1 sample and hold sample time register
(DAC_SHSR1) . . . . .		1077
26.7.18DAC channel2 sample and hold sample time register
(DAC_SHSR2) . . . . .		1077
26.7.19DAC sample and hold time register (DAC_SHHR) . . . . .1078
26.7.20DAC sample and hold refresh time register (DAC_SHRR) . . . . .1078
26.7.21DAC register map . . . . .1079
27Voltage reference buffer (VREFBUF) . . . . .1081
27.1Introduction . . . . .1081
27.2VREFBUF functional description . . . . .1081
27.3VREFBUF registers . . . . .1082
27.3.1VREFBUF control and status register (VREFBUF_CSR) . . . . .1082
27.3.2VREFBUF calibration control register (VREFBUF_CCR) . . . . .1083
27.3.3VREFBUF register map . . . . .1083
28Comparator (COMP) . . . . .1084
28.1Introduction . . . . .1084
28.2COMP main features . . . . .1084
28.3COMP functional description . . . . .1085
28.3.1COMP block diagram . . . . .1085
28.3.2COMP pins and internal signals . . . . .1085
28.3.3COMP reset and clocks . . . . .1087
28.3.4Comparator LOCK mechanism . . . . .1087
28.3.5Window comparator . . . . .1087
28.3.6Hysteresis . . . . .1087
28.3.7Comparator output blanking function . . . . .1088
28.3.8Comparator output on GPIOs . . . . .1089
28.3.9Comparator output redirection . . . . .1090
28.3.10COMP power and speed modes . . . . .1090
28.4COMP low-power modes . . . . .1091
28.5COMP interrupts . . . . .1091
28.5.1Interrupt through EXTI block . . . . .1091
28.5.2Interrupt through NVIC of the CPU . . . . .1092
28.6SCALER function . . . . .1092
28.7COMP registers . . . . .1093

29 Operational amplifiers (OPAMP) . . . . . 1100

30 Digital filter for sigma delta modulators (DFSDM) . . . . . 1118

30.4.4Serial channel transceivers . . . . .1124
30.4.5Configuring the input serial interface . . . . .1134
30.4.6Parallel data inputs . . . . .1134
30.4.7Channel selection . . . . .1136
30.4.8Digital filter configuration . . . . .1137
30.4.9Integrator unit . . . . .1138
30.4.10Analog watchdog . . . . .1139
30.4.11Short-circuit detector . . . . .1141
30.4.12Extreme detector . . . . .1142
30.4.13Data unit block . . . . .1142
30.4.14Signed data format . . . . .1143
30.4.15Launching conversions . . . . .1144
30.4.16Continuous and fast continuous modes . . . . .1144
30.4.17Request precedence . . . . .1145
30.4.18Power optimization in run mode . . . . .1146
30.5DFSDM interrupts . . . . .1146
30.6DFSDM DMA transfer . . . . .1148
30.7DFSDM channel y registers (y=0..7) . . . . .1148
30.7.1DFSDM channel y configuration register (DFSDM_CHyCFGGR1) . . . . .1148
30.7.2DFSDM channel y configuration register (DFSDM_CHyCFGGR2) . . . . .1150
30.7.3DFSDM channel y analog watchdog and short-circuit detector register
(DFSDM_CHyAWSCDR) . . . . .		1151
30.7.4DFSDM channel y watchdog filter data register
(DFSDM_CHyWDATR) . . . . .		1152
30.7.5DFSDM channel y data input register (DFSDM_CHyDATINR) . . . . .1152
30.8DFSDM filter x module registers (x=0..3) . . . . .1153
30.8.1DFSDM filter x control register 1 (DFSDM_FLTxCR1) . . . . .1153
30.8.2DFSDM filter x control register 2 (DFSDM_FLTxCR2) . . . . .1156
30.8.3DFSDM filter x interrupt and status register (DFSDM_FLTxISR) . . . . .1157
30.8.4DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) . . . . .1159
30.8.5DFSDM filter x injected channel group selection register
(DFSDM_FLTxJCHGR) . . . . .		1160
30.8.6DFSDM filter x control register (DFSDM_FLTxFCR) . . . . .1160
30.8.7DFSDM filter x data register for injected group
(DFSDM_FLTxJDATAR) . . . . .		1161
30.8.8DFSDM filter x data register for the regular channel
(DFSDM_FLTxRDATAR) . . . . .		1162

30.8.9 DFSDM filter x analog watchdog high threshold register (DFSDM_FLTxAWHTR) . . . . . 1163

30.8.10 DFSDM filter x analog watchdog low threshold register (DFSDM_FLTxAWLTR) . . . . . 1163

30.8.11 DFSDM filter x analog watchdog status register (DFSDM_FLTxAWSR) . . . . . 1164

30.8.12 DFSDM filter x analog watchdog clear flag register (DFSDM_FLTxAWCFR) . . . . . 1165

30.8.13 DFSDM filter x extremes detector maximum register (DFSDM_FLTxEXMAX) . . . . . 1165

30.8.14 DFSDM filter x extremes detector minimum register (DFSDM_FLTxEXMIN) . . . . . 1166

30.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . . . . . 1166

30.8.16 DFSDM register map . . . . . 1167

31 Digital camera interface (DCMI) . . . . . 1177

31.1 Introduction . . . . . 1177

31.2 DCMI main features . . . . . 1177

31.3 DCMI functional description . . . . . 1177

31.3.1 DCMI block diagram . . . . . 1178

31.3.2 DCMI pins and internal signals . . . . . 1178

31.3.3 DCMI clocks . . . . . 1179

31.3.4 DCMI DMA interface . . . . . 1179

31.3.5 DCMI physical interface . . . . . 1179

31.3.6 DCMI synchronization . . . . . 1181

31.3.7 DCMI capture modes . . . . . 1183

31.3.8 DCMI crop feature . . . . . 1184

31.3.9 DCMI JPEG format . . . . . 1185

31.3.10 DCMI FIFO . . . . . 1185

31.3.11 DCMI data format description . . . . . 1186

31.4 DCMI interrupts . . . . . 1188

31.5 DCMI registers . . . . . 1189

31.5.1 DCMI control register (DCMI_CR) . . . . . 1189

31.5.2 DCMI status register (DCMI_SR) . . . . . 1191

31.5.3 DCMI raw interrupt status register (DCMI_RIS) . . . . . 1192

31.5.4 DCMI interrupt enable register (DCMI_IER) . . . . . 1193

31.5.5 DCMI masked interrupt status register (DCMI_MIS) . . . . . 1194

31.5.6 DCMI interrupt clear register (DCMI_ICR) . . . . . 1195

31.5.7DCMI embedded synchronization code register (DCMI_ESCR) . . . .1195
31.5.8DCMI embedded synchronization unmask register (DCMI_ESUR) . .1196
31.5.9DCMI crop window start (DCMI_CWSTRT) . . . . .1197
31.5.10DCMI crop window size (DCMI_CWSIZE) . . . . .1197
31.5.11DCMI data register (DCMI_DR) . . . . .1198
31.5.12DCMI register map . . . . .1198
32LCD-TFT display controller (LTDC) . . . . .1200
32.1Introduction . . . . .1200
32.2LTDC main features . . . . .1200
32.3LTDC functional description . . . . .1201
32.3.1LTDC block diagram . . . . .1201
32.3.2LTDC pins and internal signals . . . . .1201
32.3.3LTDC reset and clocks . . . . .1202
32.4LTDC programmable parameters . . . . .1204
32.4.1LTDC global configuration parameters . . . . .1204
32.4.2Layer programmable parameters . . . . .1206
32.5LTDC interrupts . . . . .1210
32.6LTDC programming procedure . . . . .1211
32.7LTDC registers . . . . .1212
32.7.1LTDC synchronization size configuration register (LTDC_SSCR) . .1212
32.7.2LTDC back porch configuration register (LTDC_BPCR) . . . . .1212
32.7.3LTDC active width configuration register (LTDC_AWCR) . . . . .1213
32.7.4LTDC total width configuration register (LTDC_TWCR) . . . . .1214
32.7.5LTDC global control register (LTDC_GCR) . . . . .1214
32.7.6LTDC shadow reload configuration register (LTDC_SRCR) . . . . .1216
32.7.7LTDC background color configuration register (LTDC_BCCR) . . . . .1216
32.7.8LTDC interrupt enable register (LTDC_IER) . . . . .1217
32.7.9LTDC interrupt status register (LTDC_ISR) . . . . .1218
32.7.10LTDC interrupt clear register (LTDC_ICR) . . . . .1218
32.7.11LTDC line interrupt position configuration register (LTDC_LIPCR) . .1219
32.7.12LTDC current position status register (LTDC_CPSR) . . . . .1219
32.7.13LTDC current display status register (LTDC_CDSR) . . . . .1220
32.7.14LTDC layer x control register (LTDC_LxCR) . . . . .1220
32.7.15LTDC layer x window horizontal position configuration register
(LTDC_LxWHPER) . . . . .		1221

32.7.16 LTDC layer x window vertical position configuration register (LTDC_LxWVPCR) . . . . . 1222

32.7.17 LTDC layer x color keying configuration register (LTDC_LxCKCR) . . . . . 1223

32.7.18 LTDC layer x pixel format configuration register (LTDC_LxPFCR) . . . . . 1223

32.7.19 LTDC layer x constant alpha configuration register (LTDC_LxCACR) . . . . . 1224

32.7.20 LTDC layer x default color configuration register (LTDC_LxDCCR) . . . . . 1224

32.7.21 LTDC layer x blending factors configuration register (LTDC_LxBFCR) . . . . . 1225

32.7.22 LTDC layer x color frame buffer address register (LTDC_LxCFBAR) . . . . . 1226

32.7.23 LTDC layer x color frame buffer length register (LTDC_LxCFBLR) . . . . . 1226

32.7.24 LTDC layer x color frame buffer line number register (LTDC_LxCFBLNR) . . . . . 1227

32.7.25 LTDC layer x CLUT write register (LTDC_LxCLUTWR) . . . . . 1227

32.7.26 LTDC register map . . . . . 1228

33 JPEG codec (JPEG) . . . . . 1231

33.1 Introduction . . . . . 1231

33.2 JPEG codec main features . . . . . 1231

33.3 JPEG codec block functional description . . . . . 1232

33.3.1 General description . . . . . 1232

33.3.2 JPEG internal signals . . . . . 1232

33.3.3 JPEG decoding procedure . . . . . 1233

33.3.4 JPEG encoding procedure . . . . . 1234

33.4 JPEG codec interrupts . . . . . 1236

33.5 JPEG codec registers . . . . . 1237

33.5.1 JPEG codec control register (JPEG_CONFR0) . . . . . 1237

33.5.2 JPEG codec configuration register 1 (JPEG_CONFR1) . . . . . 1237

33.5.3 JPEG codec configuration register 2 (JPEG_CONFR2) . . . . . 1238

33.5.4 JPEG codec configuration register 3 (JPEG_CONFR3) . . . . . 1239

33.5.5 JPEG codec configuration register x (JPEG_CONFRx) . . . . . 1239

33.5.6 JPEG control register (JPEG_CR) . . . . . 1240

33.5.7 JPEG status register (JPEG_SR) . . . . . 1241

33.5.8 JPEG clear flag register (JPEG_CFR) . . . . . 1242

33.5.9JPEG data input register (JPEG_DIR) . . . . .1243
33.5.10JPEG data output register (JPEG_DOR) . . . . .1243
33.5.11JPEG quantization memory x (JPEG_QMEMx_y) . . . . .1244
33.5.12JPEG Huffman min (JPEG_HUFFMINx_y) . . . . .1244
33.5.13JPEG Huffman min x [alternate] (JPEG_HUFFMINx_y) . . . . .1245
33.5.14JPEG Huffman base (JPEG_HUFFBASEx) . . . . .1245
33.5.15JPEG Huffman symbol (JPEG_HUFFSYMBx) . . . . .1246
33.5.16JPEG DHT memory (JPEG_DHTMEMx) . . . . .1247
33.5.17JPEG Huffman encoder ACx (JPEG_HUFFENC_ACx_y) . . . . .1247
33.5.18JPEG Huffman encoder DCx (JPEG_HUFFENC_DCx_y) . . . . .1248
33.5.19JPEG codec register map . . . . .1249
34True random number generator (RNG) . . . . .1251
34.1Introduction . . . . .1251
34.2RNG main features . . . . .1251
34.3RNG functional description . . . . .1252
34.3.1RNG block diagram . . . . .1252
34.3.2RNG internal signals . . . . .1252
34.3.3Random number generation . . . . .1252
34.3.4RNG initialization . . . . .1255
34.3.5RNG operation . . . . .1256
34.3.6RNG clocking . . . . .1257
34.3.7Error management . . . . .1257
34.3.8In this case application must clear the SEIS bit interrupt flag. RNG low-power use 1258
34.4RNG interrupts . . . . .1258
34.5RNG processing time . . . . .1258
34.6RNG entropy source validation . . . . .1259
34.6.1Introduction . . . . .1259
34.6.2Validation conditions . . . . .1259
34.6.3Data collection . . . . .1259
34.7RNG registers . . . . .1259
34.7.1RNG control register (RNG_CR) . . . . .1259
34.7.2RNG status register (RNG_SR) . . . . .1260
34.7.3RNG data register (RNG_DR) . . . . .1261
34.7.4RNG register map . . . . .1262
35Cryptographic processor (CRYP) . . . . .1263
35.1Introduction . . . . .1263
35.2CRYP main features . . . . .1263
35.3CRYP implementation . . . . .1264
35.4CRYP functional description . . . . .1265
35.4.1CRYP block diagram . . . . .1265
35.4.2CRYP internal signals . . . . .1266
35.4.3CRYP DES/TDES cryptographic core . . . . .1266
35.4.4CRYP AES cryptographic core . . . . .1267
35.4.5CRYP procedure to perform a cipher operation . . . . .1273
35.4.6CRYP busy state . . . . .1275
35.4.7Preparing the CRYP AES key for decryption . . . . .1276
35.4.8CRYP stealing and data padding . . . . .1276
35.4.9CRYP suspend/resume operations . . . . .1278
35.4.10CRYP DES/TDES basic chaining modes (ECB, CBC) . . . . .1279
35.4.11CRYP AES basic chaining modes (ECB, CBC) . . . . .1284
35.4.12CRYP AES counter mode (AES-CTR) . . . . .1289
35.4.13CRYP AES Galois/counter mode (GCM) . . . . .1293
35.4.14CRYP AES Galois message authentication code (GMAC) . . . . .1298
35.4.15CRYP AES Counter with CBC-MAC (CCM) . . . . .1299
35.4.16CRYP data registers and data swapping . . . . .1304
35.4.17CRYP key registers . . . . .1308
35.4.18CRYP initialization vector registers . . . . .1308
35.4.19CRYP DMA interface . . . . .1309
35.4.20CRYP error management . . . . .1311
35.5CRYP interrupts . . . . .1312
35.6CRYP processing time . . . . .1313
35.7CRYP registers . . . . .1314
35.7.1CRYP control register (CRYP_CR) . . . . .1314
35.7.2CRYP status register (CRYP_SR) . . . . .1316
35.7.3CRYP data input register (CRYP_DIN) . . . . .1317
35.7.4CRYP data output register (CRYP_DOUT) . . . . .1317
35.7.5CRYP DMA control register (CRYP_DMACR) . . . . .1318
35.7.6CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . .1319
35.7.7CRYP raw interrupt status register (CRYP_RISR) . . . . .1319
35.7.8CRYP masked interrupt status register (CRYP_MISR) . . . . .1320
35.7.9CRYP key register 0L (CRYP_K0LR)1321
35.7.10CRYP key register 0R (CRYP_K0RR)1321
35.7.11CRYP key register 1L (CRYP_K1LR)1322
35.7.12CRYP key register 1R (CRYP_K1RR)1322
35.7.13CRYP key register 2L (CRYP_K2LR)1323
35.7.14CRYP key register 2R (CRYP_K2RR)1323
35.7.15CRYP key register 3L (CRYP_K3LR)1324
35.7.16CRYP key register 3R (CRYP_K3RR)1324
35.7.17CRYP initialization vector register 0L (CRYP_IV0LR)1325
35.7.18CRYP initialization vector register 0R (CRYP_IV0RR)1325
35.7.19CRYP initialization vector register 1L (CRYP_IV1LR)1326
35.7.20CRYP initialization vector register 1R (CRYP_IV1RR)1326
35.7.21CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR)1326
35.7.22CRYP context swap GCM registers (CRYP_CSGCMxR)1327
35.7.23CRYP register map1327
36Hash processor (HASH)1330
36.1Introduction1330
36.2HASH main features1330
36.3HASH implementation1331
36.4HASH functional description1331
36.4.1HASH block diagram1331
36.4.2HASH internal signals1332
36.4.3About secure hash algorithms1332
36.4.4Message data feeding1332
36.4.5Message digest computing1334
36.4.6Message padding1335
36.4.7HMAC operation1337
36.4.8HASH suspend/resume operations1339
36.4.9HASH DMA interface1341
36.4.10HASH error management1341
36.5HASH interrupts1341
36.6HASH processing time1342
36.7HASH registers1343
36.7.1HASH control register (HASH_CR)1343
36.7.2HASH data input register (HASH_DIN)1345
36.7.3HASH start register (HASH_STR) . . . . .1346
36.7.4HASH digest registers . . . . .1347
36.7.5HASH interrupt enable register (HASH_IMR) . . . . .1348
36.7.6HASH status register (HASH_SR) . . . . .1349
36.7.7HASH context swap registers . . . . .1349
36.7.8HASH register map . . . . .1350
37High-Resolution Timer (HRTIM) . . . . .1352
37.1Introduction . . . . .1352
37.2Main features . . . . .1353
37.3Functional description . . . . .1354
37.3.1General description . . . . .1354
37.3.2HRTIM pins and internal signals . . . . .1356
37.3.3Clocks . . . . .1357
37.3.4Timer A..E timing units . . . . .1360
37.3.5Master timer . . . . .1377
37.3.6Set/reset events priorities and narrow pulses management . . . . .1378
37.3.7External events global conditioning . . . . .1379
37.3.8External event filtering in timing units . . . . .1384
37.3.9Delayed Protection . . . . .1389
37.3.10Register preload and update management . . . . .1395
37.3.11Events propagation within or across multiple timers . . . . .1398
37.3.12Output management . . . . .1402
37.3.13Burst mode controller . . . . .1404
37.3.14Chopper . . . . .1413
37.3.15Fault protection . . . . .1414
37.3.16Auxiliary outputs . . . . .1417
37.3.17Synchronizing the HRTIM with other timers or HRTIM instances . . . . .1420
37.3.18ADC triggers . . . . .1423
37.3.19DAC triggers . . . . .1424
37.3.20HRTIM Interrupts . . . . .1426
37.3.21DMA . . . . .1428
37.3.22HRTIM initialization . . . . .1431
37.3.23Debug . . . . .1432
37.4Application use cases . . . . .1433
37.4.1Buck converter . . . . .1433
37.4.2Buck converter with synchronous rectification . . . . .1434
37.4.3Multiphase converters .....1435
37.4.4Transition mode Power Factor Correction .....1437
37.5HRTIM registers .....1439
37.5.1HRTIM Master Timer Control Register (HRTIM_MCR) .....1439
37.5.2HRTIM Master Timer Interrupt Status Register (HRTIM_MISR) .....1442
37.5.3HRTIM Master Timer Interrupt Clear Register (HRTIM_MICR) .....1443
37.5.4HRTIM Master Timer DMA / Interrupt Enable Register
(HRTIM_MDIER) .....		1444
37.5.5HRTIM Master Timer Counter Register (HRTIM_MCNTR) .....1446
37.5.6HRTIM Master Timer Period Register (HRTIM_MPER) .....1446
37.5.7HRTIM Master Timer Repetition Register (HRTIM_MREP) .....1447
37.5.8HRTIM Master Timer Compare 1 Register (HRTIM_MCMP1R) .....1447
37.5.9HRTIM Master Timer Compare 2 Register (HRTIM_MCMP2R) .....1448
37.5.10HRTIM Master Timer Compare 3 Register (HRTIM_MCMP3R) .....1448
37.5.11HRTIM Master Timer Compare 4 Register (HRTIM_MCMP4R) .....1449
37.5.12HRTIM Timerx Control Register (HRTIM_TIMxCR) .....1450
37.5.13HRTIM Timerx Interrupt Status Register (HRTIM_TIMxISR) .....1454
37.5.14HRTIM Timerx Interrupt Clear Register (HRTIM_TIMxICR) .....1456
37.5.15HRTIM Timerx DMA / Interrupt Enable Register
(HRTIM_TIMxDIER) .....		1457
37.5.16HRTIM Timerx Counter Register (HRTIM_CNTxR) .....1460
37.5.17HRTIM Timerx Period Register (HRTIM_PERxR) .....1460
37.5.18HRTIM Timerx Repetition Register (HRTIM_REPxR) .....1461
37.5.19HRTIM Timerx Compare 1 Register (HRTIM_CMP1xR) .....1461
37.5.20HRTIM Timerx Compare 1 Compound Register
(HRTIM_CMP1CxR) .....		1462
37.5.21HRTIM Timerx Compare 2 Register (HRTIM_CMP2xR) .....1462
37.5.22HRTIM Timerx Compare 3 Register (HRTIM_CMP3xR) .....1463
37.5.23HRTIM Timerx Compare 4 Register (HRTIM_CMP4xR) .....1463
37.5.24HRTIM Timerx Capture 1 Register (HRTIM_CPT1xR) .....1464
37.5.25HRTIM Timerx Capture 2 Register (HRTIM_CPT2xR) .....1464
37.5.26HRTIM Timerx Deadtime Register (HRTIM_DTxR) .....1465
37.5.27HRTIM Timerx Output1 Set Register (HRTIM_SETx1R) .....1467
37.5.28HRTIM Timerx Output1 Reset Register (HRTIM_RSTx1R) .....1469
37.5.29HRTIM Timerx Output2 Set Register (HRTIM_SETx2R) .....1469
37.5.30HRTIM Timerx Output2 Reset Register (HRTIM_RSTx2R) .....1470
37.5.31HRTIM Timerx External Event Filtering Register 1
(HRTIM_EEFxR1) .....		1471
37.5.32HRTIM Timerx External Event Filtering Register 2 (HRTIM_EEFxR2) . . . . .1473
37.5.33HRTIM Timerx Reset Register (HRTIM_RSTxR) . . . . .1474
37.5.34HRTIM Timerx Chopper Register (HRTIM_CHPxR) . . . . .1477
37.5.35HRTIM Timerx Capture 1 Control Register (HRTIM_CPT1xCR) . . . . .1479
37.5.36HRTIM Timerx Capture 2 Control Register (HRTIM_CPT2xCR) . . . . .1480
37.5.37HRTIM Timerx Output Register (HRTIM_OUTxR) . . . . .1483
37.5.38HRTIM Timerx Fault Register (HRTIM_FLTxR) . . . . .1486
37.5.39HRTIM Control Register 1 (HRTIM_CR1) . . . . .1487
37.5.40HRTIM Control Register 2 (HRTIM_CR2) . . . . .1489
37.5.41HRTIM Interrupt Status Register (HRTIM_ISR) . . . . .1490
37.5.42HRTIM Interrupt Clear Register (HRTIM_ICR) . . . . .1491
37.5.43HRTIM Interrupt Enable Register (HRTIM_IER) . . . . .1492
37.5.44HRTIM Output Enable Register (HRTIM_OENR) . . . . .1493
37.5.45HRTIM Output Disable Register (HRTIM_ODISR) . . . . .1494
37.5.46HRTIM Output Disable Status Register (HRTIM_ODSR) . . . . .1495
37.5.47HRTIM Burst Mode Control Register (HRTIM_BMCR) . . . . .1496
37.5.48HRTIM Burst Mode Trigger Register (HRTIM_BMTRGR) . . . . .1498
37.5.49HRTIM Burst Mode Compare Register (HRTIM_BMCMPR) . . . . .1500
37.5.50HRTIM Burst Mode Period Register (HRTIM_BMPER) . . . . .1500
37.5.51HRTIM Timer External Event Control Register 1 (HRTIM_EECR1) . . . . .1501
37.5.52HRTIM Timer External Event Control Register 2 (HRTIM_EECR2) . . . . .1503
37.5.53HRTIM Timer External Event Control Register 3 (HRTIM_EECR3) . . . . .1504
37.5.54HRTIM ADC Trigger 1 Register (HRTIM_ADC1R) . . . . .1505
37.5.55HRTIM ADC Trigger 2 Register (HRTIM_ADC2R) . . . . .1506
37.5.56HRTIM ADC Trigger 3 Register (HRTIM_ADC3R) . . . . .1507
37.5.57HRTIM ADC Trigger 4 Register (HRTIM_ADC4R) . . . . .1509
37.5.58HRTIM Fault Input Register 1 (HRTIM_FLTINR1) . . . . .1511
37.5.59HRTIM Fault Input Register 2 (HRTIM_FLTINR2) . . . . .1513
37.5.60HRTIM Burst DMA Master timer update Register (HRTIM_BDMUPR) . . . . .1515
37.5.61HRTIM Burst DMA Timerx update Register (HRTIM_BDTxUPR) . . . . .1516
37.5.62HRTIM Burst DMA Data Register (HRTIM_BDMADR) . . . . .1517
37.5.63HRTIM register map . . . . .1518
38Advanced-control timers (TIM1/TIM8) . . . . .1527
38.1TIM1/TIM8 introduction . . . . .1527
38.2TIM1/TIM8 main features . . . . .1527
38.3TIM1/TIM8 functional description . . . . .1529
38.3.1Time-base unit . . . . .1529
38.3.2Counter modes . . . . .1531
38.3.3Repetition counter . . . . .1542
38.3.4External trigger input . . . . .1544
38.3.5Clock selection . . . . .1545
38.3.6Capture/compare channels . . . . .1549
38.3.7Input capture mode . . . . .1551
38.3.8PWM input mode . . . . .1552
38.3.9Forced output mode . . . . .1553
38.3.10Output compare mode . . . . .1554
38.3.11PWM mode . . . . .1555
38.3.12Asymmetric PWM mode . . . . .1558
38.3.13Combined PWM mode . . . . .1559
38.3.14Combined 3-phase PWM mode . . . . .1560
38.3.15Complementary outputs and dead-time insertion . . . . .1561
38.3.16Using the break function . . . . .1563
38.3.17Bidirectional break inputs . . . . .1569
38.3.18Clearing the OCxREF signal on an external event . . . . .1569
38.3.196-step PWM generation . . . . .1571
38.3.20One-pulse mode . . . . .1572
38.3.21Retriggerable one pulse mode . . . . .1573
38.3.22Encoder interface mode . . . . .1574
38.3.23UIF bit remapping . . . . .1576
38.3.24Timer input XOR function . . . . .1577
38.3.25Interfacing with Hall sensors . . . . .1577
38.3.26Timer synchronization . . . . .1580
38.3.27ADC synchronization . . . . .1584
38.3.28DMA burst mode . . . . .1584
38.3.29Debug mode . . . . .1585
38.4TIM1/TIM8 registers . . . . .1586
38.4.1TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . .1586
38.4.2TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . .1587
38.4.3TIMx slave mode control register
(TIMx_SMCR)(x = 1, 8) . . . . .		1590
38.4.4TIMx DMA/interrupt enable register
(TIMx_DIER)(x = 1, 8) . . . . .		1592
38.4.5TIMx status register (TIMx_SR)(x = 1, 8) . . . . .1594
38.4.6TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . .1596
38.4.7TIMx capture/compare mode register 1(TIMx_CCMR1)(x = 1, 8) . . .1597
38.4.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . .		1598
38.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 1, 8) . .1601
38.4.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . .		1602
38.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 1, 8) . . . . .		1604
38.4.12TIMx counter (TIMx_CNT)(x = 1, 8) . . . . .1607
38.4.13TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . .1607
38.4.14TIMx auto-reload register (TIMx_ARR)(x = 1, 8) . . . . .1607
38.4.15TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . .1608
38.4.16TIMx capture/compare register 1
(TIMx_CCR1)(x = 1, 8) . . . . .		1608
38.4.17TIMx capture/compare register 2
(TIMx_CCR2)(x = 1, 8) . . . . .		1609
38.4.18TIMx capture/compare register 3
(TIMx_CCR3)(x = 1, 8) . . . . .		1609
38.4.19TIMx capture/compare register 4
(TIMx_CCR4)(x = 1, 8) . . . . .		1610
38.4.20TIMx break and dead-time register
(TIMx_BDTR)(x = 1, 8) . . . . .		1610
38.4.21TIMx DMA control register
(TIMx_DCR)(x = 1, 8) . . . . .		1613
38.4.22TIMx DMA address for full transfer
(TIMx_DMAR)(x = 1, 8) . . . . .		1614
38.4.23TIMx capture/compare mode register 3
(TIMx_CCMR3)(x = 1, 8) . . . . .		1615
38.4.24TIMx capture/compare register 5
(TIMx_CCR5)(x = 1, 8) . . . . .		1616
38.4.25TIMx capture/compare register 6
(TIMx_CCR6)(x = 1, 8) . . . . .		1617
38.4.26TIM1 alternate function option register 1 (TIM1_AF1) . . . . .1617
38.4.27TIM1 Alternate function register 2 (TIM1_AF2) . . . . .1619
38.4.28TIM8 Alternate function option register 1 (TIM8_AF1) . . . . .1620
38.4.29TIM8 Alternate function option register 2 (TIM8_AF2) . . . . .1622
38.4.30TIM1 timer input selection register (TIM1_TISEL) . . . . .1624
38.4.31TIM8 timer input selection register (TIM8_TISEL) . . . . .1624
38.4.32TIM1 register map . . . . .1626
38.4.33TIM8 register map . . . . .1628
39General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . .1631
39.1TIM2/TIM3/TIM4/TIM5 introduction . . . . .1631
39.2TIM2/TIM3/TIM4/TIM5 main features . . . . .1631
39.3TIM2/TIM3/TIM4/TIM5 functional description . . . . .1633
39.3.1Time-base unit . . . . .1633
39.3.2Counter modes . . . . .1635
39.3.3Clock selection . . . . .1645
39.3.4Capture/Compare channels . . . . .1649
39.3.5Input capture mode . . . . .1650
39.3.6PWM input mode . . . . .1651
39.3.7Forced output mode . . . . .1652
39.3.8Output compare mode . . . . .1653
39.3.9PWM mode . . . . .1654
39.3.10Asymmetric PWM mode . . . . .1657
39.3.11Combined PWM mode . . . . .1658
39.3.12Clearing the OCxREF signal on an external event . . . . .1659
39.3.13One-pulse mode . . . . .1661
39.3.14Retriggerable one pulse mode . . . . .1662
39.3.15Encoder interface mode . . . . .1663
39.3.16UIF bit remapping . . . . .1665
39.3.17Timer input XOR function . . . . .1665
39.3.18Timers and external trigger synchronization . . . . .1666
39.3.19Timer synchronization . . . . .1669
39.3.20DMA burst mode . . . . .1674
39.3.21Debug mode . . . . .1675
39.4TIM2/TIM3/TIM4/TIM5 registers . . . . .1676
39.4.1TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . .1676
39.4.2TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . .1677
39.4.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . .1679
39.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . .1682
39.4.5TIMx status register (TIMx_SR)(x = 2 to 5) . . . . .1683
39.4.6TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . .1684
39.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) . . . . .1686
39.4.8TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5) .....		1688
39.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) .1690
39.4.10TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5) .....		1691
39.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 5) .....		1692
39.4.12TIMx counter (TIMx_CNT)(x = 2 to 5) .....1693
39.4.13TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) .....1694
39.4.14TIMx prescaler (TIMx_PSC)(x = 2 to 5) .....1694
39.4.15TIMx auto-reload register (TIMx_ARR)(x = 2 to 5) .....1695
39.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) .....1695
39.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) .....1696
39.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) .....1696
39.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) .....1697
39.4.20TIMx DMA control register (TIMx_DCR)(x = 2 to 5) .....1698
39.4.21TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) .....1698
39.4.22TIM2 alternate function option register 1 (TIM2_AF1) .....1699
39.4.23TIM3 alternate function option register 1 (TIM3_AF1) .....1699
39.4.24TIM4 alternate function option register 1 (TIM4_AF1) .....1700
39.4.25TIM5 alternate function option register 1 (TIM5_AF1) .....1700
39.4.26TIM2 timer input selection register (TIM2_TISEL) .....1701
39.4.27TIM3 timer input selection register (TIM3_TISEL) .....1701
39.4.28TIM4 timer input selection register (TIM4_TISEL) .....1702
39.4.29TIM5 timer input selection register (TIM5_TISEL) .....1703
39.4.30TIMx register map .....1705
40General-purpose timers (TIM12/TIM13/TIM14) .....1708
40.1TIM12/TIM13/TIM14 introduction .....1708
40.2TIM12/TIM13/TIM14 main features .....1708
40.2.1TIM12 main features .....1708
40.2.2TIM13/TIM14 main features .....1709
40.3TIM12/TIM13/TIM14 functional description .....1711
40.3.1Time-base unit .....1711
40.3.2Counter modes .....1713
40.3.3Clock selection .....1716
40.3.4Capture/compare channels .....1718
40.3.5Input capture mode .....1720
40.3.6PWM input mode (only for TIM12) . . . . .1721
40.3.7Forced output mode . . . . .1722
40.3.8Output compare mode . . . . .1723
40.3.9PWM mode . . . . .1724
40.3.10Combined PWM mode (TIM12 only) . . . . .1725
40.3.11One-pulse mode . . . . .1726
40.3.12Retriggerable one pulse mode (TIM12 only) . . . . .1728
40.3.13UIF bit remapping . . . . .1728
40.3.14Timer input XOR function . . . . .1729
40.3.15TIM12 external trigger synchronization . . . . .1729
40.3.16Slave mode – combined reset + trigger mode . . . . .1732
40.3.17Timer synchronization (TIM12) . . . . .1733
40.3.18Using timer output as trigger for other timers (TIM13/TIM14) . . . . .1733
40.3.19Debug mode . . . . .1733
40.4TIM12 registers . . . . .1733
40.4.1TIM12 control register 1 (TIM12_CR1) . . . . .1733
40.4.2TIM12 control register 2 (TIM12_CR2) . . . . .1734
40.4.3TIM12 slave mode control register (TIM12_SMCR) . . . . .1735
40.4.4TIM12 Interrupt enable register (TIM12_DIER) . . . . .1737
40.4.5TIM12 status register (TIM12_SR) . . . . .1737
40.4.6TIM12 event generation register (TIM12_EGR) . . . . .1738
40.4.7TIM12 capture/compare mode register 1 (TIM12_CCMR1) . . . . .1739
40.4.8TIM12 capture/compare mode register 1 [alternate]
(TIM12_CCMR1) . . . . .		1740
40.4.9TIM12 capture/compare enable register (TIM12_CCER) . . . . .1743
40.4.10TIM12 counter (TIM12_CNT) . . . . .1744
40.4.11TIM12 prescaler (TIM12_PSC) . . . . .1745
40.4.12TIM12 auto-reload register (TIM12_ARR) . . . . .1745
40.4.13TIM12 capture/compare register 1 (TIM12_CCR1) . . . . .1745
40.4.14TIM12 capture/compare register 2 (TIM12_CCR2) . . . . .1746
40.4.15TIM12 timer input selection register (TIM12_TISEL) . . . . .1746
40.4.16TIM12 register map . . . . .1747
40.5TIM13/TIM14 registers . . . . .1749
40.5.1TIMx control register 1 (TIMx_CR1)(x = 13 to 14) . . . . .1749
40.5.2TIMx Interrupt enable register (TIMx_DIER)(x = 13 to 14) . . . . .1750
40.5.3TIMx status register (TIMx_SR)(x = 13 to 14) . . . . .1750
40.5.4TIMx event generation register (TIMx_EGR)(x = 13 to 14) . . . . .1751
41.4.20Slave mode – combined reset + trigger mode . . . . .1796
41.4.21DMA burst mode . . . . .1796
41.4.22Timer synchronization (TIM15) . . . . .1798
41.4.23Using timer output as trigger for other timers (TIM16/TIM17) . . . . .1798
41.4.24Debug mode . . . . .1798
41.5TIM15 registers . . . . .1799
41.5.1TIM15 control register 1 (TIM15_CR1) . . . . .1799
41.5.2TIM15 control register 2 (TIM15_CR2) . . . . .1800
41.5.3TIM15 slave mode control register (TIM15_SMCR) . . . . .1802
41.5.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .1803
41.5.5TIM15 status register (TIM15_SR) . . . . .1804
41.5.6TIM15 event generation register (TIM15_EGR) . . . . .1806
41.5.7TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .1807
41.5.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		1808
41.5.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .1811
41.5.10TIM15 counter (TIM15_CNT) . . . . .1814
41.5.11TIM15 prescaler (TIM15_PSC) . . . . .1814
41.5.12TIM15 auto-reload register (TIM15_ARR) . . . . .1814
41.5.13TIM15 repetition counter register (TIM15_RCR) . . . . .1815
41.5.14TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .1815
41.5.15TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .1816
41.5.16TIM15 break and dead-time register (TIM15_BDTR) . . . . .1816
41.5.17TIM15 DMA control register (TIM15_DCR) . . . . .1819
41.5.18TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .1819
41.5.19TIM15 alternate register 1 (TIM15_AF1) . . . . .1820
41.5.20TIM15 input selection register (TIM15_TISEL) . . . . .1821
41.5.21TIM15 register map . . . . .1822
41.6TIM16/TIM17 registers . . . . .1824
41.6.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .1824
41.6.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .1825
41.6.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .1826
41.6.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .1827
41.6.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .1828
41.6.6TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 16 to 17) . . . . .		1829
41.6.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . .		1830
41.6.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .1832
41.6.9TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .1834
41.6.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .1835
41.6.11TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . .1835
41.6.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .1836
41.6.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .1836
41.6.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .1837
41.6.15TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .1839
41.6.16TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . .1840
41.6.17TIM16 alternate function register 1 (TIM16_AF1) . . . . .1841
41.6.18TIM16 input selection register (TIM16_TISEL) . . . . .1842
41.6.19TIM17 alternate function register 1 (TIM17_AF1) . . . . .1843
41.6.20TIM17 input selection register (TIM17_TISEL) . . . . .1844
41.6.21TIM16/TIM17 register map . . . . .1845
42Basic timers (TIM6/TIM7) . . . . .1847
42.1TIM6/TIM7 introduction . . . . .1847
42.2TIM6/TIM7 main features . . . . .1847
42.3TIM6/TIM7 functional description . . . . .1848
42.3.1Time-base unit . . . . .1848
42.3.2Counting mode . . . . .1850
42.3.3UIF bit remapping . . . . .1853
42.3.4Clock source . . . . .1853
42.3.5Debug mode . . . . .1854
42.4TIM6/TIM7 registers . . . . .1854
42.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . .1854
42.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . .1856
42.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . .1856
42.4.4TIMx status register (TIMx_SR)(x = 6 to 7) . . . . .1857
42.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . .1857
42.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . .1857
42.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . .1858
42.4.8TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . .1858
42.4.9TIMx register map . . . . .1859
43Low-power timer (LPTIM) . . . . .1860
43.1Introduction . . . . .1860
43.2LPTIM main features . . . . .1860
43.3LPTIM implementation . . . . .1861
43.4LPTIM functional description . . . . .1861
43.4.1LPTIM block diagram . . . . .1861
43.4.2LPTIM pins and internal signals . . . . .1863
43.4.3LPTIM input and trigger mapping . . . . .1863
43.4.4LPTIM reset and clocks . . . . .1866
43.4.5Glitch filter . . . . .1866
43.4.6Prescaler . . . . .1867
43.4.7Trigger multiplexer . . . . .1868
43.4.8Operating mode . . . . .1868
43.4.9Timeout function . . . . .1870
43.4.10Waveform generation . . . . .1870
43.4.11Register update . . . . .1871
43.4.12Counter mode . . . . .1872
43.4.13Timer enable . . . . .1872
43.4.14Timer counter reset . . . . .1873
43.4.15Encoder mode . . . . .1873
43.4.16Debug mode . . . . .1875
43.5LPTIM low-power modes . . . . .1875
43.6LPTIM interrupts . . . . .1876
43.7LPTIM registers . . . . .1876
43.7.1LPTIM interrupt and status register (LPTIM_ISR) . . . . .1877
43.7.2LPTIM interrupt clear register (LPTIM_ICR) . . . . .1878
43.7.3LPTIM interrupt enable register (LPTIM_IER) . . . . .1878
43.7.4LPTIM configuration register (LPTIM_CFGR) . . . . .1879
43.7.5LPTIM control register (LPTIM_CR) . . . . .1882
43.7.6LPTIM compare register (LPTIM_CMP) . . . . .1884
43.7.7LPTIM autoreload register (LPTIM_ARR) . . . . .1884
43.7.8LPTIM counter register (LPTIM_CNT) . . . . .1885
43.7.9LPTIM configuration register 2 (LPTIM_CFGR2) . . . . .1885
43.7.10LPTIM3 configuration register 2 (LPTIM3_CFGR2) . . . . .1886
43.7.11LPTIM register map . . . . .1887
44System window watchdog (WWDG) . . . . .1888
44.1Introduction . . . . .1888
46.2RTC main features . . . . .1905
46.3RTC functional description . . . . .1905
46.3.1RTC block diagram . . . . .1905
46.3.2RTC pins and internal signals . . . . .1908
46.3.3GPIOs controlled by the RTC . . . . .1908
46.3.4Clock and prescalers . . . . .1910
46.3.5Real-time clock and calendar . . . . .1911
46.3.6Programmable alarms . . . . .1911
46.3.7Periodic auto-wake-up . . . . .1911
46.3.8RTC initialization and configuration . . . . .1912
46.3.9Reading the calendar . . . . .1914
46.3.10Resetting the RTC . . . . .1915
46.3.11RTC synchronization . . . . .1915
46.3.12RTC reference clock detection . . . . .1916
46.3.13RTC smooth digital calibration . . . . .1916
46.3.14Time-stamp function . . . . .1918
46.3.15Tamper detection . . . . .1919
46.3.16Calibration clock output . . . . .1921
46.3.17Alarm output . . . . .1922
46.4RTC low-power modes . . . . .1922
46.5RTC interrupts . . . . .1922
46.6RTC registers . . . . .1923
46.6.1RTC time register (RTC_TR) . . . . .1923
46.6.2RTC date register (RTC_DR) . . . . .1924
46.6.3RTC control register (RTC_CR) . . . . .1926
46.6.4RTC initialization and status register (RTC_ISR) . . . . .1929
46.6.5RTC prescaler register (RTC_PRER) . . . . .1932
46.6.6RTC wake-up timer register (RTC_WUTR) . . . . .1933
46.6.7RTC alarm A register (RTC_ALRMAR) . . . . .1934
46.6.8RTC alarm B register (RTC_ALRMBR) . . . . .1935
46.6.9RTC write protection register (RTC_WPR) . . . . .1936
46.6.10RTC sub second register (RTC_SSR) . . . . .1936
46.6.11RTC shift control register (RTC_SHIFTR) . . . . .1937
46.6.12RTC timestamp time register (RTC_TSTR) . . . . .1938
46.6.13RTC timestamp date register (RTC_TSDR) . . . . .1939
46.6.14RTC time-stamp sub second register (RTC_TSSSR) . . . . .1940
46.6.15RTC calibration register (RTC_CALR) . . . . .1941
46.6.16RTC tamper configuration register (RTC_TAMPCR) . . . . .1942
46.6.17RTC alarm A sub second register (RTC_ALRMASSR) . . . . .1945
46.6.18RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .1946
46.6.19RTC option register (RTC_OR) . . . . .1947
46.6.20RTC backup registers (RTC_BKPxR) . . . . .1947
46.6.21RTC register map . . . . .1948
47Inter-integrated circuit (I2C) interface . . . . .1950
47.1Introduction . . . . .1950
47.2I2C main features . . . . .1950
47.3I2C implementation . . . . .1951
47.4I2C functional description . . . . .1951
47.4.1I2C block diagram . . . . .1952
47.4.2I2C pins and internal signals . . . . .1953
47.4.3I2C clock requirements . . . . .1953
47.4.4Mode selection . . . . .1953
47.4.5I2C initialization . . . . .1954
47.4.6Software reset . . . . .1959
47.4.7Data transfer . . . . .1960
47.4.8I2C slave mode . . . . .1962
47.4.9I2C master mode . . . . .1971
47.4.10I2C_TIMINGR register configuration examples . . . . .1982
47.4.11SMBus specific features . . . . .1984
47.4.12SMBus initialization . . . . .1987
47.4.13SMBus: I2C_TIMEOUTR register configuration examples . . . . .1989
47.4.14SMBus slave mode . . . . .1989
47.4.15Wake-up from Stop mode on address match . . . . .1996
47.4.16Error conditions . . . . .1997
47.4.17DMA requests . . . . .1999
47.4.18Debug mode . . . . .1999
47.5I2C low-power modes . . . . .2000
47.6I2C interrupts . . . . .2001
47.7I2C registers . . . . .2003
47.7.1I2C control register 1 (I2C_CR1) . . . . .2003
47.7.2I2C control register 2 (I2C_CR2) . . . . .2006
47.7.3I2C own address 1 register (I2C_OAR1) . . . . .2008
47.7.4I2C own address 2 register (I2C_OAR2) . . . . .2008
47.7.5I2C timing register (I2C_TIMINGR) . . . . .2009
47.7.6I2C timeout register (I2C_TIMEOUTR) . . . . .2010
47.7.7I2C interrupt and status register (I2C_ISR) . . . . .2011
47.7.8I2C interrupt clear register (I2C_ICR) . . . . .2014
47.7.9I2C PEC register (I2C_PECR) . . . . .2015
47.7.10I2C receive data register (I2C_RXDR) . . . . .2015
47.7.11I2C transmit data register (I2C_TXDR) . . . . .2016
47.7.12I2C register map . . . . .2016
48Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .2018
48.1USART introduction . . . . .2018
48.2USART main features . . . . .2019
48.3USART extended features . . . . .2020
48.4USART implementation . . . . .2020
48.5USART functional description . . . . .2021
48.5.1USART block diagram . . . . .2021
48.5.2USART signals . . . . .2022
48.5.3USART character description . . . . .2023
48.5.4USART FIFOs and thresholds . . . . .2025
48.5.5USART transmitter . . . . .2025
48.5.6USART receiver . . . . .2029
48.5.7USART baud rate generation . . . . .2036
48.5.8Tolerance of the USART receiver to clock deviation . . . . .2037
48.5.9USART auto baud rate detection . . . . .2039
48.5.10USART multiprocessor communication . . . . .2041
48.5.11USART Modbus communication . . . . .2043
48.5.12USART parity control . . . . .2044
48.5.13USART LIN (local interconnection network) mode . . . . .2045
48.5.14USART synchronous mode . . . . .2047
48.5.15USART single-wire Half-duplex communication . . . . .2051
48.5.16USART receiver timeout . . . . .2051
48.5.17USART Smartcard mode . . . . .2052
48.5.18USART IrDA SIR ENDEC block . . . . .2056
48.5.19Continuous communication using USART and DMA . . . . .2059
48.5.20RS232 Hardware flow control and RS485 Driver Enable . . . . .2061
48.5.21USART low-power management . . . . .2064
48.6USART in low-power modes . . . . .2067
48.7USART interrupts . . . . .2068
48.8USART registers . . . . .2069
48.8.1USART control register 1 (USART_CR1) . . . . .2069
48.8.2USART control register 1 [alternate] (USART_CR1) . . . . .2073
48.8.3USART control register 2 (USART_CR2) . . . . .2076
48.8.4USART control register 3 (USART_CR3) . . . . .2080
48.8.5USART baud rate register (USART_BRR) . . . . .2085
48.8.6USART guard time and prescaler register (USART_GTPR) . . . . .2085
48.8.7USART receiver timeout register (USART_RTOR) . . . . .2086
48.8.8USART request register (USART_RQR) . . . . .2087
48.8.9USART interrupt and status register (USART_ISR) . . . . .2088
48.8.10USART interrupt and status register [alternate] (USART_ISR) . . . . .2094
48.8.11USART interrupt flag clear register (USART_ICR) . . . . .2099
48.8.12USART receive data register (USART_RDR) . . . . .2101
48.8.13USART transmit data register (USART_TDR) . . . . .2101
48.8.14USART prescaler register (USART_PRESC) . . . . .2102
48.8.15USART register map . . . . .2103
49Low-power universal asynchronous receiver transmitter (LPUART) . . . . .2105
49.1LPUART introduction . . . . .2105
49.2LPUART main features . . . . .2106
49.3LPUART implementation . . . . .2107
49.4LPUART functional description . . . . .2108
49.4.1LPUART block diagram . . . . .2108
49.4.2LPUART signals . . . . .2109
49.4.3LPUART character description . . . . .2109
49.4.4LPUART FIFOs and thresholds . . . . .2110
49.4.5LPUART transmitter . . . . .2111
49.4.6LPUART receiver . . . . .2114
49.4.7LPUART baud rate generation . . . . .2118
49.4.8Tolerance of the LPUART receiver to clock deviation . . . . .2119
49.4.9LPUART multiprocessor communication . . . . .2120
49.4.10LPUART parity control . . . . .2122
49.4.11LPUART single-wire Half-duplex communication . . . . .2123
49.4.12Continuous communication using DMA and LPUART . . . . .2123
49.4.13RS232 Hardware flow control and RS485 Driver Enable . . . . .2126
49.4.14LPUART low-power management . . . . .2128
49.5LPUART in low-power modes . . . . .2131
49.6LPUART interrupts . . . . .2132
49.7LPUART registers . . . . .2133
49.7.1LPUART control register 1 (LPUART_CR1) . . . . .2133
49.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .2136
49.7.3LPUART control register 2 (LPUART_CR2) . . . . .2139
49.7.4LPUART control register 3 (LPUART_CR3) . . . . .2141
49.7.5LPUART baud rate register (LPUART_BRR) . . . . .2144
49.7.6LPUART request register (LPUART_RQR) . . . . .2145
49.7.7LPUART interrupt and status register (LPUART_ISR) . . . . .2145
49.7.8LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .2150
49.7.9LPUART interrupt flag clear register (LPUART_ICR) . . . . .2153
49.7.10LPUART receive data register (LPUART_RDR) . . . . .2154
49.7.11LPUART transmit data register (LPUART_TDR) . . . . .2154
49.7.12LPUART prescaler register (LPUART_PRESC) . . . . .2155
49.7.13LPUART register map . . . . .2156
50Serial peripheral interface (SPI) . . . . .2158
50.1Introduction . . . . .2158
50.2SPI main features . . . . .2158
50.3SPI implementation . . . . .2159
50.4SPI functional description . . . . .2159
50.4.1SPI block diagram . . . . .2159
50.4.2SPI signals . . . . .2161
50.4.3SPI communication general aspects . . . . .2161
50.4.4Communications between one master and one slave . . . . .2161
50.4.5Standard multislave communication . . . . .2164
50.4.6Multimaster communication . . . . .2167
50.4.7Slave select (SS) pin management . . . . .2167
50.4.8Communication formats . . . . .2171
50.4.9Configuration of SPI . . . . .2173
50.11.6SPI/I2S status register (SPI_SR) . . . . .2225
50.11.7SPI/I2S interrupt/status flags clear register (SPI_IFCR) . . . . .2228
50.11.8SPI/I2S transmit data register (SPI_TXDR) . . . . .2229
50.11.9SPI/I2S receive data register (SPI_RXDR) . . . . .2229
50.11.10SPI polynomial register (SPI_CRCPOLY) . . . . .2230
50.11.11SPI transmitter CRC register (SPI_TXCRC) . . . . .2230
50.11.12SPI receiver CRC register (SPI_RXCRC) . . . . .2231
50.11.13SPI underrun data register (SPI_UDRDR) . . . . .2232
50.11.14SPI/I2S configuration register (SPI_I2SCFGR) . . . . .2232
50.12SPI register map and reset values . . . . .2235
51Serial audio interface (SAI) . . . . .2237
51.1Introduction . . . . .2237
51.2SAI main features . . . . .2237
51.3SAI implementation . . . . .2238
51.4SAI functional description . . . . .2238
51.4.1SAI block diagram . . . . .2238
51.4.2SAI pins and internal signals . . . . .2240
51.4.3Main SAI modes . . . . .2240
51.4.4SAI synchronization mode . . . . .2241
51.4.5Audio data size . . . . .2242
51.4.6Frame synchronization . . . . .2243
51.4.7Slot configuration . . . . .2246
51.4.8SAI clock generator . . . . .2248
51.4.9Internal FIFOs . . . . .2250
51.4.10PDM interface . . . . .2252
51.4.11AC'97 link controller . . . . .2260
51.4.12SPDIF output . . . . .2262
51.4.13Specific features . . . . .2265
51.4.14Error flags . . . . .2269
51.4.15Disabling the SAI . . . . .2272
51.4.16SAI DMA interface . . . . .2272
51.5SAI interrupts . . . . .2273
51.6SAI registers . . . . .2274
51.6.1SAI global configuration register (SAI_GCR) . . . . .2274
51.6.2SAI configuration register 1 (SAI_ACR1) . . . . .2275
51.6.3SAI configuration register 1 (SAI_BCR1) . . . . .2277
51.6.4SAI configuration register 2 (SAI_ACR2) . . . . .2280
51.6.5SAI configuration register 2 (SAI_BCR2) . . . . .2282
51.6.6SAI frame configuration register (SAI_AFRCR) . . . . .2284
51.6.7SAI frame configuration register (SAI_BFRCR) . . . . .2286
51.6.8SAI slot register (SAI_ASLOTR) . . . . .2287
51.6.9SAI slot register (SAI_BSLOTR) . . . . .2288
51.6.10SAI interrupt mask register (SAI_AIM) . . . . .2289
51.6.11SAI interrupt mask register (SAI_BIM) . . . . .2291
51.6.12SAI status register (SAI_ASR) . . . . .2292
51.6.13SAI status register (SAI_BSR) . . . . .2294
51.6.14SAI clear flag register (SAI_ACLRFR) . . . . .2296
51.6.15SAI clear flag register (SAI_BCLRFR) . . . . .2297
51.6.16SAI data register (SAI_ADR) . . . . .2298
51.6.17SAI data register (SAI_BDR) . . . . .2299
51.6.18SAI PDM control register (SAI_PDMCR) . . . . .2299
51.6.19SAI PDM delay register (SAI_PDMDLY) . . . . .2301
51.6.20SAI register map . . . . .2303
52SPDIF receiver interface (SPDIFRX) . . . . .2305
52.1SPDIFRX interface introduction . . . . .2305
52.2SPDIFRX main features . . . . .2305
52.3SPDIFRX functional description . . . . .2305
52.3.1SPDIFRX pins and internal signals . . . . .2306
52.3.2S/PDIF protocol (IEC-60958) . . . . .2307
52.3.3SPDIFRX decoder (SPDIFRX_DC) . . . . .2309
52.3.4SPDIFRX tolerance to clock deviation . . . . .2313
52.3.5SPDIFRX synchronization . . . . .2313
52.3.6SPDIFRX handling . . . . .2315
52.3.7Data reception management . . . . .2317
52.3.8Dedicated control flow . . . . .2319
52.3.9Reception errors . . . . .2320
52.3.10Clocking strategy . . . . .2322
52.3.11DMA interface . . . . .2322
52.3.12Interrupt generation . . . . .2323
52.3.13Register protection . . . . .2324
52.4Programming procedures . . . . .2325
52.4.1Initialization phase . . . . .2325
52.4.2Handling of interrupts coming from SPDIFRX . . . . .2326
52.4.3Handling of interrupts coming from DMA . . . . .2326
52.5SPDIFRX interface registers . . . . .2327
52.5.1SPDIFRX control register (SPDIFRX_CR) . . . . .2327
52.5.2SPDIFRX interrupt mask register (SPDIFRX_IMR) . . . . .2329
52.5.3SPDIFRX status register (SPDIFRX_SR) . . . . .2330
52.5.4SPDIFRX interrupt flag clear register (SPDIFRX_IFCR) . . . . .2332
52.5.5SPDIFRX data input register (SPDIFRX_FMT0_DR) . . . . .2333
52.5.6SPDIFRX data input register (SPDIFRX_FMT1_DR) . . . . .2333
52.5.7SPDIFRX data input register (SPDIFRX_FMT2_DR) . . . . .2334
52.5.8SPDIFRX channel status register (SPDIFRX_CSR) . . . . .2335
52.5.9SPDIFRX debug information register (SPDIFRX_DIR) . . . . .2335
52.5.10SPDIFRX interface register map . . . . .2336
53Single wire protocol master interface (SWPMI) . . . . .2337
53.1Introduction . . . . .2337
53.2SWPMI main features . . . . .2338
53.3SWPMI functional description . . . . .2339
53.3.1SWPMI block diagram . . . . .2339
53.3.2SWPMI pins and internal signals . . . . .2339
53.3.3SWP initialization and activation . . . . .2340
53.3.4SWP bus states . . . . .2341
53.3.5SWPMI_IO (internal transceiver) bypass . . . . .2342
53.3.6SWPMI bit rate . . . . .2342
53.3.7SWPMI frame handling . . . . .2343
53.3.8Transmission procedure . . . . .2343
53.3.9Reception procedure . . . . .2348
53.3.10Error management . . . . .2352
53.3.11Loopback mode . . . . .2354
53.4SWPMI low-power modes . . . . .2354
53.5SWPMI interrupts . . . . .2355
53.6SWPMI registers . . . . .2356
53.6.1SWPMI configuration/control register (SWPMI_CR) . . . . .2356
53.6.2SWPMI Bitrate register (SWPMI_BRR) . . . . .2357
53.6.3SWPMI Interrupt and Status register (SWPMI_ISR) . . . . .2358
53.6.4SWPMI Interrupt Flag Clear register (SWPMI_ICR) . . . . .2359
53.6.5SWPMI Interrupt Enable register (SWPMI_IER) . . . . .2360
53.6.6SWPMI Receive Frame Length register (SWPMI_RFL) . . . . .2362
53.6.7SWPMI Transmit data register (SWPMI_TDR) . . . . .2362
53.6.8SWPMI Receive data register (SWPMI_RDR) . . . . .2362
53.6.9SWPMI Option register (SWPMI_OR) . . . . .2363
53.6.10SWPMI register map and reset value table . . . . .2364
54Management data input/output (MDIOS) . . . . .2365
54.1MDIOS introduction . . . . .2365
54.2MDIOS main features . . . . .2365
54.3MDIOS functional description . . . . .2366
54.3.1MDIOS block diagram . . . . .2366
54.3.2MDIOS pins and internal signals . . . . .2366
54.3.3MDIOS protocol . . . . .2366
54.3.4MDIOS enabling and disabling . . . . .2367
54.3.5MDIOS data . . . . .2368
54.3.6MDIOS APB frequency . . . . .2369
54.3.7Write/read flags and interrupts . . . . .2369
54.3.8MDIOS error management . . . . .2370
54.3.9MDIOS in Stop mode . . . . .2371
54.3.10MDIOS interrupts . . . . .2371
54.4MDIOS registers . . . . .2371
54.4.1MDIOS configuration register (MDIOS_CR) . . . . .2371
54.4.2MDIOS write flag register (MDIOS_WRFR) . . . . .2372
54.4.3MDIOS clear write flag register (MDIOS_CWRFR) . . . . .2373
54.4.4MDIOS read flag register (MDIOS_RDFR) . . . . .2373
54.4.5MDIOS clear read flag register (MDIOS_CRDFR) . . . . .2374
54.4.6MDIOS status register (MDIOS_SR) . . . . .2374
54.4.7MDIOS clear flag register (MDIOS_CLRFR) . . . . .2375
54.4.8MDIOS input data register x (MDIOS_DINRx) . . . . .2375
54.4.9MDIOS output data register x (MDIOS_DOUTRx) . . . . .2376
54.4.10MDIOS register map . . . . .2376
55Secure digital input/output MultiMediaCard interface (SDMMC) . . .2378
55.1SDMMC main features . . . . .2378
55.2SDMMC implementation . . . . .2378
55.3SDMMC bus topology . . . . .2379
55.4SDMMC operation modes . . . . .2381
55.5SDMMC functional description . . . . .2382
55.5.1SDMMC block diagram . . . . .2382
55.5.2SDMMC pins and internal signals . . . . .2382
55.5.3General description . . . . .2383
55.5.4SDMMC adapter . . . . .2385
55.5.5SDMMC AHB slave interface . . . . .2407
55.5.6SDMMC AHB master interface . . . . .2407
55.5.7MDMA request generation . . . . .2409
55.5.8AHB and SDMMC_CK clock relation . . . . .2410
55.6Card functional description . . . . .2411
55.6.1SD I/O mode . . . . .2411
55.6.2CMD12 send timing . . . . .2419
55.6.3Sleep (CMD5) . . . . .2422
55.6.4Interrupt mode (Wait-IRQ) . . . . .2423
55.6.5Boot operation . . . . .2424
55.6.6Response R1b handling . . . . .2427
55.6.7Reset and card cycle power . . . . .2428
55.7Hardware flow control . . . . .2429
55.8Ultra-high-speed phase I (UHS-I) voltage switch . . . . .2430
55.9SDMMC interrupts . . . . .2433
55.10SDMMC registers . . . . .2435
55.10.1SDMMC power control register (SDMMC_POWER) . . . . .2435
55.10.2SDMMC clock control register (SDMMC_CLKCR) . . . . .2436
55.10.3SDMMC argument register (SDMMC_ARGR) . . . . .2438
55.10.4SDMMC command register (SDMMC_CMDR) . . . . .2438
55.10.5SDMMC command response register (SDMMC_RESPCMDR) . . . . .2440
55.10.6SDMMC response x register (SDMMC_RESPxR) . . . . .2441
55.10.7SDMMC data timer register (SDMMC_TIMER) . . . . .2441
55.10.8SDMMC data length register (SDMMC_DLENR) . . . . .2442
55.10.9SDMMC data control register (SDMMC_DCTRL) . . . . .2443
55.10.10SDMMC data counter register (SDMMC_DCNTR) . . . . .2444
55.10.11SDMMC status register (SDMMC_STAR) . . . . .2445
55.10.12SDMMC interrupt clear register (SDMMC_ICR) . . . . .2448
55.10.13SDMMC mask register (SDMMC_MASKR) . . . . .2450
55.10.14SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . .2453
55.10.15SDMMC data FIFO registers x (SDMMC_FIFORx) . . . . .2453
55.10.16SDMMC DMA control register (SDMMC_IDMACTRLR) . . . . .2454
55.10.17SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) . . . . .2455
55.10.18SDMMC IDMA buffer 0 base address register
(SDMMC_IDMABASE0R) . . . . .		2455
55.10.19SDMMC IDMA buffer 1 base address register
(SDMMC_IDMABASE1R) . . . . .		2456
55.10.20SDMMC register map . . . . .2456
56Controller area network with flexible data rate (FDCAN) . . . . .2459
56.1Introduction . . . . .2459
56.2FDCAN main features . . . . .2462
56.3FDCAN implementation . . . . .2462
56.4FDCAN functional description . . . . .2463
56.4.1Operating modes . . . . .2464
56.4.2Message RAM . . . . .2473
56.4.3FIFO acknowledge handling . . . . .2484
56.4.4Bit timing . . . . .2485
56.4.5Clock calibration on CAN . . . . .2486
56.4.6Application . . . . .2490
56.4.7TTCAN operations (FDCAN1 only) . . . . .2491
56.4.8TTCAN configuration . . . . .2492
56.4.9Message scheduling . . . . .2494
56.4.10TTCAN gap control . . . . .2501
56.4.11Stop watch . . . . .2502
56.4.12Local time, cycle time, global time,
and external clock synchronization . . . . .		2502
56.4.13TTCAN error level . . . . .2505
56.4.14TTCAN message handling . . . . .2506
56.4.15TTCAN interrupt and error handling . . . . .2509
56.4.16Level 0 . . . . .2510
56.4.17Synchronization to external time schedule . . . . .2512
56.4.18FDCAN Rx buffer and FIFO element . . . . .2513
56.4.19FDCAN Tx buffer element . . . . .2515
56.4.20FDCAN Tx event FIFO element . . . . .2517
56.4.21FDCAN standard message ID filter element . . . . .2518
56.4.22FDCAN extended message ID filter element . . . . .2520
56.4.23FDCAN trigger memory element . . . . .2521
56.5FDCAN registers . . . . .2523
56.5.1FDCAN core release register (FDCAN_CREL) . . . . .2523
56.5.2FDCAN Endian register (FDCAN_ENDN) . . . . .2523
56.5.3FDCAN data bit timing and prescaler register (FDCAN_DBTP) . . . . .2524
56.5.4FDCAN test register (FDCAN_TEST) . . . . .2525
56.5.5FDCAN RAM watchdog register (FDCAN_RWD) . . . . .2525
56.5.6FDCAN CC control register (FDCAN_CCCR) . . . . .2526
56.5.7FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . . . . .2528
56.5.8FDCAN timestamp counter configuration register (FDCAN_TSCC) . . . . .2529
56.5.9FDCAN timestamp counter value register (FDCAN_TSCV) . . . . .2530
56.5.10FDCAN timeout counter configuration register (FDCAN_TOCC) . . . . .2530
56.5.11FDCAN timeout counter value register (FDCAN_TOCV) . . . . .2531
56.5.12FDCAN error counter register (FDCAN_ECR) . . . . .2532
56.5.13FDCAN protocol status register (FDCAN_PSR) . . . . .2532
56.5.14FDCAN transmitter delay compensation register (FDCAN_TDCR) . . . . .2534
56.5.15FDCAN interrupt register (FDCAN_IR) . . . . .2535
56.5.16FDCAN interrupt enable register (FDCAN_IE) . . . . .2538
56.5.17FDCAN interrupt line select register (FDCAN_ILS) . . . . .2540
56.5.18FDCAN interrupt line enable register (FDCAN_ILE) . . . . .2541
56.5.19FDCAN global filter configuration register (FDCAN_GFC) . . . . .2542
56.5.20FDCAN standard ID filter configuration register (FDCAN_SIDFC) . . . . .2543
56.5.21FDCAN extended ID filter configuration register (FDCAN_XIDFC) . . . . .2543
56.5.22FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . .2544
56.5.23FDCAN high priority message status register (FDCAN_HPMS) . . . . .2545
56.5.24FDCAN new data 1 register (FDCAN_NDAT1) . . . . .2545
56.5.25FDCAN new data 2 register (FDCAN_NDAT2) . . . . .2546
56.5.26FDCAN Rx FIFO 0 configuration register (FDCAN_RXF0C) . . . . .2546
56.5.27FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . .2547
56.5.28FDCAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . .2548
56.5.29FDCAN Rx buffer configuration register (FDCAN_RXBC) . . . . .2548
56.5.30FDCAN Rx FIFO 1 configuration register (FDCAN_RXF1C) . . . . .2549
56.5.31FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . .2550
56.5.32FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . .2551
56.5.33FDCAN Rx buffer element size configuration register
(FDCAN_RXESC) . . . . .		2551
56.5.34FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . .2552
56.5.35FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . .2553
56.5.36FDCAN Tx buffer element size configuration register
(FDCAN_TXESC) . . . . .		2554
56.5.37FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . .2554
56.5.38FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . .2555
56.5.39FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . . . . .2556
56.5.40FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) . . . . .2556
56.5.41FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . . . . .2557
56.5.42FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE) . . . . .		2557
56.5.43FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_TXBCIE) . . . . .		2558
56.5.44FDCAN Tx event FIFO configuration register (FDCAN_TXEFC) . . . . .2558
56.5.45FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . .2559
56.5.46FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . . . .2560
56.5.47FDCAN register map . . . . .2560
56.6TTCAN registers . . . . .2564
56.6.1FDCAN TT trigger memory configuration register (FDCAN_TTTMC) . . . . .2564
56.6.2FDCAN TT reference message configuration register
(FDCAN_TTRMC) . . . . .		2564
56.6.3FDCAN TT operation configuration register (FDCAN_TTOCF) . . . . .2565
56.6.4FDCAN TT matrix limits register (FDCAN_TTMLM) . . . . .2567
56.6.5FDCAN TUR configuration register (FDCAN_TURCF) . . . . .2568
56.6.6FDCAN TT operation control register (FDCAN_TTOCN) . . . . .2569
56.6.7FDCAN TT global time preset register (FDCAN_TTGTP) . . . . .2571
56.6.8FDCAN TT time mark register (FDCAN_TTTMK) . . . . .2571
56.6.9FDCAN TT interrupt register (FDCAN_TTIR) . . . . .2572
56.6.10FDCAN TT interrupt enable register (FDCAN_TTIE) . . . . .2574
56.6.11FDCAN TT interrupt line select register (FDCAN_TTILS) . . . . .2576
56.6.12FDCAN TT operation status register (FDCAN_TTOST) . . . . .2577
56.6.13FDCAN TUR numerator actual register (FDCAN_TURNA) . . . . .2579
56.6.14FDCAN TT local and global time register (FDCAN_TTLGT) . . . . .2580
56.6.15FDCAN TT cycle time and count register (FDCAN_TTCTC) . . . . .2580
56.6.16FDCAN TT capture time register (FDCAN_TTCPT) . . . . .2581
56.6.17FDCAN TT cycle sync mark register (FDCAN_TTCSM) . . . . .2581
56.6.18FDCAN TT trigger select register (FDCAN_TTTS) . . . . .2582
56.6.19FDCAN TT register map . . . . .2582
56.7CCU registers . . . . .2584
56.7.1Clock calibration unit core release register (FDCAN_CCU_CREL) . . .2584
56.7.2Calibration configuration register (FDCAN_CCU_CCFG) . . . . .2584
56.7.3Calibration status register (FDCAN_CCU_CSTAT) . . . . .2586
56.7.4Calibration watchdog register (FDCAN_CCU_CWD) . . . . .2586
56.7.5Clock calibration unit interrupt register (FDCAN_CCU_IR) . . . . .2587
56.7.6Clock calibration unit interrupt enable register (FDCAN_CCU_IE) . . .2588
56.7.7CCU register map . . . . .2588
57USB on-the-go high-speed (OTG_HS) . . . . .2590
57.1Introduction . . . . .2590
57.2OTG_HS main features . . . . .2591
57.2.1General features . . . . .2591
57.2.2Host-mode features . . . . .2592
57.2.3Peripheral-mode features . . . . .2592
57.3OTG_HS implementation . . . . .2593
57.4OTG_HS functional description . . . . .2593
57.4.1OTG_HS block diagram . . . . .2593
57.4.2OTG_HS pin and internal signals . . . . .2595
57.4.3OTG_HS core . . . . .2595
57.4.4Embedded full-speed OTG PHY connected to OTG_HS . . . . .2596
57.4.5OTG detections . . . . .2596
57.4.6High-speed OTG PHY connected to OTG_HS . . . . .2596
57.5OTG_HS dual role device (DRD) . . . . .2597
57.5.1ID line detection . . . . .2597
57.5.2HNP dual role device . . . . .2597
57.5.3SRP dual role device . . . . .2598
57.6OTG_HS as a USB peripheral . . . . .2598
57.6.1SRP-capable peripheral . . . . .2599
57.6.2Peripheral states . . . . .2599
57.6.3Peripheral endpoints . . . . .2600
57.7OTG_HS as a USB host . . . . .2602
57.7.1SRP-capable host . . . . .2603
57.7.2USB host states . . . . .2603
57.7.3Host channels . . . . .2605
57.7.4Host scheduler . . . . .2606
57.8OTG_HS SOF trigger . . . . .2607
57.8.1Host SOFs2607
57.8.2Peripheral SOFs2607
57.9OTG_HS low-power modes2608
57.10OTG_HS Dynamic update of the OTG_HFIR register2609
57.11OTG_HS data FIFOs2609
57.11.1Peripheral FIFO architecture2610
57.11.2Host FIFO architecture2611
57.11.3FIFO RAM allocation2612
57.12OTG_HS interrupts2614
57.13OTG_HS control and status registers2616
57.13.1CSR memory map2616
57.14OTG_HS registers2621
57.14.1OTG control and status register (OTG_GOTGCTL)2621
57.14.2OTG interrupt register (OTG_GOTGINT)2624
57.14.3OTG AHB configuration register (OTG_GAHBCFG)2626
57.14.4OTG USB configuration register (OTG_GUSBCFG)2627
57.14.5OTG reset register (OTG_GRSTCTL)2630
57.14.6OTG core interrupt register (OTG_GINTSTS)2633
57.14.7OTG interrupt mask register (OTG_GINTMSK)2637
57.14.8OTG receive status debug read register (OTG_GRXSTSR)2641
57.14.9OTG receive status debug read [alternate] (OTG_GRXSTSR)2642
57.14.10OTG status read and pop registers (OTG_GRXSTSP)2643
57.14.11OTG status read and pop registers [alternate] (OTG_GRXSTSP)2644
57.14.12OTG receive FIFO size register (OTG_GRXFSIZ)2645
57.14.13OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0)		2645
57.14.14OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS)		2646
57.14.15OTG general core configuration register (OTG_GCCFG)2647
57.14.16OTG core ID register (OTG_CID)2649
57.14.17OTG core LPM configuration register (OTG_GLPMCFG)2649
57.14.18OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ)		2653
57.14.19OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx)		2653
57.14.20Host-mode registers2654
57.14.21OTG host configuration register (OTG_HCFG)2654
57.14.22OTG host frame interval register (OTG_HFIR) . . . . .2655
57.14.23OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . .		2656
57.14.24OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . .		2657
57.14.25OTG host all channels interrupt register (OTG_HAINT) . . . . .2658
57.14.26OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . .		2658
57.14.27OTG host frame list base address register
(OTG_HFLBADDR) . . . . .		2659
57.14.28OTG host port control and status register (OTG_HPRT) . . . . .2659
57.14.29OTG host channel x characteristics register (OTG_HCCHARx) . . . . .2662
57.14.30OTG host channel x split control register (OTG_HCSPLTx) . . . . .2663
57.14.31OTG host channel x interrupt register (OTG_HCINTx) . . . . .2664
57.14.32OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . . . .2665
57.14.33OTG host channel x transfer size register (OTG_HCTSIZx) . . . . .2667
57.14.34OTG host channel x transfer size register (OTG_HCTSIZSGx) . . . . .2668
57.14.35OTG host channel x DMA address register in buffer DMA [alternate]
(OTG_HCDMAx) . . . . .		2670
57.14.36OTG host channel x DMA address register in scatter/gather DMA
[alternate] (OTG_HCDMASGx) . . . . .		2670
57.14.37OTG host channel-n DMA address buffer register
(OTG_HCDMABx) . . . . .		2671
57.14.38Device-mode registers . . . . .2672
57.14.39OTG device configuration register (OTG_DCFG) . . . . .2672
57.14.40OTG device control register (OTG_DCTL) . . . . .2674
57.14.41OTG device status register (OTG_DSTS) . . . . .2676
57.14.42OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . .		2677
57.14.43OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . .		2678
57.14.44OTG device all endpoints interrupt register (OTG_DAINIT) . . . . .2679
57.14.45OTG all endpoints interrupt mask register
(OTG_DAINMSK) . . . . .		2680
57.14.46OTG device V BUS discharge time register
(OTG_DVBUSDIS) . . . . .		2681
57.14.47OTG device V BUS pulsing time register
(OTG_DVBUSPULSE) . . . . .		2681
57.14.48OTG device threshold control register (OTG_DTHRCTL) . . . . .2682
57.14.49OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) . . . . .		2683
57.14.50OTG device each endpoint interrupt register (OTG_DEACHINT)2683
57.14.51OTG device each endpoint interrupt mask register
(OTG_DEACHINTMSK)		2684
57.14.52OTG device each IN endpoint-1 interrupt mask register
(OTG_HS_DIEPEACHMSK1)		2684
57.14.53OTG device each OUT endpoint-1 interrupt mask register
(OTG_HS_DOEPEACHMSK1)		2685
57.14.54OTG device IN endpoint x control register (OTG_DIEPCTLx)2687
57.14.55OTG device IN endpoint x interrupt register (OTG_DIEPINTx)2689
57.14.56OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0)		2691
57.14.57OTG device IN endpoint x DMA address register
(OTG_DIEPDMAX)		2691
57.14.58OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx)		2692
57.14.59OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx)2692
57.14.60OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0)		2693
57.14.61OTG device OUT endpoint x interrupt register (OTG_DOEPINTx)2695
57.14.62OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0)		2697
57.14.63OTG device OUT endpoint x DMA address register
(OTG_DOEPDMAX)		2698
57.14.64OTG device OUT endpoint x control register
(OTG_DOEPCTLx)		2698
57.14.65OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx)		2701
57.14.66OTG power and clock gating control register (OTG_PCGCCTL)2702
57.14.67OTG_HS register map2703
57.15OTG_HS programming model2715
57.15.1Core initialization2715
57.15.2Host initialization2716
57.15.3Device initialization2717
57.15.4DMA mode2717
57.15.5Host programming model2718
57.15.6Device programming model2750
57.15.7Worst case response time2770
57.15.8OTG programming model2772
58Ethernet (ETH): media access control (MAC) with DMA controller . . . . .2778
58.1Ethernet introduction . . . . .2778
58.2Ethernet main features . . . . .2778
58.2.1Standard compliance . . . . .2778
58.2.2MAC features . . . . .2778
58.2.3Transaction layer (MTL) features . . . . .2780
58.2.4DMA block features . . . . .2781
58.2.5Bus interface features . . . . .2781
58.3Ethernet pins and internal signals . . . . .2782
58.4Ethernet architecture . . . . .2783
58.4.1DMA controller . . . . .2784
58.4.2MTL . . . . .2793
58.4.3MAC . . . . .2793
58.5)Ethernet functional description: MAC . . . . .2798
58.5.1Double VLAN processing . . . . .2798
58.5.2Source address and VLAN insertion, replacement, or deletion . . . . .2799
58.5.3Packet filtering . . . . .2801
58.5.4IEEE 1588 timestamp support . . . . .2807
58.5.5Checksum offload engine . . . . .2832
58.5.6TCP segmentation offload . . . . .2838
58.5.7IPv4 ARP offload . . . . .2844
58.5.8Loopback . . . . .2845
58.5.9Flow control . . . . .2846
58.5.10MAC management counters . . . . .2849
58.5.11Interrupts generated by the MAC . . . . .2851
58.5.12MAC and MMC register descriptions . . . . .2851
58.6Ethernet functional description: PHY interfaces . . . . .2852
58.6.1Station management agent (SMA) . . . . .2852
58.6.2Media independent interface (MII) . . . . .2859
58.6.3Reduced media independent interface (RMII) . . . . .2860
58.7Ethernet low-power modes . . . . .2864
58.7.1Low-power management . . . . .2864
58.7.2Energy Efficient Ethernet (EEE) . . . . .2870
58.8Ethernet interrupts . . . . .2875
58.8.1DMA interrupts . . . . .2875
59.4Arbitration . . . . .3059
59.4.1SFT option bit . . . . .3061
59.5Error handling . . . . .3061
59.5.1Bit error . . . . .3061
59.5.2Message error . . . . .3062
59.5.3Bit rising error (BRE) . . . . .3062
59.5.4Short bit period error (SBPE) . . . . .3062
59.5.5Long bit period error (LBPE) . . . . .3062
59.5.6Transmission error detection (TXERR) . . . . .3064
59.6HDMI-CEC interrupts . . . . .3065
59.7HDMI-CEC registers . . . . .3066
59.7.1CEC control register (CEC_CR) . . . . .3066
59.7.2CEC configuration register (CEC_CFGR) . . . . .3067
59.7.3CEC Tx data register (CEC_TXDR) . . . . .3069
59.7.4CEC Rx data register (CEC_RXDR) . . . . .3069
59.7.5CEC interrupt and status register (CEC_ISR) . . . . .3069
59.7.6CEC interrupt enable register (CEC_IER) . . . . .3071
59.7.7HDMI-CEC register map . . . . .3073
60Debug infrastructure . . . . .3074
60.1Introduction . . . . .3074
60.2Debug infrastructure features . . . . .3075
60.3Debug infrastructure functional description . . . . .3075
60.3.1Debug infrastructure block diagram . . . . .3075
60.3.2Debug infrastructure pins and internal signals . . . . .3076
60.3.3Debug infrastructure powering, clocking and reset . . . . .3077
60.4Debug access port functional description . . . . .3079
60.4.1Serial-wire and JTAG debug port (SWJ-DP) . . . . .3079
60.4.2Access ports . . . . .3093
60.5Trace and debug subsystem functional description . . . . .3099
60.5.1System ROM tables . . . . .3099
60.5.2Global timestamp generator (TSG) . . . . .3108
60.5.3Cross trigger interfaces (CTI) and matrix (CTM) . . . . .3115
60.5.4Trace funnel (CSTF) . . . . .3135
60.5.5Embedded trace FIFO (ETF) . . . . .3145
60.5.6Trace port interface unit (TPIU) . . . . .3167
60.5.7Serial wire output (SWO) and SWO trace funnel (SWTF) . . . . .3185
60.5.8Microcontroller debug unit (DBGMCU) . . . . .3208
60.6Cortex-M7 debug functional description . . . . .3214
60.6.1Cortex-M7 ROM tables . . . . .3215
60.6.2Cortex-M7 data watchpoint and trace unit (DWT) . . . . .3227
60.6.3Cortex-M7 instrumentation trace macrocell (ITM) . . . . .3240
60.6.4Cortex-M7 breakpoint unit (FPB) . . . . .3249
60.6.5Cortex-M7 embedded trace macrocell (ETM) . . . . .3257
60.6.6Cortex-M7 cross trigger interface (CTI) . . . . .3289
60.7References for debug infrastructure . . . . .3289
61Device electronic signature . . . . .3290
61.1Unique device ID register (96 bits) . . . . .3290
61.2Flash size . . . . .3292
61.3Package data register . . . . .3292
62Important security notice . . . . .3293
63Revision history . . . . .3294

List of tables

Table 1.Peripherals versus products . . . . .102
Table 2.Availability of security features . . . . .103
Table 3.Bus-master-to-bus-slave interconnect . . . . .104
Table 4.ASIB configuration . . . . .110
Table 5.AMIB configuration . . . . .111
Table 6.AXI interconnect register map and reset values . . . . .121
Table 7.Memory map and default device memory area attributes . . . . .130
Table 8.Register boundary addresses . . . . .132
Table 9.Boot modes . . . . .138
Table 10.RAMECC internal input/output signals . . . . .142
Table 11.ECC controller mapping . . . . .142
Table 12.RAMECC register map and reset values . . . . .147
Table 13.FLASH internal input/output signals . . . . .150
Table 14.Flash memory organization on STM32H750xB devices . . . . .153
Table 15.Flash memory organization on STM32H742xl/743xl/753xl devices . . . . .153
Table 16.Flash memory organization on STM32H742xG/743xG devices . . . . .154
Table 17.FLASH recommended number of wait states and programming delay . . . . .160
Table 18.FLASH parallelism parameter . . . . .164
Table 19.FLASH AXI interface memory map vs swapping option . . . . .170
Table 20.Flash register map vs swapping option . . . . .172
Table 21.Option byte organization . . . . .177
Table 22.Flash interface register protection summary . . . . .183
Table 23.RDP value vs readout protection level . . . . .184
Table 24.Protection vs RDP Level . . . . .186
Table 25.RDP transition and its effects . . . . .187
Table 26.Effect of low-power modes on the embedded flash memory . . . . .191
Table 27.Flash interrupt request . . . . .199
Table 28.Register map and reset value table . . . . .241
Table 29.List of preferred terms . . . . .246
Table 30.RSS API addresses . . . . .250
Table 31.Summary of flash protected areas access rights . . . . .252
Table 32.PWR input/output signals connected to package pins or balls . . . . .256
Table 33.PWR internal input/output signals . . . . .256
Table 34.Supply configuration control . . . . .260
Table 35.Low-power mode summary . . . . .278
Table 36.PDDS_Dn low-power mode control . . . . .282
Table 37.Low-power exit mode flags . . . . .284
Table 38.CSleep mode . . . . .293
Table 39.CStop mode . . . . .294
Table 40.DStop mode overview . . . . .295
Table 41.DStop mode . . . . .296
Table 42.Stop mode operation . . . . .297
Table 43.Stop mode . . . . .298
Table 44.DStandby mode . . . . .299
Table 45.Standby and Stop flags . . . . .301
Table 46.Standby mode . . . . .301
Table 47.Low-power modes monitoring pin overview . . . . .302
Table 48.GPIO state according to CPU and domain state . . . . .302
Table 49.Power control register map and reset values . . . . .312
Table 50.BDMA and DMAMUX2 initialization sequence (DMAMUX2_INIT) . . . . .320
Table 51.LPUART1 Initial programming (LPUART1_INIT) . . . . .322
Table 52.LPUART1 start programming (LPUART1_Start) . . . . .322
Table 53.RCC input/output signals connected to package pins or balls . . . . .326
Table 54.RCC internal input/output signals . . . . .327
Table 55.Reset distribution summary . . . . .330
Table 56.Reset source identification (RCC_RSR) . . . . .332
Table 57.Ratio between clock timer and pclk . . . . .350
Table 58.STOPWUCK and STOPKERWUCK description . . . . .351
Table 59.HSIKERON and CSIKERON behavior . . . . .352
Table 60.Kernel clock distribution overview . . . . .354
Table 61.System states overview . . . . .369
Table 62.Peripheral clock enabling for D1 and D2 peripherals . . . . .375
Table 63.Peripheral clock enabling for D3 peripherals . . . . .376
Table 64.Interrupt sources and control . . . . .380
Table 65.RCC_RSR address offset and reset value . . . . .449
Table 66.RCC_AHB3ENR address offset and reset value . . . . .451
Table 67.RCC_AHB1ENR address offset and reset value . . . . .453
Table 68.RCC_AHB2ENR address offset and reset value . . . . .455
Table 69.RCC_AHB4ENR address offset and reset value . . . . .457
Table 70.RCC_APB3ENR address offset and reset value . . . . .460
Table 71.RCC_APB1ENR address offset and reset value . . . . .461
Table 72.RCC_APB1ENR address offset and reset value . . . . .465
Table 73.RCC_APB2ENR address offset and reset value . . . . .467
Table 74.RCC_APB4ENR address offset and reset value . . . . .470
Table 75.RCC_AHB3LPENR address offset and reset value . . . . .473
Table 76.RCC_AHB1LPENR address offset and reset value . . . . .475
Table 77.RCC_AHB2LPENR address offset and reset value . . . . .477
Table 78.RCC_AHB4LPENR address offset and reset value . . . . .479
Table 79.RCC_APB3LPENR address offset and reset value . . . . .482
Table 80.RCC_APB1LLPENR address offset and reset value . . . . .483
Table 81.RCC_APB1HLPENR address offset and reset value . . . . .487
Table 82.RCC_APB2LPENR address offset and reset value . . . . .489
Table 83.RCC_APB4LPENR address offset and reset value . . . . .492
Table 84.RCC register map and reset values . . . . .495
Table 85.CRS features . . . . .505
Table 86.CRS internal input/output signals . . . . .506
Table 87.Effect of low-power modes on CRS . . . . .510
Table 88.Interrupt control bits . . . . .510
Table 89.CRS register map and reset values . . . . .515
Table 90.HSEM internal input/output signals . . . . .518
Table 91.Authorized AHB bus master ID . . . . .523
Table 92.HSEM register map and reset values . . . . .529
Table 93.Port bit configuration table . . . . .532
Table 94.GPIO register map and reset values . . . . .546
Table 95.SYSCFG register map and reset values . . . . .572
Table 96.Peripherals interconnect matrix (D2 domain) . . . . .576
Table 97.Peripherals interconnect matrix (D3 domain) . . . . .577
Table 98.Peripherals interconnect matrix details . . . . .578
Table 99.EXTI wakeup inputs . . . . .595
Table 100.EXTI pending requests clear inputs . . . . .598
Table 101.MDMA600
Table 102.DMAMUX1, DMA1 and DMA2 connections602
Table 103.DMAMUX2 and BDMA connections607
Table 104.MDMA internal input/output signals612
Table 105.MDMA interrupt requests618
Table 106.MDMA register map and reset values634
Table 107.DMA internal input/output signals637
Table 108.Source and destination address639
Table 109.Source and destination address registers in double-buffer mode (DBM = 1)645
Table 110.Packing/unpacking and endian behavior (bit PINC = MINC = 1)646
Table 111.Restriction on NDT versus PSIZE and MSIZE646
Table 112.FIFO threshold configurations649
Table 113.Possible DMA configurations653
Table 114.DMA interrupt requests655
Table 115.DMA register map and reset values665
Table 116.BDMA implementation670
Table 117.BDMA internal input/output signals671
Table 118.Programmable data width and endian behavior (when PINC = MINC = 1)677
Table 119.BDMA interrupt requests679
Table 120.BDMA register map and reset values689
Table 121.DMAMUX1 and DMAMUX2 instantiation693
Table 122.DMAMUX1: assignment of multiplexer inputs to resources694
Table 123.DMAMUX1: assignment of multiplexer inputs to resources695
Table 124.DMAMUX1: assignment of trigger inputs to resources696
Table 125.DMAMUX1: assignment of synchronization inputs to resources696
Table 126.DMAMUX2: assignment of multiplexer inputs to resources697
Table 127.DMAMUX2: assignment of trigger inputs to resources697
Table 128.DMAMUX2: assignment of synchronization inputs to resources698
Table 129.DMAMUX signals700
Table 130.DMAMUX interrupts704
Table 131.DMAMUX register map and reset values713
Table 132.DMA2D internal input/output signals717
Table 133.Supported color mode in input718
Table 134.Data order in memory719
Table 135.Alpha mode configuration720
Table 136.Supported CLUT color mode721
Table 137.CLUT data order in memory721
Table 138.Supported color mode in output722
Table 139.Data order in memory722
Table 140.Standard data order in memory723
Table 141.Output FIFO byte reordering steps724
Table 142.MCU order in memory729
Table 143.DMA2D interrupt requests730
Table 144.DMA2D register map and reset values747
Table 145.NVIC750
Table 146.EXTI Event input configurations and register control760
Table 147.Configurable Event input Asynchronous Edge detector reset762
Table 148.EXTI Event input mapping767
Table 149.Masking functionality769
Table 150.Asynchronous interrupt/event controller register map and reset values787
Table 151.CRC internal input/output signals791
Table 152.CRC register map and reset values796
Table 153.FMC pins . . . . .800
Table 154.FMC bank mapping options . . . . .803
Table 155.NOR/PSRAM bank selection . . . . .803
Table 156.NOR/PSRAM External memory address . . . . .803
Table 157.NAND memory mapping and timing registers. . . . .804
Table 158.NAND bank selection . . . . .804
Table 159.SDRAM bank selection. . . . .804
Table 160.SDRAM address mapping . . . . .805
Table 161.SDRAM address mapping with 8-bit data bus width. . . . .805
Table 162.SDRAM address mapping with 16-bit data bus width. . . . .806
Table 163.SDRAM address mapping with 32-bit data bus width. . . . .807
Table 164.Programmable NOR/PSRAM access parameters . . . . .809
Table 165.Non-multiplexed I/O NOR flash memory. . . . .809
Table 166.16-bit multiplexed I/O NOR flash memory . . . . .810
Table 167.Non-multiplexed I/Os PSRAM/SRAM . . . . .810
Table 168.16-Bit multiplexed I/O PSRAM . . . . .810
Table 169.NOR flash/PSRAM: Example of supported memories
and transactions . . . . .		811
Table 170.FMC_BCRx bitfields (mode 1) . . . . .814
Table 171.FMC_BTRx bitfields (mode 1) . . . . .815
Table 172.FMC_BCRx bitfields (mode A) . . . . .817
Table 173.FMC_BTRx bitfields (mode A) . . . . .818
Table 174.FMC_BWTRx bitfields (mode A). . . . .818
Table 175.FMC_BCRx bitfields (mode 2/B). . . . .820
Table 176.FMC_BTRx bitfields (mode 2/B). . . . .821
Table 177.FMC_BWTRx bitfields (mode 2/B) . . . . .821
Table 178.FMC_BCRx bitfields (mode C) . . . . .823
Table 179.FMC_BTRx bitfields (mode C) . . . . .824
Table 180.FMC_BWTRx bitfields (mode C). . . . .824
Table 181.FMC_BCRx bitfields (mode D) . . . . .826
Table 182.FMC_BTRx bitfields (mode D) . . . . .826
Table 183.FMC_BWTRx bitfields (mode D). . . . .827
Table 184.FMC_BCRx bitfields (Muxed mode) . . . . .829
Table 185.FMC_BTRx bitfields (Muxed mode) . . . . .829
Table 186.FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .835
Table 187.FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .835
Table 188.FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .836
Table 189.FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .837
Table 190.Programmable NAND flash access parameters . . . . .847
Table 191.8-bit NAND flash memory . . . . .847
Table 192.16-bit NAND flash memory . . . . .848
Table 193.Supported memories and transactions . . . . .848
Table 194.ECC result relevant bits . . . . .858
Table 195.SDRAM signals. . . . .859
Table 196.FMC register map . . . . .876
Table 197.QUADSPI internal signals. . . . .880
Table 198.QUADSPI pins . . . . .880
Table 199.QUADSPI interrupt requests. . . . .894
Table 200.QUADSPI register map and reset values . . . . .906
Table 201.DLYB internal input/output signals . . . . .908
Table 202.Delay block control . . . . .908
Table 203.DLYB register map and reset values . . . . .911
Table 204.ADC features . . . . .914
Table 205.ADC input/output pins . . . . .916
Table 206.ADC internal input/output signals . . . . .916
Table 207.ADC interconnection . . . . .917
Table 208.Configuring the trigger polarity for regular external triggers . . . . .938
Table 209.Configuring the trigger polarity for injected external triggers . . . . .938
Table 210.ADC1, ADC2 and ADC3 - External triggers for regular channels . . . . .939
Table 211.ADC1, ADC2 and ADC3 - External triggers for injected channels . . . . .940
Table 212.TSAR timings depending on resolution . . . . .952
Table 213.Offset computation versus data resolution . . . . .955
Table 214.16-bit data formats . . . . .958
Table 215.Numerical examples for 16-bit format (bold indicates saturation) . . . . .958
Table 216.Analog watchdog channel selection . . . . .967
Table 217.Analog watchdog 1,2,3 comparison . . . . .968
Table 218.Oversampler operating modes summary . . . . .976
Table 219.ADC interrupts per each ADC . . . . .995
Table 220.DELAY bits versus ADC resolution . . . . .1037
Table 221.ADC global register map . . . . .1040
Table 222.ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) . . . . .1040
Table 223.ADC register map and reset values (master and slave ADC common registers) offset =0x300) . . . . .1043
Table 224.DAC features . . . . .1045
Table 225.DAC input/output pins . . . . .1047
Table 226.DAC internal input/output signals . . . . .1047
Table 227.DAC interconnection . . . . .1048
Table 228.Sample and refresh timings . . . . .1055
Table 229.Channel output modes summary . . . . .1056
Table 230.Effect of low-power modes on DAC . . . . .1062
Table 231.DAC interrupts . . . . .1063
Table 232.DAC register map and reset values . . . . .1079
Table 233.VREF buffer modes . . . . .1081
Table 234.VREFBUF register map and reset values . . . . .1083
Table 235.COMP input/output internal signals . . . . .1086
Table 236.COMP input/output pins . . . . .1086
Table 237.COMP1_OUT assignment to GPIOs . . . . .1089
Table 238.COMP2_OUT assignment to GPIOs . . . . .1089
Table 239.Comparator behavior in the low-power modes . . . . .1091
Table 240.Interrupt control bits . . . . .1091
Table 241.Interrupt control bits . . . . .1092
Table 242.COMP register map and reset values . . . . .1099
Table 243.Operational amplifier possible connections . . . . .1101
Table 244.Operating modes and calibration . . . . .1108
Table 245.Effect of low-power modes on the OPAMP . . . . .1110
Table 246.OPAMP register map and reset values . . . . .1117
Table 247.DFSDM1 implementation . . . . .1120
Table 248.DFSDM external pins . . . . .1122
Table 249.DFSDM internal signals . . . . .1122
Table 250.DFSDM triggers connection . . . . .1122
Table 251.DFSDM break connection . . . . .1123
Table 252.Filter maximum output resolution (peak data values from filter output) for some FOSR values . . . . .1138
Table 253.Integrator maximum output resolution (peak data values from integrator output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . .1139
Table 254.DFSDM interrupt requests . . . . .1147
Table 255.DFSDM register map and reset values. . . . .1167
Table 256.DCMI input/output pins . . . . .1178
Table 257.DCMI internal input/output signals . . . . .1178
Table 258.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .1180
Table 259.Positioning of captured data bytes in 32-bit words (10-bit width) . . . . .1180
Table 260.Positioning of captured data bytes in 32-bit words (12-bit width) . . . . .1180
Table 261.Positioning of captured data bytes in 32-bit words (14-bit width) . . . . .1181
Table 262.Data storage in monochrome progressive video format. . . . .1186
Table 263.Data storage in RGB progressive video format . . . . .1187
Table 264.Data storage in YCbCr progressive video format . . . . .1187
Table 265.Data storage in YCbCr progressive video format - Y extraction mode . . . . .1188
Table 266.DCMI interrupts. . . . .1188
Table 267.DCMI register map and reset values . . . . .1198
Table 268.LTDC external pins . . . . .1201
Table 269.LTDC internal signals . . . . .1202
Table 270.Clock domain for each register . . . . .1202
Table 271.LTDC register access and update durations . . . . .1203
Table 272.Pixel data mapping versus color format . . . . .1207
Table 273.LTDC interrupt requests . . . . .1211
Table 274.LTDC register map and reset values . . . . .1228
Table 275.JPEG internal signals . . . . .1232
Table 276.JPEG codec interrupt requests . . . . .1236
Table 277.JPEG codec register map and reset values . . . . .1249
Table 278.RNG internal input/output signals . . . . .1252
Table 279.RNG interrupt requests . . . . .1258
Table 280.RNG register map and reset map. . . . .1262
Table 281.CRYP internal input/output signals. . . . .1266
Table 282.Counter mode initialization vector. . . . .1291
Table 283.GCM last block definition . . . . .1294
Table 284.GCM mode IV registers initialization. . . . .1294
Table 285.CCM mode IV registers initialization. . . . .1301
Table 286.DES/TDES data swapping example. . . . .1305
Table 287.AES data swapping example . . . . .1306
Table 288.Key endianness in CRYP_KxR/LR registers (AES 128/192/256-bit keys) . . . . .1308
Table 289.Key endianness in CRYP_KxR/LR registers (DES K1 and TDES K1/2/3) . . . . .1308
Table 290.Initialization vector endianness in CRYP_IVx(L/R)R registers (AES) . . . . .1309
Table 291.Initialization vector endianness in CRYP_IVx(L/R)R registers (DES/TDES) . . . . .1309
Table 292.Cryptographic processor configuration for memory-to-peripheral DMA transfers . . . . .1309
Table 293.Cryptographic processor configuration for peripheral-to-memory DMA transfers . . . . .1310
Table 294.CRYP interrupt requests. . . . .1312
Table 295.Processing latency for ECB, CBC and CTR. . . . .1313
Table 296.Processing time (in clock cycle) for GCM and CCM per 128-bit block . . . . .1313
Table 297.CRYP register map and reset values . . . . .1327
Table 298.HASH internal input/output signals. . . . .1332
Table 299.Hash processor outputs . . . . .1335
Table 300.HASH interrupt requests. . . . .1342
Table 301.Processing time (in clock cycle) . . . . .1342
Table 302.HASH register map and reset values . . . . .1350
Table 303.HRTIM Input/output summary. . . . .1356
Table 304.Timer resolution and min. PWM frequency for \( f_{HRTIM} = 400 \) MHz . . . . .1358
Table 305.Period and Compare registers min and max values . . . . .1360
Table 306.Timer operating modes. . . . .1361
Table 307.Events mapping across Timer A to E . . . . .1366
Table 308.Deadtime resolution and max absolute values . . . . .1374
Table 309.External events mapping and associated features . . . . .1381
Table 310.Output set/reset latency and jitter vs external event operating mode. . . . .1382
Table 311.Filtering signals mapping per time . . . . .1385
Table 312.Windowing signals mapping per timer (EEFLTR[3:0] = 1111) . . . . .1387
Table 313.HRTIM preloadable control registers and associated update sources . . . . .1396
Table 314.Update enable inputs and sources . . . . .1397
Table 315.Master timer update event propagation . . . . .1399
Table 316.TIMx update event propagation . . . . .1399
Table 317.Reset events able to generate an update. . . . .1400
Table 318.Update event propagation for a timer reset . . . . .1401
Table 319.Output state programming, x= A..E, y = 1 or 2 . . . . .1402
Table 320.Timer output programming for burst mode . . . . .1405
Table 321.Burst mode clock sources from general purpose timer. . . . .1407
Table 322.Fault inputs . . . . .1415
Table 323.Sampling rate and filter length vs FLTFxF[3:0] and clock setting . . . . .1416
Table 324.Effect of sync event vs timer operating modes . . . . .1421
Table 325.HRTIM interrupt summary . . . . .1427
Table 326.HRTIM DMA request summary. . . . .1428
Table 327.RTIM global register map . . . . .1518
Table 328.HRTIM Register map and reset values: Master timer. . . . .1518
Table 329.HRTIM Register map and reset values: TIMx (x= A..E) . . . . .1520
Table 330.HRTIM Register map and reset values: Common functions. . . . .1524
Table 331.Behavior of timer outputs versus BRK/BRK2 inputs. . . . .1568
Table 332.Counting direction versus encoder signals . . . . .1575
Table 333.TIMx internal trigger connection . . . . .1592
Table 334.Output control bits for complementary OCx and OCxN channels with break feature . . . . .1606
Table 335.TIM1 register map and reset values . . . . .1626
Table 336.TIM8 register map and reset values . . . . .1628
Table 337.Counting direction versus encoder signals . . . . .1664
Table 338.TIMx internal trigger connection . . . . .1682
Table 339.Output control bit for standard OCx channels. . . . .1693
Table 340.TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . .1705
Table 341.TIMx internal trigger connection . . . . .1736
Table 342.Output control bit for standard OCx channels. . . . .1744
Table 343.TIM12 register map and reset values . . . . .1747
Table 344.Output control bit for standard OCx channels. . . . .1756
Table 345.TIM13/TIM14 register map and reset values . . . . .1759
Table 346.TIMx Internal trigger connection . . . . .1803
Table 347.Output control bits for complementary OCx and OCxN channels with break feature (TIM15) . . . . .1813
Table 348.TIM15 register map and reset values . . . . .1822
Table 349.Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . . . . .1834
Table 350.TIM16/TIM17 register map and reset values . . . . .1845
Table 351.TIMx register map and reset values . . . . .1859
Table 352.STM32H742, STM32H743/753 and STM32H750 LPTIM features . . . . .1861
Table 353.LPTIM input/output pins . . . . .1863
Table 354.LPTIM internal signals . . . . .1863
Table 355.LPTIM1 external trigger connection . . . . .1863
Table 356.LPTIM2 external trigger connection . . . . .1864
Table 357.LPTIM3 external trigger connection . . . . .1864
Table 358.LPTIM4 external trigger connection . . . . .1864
Table 359.LPTIM5 external trigger connection . . . . .1865
Table 360.LPTIM1 input 1 connection . . . . .1865
Table 361.LPTIM1 input 2 connection . . . . .1865
Table 362.LPTIM2 input 1 connection . . . . .1865
Table 363.LPTIM2 input 2 connection . . . . .1866
Table 364.LPTIM3 input 1 connection . . . . .1866
Table 365.Prescaler division ratios . . . . .1867
Table 366.Encoder counting scenarios . . . . .1874
Table 367.Effect of low-power modes on the LPTIM . . . . .1875
Table 368.Interrupt events . . . . .1876
Table 369.LPTIM register map and reset values . . . . .1887
Table 370.WWDG internal input/output signals . . . . .1889
Table 371.WWDG register map and reset values . . . . .1893
Table 372.IWDG internal input/output signals . . . . .1895
Table 373.IWDG register map and reset values . . . . .1903
Table 374.RTC pins and internal signals . . . . .1908
Table 375.RTC pin PC13 configuration . . . . .1908
Table 376.RTC_OUT mapping . . . . .1909
Table 377.RTC functions over modes . . . . .1910
Table 378.Effect of low-power modes on RTC . . . . .1922
Table 379.Interrupt control bits . . . . .1923
Table 380.RTC register map and reset values . . . . .1948
Table 381.STM32H742, STM32H743/753 and STM32H750 I2C implementation . . . . .1951
Table 382.I2C input/output pins . . . . .1953
Table 383.I2C internal input/output signals . . . . .1953
Table 384.Comparison of analog vs. digital filters . . . . .1955
Table 385.I2C-SMBus specification data setup and hold times . . . . .1957
Table 386.I2C configuration . . . . .1962
Table 387.I2C-SMBus specification clock timings . . . . .1973
Table 388.Examples of timing settings for f I2CCLK = 8 MHz . . . . .1983
Table 389.Examples of timing settings for f I2CCLK = 16 MHz . . . . .1983
Table 390.Examples of timing settings for f I2CCLK = 48 MHz . . . . .1984
Table 391.SMBus timeout specifications . . . . .1986
Table 392.SMBus with PEC configuration . . . . .1987
Table 393.Examples of TIMEOUTA settings (max t TIMEOUT = 25 ms) . . . . .1989
Table 394.Examples of TIMEOUTB settings . . . . .1989
Table 395.Examples of TIMEOUTA settings (max t IDLE = 50 µs) . . . . .1989
Table 396.Effect of low-power modes on the I2C . . . . .2000
Table 397.I2C Interrupt requests . . . . .2001
Table 398.I2C register map and reset values . . . . .2016
Table 399.USART / LPUART features . . . . .2020
Table 400.Noise detection from sampled data . . . . .2035
Table 401.Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .2038
Table 402.Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . .2039
Table 403.USART frame formats . . . . .2044
Table 404.Effect of low-power modes on the USART . . . . .2067
Table 405.USART interrupt requests. . . . .2068
Table 406.USART register map and reset values . . . . .2103
Table 407.USART / LPUART features . . . . .2107
Table 408.Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz . . . . .2118
Table 409.Error calculation for programmed baud rates at fCK = 100 MHz . . . . .2119
Table 410.Tolerance of the LPUART receiver. . . . .2120
Table 412.Effect of low-power modes on the LPUART . . . . .2131
Table 413.LPUART interrupt requests. . . . .2132
Table 414.LPUART register map and reset values . . . . .2156
Table 415.STM32H742xx, STM32H743/53xx and STM32H750xB SPI features . . . . .2159
Table 416.SPI wakeup and interrupt requests. . . . .2191
Table 417.Bitfields usable in PCM/I2S mode . . . . .2194
Table 418.WS and CK level before SPI/I2S is enabled when AFCNTR = 1 . . . . .2202
Table 419.Serial data line swapping . . . . .2202
Table 420.CLKGEN programming examples for usual I2S frequencies . . . . .2207
Table 421.I2S interrupt requests . . . . .2216
Table 422.SPI register map and reset values . . . . .2235
Table 423.STM32H743/753/745/755/747/757 SAI features . . . . .2238
Table 424.SAI internal input/output signals . . . . .2240
Table 425.SAI input/output pins. . . . .2240
Table 426.External synchronization selection . . . . .2242
Table 427.Clock generator programming examples . . . . .2250
Table 428.TDM settings. . . . .2257
Table 429.TDM frame configuration examples . . . . .2259
Table 430.SOPD pattern . . . . .2263
Table 431.Parity bit calculation . . . . .2263
Table 432.Audio sampling frequency versus symbol rates . . . . .2264
Table 433.SAI interrupt sources . . . . .2273
Table 434.SAI register map and reset values . . . . .2303
Table 435.SPDIFRX internal input/output signals . . . . .2306
Table 436.SPDIFRX pins. . . . .2306
Table 437.Transition sequence for preamble . . . . .2312
Table 438.Minimum spdifrx_ker_ck frequency versus audio sampling rate . . . . .2322
Table 439.Bit field property versus SPDIFRX state. . . . .2324
Table 440.SPDIFRX interface register map and reset values . . . . .2336
Table 441.SWPMI input/output signals connected to package pins or balls . . . . .2339
Table 442.SWPMI internal input/output signals. . . . .2340
Table 443.Effect of low-power modes on SWPMI . . . . .2354
Table 444.Interrupt control bits . . . . .2355
Table 445.Buffer modes selection for transmission/reception . . . . .2357
Table 446.SWPMI register map and reset values . . . . .2364
Table 447.MDIOS input/output signals connected to package pins or balls . . . . .2366
Table 448.MDIOS internal input/output signals . . . . .2366
Table 449.Interrupt control bits . . . . .2371
Table 450.MDIOS register map and reset values . . . . .2376
Table 451.SDMMC features . . . . .2378
Table 452.SDMMC operation modes SD and SDIO . . . . .2381
Table 453.SDMMC operation modes e•MMC . . . . .2381
Table 454.SDMMC internal input/output signals . . . . .2382
Table 455.SDMMC pins. . . . .2383
Table 456.SDMMC Command and data phase selection . . . . .2384
Table 457.Command token format . . . . .2390
Table 458.Short response with CRC token format . . . . .2391
Table 459.Short response without CRC token format . . . . .2391
Table 460.Long response with CRC token format . . . . .2391
Table 461.Specific Commands overview . . . . .2392
Table 462.Command path status flags . . . . .2393
Table 463.Command path error handling . . . . .2393
Table 464.Data token format . . . . .2401
Table 465.Data path status flags and clear bits . . . . .2401
Table 466.Data path error handling . . . . .2403
Table 467.Data FIFO access . . . . .2404
Table 468.Transmit FIFO status flags . . . . .2405
Table 469.Receive FIFO status flags . . . . .2406
Table 470.SDMMC connections to MDMA . . . . .2410
Table 471.AHB and SDMMC_CK clock frequency relation . . . . .2410
Table 472.SDIO special operation control . . . . .2411
Table 473.4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . .2415
Table 474.CMD12 use cases . . . . .2419
Table 475.SDMMC interrupts . . . . .2433
Table 476.Response type and SDMMC_RESPxR registers . . . . .2441
Table 477.SDMMC register map . . . . .2456
Table 478.CAN subsystem I/O signals . . . . .2459
Table 479.CAN subsystem I/O pins . . . . .2460
Table 480.Main features . . . . .2462
Table 481.DLC coding in FDCAN . . . . .2467
Table 482.Example of filter configuration for Rx buffers . . . . .2479
Table 483.Example of filter configuration for Debug messages . . . . .2480
Table 484.Possible configurations for frame transmission . . . . .2480
Table 485.Tx buffer/FIFO - queue element size . . . . .2481
Table 486.First byte of level 1 reference message . . . . .2491
Table 487.First four bytes of level 2 reference message . . . . .2492
Table 488.First four bytes of level 0 reference message . . . . .2492
Table 489.TUR configuration example . . . . .2493
Table 490.System matrix, Node A . . . . .2498
Table 491.Trigger list, Node A . . . . .2499
Table 492.Number of data bytes transmitted with a reference message . . . . .2506
Table 493.Rx buffer and FIFO element . . . . .2513
Table 494.Rx buffer and FIFO element description . . . . .2513
Table 495.Tx buffer and FIFO element . . . . .2515
Table 496.Tx buffer element description . . . . .2515
Table 497.Tx Event FIFO element . . . . .2517
Table 498.Tx Event FIFO element description . . . . .2517
Table 499.Standard message ID filter element . . . . .2518
Table 500.Standard message ID filter element field description . . . . .2519
Table 501.Extended message ID filter element . . . . .2520
Table 502.Extended message ID filter element field description . . . . .2520
Table 503.Trigger memory element . . . . .2521
Table 504.Trigger memory element description . . . . .2521
Table 505.FDCAN register map and reset values . . . . .2560
Table 506.FDCAN TT register map and reset values . . . . .2582
Table 507.CCU register map and reset values . . . . .2588
Table 508.OTG_HS speeds supported . . . . .2591
Table 509.OTG_HS implementation . . . . .2593
Table 510.OTG_FS input/output pins . . . . .2595
Table 511.OTG_HS input/output pins . . . . .2595
Table 512.OTG_HS input/output signals . . . . .2595
Table 513.Compatibility of STM32 low power modes with the OTG . . . . .2608
Table 514.Core global control and status registers (CSRs). . . . .2616
Table 515.Host-mode control and status registers (CSRs) . . . . .2617
Table 516.Device-mode control and status registers . . . . .2619
Table 517.Data FIFO (DFIFO) access register map . . . . .2621
Table 518.Power and clock gating control and status registers . . . . .2621
Table 519.TRDT values . . . . .2630
Table 520.Minimum duration for soft disconnect . . . . .2675
Table 521.OTG_HS register map and reset values . . . . .2703
Table 522.Ethernet peripheral pins . . . . .2782
Table 523.Ethernet internal input/output signals . . . . .2783
Table 524.Priority scheme for Tx DMA and Rx DMA . . . . .2792
Table 525.Double VLAN processing features in Tx path . . . . .2798
Table 526.Double VLAN processing in Rx path . . . . .2799
Table 527.VLAN insertion or replacement based on VLTi bit . . . . .2800
Table 528.Destination address filtering . . . . .2803
Table 529.Source address filtering . . . . .2804
Table 530.VLAN match status . . . . .2805
Table 531.Ordinary clock: PTP messages for snapshot . . . . .2808
Table 532.End-to-end transparent clock: PTP messages for snapshot . . . . .2809
Table 533.Peer-to-peer transparent clock: PTP messages for snapshot . . . . .2810
Table 534.Egress and ingress latency for PHY interfaces . . . . .2813
Table 535.Minimum PTP clock frequency example . . . . .2814
Table 536.Message format defined in IEEE 1588-2008 . . . . .2815
Table 537.Message format defined in IEEE 1588-2008 . . . . .2815
Table 538.IPv6-UDP PTP packet fields required for control and status . . . . .2816
Table 539.Ethernet PTP packet fields required for control and status . . . . .2817
Table 540.Timestamp Snapshot Dependency on ETH_MACTSCR bits . . . . .2819
Table 541.PTP message generation criteria . . . . .2825
Table 542.Common PTP message header fields . . . . .2827
Table 543.MAC Transmit PTP mode and one-step timestamping operation . . . . .2830
Table 544.Transmit checksum offload engine functions for different packet types . . . . .2835
Table 545.Receive checksum offload engine functions for different packet types . . . . .2837
Table 546.TSO: TCP and IP header fields . . . . .2841
Table 547.Pause packet fields . . . . .2846
Table 548.Tx MAC flow control . . . . .2847
Table 549.Rx MAC flow control . . . . .2847
Table 550.Size of the maximum receive packet . . . . .2850
Table 551.MCD clock selection . . . . .2853
Table 552.MDIO Clause 45 frame structure . . . . .2854
Table 553.MDIO Clause 22 frame structure . . . . .2855
Table 554.Remote wake-up packet filter register . . . . .2866
Table 555.Description of the remote wake-up filter fields . . . . .2867
Table 556.Remote wake-up packet and PMT interrupt generation . . . . .2868
Table 557.Transfer complete interrupt behavior . . . . .2876
Table 558.TDES0 normal descriptor (read format) . . . . .2896
Table 559.TDES1 normal descriptor (read format) . . . . .2897
Table 560.TDES2 normal descriptor (read format) . . . . .2897
Table 561.TDES3 normal descriptor (read format) . . . . .2898
Table 562.TDES0 normal descriptor (write-back format). . . . .2901
Table 563.TDES1 normal descriptor (write-back format). . . . .2901
Table 564.TDES2 normal descriptor (write-back format). . . . .2902
Table 565.TDES3 normal descriptor (write-back format). . . . .2902
Table 566.TDES0 context descriptor. . . . .2905
Table 567.TDES1 context descriptor. . . . .2906
Table 568.TDES2 context descriptor. . . . .2906
Table 569.TDES3 context descriptor. . . . .2906
Table 570.RDES0 normal descriptor (read format) . . . . .2910
Table 571.RDES1 normal descriptor (read format) . . . . .2910
Table 572.RDES2 normal descriptor (read format) . . . . .2910
Table 573.RDES3 normal descriptor (read format) . . . . .2911
Table 574.RDES0 normal descriptor (write-back format) . . . . .2912
Table 575.RDES1 normal descriptor (write-back format) . . . . .2913
Table 576.RDES2 normal descriptor (write-back format) . . . . .2915
Table 577.RDES3 normal descriptor (write-back format) . . . . .2916
Table 578.RDES0 context descriptor . . . . .2919
Table 579.RDES1 context descriptor . . . . .2920
Table 580.RDES2 context descriptor . . . . .2920
Table 581.RDES3 context descriptor . . . . .2920
Table 582.ETH_DMA common register map and reset values . . . . .2944
Table 583.ETH_DMA_CH register map and reset values . . . . .2944
Table 584.ETH_MTL register map and reset values . . . . .2957
Table 585.Giant Packet Status based on S2KP and JE Bits . . . . .2963
Table 586.Packet Length based on the CST and ACS bits . . . . .2963
Table 587.Ethernet MAC register map and reset values . . . . .3045
Table 588.HDMI pin . . . . .3057
Table 589.HDMI-CEC internal input/output signals . . . . .3057
Table 590.Error handling timing parameters . . . . .3063
Table 591.TXERR timing parameters . . . . .3064
Table 592.HDMI-CEC interrupts . . . . .3065
Table 593.HDMI-CEC register map and reset values . . . . .3073
Table 594.JTAG/Serial-wire debug port pins . . . . .3076
Table 595.Trace port pins . . . . .3076
Table 596.Serial-wire trace port pins . . . . .3076
Table 597.Trigger pins . . . . .3076
Table 598.Packet request . . . . .3080
Table 599.ACK response . . . . .3080
Table 600.Data transfer . . . . .3080
Table 601.JTAG-DP data registers . . . . .3083
Table 602.Debug port registers . . . . .3085
Table 603.MEM-AP registers . . . . .3095
Table 604.System ROM table 1 . . . . .3099
Table 605.System ROM table 2 . . . . .3100
Table 606.System ROM table 1 register map and reset values . . . . .3106
Table 607.System ROM table 2 register map and reset values . . . . .3107
Table 608.TSG register map and reset values . . . . .3115
Table 609.System CTI inputs . . . . .3116
Table 610.System CTI outputs . . . . .3117
Table 611.Cortex-M7 CTI inputs . . . . .3117
Table 612.Cortex-M7 CTI outputs . . . . .3118
Table 613.CTI register map and reset values . . . . .3133
Table 614.CSTF register map and reset values . . . . .3144
Table 615.ETF register map and reset values. . . . .3165
Table 616.TPIU register map and reset values . . . . .3183
Table 617.SWO register map and reset values. . . . .3195
Table 618.SWTF register map and reset values . . . . .3206
Table 619.DBGMCU register map and reset values . . . . .3214
Table 620.Cortex-M7 processor ROM table . . . . .3215
Table 621.Cortex-M7 PPB ROM table. . . . .3215
Table 622.Cortex-M7 processor ROM table register map and reset values . . . . .3221
Table 623.Cortex-M7 PPB ROM table register map and reset values . . . . .3226
Table 624.Cortex-M7 DWT register map and reset values . . . . .3238
Table 625.Cortex-M7 ITM register map and reset values . . . . .3248
Table 626.Cortex-M7 FPB register map and reset values. . . . .3255
Table 627.Cortex-M7 ETM register map and reset values . . . . .3285
Table 628.Document revision history . . . . .3294

List of figures

Figure 1.System architecture for STM32H742xx, STM32H743/53xx and STM32H750xB devices105
Figure 2.AXI interconnect . . . . .110
Figure 3.RAM ECC controller implementation schematic. . . . .141
Figure 4.Connection between RAM ECC controller and RAMECC monitoring unit . . . . .141
Figure 5.FLASH block diagram . . . . .149
Figure 6.Detailed FLASH architecture . . . . .151
Figure 7.Embedded flash memory organization . . . . .152
Figure 8.Embedded flash memory usage . . . . .155
Figure 9.FLASH protection mechanisms . . . . .156
Figure 10.FLASH read pipeline architecture. . . . .159
Figure 11.FLASH write pipeline architecture . . . . .162
Figure 12.Flash bank swapping sequence . . . . .171
Figure 13.RDP protection transition scheme . . . . .187
Figure 14.Example of protected region overlapping . . . . .188
Figure 15.Flash memory areas and services in Standard and Secure access modes. . . . .248
Figure 16.Bootloader state machine in Secure access mode . . . . .249
Figure 17.Core access to flash memory areas . . . . .252
Figure 18.Power control block diagram . . . . .255
Figure 19.Power supply overview. . . . .259
Figure 20.System supply configurations. . . . .260
Figure 21.Device startup with V CORE supplied from voltage regulator . . . . .262
Figure 22.Device startup with V CORE supplied in Bypass mode
from external regulator . . . . .		263
Figure 23.Backup domain . . . . .267
Figure 24.USB supply configurations . . . . .268
Figure 25.Power-on reset/power-down reset waveform . . . . .269
Figure 26.BOR thresholds . . . . .270
Figure 27.PVD thresholds. . . . .271
Figure 28.AVD thresholds. . . . .272
Figure 29.VBAT thresholds. . . . .273
Figure 30.Temperature thresholds . . . . .274
Figure 31.Switching V CORE from V OS1 to V OS0 . . . . .280
Figure 32.V CORE voltage scaling versus system power modes . . . . .281
Figure 33.Power control modes detailed state diagram . . . . .283
Figure 34.Dynamic voltage scaling in Run mode . . . . .286
Figure 35.Dynamic voltage scaling behavior with D1,
D2 and system in Stop mode . . . . .		287
Figure 36.Dynamic Voltage Scaling D1, D2, system Standby mode . . . . .288
Figure 37.Dynamic voltage scaling behavior with D1 and D2 in DStandby mode and
D3 in autonomous mode . . . . .		290
Figure 38.EXTI, RCC and PWR interconnections . . . . .314
Figure 39.Timing diagram of SRAM4-to-LPUART1 transfer with BDMA and D3 domain
in Autonomous mode . . . . .		318
Figure 40.BDMA and DMAMUX2 interconnection . . . . .320
Figure 41.Timing diagram of LPUART1 transmission with D3 domain
in Autonomous mode . . . . .		323
Figure 42.RCC Block diagram . . . . .326
Figure 43.System reset circuit . . . . .329
Figure 44.Boot sequences versus system states . . . . .335
Figure 45.Top-level clock tree. . . . .337
Figure 46.HSE/LSE clock source . . . . .338
Figure 47.PLL block diagram . . . . .345
Figure 48.PLLs Initialization Flowchart . . . . .348
Figure 49.Core and bus clock generation . . . . .350
Figure 50.Kernel clock distribution for SAIs and DFSDM . . . . .357
Figure 51.Kernel clock distribution for SPIs and SPI/I2S . . . . .358
Figure 52.Kernel clock distribution for I2Cs . . . . .359
Figure 53.Kernel clock distribution for UARTs, USARTs and LPUART1 . . . . .359
Figure 54.Kernel clock distribution for LTDC . . . . .360
Figure 55.Kernel clock distribution for SDMMC, QUADSPI and FMC . . . . .360
Figure 56.Kernel clock distribution for USB (2) . . . . .361
Figure 57.Kernel clock distribution for Ethernet . . . . .362
Figure 58.Kernel clock distribution for ADCs, SWPMI, RNG and FDCAN (2) . . . . .363
Figure 59.Kernel clock distribution for LPTIMs and HDMI-CEC (2) . . . . .364
Figure 60.Peripheral allocation example. . . . .367
Figure 61.Kernel Clock switching . . . . .370
Figure 62.Peripheral kernel clock enable logic details . . . . .374
Figure 63.Bus clock enable logic . . . . .379
Figure 64.RCC mapping overview . . . . .381
Figure 65.CRS block diagram. . . . .506
Figure 66.CRS counter behavior . . . . .508
Figure 67.HSEM block diagram . . . . .518
Figure 68.Procedure state diagram . . . . .519
Figure 69.Interrupt state diagram . . . . .522
Figure 70.Basic structure of an I/O port bit . . . . .531
Figure 71.Basic structure of a 5-Volt tolerant I/O port bit . . . . .531
Figure 72.Input floating / pull up / pull down configurations . . . . .536
Figure 73.Output configuration . . . . .537
Figure 74.Alternate function configuration . . . . .538
Figure 75.High impedance-analog configuration . . . . .538
Figure 76.Analog inputs connected to ADC inputs . . . . .539
Figure 77.MDMA block diagram . . . . .612
Figure 78.DMA block diagram . . . . .637
Figure 79.Peripheral-to-memory mode . . . . .641
Figure 80.Memory-to-peripheral mode . . . . .642
Figure 81.Memory-to-memory mode . . . . .643
Figure 82.FIFO structure. . . . .648
Figure 83.BDMA block diagram . . . . .670
Figure 84.DMAMUX block diagram . . . . .699
Figure 85.Synchronization mode of the DMAMUX request line multiplexer channel . . . . .702
Figure 86.Event generation of the DMA request line multiplexer channel . . . . .702
Figure 87.DMA2D block diagram . . . . .717
Figure 88.Intel 8080 16-bit mode (RGB565) . . . . .723
Figure 89.Intel 8080 18/24-bit mode (RGB888) . . . . .724
Figure 90.EXTI block diagram . . . . .759
Figure 91.Configurable event triggering logic CPU wakeup . . . . .761
Figure 92.Configurable event triggering logic Any wakeup . . . . .763
Figure 93.Direct event triggering logic CPU Wakeup . . . . .764
Figure 94.Direct event triggering logic Any Wakeup . . . . .765
Figure 95.D3 domain Pending request clear logic . . . . .766
Figure 96.CRC calculation unit block diagram . . . . .791
Figure 97.FMC block diagram. . . . .799
Figure 98.FMC memory banks (default mapping) . . . . .802
Figure 99.Mode 1 read access waveforms . . . . .813
Figure 100.Mode 1 write access waveforms. . . . .814
Figure 101.Mode A read access waveforms. . . . .816
Figure 102.Mode A write access waveforms . . . . .817
Figure 103.Mode 2 and mode B read access waveforms. . . . .819
Figure 104.Mode 2 write access waveforms. . . . .819
Figure 105.Mode B write access waveforms . . . . .820
Figure 106.Mode C read access waveforms . . . . .822
Figure 107.Mode C write access waveforms . . . . .822
Figure 108.Mode D read access waveforms . . . . .825
Figure 109.Mode D write access waveforms . . . . .825
Figure 110.Muxed read access waveforms . . . . .828
Figure 111.Muxed write access waveforms . . . . .828
Figure 112.Asynchronous wait during a read access waveforms. . . . .831
Figure 113.Asynchronous wait during a write access waveforms. . . . .831
Figure 114.Wait configuration waveforms. . . . .834
Figure 115.Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM). . . . .834
Figure 116.Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . .836
Figure 117.NAND flash controller waveforms for common memory access. . . . .850
Figure 118.Access to non 'CE don't care' NAND-flash. . . . .851
Figure 119.Burst write SDRAM access waveforms . . . . .861
Figure 120.Burst read SDRAM access . . . . .862
Figure 121.Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0) . . . . .863
Figure 122.Read access crossing row boundary . . . . .865
Figure 123.Write access crossing row boundary . . . . .865
Figure 124.Self-refresh mode . . . . .868
Figure 125.Power-down mode . . . . .869
Figure 126.QUADSPI block diagram when dual-flash mode is disabled . . . . .879
Figure 127.QUADSPI block diagram when dual-flash mode is enabled. . . . .880
Figure 128.Example of read command in quad-SPI mode . . . . .881
Figure 129.Example of a DDR command in quad-SPI mode . . . . .884
Figure 130.NCS when CKMODE = 0 (T = CLK period) . . . . .892
Figure 131.NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .893
Figure 132.NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . .893
Figure 133.NCS when CKMODE = 1 with an abort (T = CLK period). . . . .894
Figure 134.DLYB block diagram. . . . .907
Figure 135.ADC block diagram . . . . .915
Figure 136.ADC Clock scheme. . . . .918
Figure 137.ADC clock scheme . . . . .919
Figure 138.ADC1 connectivity . . . . .920
Figure 139.ADC2 connectivity . . . . .921
Figure 140.ADC3 connectivity . . . . .922
Figure 141.ADC calibration . . . . .926
Figure 142.Updating the ADC offset calibration factor . . . . .926
Figure 143.Mixing single-ended and differential channels . . . . .927
Figure 144.Enabling / Disabling the ADC . . . . .930
Figure 145.Analog to digital conversion time . . . . .936
Figure 146.Stopping ongoing regular conversions . . . . .937
Figure 147.Stopping ongoing regular and injected conversions. . . . .937
Figure 148. Triggers are shared between ADC master and ADC slave . . . . .939
Figure 149. Injected conversion latency . . . . .942
Figure 150. Example of JSQR queue of context (sequence change) . . . . .945
Figure 151. Example of JSQR queue of context (trigger change) . . . . .946
Figure 152. Example of JSQR queue of context with overflow before conversion . . . . .946
Figure 153. Example of JSQR queue of context with overflow during conversion . . . . .947
Figure 154. Example of JSQR queue of context with empty queue (case JQM=0). . . . .947
Figure 155. Example of JSQR queue of context with empty queue (case JQM=1). . . . .948
Figure 156. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion. . . . .		948
Figure 157. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . .		949
Figure 158. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs outside an ongoing conversion . . . . .		949
Figure 159. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . .950
Figure 160. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . .950
Figure 161. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . .951
Figure 162. Single conversions of a sequence, software trigger . . . . .953
Figure 163. Continuous conversion of a sequence, software trigger. . . . .953
Figure 164. Single conversions of a sequence, hardware trigger . . . . .954
Figure 165. Continuous conversions of a sequence, hardware trigger . . . . .954
Figure 166. Right alignment (offset disabled, unsigned value) . . . . .956
Figure 167. Right alignment (offset enabled, signed value) . . . . .956
Figure 168. Left alignment (offset disabled, unsigned value) . . . . .957
Figure 169. Left alignment (offset enabled, signed value) . . . . .957
Figure 170. Example of overrun (OVRMOD = 0). . . . .960
Figure 171. Example of overrun (OVRMOD = 1). . . . .960
Figure 172. AUTDLY=1, regular conversion in continuous mode, software trigger . . . . .964
Figure 173. AUTDLY=1, regular HW conversions interrupted by injected conversions
(DISCEN=0; JDISCEN=0) . . . . .		964
Figure 174. AUTDLY=1, regular HW conversions interrupted by injected conversions.
(DISCEN=1, JDISCEN=1) . . . . .		965
Figure 175. AUTDLY=1, regular continuous conversions interrupted by injected conversions . . . . .966
Figure 176. AUTDLY=1 in auto- injected mode (JAUTO=1) . . . . .966
Figure 177. Analog watchdog guarded area . . . . .967
Figure 178. ADCy_AWDx_OUT signal generation (on all regular channels). . . . .969
Figure 179. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by SW) . . . . .969
Figure 180. ADCy_AWDx_OUT signal generation (on a single regular channel) . . . . .970
Figure 181. ADCy_AWDx_OUT signal generation (on all injected channels) . . . . .970
Figure 182. 16-bit result oversampling with 10-bits right shift and rounding . . . . .971
Figure 183. Triggered regular oversampling mode (TROVS bit = 1). . . . .973
Figure 184. Regular oversampling modes (4x ratio) . . . . .974
Figure 185. Regular and injected oversampling modes used simultaneously . . . . .974
Figure 186. Triggered regular oversampling with injection . . . . .975
Figure 187. Oversampling in auto-injected mode . . . . .975
Figure 188. Dual ADC block diagram (1) . . . . .978
Figure 189. Injected simultaneous mode on 4 channels: dual ADC mode . . . . .979
Figure 190. Regular simultaneous mode on 16 channels: dual ADC mode . . . . .981
Figure 191. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode . . . . .982
Figure 192. Interleaved mode on 1 channel in single conversion mode: dual ADC mode . . . . .983
Figure 193. Interleaved conversion with injection . . . . .983
Figure 194. Alternate trigger: injected group of each ADC . . . . .984
Figure 195. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . .985
Figure 196. Alternate + regular simultaneous . . . . .986
Figure 197. Case of trigger occurring during injected conversion . . . . .986
Figure 198. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . .987
Figure 199. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . .		987
Figure 200. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . .		987
Figure 201. DMA Requests in regular simultaneous mode when DAMDF=0b00 . . . . .988
Figure 202. DMA requests in regular simultaneous mode when DAMDF=0b10 . . . . .989
Figure 203. DMA requests in interleaved mode when DAMDF=0b10 . . . . .989
Figure 204. Temperature sensor channel block diagram . . . . .991
Figure 205. VBAT channel block diagram . . . . .993
Figure 206. VREFINT channel block diagram . . . . .993
Figure 207. Dual-channel DAC block diagram . . . . .1046
Figure 208. Data registers in single DAC channel mode . . . . .1049
Figure 209. Data registers in dual DAC channel mode . . . . .1049
Figure 210. Timing diagram for conversion with trigger disabled TEN = 0 . . . . .1050
Figure 211. DAC LFSR register calculation algorithm . . . . .1052
Figure 212. DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .1052
Figure 213. DAC triangle wave generation . . . . .1053
Figure 214. DAC conversion (SW trigger enabled) with triangle wave generation . . . . .1053
Figure 215. DAC Sample and hold mode phase diagram . . . . .1056
Figure 216. Comparator functional block diagram . . . . .1085
Figure 217. Comparator hysteresis . . . . .1088
Figure 218. Comparator output blanking . . . . .1088
Figure 219. Output redirection . . . . .1090
Figure 220. Scaler block diagram . . . . .1092
Figure 221. Standalone mode: external gain setting mode . . . . .1102
Figure 222. Follower configuration . . . . .1103
Figure 223. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . .1104
Figure 224. PGA mode, internal gain setting (x2/x4/x8/x16),
inverting input used for filtering . . . . .		1105
Figure 225. PGA mode, non-inverting gain setting (x2/x4/x8/x16)
or inverting gain setting (x-1/x-3/x-7/x-15) . . . . .		1106
Figure 226. Example configuration . . . . .1106
Figure 227. PGA mode, non-inverting gain setting (x2/x4/x8/x16) or inverting gain
setting (x-1/x-3/x-7/x-15) with filtering . . . . .		1107
Figure 228. Example configuration . . . . .1107
Figure 229. Single DFSDM block diagram . . . . .1121
Figure 230. Input channel pins redirection . . . . .1125
Figure 231. Channel transceiver timing diagrams . . . . .1128
Figure 232. Clock absence timing diagram for SPI . . . . .1129
Figure 233. Clock absence timing diagram for Manchester coding . . . . .1130
Figure 234. First conversion for Manchester coding (Manchester synchronization) . . . . .1132
Figure 235. DFSDM_CHyDATINR registers operation modes and assignment . . . . .1136
Figure 236. Example: Sinc3 filter response . . . . .1138
Figure 237. DCMI block diagram . . . . .1178
Figure 238. DCMI signal waveforms . . . . .1179
Figure 239. Timing diagram . . . . .1181
Figure 240. Frame capture waveforms in snapshot mode . . . . .1183
Figure 241. Frame capture waveforms in continuous grab mode . . . . .1184
Figure 242. Coordinates and size of the window after cropping . . . . .1184
Figure 243. Data capture waveforms . . . . .1185
Figure 244. Pixel raster scan order . . . . .1186
Figure 245. LTDC block diagram . . . . .1201
Figure 246. LTDC synchronous timings . . . . .1204
Figure 247. Layer window programmable parameters . . . . .1207
Figure 248. Blending two layers with background . . . . .1209
Figure 249. Interrupt events . . . . .1211
Figure 250. JPEG codec block diagram . . . . .1232
Figure 251. RNG block diagram . . . . .1252
Figure 252. Entropy source model . . . . .1253
Figure 253. RNG initialization overview . . . . .1255
Figure 254. CRYPT block diagram . . . . .1265
Figure 255. AES-ECB mode overview . . . . .1268
Figure 256. AES-CBC mode overview . . . . .1269
Figure 257. AES-CTR mode overview . . . . .1270
Figure 258. AES-GCM mode overview . . . . .1271
Figure 259. AES-GMAC mode overview . . . . .1271
Figure 260. AES-CCM mode overview . . . . .1272
Figure 261. Example of suspend mode management . . . . .1278
Figure 262. DES/TDES-ECB mode encryption . . . . .1279
Figure 263. DES/TDES-ECB mode decryption . . . . .1280
Figure 264. DES/TDES-CBC mode encryption . . . . .1281
Figure 265. DES/TDES-CBC mode decryption . . . . .1282
Figure 266. AES-ECB mode encryption . . . . .1284
Figure 267. AES-ECB mode decryption . . . . .1285
Figure 268. AES-CBC mode encryption . . . . .1286
Figure 269. AES-CBC mode decryption . . . . .1287
Figure 270. Message construction for the Counter mode . . . . .1289
Figure 271. AES-CTR mode encryption . . . . .1290
Figure 272. AES-CTR mode decryption . . . . .1291
Figure 273. Message construction for the Galois/counter mode . . . . .1293
Figure 274. Message construction for the Galois Message Authentication Code mode . . . . .1298
Figure 275. Message construction for the Counter with CBC-MAC mode . . . . .1299
Figure 276. 64-bit block construction according to the data type (IN FIFO) . . . . .1306
Figure 277. 128-bit block construction according to the data type . . . . .1307
Figure 278. HASH block diagram . . . . .1331
Figure 279. Message data swapping feature . . . . .1333
Figure 280. HASH suspend/resume mechanism . . . . .1339
Figure 281. High-resolution timer block diagram . . . . .1355
Figure 282. Timer A..E overview . . . . .1360
Figure 283. Continuous timer operation . . . . .1361
Figure 284. Single-shot timer operation . . . . .1362
Figure 285. Timer reset resynchronization (prescaling ratio above 32) . . . . .1363
Figure 286. Repetition rate vs HRTIM_REPxR content in continuous mode . . . . .1364
Figure 287. Repetition counter behavior in single-shot mode . . . . .1365
Figure 288. Compare events action on outputs: set on compare 1, reset on compare 2 . . . . .1366
Figure 289. Timing unit capture circuitry . . . . .1368
Figure 290. Auto-delayed overview (Compare 2 only) . . . . .1369
Figure 291. Auto-delayed compare . . . . .1370
Figure 292. Push-pull mode block diagram . . . . .1372
Figure 293. Push-pull mode example . . . . .1373
Figure 294. Complementary outputs with deadtime insertion . . . . .1373
Figure 295. Deadtime insertion vs deadtime sign (1 indicates negative deadtime). . . . .1374
Figure 296. Complementary outputs for low pulse width (SDTRx = SDTFx = 0). . . . .1375
Figure 297. Complementary outputs for low pulse width (SDTRx = SDTFx = 1). . . . .1375
Figure 298. Complementary outputs for low pulse width (SDTRx = 0, SDTFx = 1). . . . .1375
Figure 299. Complementary outputs for low pulse width (SDTRx = 1, SDTFx=0). . . . .1376
Figure 300. Master timer overview. . . . .1377
Figure 301. External event conditioning overview (1 channel represented) . . . . .1380
Figure 302. Latency to external events falling edge (counter reset and output set) . . . . .1383
Figure 303. Latency to external events (output reset on external event). . . . .1383
Figure 304. Event blanking mode . . . . .1384
Figure 305. Event postpone mode. . . . .1384
Figure 306. External trigger blanking with edge-sensitive trigger . . . . .1386
Figure 307. External trigger blanking, level sensitive triggering. . . . .1386
Figure 308. Event windowing mode. . . . .1387
Figure 309. External trigger windowing with edge-sensitive trigger. . . . .1388
Figure 310. External trigger windowing, level sensitive triggering . . . . .1388
Figure 311. Delayed Idle mode entry. . . . .1390
Figure 312. Burst mode and delayed protection priorities (DIDL = 0) . . . . .1391
Figure 313. Burst mode and delayed protection priorities (DIDL = 1) . . . . .1392
Figure 314. Balanced Idle protection example. . . . .1393
Figure 315. Output management overview . . . . .1403
Figure 316. HRTIM output states and transitions . . . . .1403
Figure 317. Burst mode operation example. . . . .1405
Figure 318. Burst mode trigger on external event . . . . .1407
Figure 319. Delayed burst mode entry with deadtime enabled and IDLESx = 1 . . . . .1409
Figure 320. Delayed Burst mode entry during deadtime . . . . .1410
Figure 321. Burst mode exit when the deadtime generator is enabled . . . . .1411
Figure 322. Burst mode emulation example . . . . .1413
Figure 323. Carrier frequency signal insertion . . . . .1413
Figure 324. HRTIM outputs with Chopper mode enabled . . . . .1414
Figure 325. Fault protection circuitry (FAULT1 fully represented, FAULT2..5 partially). . . . .1415
Figure 326. Fault signal filtering (FLTxF[3:0]= 0010: f SAMPLING = f HRTIM , N = 4) . . . . .1416
Figure 327. Auxiliary outputs . . . . .1418
Figure 328. Auxiliary and main outputs during burst mode (DIDLx = 0) . . . . .1419
Figure 329. Deadtime distortion on auxiliary output when exiting burst mode. . . . .1419
Figure 330. Counter behavior in synchronized start mode . . . . .1423
Figure 331. ADC trigger selection overview . . . . .1424
Figure 332. Combining several updates on a single hrtim_dac_trgx output . . . . .1425
Figure 333. DMA burst overview . . . . .1429
Figure 334. Burst DMA operation flowchart. . . . .1430
Figure 335. Registers update following DMA burst transfer . . . . .1431
Figure 336. Buck converter topology . . . . .1433
Figure 337. Dual Buck converter management . . . . .1434
Figure 338. Synchronous rectification depending on output current . . . . .1434
Figure 339. Buck with synchronous rectification . . . . .1435
Figure 340. 3-phase interleaved buck converter . . . . .1436
Figure 341. 3-phase interleaved buck converter control . . . . .1437
Figure 342. Transition mode PFC . . . . .1437
Figure 343. Transition mode PFC waveforms . . . . .1438
Figure 344. Advanced-control timer block diagram . . . . .1528
Figure 345. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1530
Figure 346. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1530
Figure 347. Counter timing diagram, internal clock divided by 1 . . . . .1532
Figure 348. Counter timing diagram, internal clock divided by 2 . . . . .1532
Figure 349. Counter timing diagram, internal clock divided by 4 . . . . .1533
Figure 350. Counter timing diagram, internal clock divided by N . . . . .1533
Figure 351. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .1534
Figure 352. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .1534
Figure 353. Counter timing diagram, internal clock divided by 1 . . . . .1536
Figure 354. Counter timing diagram, internal clock divided by 2 . . . . .1536
Figure 355. Counter timing diagram, internal clock divided by 4 . . . . .1537
Figure 356. Counter timing diagram, internal clock divided by N . . . . .1537
Figure 357. Counter timing diagram, update event when repetition counter is not used . . . . .1538
Figure 358. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .1539
Figure 359. Counter timing diagram, internal clock divided by 2 . . . . .1540
Figure 360. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .1540
Figure 361. Counter timing diagram, internal clock divided by N . . . . .1541
Figure 362. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .1541
Figure 363. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .1542
Figure 364. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1543
Figure 365. External trigger input block . . . . .1544
Figure 366. TIM1/TIM8 ETR input circuitry . . . . .1544
Figure 367. Control circuit in normal mode, internal clock divided by 1 . . . . .1545
Figure 368. TI2 external clock connection example . . . . .1546
Figure 369. Control circuit in external clock mode 1 . . . . .1547
Figure 370. External trigger input block . . . . .1547
Figure 371. Control circuit in external clock mode 2 . . . . .1548
Figure 372. Capture/compare channel (example: channel 1 input stage) . . . . .1549
Figure 373. Capture/compare channel 1 main circuit . . . . .1549
Figure 374. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .1550
Figure 375. Output stage of capture/compare channel (channel 4) . . . . .1550
Figure 376. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .1551
Figure 377. PWM input mode timing . . . . .1553
Figure 378. Output compare mode, toggle on OC1 . . . . .1555
Figure 379. Edge-aligned PWM waveforms (ARR=8) . . . . .1556
Figure 380. Center-aligned PWM waveforms (ARR=8) . . . . .1557
Figure 381. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1559
Figure 382. Combined PWM mode on channel 1 and 3 . . . . .1560
Figure 383. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .1561
Figure 384. Complementary output with dead-time insertion . . . . .1562
Figure 385. Dead-time waveforms with delay greater than the negative pulse . . . . .1562
Figure 386. Dead-time waveforms with delay greater than the positive pulse . . . . .1563
Figure 387. Break and Break2 circuitry overview . . . . .1565
Figure 388. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .1567
Figure 389. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .1568
Figure 390. PWM output state following BRK assertion (OSSI=0) . . . . .1569
Figure 391. Output redirection . . . . .1569
Figure 392. Clearing TIMx_OCxREF . . . . .1570
Figure 393. 6-step generation, COM example (OSSR=1) . . . . .1571
Figure 394. Example of one pulse mode . . . . .1572
Figure 395. Retriggerable one pulse mode . . . . .1574
Figure 396. Example of counter operation in encoder interface mode . . . . .1575
Figure 397. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .1576
Figure 398. Measuring time interval between edges on 3 signals . . . . .1577
Figure 399. Example of Hall sensor interface . . . . .1579
Figure 400. Control circuit in reset mode . . . . .1580
Figure 401. Control circuit in Gated mode . . . . .1581
Figure 402. Control circuit in trigger mode . . . . .1582
Figure 403. Control circuit in external clock mode 2 + trigger mode . . . . .1583
Figure 404. General-purpose timer block diagram . . . . .1632
Figure 405. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1634
Figure 406. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1634
Figure 407. Counter timing diagram, internal clock divided by 1 . . . . .1635
Figure 408. Counter timing diagram, internal clock divided by 2 . . . . .1636
Figure 409. Counter timing diagram, internal clock divided by 4 . . . . .1636
Figure 410. Counter timing diagram, internal clock divided by N . . . . .1637
Figure 411. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1637
Figure 412. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .1638
Figure 413. Counter timing diagram, internal clock divided by 1 . . . . .1639
Figure 414. Counter timing diagram, internal clock divided by 2 . . . . .1639
Figure 415. Counter timing diagram, internal clock divided by 4 . . . . .1640
Figure 416. Counter timing diagram, internal clock divided by N . . . . .1640
Figure 417. Counter timing diagram, Update event . . . . .1641
Figure 418. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .1642
Figure 419. Counter timing diagram, internal clock divided by 2 . . . . .1643
Figure 420. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .1643
Figure 421. Counter timing diagram, internal clock divided by N . . . . .1644
Figure 422. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .1644
Figure 423. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .1645
Figure 424. Control circuit in normal mode, internal clock divided by 1 . . . . .1646
Figure 425. TI2 external clock connection example. . . . .1646
Figure 426. Control circuit in external clock mode 1 . . . . .1647
Figure 427. External trigger input block . . . . .1648
Figure 428. Control circuit in external clock mode 2 . . . . .1649
Figure 429. Capture/Compare channel (example: channel 1 input stage) . . . . .1649
Figure 430. Capture/Compare channel 1 main circuit . . . . .1650
Figure 431. Output stage of Capture/Compare channel (channel 1). . . . .1650
Figure 432. PWM input mode timing . . . . .1652
Figure 433. Output compare mode, toggle on OC1 . . . . .1654
Figure 434. Edge-aligned PWM waveforms (ARR=8) . . . . .1655
Figure 435. Center-aligned PWM waveforms (ARR=8). . . . .1656
Figure 436. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1657
Figure 437. Combined PWM mode on channels 1 and 3 . . . . .1659
Figure 438. Clearing TIMx_OCxREF . . . . .1660
Figure 439. Example of one-pulse mode. . . . .1661
Figure 440. Retriggerable one-pulse mode. . . . .1663
Figure 441. Example of counter operation in encoder interface mode . . . . .1664
Figure 442. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .1665
Figure 443. Control circuit in reset mode . . . . .1666
Figure 444. Control circuit in gated mode . . . . .1667
Figure 445. Control circuit in trigger mode . . . . .1668
Figure 446. Control circuit in external clock mode 2 + trigger mode . . . . .1669
Figure 447. Master/Slave timer example . . . . .1669
Figure 448. Master/slave connection example with 1 channel only timers . . . . .1670
Figure 449. Gating TIM2 with OC1REF of TIM3 . . . . .1671
Figure 450. Gating TIM2 with Enable of TIM3 . . . . .1672
Figure 451. Triggering TIM2 with update of TIM3 . . . . .1672
Figure 452. Triggering TIM2 with Enable of TIM3 . . . . .1673
Figure 453. Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . .1674
Figure 454. General-purpose timer block diagram (TIM12). . . . .1709
Figure 455. General-purpose timer block diagram (TIM13/TIM14) . . . . .1710
Figure 456. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1712
Figure 457. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1712
Figure 458. Counter timing diagram, internal clock divided by 1 . . . . .1713
Figure 459. Counter timing diagram, internal clock divided by 2 . . . . .1714
Figure 460. Counter timing diagram, internal clock divided by 4 . . . . .1714
Figure 461. Counter timing diagram, internal clock divided by N . . . . .1715
Figure 462. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1715
Figure 463. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .1716
Figure 464. Control circuit in normal mode, internal clock divided by 1 . . . . .1717
Figure 465. TI2 external clock connection example. . . . .1717
Figure 466. Control circuit in external clock mode 1 . . . . .1718
Figure 467. Capture/compare channel (example: channel 1 input stage). . . . .1719
Figure 468. Capture/compare channel 1 main circuit . . . . .1719
Figure 469. Output stage of capture/compare channel (channel 1). . . . .1720
Figure 470. PWM input mode timing . . . . .1722
Figure 471. Output compare mode, toggle on OC1. . . . .1724
Figure 472. Edge-aligned PWM waveforms (ARR=8). . . . .1725
Figure 473. Combined PWM mode on channel 1 and 2 . . . . .1726
Figure 474. Example of one pulse mode. . . . .1727
Figure 475. Retriggerable one pulse mode . . . . .1728
Figure 476. Measuring time interval between edges on 2 signals. . . . .1729
Figure 477. Control circuit in reset mode . . . . .1730
Figure 478. Control circuit in gated mode . . . . .1731
Figure 479. Control circuit in trigger mode. . . . .1731
Figure 480. TIM15 block diagram . . . . .1763
Figure 481. TIM16/TIM17 block diagram . . . . .1764
Figure 482. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1766
Figure 483. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1766
Figure 484. Counter timing diagram, internal clock divided by 1 . . . . .1768
Figure 485. Counter timing diagram, internal clock divided by 2 . . . . .1768
Figure 486. Counter timing diagram, internal clock divided by 4 . . . . .1769
Figure 487. Counter timing diagram, internal clock divided by N . . . . .1769
Figure 488. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1770
Figure 489. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .1770
Figure 490. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1772
Figure 491. Control circuit in normal mode, internal clock divided by 1 . . . . .1773
Figure 492. TI2 external clock connection example. . . . .1773
Figure 493. Control circuit in external clock mode 1 . . . . .1774
Figure 494. Capture/compare channel (example: channel 1 input stage). . . . .1775
Figure 495. Capture/compare channel 1 main circuit . . . . .1775
Figure 496. Output stage of capture/compare channel (channel 1). . . . .1776
Figure 497. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .1776
Figure 498. PWM input mode timing . . . . .1778
Figure 499. Output compare mode, toggle on OC1 . . . . .1780
Figure 500. Edge-aligned PWM waveforms (ARR=8) . . . . .1781
Figure 501. Combined PWM mode on channel 1 and 2 . . . . .1782
Figure 502. Complementary output with dead-time insertion. . . . .1783
Figure 503. Dead-time waveforms with delay greater than the negative pulse. . . . .1783
Figure 504. Dead-time waveforms with delay greater than the positive pulse. . . . .1784
Figure 505. Break circuitry overview . . . . .1786
Figure 506. Output behavior in response to a break . . . . .1788
Figure 507. 6-step generation, COM example (OSSR=1) . . . . .1789
Figure 508. Example of one pulse mode . . . . .1790
Figure 509. Retriggerable one pulse mode . . . . .1792
Figure 510. Measuring time interval between edges on 2 signals . . . . .1793
Figure 511. Control circuit in reset mode . . . . .1794
Figure 512. Control circuit in gated mode . . . . .1795
Figure 513. Control circuit in trigger mode . . . . .1796
Figure 514. Basic timer block diagram. . . . .1847
Figure 515. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1849
Figure 516. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1849
Figure 517. Counter timing diagram, internal clock divided by 1 . . . . .1850
Figure 518. Counter timing diagram, internal clock divided by 2 . . . . .1851
Figure 519. Counter timing diagram, internal clock divided by 4 . . . . .1851
Figure 520. Counter timing diagram, internal clock divided by N . . . . .1852
Figure 521. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .1852
Figure 522. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .1853
Figure 523. Control circuit in normal mode, internal clock divided by 1 . . . . .1854
Figure 524. Low-power timer block diagram (LPTIM1 and LPTIM2) . . . . .1861
Figure 525. Low-power timer block diagram (LPTIM3) . . . . .1862
Figure 526. Low-power timer block diagram (LPTIM4 and LPTIM5) . . . . .1862
Figure 527. Glitch filter timing diagram . . . . .1867
Figure 528. LPTIM output waveform, single counting mode configuration . . . . .1869
Figure 529. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set). . . . .1869
Figure 530. LPTIM output waveform, Continuous counting mode configuration . . . . .1870
Figure 531. Waveform generation . . . . .1871
Figure 532. Encoder mode counting sequence . . . . .1875
Figure 533. Watchdog block diagram . . . . .1889
Figure 534. Window watchdog timing diagram . . . . .1890
Figure 535. Independent watchdog block diagram . . . . .1895
Figure 536. RTC block overview . . . . .1905
Figure 537. Detailed RTC block diagram. . . . .1906
Figure 538. Tamper detection . . . . .1907
Figure 539. I2C block diagram . . . . .1952
Figure 540. I2C bus protocol . . . . .1954
Figure 541. Setup and hold timings . . . . .1956
Figure 542. I2C initialization flow . . . . .1959
Figure 543. Data reception . . . . .1960
Figure 544. Data transmission . . . . .1961
Figure 545. Slave initialization flow . . . . .1964
Figure 546.Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0 . . . . .1966
Figure 547.Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1 . . . . .1967
Figure 548.Transfer bus diagrams for I2C slave transmitter (mandatory events only) . . . . .1968
Figure 549.Transfer sequence flow for slave receiver with NOSTRETCH = 0 . . . . .1969
Figure 550.Transfer sequence flow for slave receiver with NOSTRETCH = 1 . . . . .1970
Figure 551.Transfer bus diagrams for I2C slave receiver
(mandatory events only) . . . . .		1970
Figure 552.Master clock generation . . . . .1972
Figure 553.Master initialization flow . . . . .1974
Figure 554.10-bit address read access with HEAD10R = 0 . . . . .1974
Figure 555.10-bit address read access with HEAD10R = 1 . . . . .1975
Figure 556.Transfer sequence flow for I2C master transmitter for N ≤ 255 bytes . . . . .1976
Figure 557.Transfer sequence flow for I2C master transmitter for N > 255 bytes . . . . .1977
Figure 558.Transfer bus diagrams for I2C master transmitter
(mandatory events only) . . . . .		1978
Figure 559.Transfer sequence flow for I2C master receiver for N ≤ 255 bytes . . . . .1980
Figure 560.Transfer sequence flow for I2C master receiver for N > 255 bytes . . . . .1981
Figure 561.Transfer bus diagrams for I2C master receiver
(mandatory events only) . . . . .		1982
Figure 562.Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .1986
Figure 563.Transfer sequence flow for SMBus slave transmitter N bytes + PEC . . . . .1990
Figure 564.Transfer bus diagrams for SMBus slave transmitter (SBC = 1) . . . . .1990
Figure 565.Transfer sequence flow for SMBus slave receiver N bytes + PEC . . . . .1992
Figure 566.Bus transfer diagrams for SMBus slave receiver (SBC = 1) . . . . .1993
Figure 567.Bus transfer diagrams for SMBus master transmitter . . . . .1994
Figure 568.Bus transfer diagrams for SMBus master receiver . . . . .1996
Figure 569.I2C interrupt mapping diagram . . . . .2002
Figure 570.USART block diagram . . . . .2021
Figure 571.Word length programming . . . . .2024
Figure 572.Configurable stop bits . . . . .2026
Figure 573.TC/TXE behavior when transmitting . . . . .2029
Figure 574.Start bit detection when oversampling by 16 or 8 . . . . .2030
Figure 575.usart_ker_ck clock divider block diagram . . . . .2033
Figure 576.Data sampling when oversampling by 16 . . . . .2034
Figure 577.Data sampling when oversampling by 8 . . . . .2035
Figure 578.Mute mode using Idle line detection . . . . .2042
Figure 579.Mute mode using address mark detection . . . . .2043
Figure 580.Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .2046
Figure 581.Break detection in LIN mode vs. Framing error detection . . . . .2047
Figure 582.USART example of synchronous master transmission . . . . .2048
Figure 583.USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		2048
Figure 584.USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		2049
Figure 585.USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		2050
Figure 586.ISO 7816-3 asynchronous protocol . . . . .2052
Figure 587.Parity error detection using the 1.5 stop bits . . . . .2054
Figure 588.IrDA SIR ENDEC block diagram . . . . .2058
Figure 589.IrDA data modulation (3/16) - Normal mode . . . . .2058
Figure 590.Transmission using DMA . . . . .2060
Figure 591.Reception using DMA . . . . .2061
Figure 592. Hardware flow control between 2 USARTs . . . . .2061
Figure 593. RS232 RTS flow control . . . . .2062
Figure 594. RS232 CTS flow control . . . . .2063
Figure 595. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .2066
Figure 596. Wake-up event not verified (wake-up event = address match, FIFO disabled) . . . . .2066
Figure 597. LPUART block diagram . . . . .2108
Figure 598. LPUART word length programming . . . . .2110
Figure 599. Configurable stop bits . . . . .2112
Figure 600. TC/TXE behavior when transmitting . . . . .2114
Figure 601. lpuart_ker_ck clock divider block diagram . . . . .2117
Figure 602. Mute mode using Idle line detection . . . . .2121
Figure 603. Mute mode using address mark detection . . . . .2122
Figure 604. Transmission using DMA . . . . .2124
Figure 605. Reception using DMA . . . . .2125
Figure 606. Hardware flow control between 2 LPUARTs . . . . .2126
Figure 607. RS232 RTS flow control . . . . .2126
Figure 608. RS232 CTS flow control . . . . .2127
Figure 609. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .2130
Figure 610. Wake-up event not verified (wake-up event = address match, FIFO disabled) . . . . .2130
Figure 611. SPI2S block diagram . . . . .2160
Figure 612. Full-duplex single master/ single slave application . . . . .2162
Figure 613. Half-duplex single master/ single slave application . . . . .2162
Figure 614. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . .2163
Figure 615. Master and three independent slaves at star topology . . . . .2164
Figure 616. Master and three slaves at circular (daisy chain) topology . . . . .2166
Figure 617. Multimaster application . . . . .2167
Figure 618. Scheme of SS control logic . . . . .2169
Figure 619. Data flow timing control (SSOE=1, SSOM=0, SSM=0) . . . . .2169
Figure 620. SS interleaving pulses between data (SSOE=1, SSOM=1,SSM=0). . . . .2170
Figure 621. Data clock timing diagram . . . . .2172
Figure 622. Data alignment when data size is not equal to 8-bit, 16-bit or 32-bit . . . . .2173
Figure 623. Packing data in FIFO for transmission and reception . . . . .2181
Figure 624. TI mode transfer . . . . .2183
Figure 625. Optional configurations of slave's behavior at detection of underrun condition . . . . .2185
Figure 626. Low-power mode application example . . . . .2189
Figure 627. Waveform examples . . . . .2196
Figure 628. Master I2S Philips protocol waveforms (16/32-bit full accuracy) . . . . .2197
Figure 629. I2S Philips standard waveforms . . . . .2197
Figure 630. Master MSB Justified 16-bit or 32-bit full-accuracy length . . . . .2198
Figure 631. Master MSB justified 16 or 24-bit data length . . . . .2198
Figure 632. Slave MSB justified . . . . .2199
Figure 633. LSB justified 16 or 24-bit data length . . . . .2199
Figure 634. Master PCM when the frame length is equal the data length . . . . .2200
Figure 635. Master PCM standard waveforms (16 or 24-bit data length) . . . . .2200
Figure 636. Slave PCM waveforms . . . . .2201
Figure 637. Startup sequence, I2S Philips standard, master . . . . .2204
Figure 638. Startup sequence, I2S Philips standard, slave . . . . .2204
Figure 639. Stop sequence, I2S Philips standard, master . . . . .2205
Figure 640. I 2 S clock generator architecture . . . . .2206
Figure 641. Data Format . . . . .2208
Figure 642. Handling of underrun situation . . . . .2210
Figure 643. Handling of overrun situation . . . . .2211
Figure 644. Frame error detection, with FIXCH=0 . . . . .2212
Figure 645. Frame error detection, with FIXCH=1 . . . . .2212
Figure 646. SAI functional block diagram . . . . .2239
Figure 647. Audio frame . . . . .2243
Figure 648. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .2245
Figure 649. FS role is start of frame (FSDEF = 0) . . . . .2246
Figure 650. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .2247
Figure 651. First bit offset . . . . .2247
Figure 652. Audio block clock generator overview . . . . .2248
Figure 653. PDM typical connection and timing . . . . .2252
Figure 654. Detailed PDM interface block diagram . . . . .2253
Figure 655. Start-up sequence . . . . .2254
Figure 656. SAI_ADR format in TDM, 32-bit slot width . . . . .2255
Figure 657. SAI_ADR format in TDM, 16-bit slot width . . . . .2256
Figure 658. SAI_ADR format in TDM, 8-bit slot width . . . . .2257
Figure 659. AC'97 audio frame . . . . .2260
Figure 660. Example of typical AC'97 configuration on devices featuring at least
2 embedded SAIs (three external AC'97 decoders) . . . . .		2261
Figure 661. SPDIF format . . . . .2262
Figure 662. SAI_xDR register ordering . . . . .2263
Figure 663. Data companding hardware in an audio block in the SAI . . . . .2267
Figure 664. Tristate strategy on SD output line on an inactive slot . . . . .2268
Figure 665. Tristate on output data line in a protocol like I2S . . . . .2269
Figure 666. Overrun detection error . . . . .2270
Figure 667. FIFO underrun event . . . . .2270
Figure 668. SPDIFRX block diagram . . . . .2306
Figure 669. S/PDIF sub-frame format . . . . .2307
Figure 670. S/PDIF block format . . . . .2307
Figure 671. S/PDIF Preambles . . . . .2308
Figure 672. Channel coding example . . . . .2309
Figure 673. SPDIFRX decoder . . . . .2310
Figure 674. Noise filtering and edge detection . . . . .2310
Figure 675. Thresholds . . . . .2312
Figure 676. Synchronization flowchart . . . . .2314
Figure 677. Synchronization process scheduling . . . . .2315
Figure 678. SPDIFRX States . . . . .2316
Figure 679. SPDIFRX_FMTx_DR register format . . . . .2318
Figure 680. Channel/user data format . . . . .2319
Figure 681. S/PDIF overrun error when RXSTEO = 0 . . . . .2321
Figure 682. S/PDIF overrun error when RXSTEO = 1 . . . . .2322
Figure 683. SPDIFRX interface interrupt mapping diagram . . . . .2323
Figure 684. S1 signal coding . . . . .2337
Figure 685. S2 signal coding . . . . .2337
Figure 686. SWPMI block diagram . . . . .2339
Figure 687. SWP bus states . . . . .2342
Figure 688. SWP frame structure . . . . .2343
Figure 689. SWPMI No software buffer mode transmission . . . . .2344
Figure 690. SWPMI No software buffer mode transmission, consecutive frames . . . . .2345
Figure 691. SWPMI Multi software buffer mode transmission . . . . .2347
Figure 692. SWPMI No software buffer mode reception . . . . .2349
Figure 693. SWPMI single software buffer mode reception. . . . .2350
Figure 694. SWPMI Multi software buffer mode reception . . . . .2352
Figure 695. SWPMI single buffer mode reception with CRC error. . . . .2353
Figure 696. MDIOS block diagram . . . . .2366
Figure 697. MDIO protocol write frame waveform . . . . .2367
Figure 698. MDIO protocol read frame waveform . . . . .2367
Figure 699. SDMMC “no response” and “no data” operations. . . . .2379
Figure 700. SDMMC (multiple) block read operation. . . . .2379
Figure 701. SDMMC (multiple) block write operation. . . . .2380
Figure 702. SDMMC (sequential) stream read operation . . . . .2380
Figure 703. SDMMC (sequential) stream write operation . . . . .2380
Figure 704. SDMMC block diagram. . . . .2382
Figure 705. SDMMC Command and data phase relation . . . . .2384
Figure 706. Control unit . . . . .2386
Figure 707. Command/response path . . . . .2387
Figure 708. Command path state machine (CPSM) . . . . .2388
Figure 709. Data path . . . . .2394
Figure 710. DDR mode data packet clocking . . . . .2395
Figure 711. DDR mode CRC status / boot acknowledgment clocking. . . . .2395
Figure 712. Data path state machine (DPSM) . . . . .2396
Figure 713. CLKMUX unit . . . . .2407
Figure 714. Asynchronous interrupt generation. . . . .2412
Figure 715. Synchronous interrupt period data read . . . . .2412
Figure 716. Synchronous interrupt period data write . . . . .2413
Figure 717. Asynchronous interrupt period data read . . . . .2414
Figure 718. Asynchronous interrupt period data write . . . . .2414
Figure 719. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25. . . . .2417
Figure 720. Clock stop with SDMMC_CK for DDR50, SDR50, SDR104. . . . .2417
Figure 721. Read Wait with SDMMC_CK < 50 MHz . . . . .2418
Figure 722. Read Wait with SDMMC_CK > 50 MHz . . . . .2419
Figure 723. CMD12 stream timing . . . . .2421
Figure 724. CMD5 Sleep Awake procedure . . . . .2423
Figure 725. Normal boot mode operation . . . . .2425
Figure 726. Alternative boot mode operation. . . . .2426
Figure 727. Command response R1b busy signaling . . . . .2427
Figure 728. SDMMC state control . . . . .2428
Figure 729. Card cycle power / power up diagram . . . . .2429
Figure 730. CMD11 signal voltage switch sequence . . . . .2430
Figure 731. Voltage switch transceiver typical application. . . . .2432
Figure 732. CAN subsystem . . . . .2461
Figure 733. FDCAN block diagram . . . . .2463
Figure 734. Transceiver delay measurement . . . . .2468
Figure 735. Pin control in bus monitoring mode . . . . .2470
Figure 736. Pin control in loop back mode. . . . .2472
Figure 737. Message RAM configuration. . . . .2473
Figure 738. Standard message ID filter path . . . . .2476
Figure 739. Extended message ID filter path. . . . .2477
Figure 740. Example of mixed configuration dedicated Tx buffers / Tx FIFO . . . . .2483
Figure 741. Example of mixed configuration dedicated Tx buffers / Tx queue . . . . .2483
Figure 742. Bit timing . . . . .2485
Figure 743. Bypass operation . . . . .2487
Figure 744. FSM calibration. . . . .2488
Figure 745. Cycle time and global time synchronization . . . . .2503
Figure 746. TTCAN level 0 and level 2 drift compensation . . . . .2504
Figure 747. Level 0 schedule synchronization state machine . . . . .2511
Figure 748. Level 0 master to slave relation . . . . .2512
Figure 749. USB1 OTG_HS high-speed block diagram (OTG_HS1) . . . . .2594
Figure 750. USB2 OTG_HS high-speed block diagram (OTG_HS2) . . . . .2594
Figure 751. OTG_HS A-B device connection . . . . .2597
Figure 752. OTG_HS peripheral-only connection . . . . .2599
Figure 753. OTG_HS host-only connection . . . . .2603
Figure 754. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .2607
Figure 755. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .2609
Figure 756. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .2610
Figure 757. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . .2611
Figure 758. Interrupt hierarchy. . . . .2615
Figure 759. Transmit FIFO write task . . . . .2720
Figure 760. Receive FIFO read task . . . . .2721
Figure 761. Normal bulk/control OUT/SETUP . . . . .2722
Figure 762. Bulk/control IN transactions . . . . .2726
Figure 763. Normal interrupt OUT . . . . .2729
Figure 764. Normal interrupt IN . . . . .2734
Figure 765. Isochronous OUT transactions . . . . .2736
Figure 766. Isochronous IN transactions . . . . .2739
Figure 767. Normal bulk/control OUT/SETUP transactions - DMA . . . . .2741
Figure 768. Normal bulk/control IN transaction - DMA. . . . .2743
Figure 769. Normal interrupt OUT transactions - DMA mode . . . . .2744
Figure 770. Normal interrupt IN transactions - DMA mode . . . . .2745
Figure 771. Normal isochronous OUT transaction - DMA mode . . . . .2746
Figure 772. Normal isochronous IN transactions - DMA mode . . . . .2747
Figure 773. Receive FIFO packet read . . . . .2753
Figure 774. Processing a SETUP packet . . . . .2755
Figure 775. Bulk OUT transaction . . . . .2762
Figure 776. TRDT max timing case . . . . .2771
Figure 777. A-device SRP . . . . .2772
Figure 778. B-device SRP . . . . .2773
Figure 779. A-device HNP . . . . .2774
Figure 780. B-device HNP . . . . .2776
Figure 781. Ethernet high-level block diagram . . . . .2784
Figure 782. DMA transmission flow (standard mode) . . . . .2787
Figure 783. DMA transmission flow (OSP mode) . . . . .2789
Figure 784. Receive DMA flow . . . . .2791
Figure 785. Overview of MAC transmission flow . . . . .2795
Figure 786. MAC reception flow . . . . .2797
Figure 787. Packet filtering sequence . . . . .2801
Figure 788. Networked time synchronization. . . . .2810
Figure 789. Propagation delay calculation in clocks supporting
peer-to-peer path correction . . . . .		2811
Figure 790. System time update using fine correction method . . . . .2821
Figure 791. TCP segmentation offload overview . . . . .2838
Figure 792. TCP segmentation offload flow . . . . .2839
Figure 793. Header and payload fields of segmented packets . . . . .2842
Figure 794. Supported PHY interfaces . . . . .2852
Figure 795. SMA Interface block . . . . .2852
Figure 796. MDIO packet structure (Clause 45) . . . . .2853
Figure 797. MDIO packet structure (Clause 22) . . . . .2854
Figure 798. SMA write operation flow . . . . .2856
Figure 799. Write data packet . . . . .2857
Figure 800. Read data packet . . . . .2857
Figure 801. Media independent interface (MII) signals . . . . .2859
Figure 802. RMII block diagram . . . . .2861
Figure 803. Transmission bit order . . . . .2862
Figure 804. Receive bit order . . . . .2863
Figure 805. LPI transitions (Transmit, 100 Mbds) . . . . .2871
Figure 806. LPI Tx clock gating (when LPITCSE = 1) . . . . .2872
Figure 807. LPI transitions (receive, 100 Mbps) . . . . .2873
Figure 808. Descriptor ring structure . . . . .2894
Figure 809. DMA descriptor ring . . . . .2895
Figure 810. Transmit descriptor (read format) . . . . .2896
Figure 811. Transmit descriptor write-back format . . . . .2901
Figure 812. Transmit context descriptor format . . . . .2905
Figure 813. Receive normal descriptor (read format) . . . . .2909
Figure 814. Receive normal descriptor (write-back format) . . . . .2912
Figure 815. Receive context descriptor . . . . .2919
Figure 816. Generation of ETH_DMAISR flags . . . . .2937
Figure 817. HDMI-CEC block diagram . . . . .3058
Figure 818. Message structure . . . . .3058
Figure 819. Blocks . . . . .3059
Figure 820. Bit timings . . . . .3059
Figure 821. Signal free time . . . . .3060
Figure 822. Arbitration phase . . . . .3060
Figure 823. SFT of three nominal bit periods . . . . .3060
Figure 824. Error bit timing . . . . .3061
Figure 825. Error handling . . . . .3063
Figure 826. TXERR detection . . . . .3064
Figure 827. Block diagram of debug infrastructure . . . . .3075
Figure 828. Power domains of debug infrastructure . . . . .3077
Figure 829. Clock domains of debug infrastructure . . . . .3078
Figure 830. SWD successful data transfer . . . . .3081
Figure 831. JTAG TAP state machine . . . . .3082
Figure 832. Debug and access port connections . . . . .3093
Figure 833. APB-D CoreSight component topology . . . . .3101
Figure 834. Global timestamp distribution . . . . .3109
Figure 835. Embedded cross trigger . . . . .3116
Figure 836. Mapping of trigger inputs to outputs . . . . .3118
Figure 837. ETF state transition diagram . . . . .3147
Figure 838. Cortex-M7 CoreSight topology . . . . .3216

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