59. Revision history

Table 445. Document revision history

DateRevisionChanges
13-Oct-20171Initial release.
05-Feb-20182

Added:

  • – Section 3.7.17: Flash configuration register (FLASH_CFGR)
  • – Section 12.6.7: DMAMUX size identification register (DMAMUX_SIDR)
  • – Section 12.6.8: DMAMUX IP identification register (DMAMUX_IPIDR)
  • – Section 12.6.9: DMAMUX version register (DMAMUX_VERR)
  • – Section 12.6.10: DMAMUX hardware configuration 1 register (DMAMUX_HWCFG1)
  • – Section 12.6.11: DMAMUX hardware configuration 2 register (DMAMUX_HWCFG2)
  • – CS boundary, refresh and communication regulation features on Section 19.2.4: Common functionality between the regular-command mode and HyperBus™
  • – Status flag polling mode configuration on Section 19.4.3: OCTOSPI regular-command mode configuration
  • – Section 19.4.7: OCTOSPI reconfiguration or deactivation
  • – Section 19.6.5: OCTOSPI device configuration register 4 (OCTOSPI_DCR4)
  • – Section 41.4.14: Timer counter reset
  • – Section 56.4.2: OTG_FS pin and internal signals
  • – Table 419: Compatibility of STM32 low power modes with the OTG

Figure 622: Updating OTG_HFIR dynamically (RLDCTRL = 1)

Deleted:

  • – Figure CS high time and clocked CS high timer
  • – OCTOSPI registers: OCTOSPI HW configuration register, (OCTOSPI_HWCFG), OCTOSPI version register (OCTOSPI_VER), OCTOSPI identification (OCTOSPI_ID), OCTOSPI HW magic ID (OCTOSPI_MID)

Table 445. Document revision history (continued)

DateRevisionChanges
05-Feb-20182
(continued)		Updated:
– Section 1.2: List of abbreviations for registers
– Section 2.4: Embedded SRAM
– Section 2.6.1: Boot configuration
– Section 3.3.2: Error code correction (ECC)
– Table 20: Flash interface - register map and reset values
– Section 5.1: Power supplies
– Figure 9: STM32L4P5xx/Q5xx, STM32L4S5xx/R5xx and STM32L4S7xx/L4R7xx power supply overview
– Figure 10: STM32L4S9xx/L4R9xx power supply overview
– Section 5.3.9: Standby mode
– Section 5.3.10: Shutdown mode
– Section 5.3.9: Standby mode
– Section 6.2: Clocks
– Section 6.2.11: Clock security system on LSE
– Section 6.4.4: PLL configuration register (RCC_PLLCFGGR)
– Section 8.3.8: External interrupt/wakeup lines
– Section 8.4.5: GPIO port input data register (GPIOx_IDR) (x = A to I)
– Table 43: STM32L4Rxxx and STM32L4Sxxx peripherals interconnect matrix
– Section 10.3.3: From ADC to timer (TIM1/TIM8)
– Section 10.3.5: From timer (TIM1/TIM3/TIM4/TIM6/TIM7/TIM8/TIM16/LPTIM1/LPTIM2) and EXTI to DFSDM1
– Section Table 54.: DMAMUX: assignment of multiplexer inputs to resources (STM32L4Rxxx and STM32L4Sxxx devices)
– Section 12.4.4: DMAMUX request line multiplexer
– Section 12.4.5: DMAMUX request generator
– Section 16.6.1: DMAMUX1 request line multiplexer channel x configuration register (DMAMUX1_CxCR)
– Section 19.6.7: DMAMUX1 request generator channel x configuration register (DMAMUX1_RGxCR)
– Figure 40: Virtual buffer and physical buffer memory map
– Dummy-cycles phase on Section 19.2.1: OCTOSPI regular-command mode
– Section 19.3.1: OCTOSPI indirect mode
– Section 19.3.2: OCTOSPI status flag polling mode
– Section 19.3.3: OCTOSPI memory-mapped mode
– Section 19.4.1: OCTOSPI system configuration
– Section 19.4.2: OCTOSPI device configuration
– Memory-mapped mode configuration on Section 19.4.3: OCTOSPI regular-command mode configuration
– Section 19.4.6: OCTOSPI busy bit and abort functionality
– Section 19.6.1: OCTOSPI control register (OCTOSPI_CR)
– Section 19.6.2: OCTOSPI device configuration register 1 (OCTOSPI_DCR1)

Table 445. Document revision history (continued)

DateRevisionChanges
05-Feb-20182
(continued)		Updated:
– Section 19.6.3: OCTOSPI device configuration register 2 (OCTOSPI_DCR2)
– Section 19.6.4: OCTOSPI device configuration register 3 (OCTOSPI_DCR3)
– Section 19.6.14: OCTOSPI communication configuration register (OCTOSPI_CCR)
– Section 19.6.15: OCTOSPI timing configuration register (OCTOSPI_TCR)
– Section 19.6.19: OCTOSPI wrap communication configuration register (OCTOSPI_WPCCR)
– Section 19.6.20: OCTOSPI wrap timing configuration register (OCTOSPI_WPTCR)
– Section 19.6.21: OCTOSPI wrap instruction register (OCTOSPI_WPIR)
– Section 19.6.22: OCTOSPI wrap alternate bytes register (OCTOSPI_WPABR)
– Section 19.6.24: OCTOSPI write timing configuration register (OCTOSPI_WTCR)
– Section 19.6.25: OCTOSPI write instruction register (OCTOSPI_WIR)
– Section 19.6.26: OCTOSPI write alternate bytes register (OCTOSPI_WABR)
– Section 19.6.27: OCTOSPI HyperBus™ latency configuration register (OCTOSPI_HLCR)
– Section 19.6.28: OCTOSPI register map
– Table 127: ADC internal input/output signals
– Table 128: ADC input/output pins
– Figure 89: ADC1 connectivity
– Section 21.4.7: Single-ended and differential input channels
– Table 134: Offset computation versus data resolution
– Section 21.6: ADC registers (for each ADC) (all registers naming updated, no updates on the content of the registers unless otherwise specified)
– Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
– Section 22.7.15: DAC calibration control register (DAC_CCR)
– Section 23.7: DCMI register description formatting of the reset values of all registers on this section were updated
– Table 188: DFSDM break connection
– Channel inputs selection on Section 28.4.4: Serial channel transceivers
– Section 28.7: DFSDM channel y registers (y=0..7) (all registers naming, no updates on the registers content unless otherwise specified)
– Section 28.8.13: DFSDM filter x extremes detector maximum register (DFSDM_FLTxEXMAX)

Table 445. Document revision history (continued)

DateRevisionChanges
05-Feb-20182
(continued)		Updated:
– Section 35.6: LTDC programming procedure
– Section 35.7.21: LTDC layer x blending factors configuration register (LTDC_LxBFCR)
– Section 31.6.10: TSC I/O group x counter register (TSC_IOGxCR)
– Section 37.4.25: TIMx capture/compare mode register 3 (TIMx_CCMR3)(x = 1, 8)
– Figure 369: Capture/Compare channel 1 main circuit
– Figure 370: Output stage of Capture/Compare channel (channel 1)
– Figure 437: Low-power timer block diagram
– Section 41.7.5: LPTIM control register (LPTIM_CR)
– Section 44.4.4: IWDG status register (IWDG_SR)
– Figure 454: Watchdog block diagram
– Figure 455: Window watchdog timing diagram
– Section 46.3.11: RTC reference clock detection
– Section 46.6.3: RTC control register (RTC_CR)
– Section 49: Inter-integrated circuit (I2C) interface: all section updated the SMBus version reference
– Section 49.2: I2C main features
– Table 336: I2C implementation
– Figure 459: I2C block diagram
– Figure 461: Setup and hold timings
– Section 49.4.1: I2C block diagram
– Section 49.6: I2C interrupts
– Table 356: Tolerance of the USART receiver when BRR [3:0] = 0000
– Table 357: Tolerance of the USART receiver when BRR[3:0] is different from 0000
– Section 50.8: USART registers in all subsections, the notes related to reserved bit/bitfield were updated
– Section 51.7: LPUART registers in all subsections, the notes related to reserved bit/bitfield were updated
– Clock generator programming in SPDIF generator mode on Section 53.4.12: SPDIF output
– Section 53.6.19: SAI PDM delay register (SAI_PDM Daly)
– Figure 601: CAN network topology
– Figure 604: bxCAN in silent mode
– Figure 607: Transmit mailbox states
– Figure 609: Filter bank scale configuration - Register organization
– Figure 610: Example of filter numbering
– Figure 613: Bit timing
– Figure 611: Filtering mechanism example
– Figure 615: Event flags and interrupt generation
– Figure 616: CAN mailbox registers
– Section 56.1: Introduction
– Table 416: OTG_FS implementation

Table 445. Document revision history (continued)

DateRevisionChanges
05-Feb-20182
(continued)		Updated:
– Figure 617: OTG_FS full-speed block diagram
– Section 56.7: OTG_FS as a USB host
– Section 56.9: OTG_FS low-power modes
– Figure 625: Interrupt hierarchy
– Section 56.15.1: OTG control and status register (OTG_GOTGCTL)
– Section 56.15.4: OTG USB configuration register (OTG_GUSBCFG)
– Section 56.15.7: OTG interrupt mask register (OTG_GINTMSK)
– Section 56.15.9: OTG receive status debug read [alternate] (OTG_GRXSTSR)
– Section 56.15.21: OTG device IN endpoint transmit FIFO x size register (OTG_DIEPTXFx)
– Section 56.15.24: OTG host frame interval register (OTG_HFIR)
– Section 56.15.30: OTG host channel x characteristics register (OTG_HCCHARx)
– Section 56.15.31: OTG host channel x interrupt register (OTG_HCINTx)
– Section 56.15.32: OTG host channel x interrupt mask register (OTG_HCINTMSKx)
– Section 56.15.35: OTG device configuration register (OTG_DCFG)
– Section 56.15.38: OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK)
– Section 56.15.38: OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK)
– Section 56.15.47: OTG device IN endpoint x interrupt register (OTG_DIEPINTx)
– Section 56.15.52: OTG device OUT endpoint x interrupt register (OTG_DOEPINTx)
– Section 56.16.4: Host programming model
– Figure 638: A-device SRP
– Figure 639: B-device SRP
– Table 442: Flexible TRACE pin assignment

Table 445. Document revision history (continued)

DateRevisionChanges
05-Mar-20183

Added:

  • – Section 22.3: DAC implementation

Updated:

  • – Section 1.2: List of abbreviations for registers
  • – Section 11: Direct memory access controller (DMA) and all subsections contents
  • – Section 22.7: DAC registers: naming conventions of all subsections
  • – Section 22.7.1: DAC control register (DAC_CR)
  • – Section 18.7.6: NOR/PSRAM controller registers
  • – Section 18.8.7: NAND Flash controller registers
  • – Table 118: FMC register map and reset values
  • – Section 35.7: LTDC registers: naming conventions and reset value format of all subsections
  • – Section 51.7.7: LPUART interrupt and status register [alternate] (LPUART_ISR)
  • – Section 51.7.9: LPUART interrupt flag clear register (LPUART_ICR)
  • – Table 369: LPUART register map and reset values
  • – Section 56.8.1: Host SOFs
  • – Section 56.8.2: Peripheral SOFs
  • – Section 56.11.3: FIFO RAM allocation
  • – Section 56.15: OTG_FS registers: naming conventions of all subsections

Deleted:

  • – From Section 12: DMA request multiplexer (DMAMUX): DMAMUX size identification register (DMAMUX_SIDR), DMAMUX IP identification register (DMAMUX_IPIDR), DMAMUX version register (DMAMUX_VERR), DMAMUX hardware configuration 1 register (DMAMUX_HWCFGR1) and DMAMUX hardware configuration 2 register (DMAMUX_HWCFGR2)

Table 445. Document revision history (continued)

DateRevisionChanges
03-May-20184Added:
– Section 1.1: General information
– Section 5.1.7: VDD12 domain including Figure 11: Internal main regulator overview
– Section Table 8.: Flash module - 1 Mbyte dual-bank organization, DB1M = 1 (64 bits read width)
– Section Table 9.: Flash module - 1 Mbyte single-bank organization, DB1M = 0 (128 bits read width)
Updated:
– Section 3.3.1: Flash memory organization
– Section 5.1.8: Dynamic voltage scaling management
– DB1M bit description on Section 3.4.1: Option bytes description and Section 3.7.8: Flash option register (FLASH_OPTR)
– Figure 454 was moved to the created Section 45.3.1: WWDG block diagram
– Section 8.4: GPIO registers: naming conventions of all subsections
– Figure 157: Dual-channel DAC block diagram
– Section 22: Digital-to-analog converter (DAC) naming conventions of all subsections
– Section 22.4.1: DAC block diagram
– Section 22.4.8: Noise generation
– Section 22.4.9: Triangle-wave generation
– Section Table 148.: Sample and refresh timings
– Section : Example of the sample and refresh time calculation with output buffer on on page 740
– Section 53.6: SAI registers was fully restructured
– Figure 54: Secure digital input/output MultiMediaCard interface (SDMMC) naming conventions of all subsections
– Figure 573: SDMMC block diagram
– Table 389: SDMMC internal input/output signals
– Table 390: SDMMC pins
– Figure 54.5.3: General description
– Table 391: SDMMC Command and data phase selection
– Table 391: SDMMC Command and data phase selection
– Figure 575: Control unit
– Table 408: CMD12 use cases
01-Feb-20195Updated:
– Table 8: Flash module - 1 Mbyte dual-bank organization, DB1M = 1 (64 bits read width).
– Figure 3: Memory map for STM32L4Rxxx and STM32L4Sxxx.
– Section 3.3.1: Flash memory organization.
– Address offset of Section 3.7.12: Flash WRP2 area A address register (FLASH_WRP2AR) and Section 3.7.15: Flash WRP1 area B address register (FLASH_WRP1BR)
– Section 57.6.1: MCU device ID code.
– Section 58.3: Package data register.

Table 445. Document revision history (continued)

DateRevisionChanges
10-Dec-20196

System and memory overview section

  • – Updated Section 2.1.10: BusMatrix .

Memory organization section

  • – Updated Section 2.4: Embedded SRAM

Embedded Flash memory section

  • – Updated Table 10: Flash module - 512 Kbytes dual-bank organization, DB1M = 1 (64 bits read width) removing note1.
  • – Updated Section 3.7.5: Flash status register (FLASH_SR) bit 17 type.

Power control (PWR) section

  • – Updated Table 27: Functionalities depending on the working mode .
  • – Updated Section 5.3.11: Auto-wakeup from low-power mode .

Reset and clock control (RCC) section

  • – Updated 'DLYCFGR' by 'RCC_DLYCFGR' in Section 6.4.33: OCTOSPI delay configuration register (RCC_DLYCFGR) and Section 6.4.34: RCC register map .
  • – Updated Figure 16: Clock tree for STM32L4Rxxx and STM32L4Sxxx devices .
  • – Updated Section 6.2.17: Internal/external clock measurement with TIM15/TIM16/TIM17 .
  • – Added Figure 18: Clock tree for STM32L4P5xx and STM32L4Q5xx devices .
  • – Updated OCTOSPI2_DLY and OCTOSPI1_DLY bit description in Section 6.4.33: OCTOSPI delay configuration register (RCC_DLYCFGR) .

General-purpose I/Os (GPIO) section

  • – Updated Section 8.3.2: I/O pin alternate function multiplexer and mapping additional functions paragraph.

Peripherals interconnect matrix section

  • – Updated Table 47: STM32L4+ Series peripherals interconnect matrix .
  • – Updated Section 10.3.3: From ADC to timer (TIM1/TIM8)
  • – Added Section 10.3.10: From ADC (ADC1) to ADC (ADC2) .
  • – Updated Section 10.3.16: From ADC (ADC1/ADC2) to DFSDM

Nested vectored interrupt controller (NVIC) section

  • – Updated Table 76: STM32L4Rxxx and STM32L4Sxxx vector table .
  • – Updated Table 77: STM32L4P5xx and STM32Q5xx vector table .

Parallel synchronous slave interface (PSSI) section

  • – Updated Section 25: Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32L4Q5xx only .

Digital filter for sigma delta modulators (DFSDM) section

  • – Updated Table 184: STM32L4P5xx and STM32L4Q5xx DFSDM1 implementation .

Table 445. Document revision history (continued)

DateRevisionChanges
10-Dec-20196
(continued)

Octo-SPI interface (OCTOSPI) section
Updated:
– Table 119: OCTOSPI implementation.
– Section 19.2: OCTOSPI main features
– Section 19.4.14: OCTOSPI Regular-command mode configuration 'OCTOSPI delayed data sampling when DQS is used' paragraph.
– Sending the instruction only once (SIOO)
– WRAP support part in Section 19.4.6: Specific features
– ABORT and EN bit description in Section 19.7.1: OCTOSPI control register (OCTOSPI_CR)
– DLYBYP bit description in Section 19.7.2: OCTOSPI device configuration register 1 (OCTOSPI_DCR1)
– LEVEL bit description in Section 19.7.6: OCTOSPI status register (OCTOSPI_SR)

OCTOSPI I/O manager (OCTOSPIM) section
Updated Ports for pin assignment from 3 to 2.

Analog digital converter (ADC) section
Updated:
– 2 ADCs/one interface, operating in dual mode
– Changed number of muxed channels to 19 (instead of 20)
– Section 21.2: ADC main features: DAC1 and DAC2 internal channels connected to ADC2 instead of ADC1
– Section 21.3: ADC implementation
– Figure 87: ADC block diagram
– Table 127: ADC internal input/output signals adding dac_out1 and dac_out2.
– Table 128: ADC input/output pins to support 2 ADCs
– Figure 88: ADC clock scheme to support 2 ADCs.
– Figure 89: ADC1 connectivity to support ADC2 and added Figure 90: ADC2 connectivity.
– Added Section 21.4.31: Dual ADC modes
– Added support for SMPPLUS
– Updated Section 21.4.32: Temperature sensor note in 'reading the temperature' paragraph.
– Updated Section 21.4.33: VBAT supply monitoring.

DSI Host (DSIHOST) section
– Updated Section 30: DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only.

True random number generator (RNG) sections
Updated Section 32: True random number generator (RNG) applied to STM32L4Rxxx and STM32L4Sxxx only.
– Section 32.3.5: RNG operation note.
– Section 32.7.3: RNG data register (RNG_DR).

Table 445. Document revision history (continued)

DateRevisionChanges
10-Dec-20196
(continued)

Section 33: True random number generator (RNG) applied to STM32L4Rxxx and STM32L4Sxxx only.

  • – Section 33.1: Introduction.
  • – Section 33.5: RNG processing time removing the table.
  • – Section 33.3.3: Random number generation.
  • – Table 225: RNG configurations
  • – Section 33.6.3: Data collection
  • – Section 33.7.3: RNG data register (RNG_DR).

AES hardware accelerator (AES) section

Updated:

  • – Section 34.2: AES main features with Integrated key scheduler features.
  • – Section 34.4.5: AES decryption round key preparation section title and initial paragraph modified
  • – notion of “round key” introduced in the document
  • – Table 227: AES internal input/output signals removing aes_itamp_out row.
  • – Initialization of AES and AES key registers removing notes.
  • – Table 234: Processing latency for ECB, CBC and CTR removing footnote
  • – Figure 267: CTR encryption.

Public key accelerator (PKA) section

Updated:

  • – Section 36: Public key accelerator (PKA) applied to STM32L4P5xx and STM32L4Q5xx only.
  • – Table 267: Modular exponentiation computation times.
  • – Table 268: ECC scalar multiplication computation times.
  • – Table 269: ECDSA signature average computation times.
  • – Table 270: ECDSA verification average computation times.
  • – Table 272: Montgomery parameters average computation times

Added Section 36.3.3: PKA reset and clocks..

Advanced-control timers (TIM1/TIM8) section

Updated:

  • – Section 37.3.29: Debug mode.
  • – Section 37.4.24: TIM8 option register 1 (TIM8_OR1) bit[1:0] ETR_DAC2_RMP[1:0] description.
  • – Section 37.4.28: TIM1 option register 2 (TIM1_OR2) bit[16:14] ETRSEL[2:0] description.
  • – Section 37.4.30: TIM8 option register 2 (TIM8_OR2) bit[16:14] ETRSEL[2:0] description.
  • – Section 37.4.32: TIM1 register map and Section 37.4.33: TIM8 register map.
  • – Figure 305: TIM8 ETR input circuitry.

Table 445. Document revision history (continued)

DateRevisionChanges
10-Dec-20196
(continued)

General-purpose timers (TIM15/TIM16/TIM17) section
Updated Section 39.6.17: TIM16 option register 1 (TIM16_OR1) TI1_RMP[2:0] description.

Low-power timer (LPTIM) section
Updated:
– Section 41: Low-power timer (LPTIM) applied to STM32L4Rxxx and STM32L4Sxxx only.
– Section 42: Low-power timer (LPTIM) applied to STM32L4P5xx and STM32L4Q5xx only.
– Section 42.6: LPTIM interrupts note
– Section 42.7.8: LPTIM counter register (LPTIM_CNT).

System window watchdog (WWDG) section
– Added Section 45.4: WWDG interrupts with content former ‘Advanced watchdog interrupt features’ paragraph.

Low-power universal asynchronous receiver transmitter (LPUART) section
– Added Section 51.3: LPUART implementation.

Serial audio interface (SAI) section
– SAI acronym added in all registers sections.

Secure digital input/output MultiMediaCard interface (SDMMC) section
– Updated Table 386: STM32L4P5xx and STM32L4Q5xx SDMMC features.

Debug support (DEBUG) section
Updated:
– Section 57.4.2: Flexible SWJ-DP pin assignment.
– Section 57.6.1: MCU device ID code REV_ID[15:0] description.

Table 445. Document revision history (continued)

DateRevisionChanges
12-Aug-20207

Memory organization section
Updated:
– Figure 3: Memory map for STM32L4Rxxx and STM32L4Sxxx.
– Figure 4: Memory map for STM32L4P5xx and STM32L4Q5xx.

Embedded Flash memory section
Updated:
– Table 6: Flash module - 2 Mbytes dual-bank organization, DBANK = 1 (64 bits read width).
– Table 7: Flash module - 2 Mbytes single-bank organization, DBANK = 0 (128 bits read width).
– Table 8: Flash module - 1 Mbyte dual-bank organization, DB1M = 1 (64 bits read width).
– Table 9: Flash module - 1 Mbyte single-bank organization, DB1M = 0 (128 bits read width).
– Table 10: Flash module - 512 Kbytes dual-bank organization, DB1M = 1 (64 bits read width).
– Table 11: Flash module - 512 Kbytes single-bank organization DB1M = 0 (128 bits read width).
– Table 12: Number of wait states according to CPU clock (HCLK) frequency.
– Section 3.4.1: Option bytes description:
- 'User and read protection option bytes' register DBANK and DB1M bit description.
- ST production value of: PCROP1 end address option bytes; WRP Area A address option bytes; WRP1 Area B address option bytes; PCROP2 end address option bytes; WRP2 Area A address option bytes; WRP Area B address option bytes.
– Section 3.4.2: Option bytes programming 'Activating Dual-bank mode (switching from DBANK=0 to DBANK=1)' paragraph.
– Section 3.7.7: Flash ECC register (FLASH_ECCR).
– Section 3.7.9: Flash PCROP1 Start address register (FLASH_PCROP1SR) reset value.
– Section 3.7.13: Flash PCROP2 Start address register (FLASH_PCROP2SR) reset value.
– Section 3.7.14: Flash PCROP2 End address register (FLASH_PCROP2ER) reset value.

Power control (PWR) section
Updated Table 27: Functionalities depending on the working mode.

Reset and clock control (RCC) section
Updated Section 6.4.29: Backup domain control register (RCC_BDCR) LSECSSON bit description.

Table 445. Document revision history (continued)

DateRevisionChanges
12-Aug-20207
(continued)

System configuration controller (SYSCFG) section
Updated:
– Section 9.2.2: SYSCFG configuration register 1 (SYSCFG_CFGR1) ANASWVDD bit9 and BOOSTEN bit 8 descriptions.
– Table 45: BOOSTEN and ANASWVDD set/reset (when at least one analog peripheral supplied by VDDA is enabled).

Peripherals interconnect matrix section
Updated:
– Table 47: STM32L4+ Series peripherals interconnect matrix LPTIM1, LPTIM2, DAC1_OUT1 and DAC1_OUT2.
– Section 10.3.4: From timer (TIM2/TIM4/TIM5/TIM6/TIM7/TIM8/LPTIM1/LPTIM2) and EXTI to DAC (internal channel 1 and channel 2).
– Section 10.3.12: From internal analog source to ADC and OPAMP (OPAMP1/OPAMP2).

DMA request multiplexer (DMAMUX) section
Updated:
– Table 55: DMAMUX: assignment of multiplexer inputs to resources (STM32L4P5xx and STM32L4Q5xx devices).

Touch sensing controller (TSC) section:
Updated Section 31.3.4: Charge transfer acquisition sequence.
Updated Figure 243: Charge transfer acquisition sequence.

Public key accelerator (PKA) section:
Updated Section 36.7.4: PKA RAM adding note.

Universal receiver/transmitter (USART/LPUART) section:
– Replaced microcontroller by device in the whole document.
– Updated PSC bitfield description in USART_GTPR register (alternate descriptions).
– Updated SBKF bit description in USART_ISR and LPUART_ISR (alternate description).
– Updated decimal and hexadecimal notation for values in Section : How to derive USARTDIV from USART_BRR register values.

Table 445. Document revision history (continued)

DateRevisionChanges
23-Nov-20208

Octo-SPI interface (OCTOSPI) section:

  • – Updated Section 19: Octo-SPI interface (OCTOSPI)

OCTOSPI I/O manager (OCTOSPIM) section:

Updated:

  • – Table 124: OCTOSPIM implementation on STM32L4+ Series
  • – Table 125: OCTOSPIM register map and reset values.
  • – Section 20.4.3: OCTOSPIM multiplexed mode
  • – Section 20.5.1: OCTOSPIM control register (OCTOSPIM_CR).

Analog-to-digital converters (ADC) section:

Updated:

  • – Table 127: ADC internal input/output signals.
  • – Section 21.4.7: Single-ended and differential input channels adding correspondence between ADCy_INPx and VINPi, ADCy_INNx and VINNi.
  • – Section 21.4.19: Injected channel management example related to interval between trigger events.

Public key accelerator (PKA) section:

Updated:

  • – Section 36.3.4: PKA public key acceleration
  • – Section 36.5.1: Supported elliptic curves.
  • – Table 273: PKA interrupt requests.

Universal synchronous/asynchronous (USART/UART) section:

Updated:

  • – Section 50.8.8: USART request register (USART_RQR) ABRREQ bit description.
  • – Section 50.8.9: USART interrupt and status register [alternate] (USART_ISR) ABRE bit description.

General-purpose timers (TIM2/TIM3/TIM4/TIM5) section:

  • – Updated Table 283: TIMx internal trigger connection.

DEBUG section:

  • – Updated Section 57.6.1: MCU device ID code adding V version.

Table 445. Document revision history (continued)

DateRevisionChanges
22-Jun-20219

Updated cover page

Embedded Flash memory section

Clock recovery system (CRS)

DMA request multiplexer (DMAMUX)

Nested vectored interrupt controller (NVIC) section

Cyclic redundancy check calculation unit (CRC)

Octo-SPI interface (OCTOSPI)

OCTOSPI I/O manager (OCTOSPIM)

Table 445. Document revision history (continued)

DateRevisionChanges
22-Jun-20219
continued

Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only

  • – Section 25.5.1: PSSI control register (PSSI_CR)
  • – Section 25.5.7: PSSI data register (PSSI_DR)

Digital filter for sigma delta modulators (DFSDM)

  • – Section 28.3: DFSDM implementation including both tables

Touch sensing controller (TSC)

  • – Section 31.3.2: Surface charge transfer acquisition overview including Figure 241: Surface charge transfer analog I/O group structure and Table 214: Acquisition sequence summary

True random number generator (RNG) applied to STM32L4Rxxx and STM32L4Sxxx only

  • – Section 32.3.3: Random number generation
  • – Section 32.6.2: Validation conditions
  • – Deleted section RNG health test control register (RNG_HTCR)

True random number generator (RNG) applied to STM32L4P5xx and STM32L4Q5xx only

  • – Section 33.3.3: Random number generation
  • – Section 33.5: RNG processing time

AES hardware accelerator (AES)

  • – Section 34.4.8: AES basic chaining modes (ECB, CBC)
  • – Section 34.4.9: AES counter (CTR) mode
  • – Table 228: CTR mode initialization vector definition
  • – Section 34.4.10: AES Galois/counter mode (GCM)
  • – Table 230: Initialization of SAES_IVRx registers in GCM mode
  • – Section 34.4.12: AES counter with CBC-MAC (CCM)
  • – Table 231: Initialization of AES_IVRx registers in CCM mode

Public key accelerator (PKA) applied to STM32L4P5xx and STM32L4Q5xx only

  • – Table 248: Montgomery multiplication

Advanced-control timers (TIM1/TIM8)

  • – Section 37.3.16: Using the break function

Table 445. Document revision history (continued)

DateRevisionChanges
22-Jun-20219
continued

General-purpose timers (TIM15/TIM16/TIM17)

Low-power timer (LPTIM) applied to STM32L4Rxxx and STM32L4Sxxx only

Low-power timer (LPTIM) applied to STM32L4P5xx and STM32L4Q5xx only

System window watchdog (WWDG)

Real-time clock (RTC) applied to STM32L4Rxxx and STM32L4Sxxx only

Real-time clock (RTC) applied to STM32L4P5xx and STM32L4Q5xx only

Universal synchronous/asynchronous receiver transmitter (USART/UART)

Table 445. Document revision history (continued)

DateRevisionChanges
22-Jun-20219
continued

Low-power universal asynchronous receiver transmitter (LPUART)

  • – Section 51.4.6: LPUART receiver
  • – Table 363: Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz
  • – Figure 523: Transmission using DMA
  • – Section 51.4.14: LPUART low-power management
  • – Section 51.7.3: LPUART control register 2 (LPUART_CR2)

Serial audio interface (SAI)

  • – Notes of Figure 554: Detailed PDM interface block diagram
  • – Section 53.6.9: SAI slot register (SAI_BSLTR)

Secure digital input/output MultiMediaCard interface (SDMMC)

  • – Section 54.10.9: SDMMC data control register (SDMMC_DCTRL)

Controller area network (bxCAN)

  • – Figure 614: CAN frames

USB on-the-go full-speed (OTG_FS)

  • – Section 56.15.5: OTG reset register (OTG_GRSTCTL)
  • – Section 56.15.17: OTG core LPM configuration register (OTG_GLPMCFG)
  • – Section 56.15.45: OTG device control IN endpoint 0 control register (OTG_DIEPCTL0)
  • – Section 56.15.54: OTG device OUT endpoint x control register (OTG_DOEPCTLx)
  • – Section 56.15.55: OTG device OUT endpoint x transfer size register (OTG_DOEPTSIZx)