21. Analog-to-digital converters (ADC)

21.1 Introduction

This section describes the implementation of up to 2 ADCs:

• ADC1 and ADC2 are tightly coupled and can operate in dual mode (ADC1 is master).

Each ADC consists of a 12-bit successive approximation analog-to-digital converter.

Each ADC has up to 19 multiplexed channels. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register.

The ADCs are mapped on the AHB bus to allow fast data handling.

The analog watchdog features allow the application to detect if the input voltage goes outside the user-defined high or low thresholds.

A built-in hardware oversampler allows to improve analog performance while off-loading the related computational burden from the CPU.

An efficient low-power mode is implemented to allow very low consumption at low frequency.

21.2 ADC main features

• High-performance features
- – Up to 2 ADCs which can operate in dual mode:
  ADC1 is connected to 16 external channels + 3 internal channels
  ADC2 is connected to 16 external channels + 2 internal channels
- – 12, 10, 8 or 6-bit configurable resolution
- – ADC conversion time is independent from the AHB bus clock frequency
- – Faster conversion time by lowering resolution
- – Manage single-ended or differential inputs
- – AHB slave bus interface to allow fast data handling
- – Self-calibration
- – Channel-wise programmable sampling time
- – Up to four injected channels (analog inputs assignment to regular or injected channels is fully configurable)
- – Hardware assistant to prepare the context of the injected channels to allow fast context switching
- – Data alignment with in-built data coherency
- – Data can be managed by DMA for regular channel conversions
- – Data can be routed to DFSDM for post processing
- – 4 dedicated data registers for the injected channels
• Oversampler
- – 16-bit data register
- – Oversampling ratio adjustable from 2 to 256
- – Programmable data shift up to 8-bit
• Low-power features
- – Speed adaptive low-power mode to reduce ADC consumption when operating at low frequency
- – Allows slow bus frequency application while keeping optimum ADC performance
- – Provides automatic control to avoid ADC overrun in low AHB bus clock frequency application (auto-delayed mode)
• Number of external analog input channels per ADC
- – Up to 5 fast channels from GPIO pads
- – Up to 11 slow channels from GPIO pads
• In addition, there are several internal dedicated channels
- – The internal reference voltage ( $V_{REFINT}$ ), connected to ADC1
- – The internal temperature sensor ( $V_{TS}$ ), connected to ADC1
- – The $V_{BAT}$ monitoring channel ( $V_{BAT}/3$ ), connected to ADC1
- – DAC1 and DAC2 internal channels, connected to ADC2
• Start-of-conversion can be initiated:
- – By software for both regular and injected conversions
- – By hardware triggers with configurable polarity (internal timers events or GPIO input events) for both regular and injected conversions

• Conversion modes
- – Each ADC can convert a single channel or can scan a sequence of channels
- – Single mode converts selected inputs once per trigger
- – Continuous mode converts selected inputs continuously
- – Discontinuous mode
• Dual ADC mode for ADC1 and 2
• Interrupt generation at ADC ready, the end of sampling, the end of conversion (regular or injected), end of sequence conversion (regular or injected), analog watchdog 1, 2 or 3 or overrun events
• 3 analog watchdogs per ADC
• ADC input range: $V_{REF-} \leq V_{IN} \leq V_{REF+}$

Figure 87 shows the block diagram of one ADC.

21.3 ADC implementation

Table 126. ADC features

ADC modes/features	ADC1	ADC2 ⁽¹⁾
Dual mode	X ⁽¹⁾	X
DFSDM interface	X	X
SMPPLUS control ⁽¹⁾	X	X

1. Available only on STM32L4Q5xx and STM32L4P5xx.

21.4 ADC functional description

21.4.1 ADC block diagram

Figure 87 shows the ADC block diagram and Table 128 gives the ADC pin description.

Figure 87. ADC block diagram

The block diagram illustrates the internal architecture of the ADC. At the core is the SAR ADC block, which receives analog input ( V _IN) and produces CONVERTED DATA . The Bias & Ref block provides reference voltages and includes an ADCAL (self calibration) input. The Input selection & scan control block manages ADC_INP[16:1] and ADC_INN[16:1] channels, with V _REF+(1.62 to 3.6 V) and V _REF-inputs. It also includes JAUTO , ADC_JSQRx , ADC_SQRx , and CONT (single/cont) settings. V _TS, dac_out1 ( V _REFINT, V _BAT/3), and dac_out2 ( V _INN[18:0]) are also shown. The Start & Stop Control block includes AUTDLY (auto delayed), ADSTP (stop conv), and S/W trigger inputs. EXTI lines ( EXT0 to EXT15 ) are mapped at the product level and connected to EXTEN[1:0] (trigger enable and edge selection) and EXTSEL[3:0] (trigger selection). JEXT lines ( JEXT0 to JEXT15 ) are also mapped at the product level and connected to JEXTEN[1:0] (trigger enable and edge selection) and JEXTSEL[3:0] (trigger selection). The SAR ADC block has various configuration registers: OVERMOD (overrun mode), ALIGN (left/right), RES[1:0] (12, 10, 8 bits), JOFFSETx[11:0] , and JOFFSETx_CH[11:0] . It also includes DISCEN , DISCNUM[0] (Discontinuous mode), AWD1 , AWD2 , and AWD3 (Analog watchdog 1,2,3) inputs. The AHB interface block includes RDATA[11:0] , JDATA1[11:0] , JDATA2[11:0] , JDATA3[11:0] , and JDATA4[11:0] registers. It connects to Cortex M4 with FPU (ADC Interrupt, IRQ), DMA (DMA request), and DFSDM (16-bit interface). Control signals include AREADY , EOSMP , EOC , EOS , OVR , JEOS , JQOVF , and AWDx . The Oversampler block is connected to the SAR ADC and includes DMACFG and DMAEN inputs. ROVSM , TROVS , OVSS[3:0] , OVSR[2:0] , JOVSE , and ROVSE (Oversampling options) are also shown. The Analog watchdog 1,2,3 block includes AWD1 , AWD2 , and AWD3 inputs and AWD1_OUT , AWD2_OUT , and AWD3_OUT outputs connected to TIMERS (ETR). AWD1EN , JAWD1EN , AWD1SGL , AWDCH1[4:0] , LT1[11:0] , HT1[11:0] , AWDCH2[18:0] , LT2[7:0] , HT2[7:0] , AWDCH3[18:0] , LT3[7:0] , and HT3[7:0] are also shown. The JQM (Injected Context Queue Mode) and JDISCEN , JDISCNUM[2:0] (Discontinuous mode) are also indicated.

Detailed block diagram of the ADC functional description, showing internal components like SAR ADC, Bias & Ref, and various control interfaces.

MSV43756V7

21.4.2 ADC pins and internal signals

Table 127. ADC internal input/output signals

Internal signal name	Signal type	Description
EXT[15:0]	Inputs	Up to 16 external trigger inputs for the regular conversions (can be connected to on-chip timers). These inputs are shared between the ADC master and the ADC slave.
JEXT[15:0]	Inputs	Up to 16 external trigger inputs for the injected conversions (can be connected to on-chip timers). These inputs are shared between the ADC master and the ADC slave.
ADC_AWDx_OUT	Output	Internal analog watchdog output signal connected to on-chip timers (x = Analog watchdog number 1,2,3)
V _TS	Input	Output voltage from internal temperature sensor
dac_out1	Input	DAC internal channel 1
V _REFINT	Input	Output voltage from internal reference voltage
dac_out2	Input	DAC internal channel 2
V _BAT	Input supply	External battery voltage supply

Table 128. ADC input/output pins

Pin name	Signal type	Comments
V _REF+	Input, analog reference positive	The higher/positive reference voltage for the ADC, $1.62 \text{ V} \leq V_{\text{REF+}} \leq V_{\text{DDA}}$
V _DDA	Input, analog supply	Analog power supply equal V _DDA: $1.62 \text{ V} \leq V_{\text{DDA}} \leq 3.6 \text{ V}$
V _REF-	Input, analog reference negative	The lower/negative reference voltage for the ADC. V _REF-is internally connected to V _SSA
V _SSA	Input, analog supply ground	Ground for analog power supply. On device package which do not have a dedicated V _SSApin, V _SSAis internally connected to V _SS.
V _INPi	Positive analog input channels for each ADC	Connected either to ADCx_INPi external channels or to internal channels. This input is converted in single-ended mode
V _INNi	Negative analog input channels for each ADC	Connected either to V _REF-or to external channels: ADCx_INNi and ADCx_INPi+1].

Table 128. ADC input/output pins (continued)

Pin name	Signal type	Comments
ADCx_INNi	Negative external analog input signals	Up to 16 analog input channels (x = ADC number = 1 or 2) Refer to Section 21.4.4: ADC1/2 connectivity for details.
ADCx_INPi	Positive external analog input signals	Up to 10 analog input channels (x = ADC number = 1 or 2) Refer to Section 21.4.4: ADC1/2 connectivity for details

21.4.3 ADC clocks

Dual clock domain architecture

The dual clock-domain architecture means that the ADC clock is independent from the AHB bus clock.

The input clock is the same for all ADCs and can be selected between two different clock sources (see Figure 88: ADC clock scheme ):

The ADC clock can be a specific clock source, derived from the following clock sources:
- – The system clock
- – PLLSAI1 (single ADC implementation)
Refer to RCC Section for more information on how to generate ADC dedicated clock. To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be reset.
The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). In this mode, a programmable divider factor can be selected (/1, 2 or 4 according to bits CKMODE[1:0]).
To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be different from “00”.

Note: For option 2), a prescaling factor of 1 (CKMODE[1:0]=01) can be used only if the AHB prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register).

Option 1) has the advantage of reaching the maximum ADC clock frequency whatever the AHB clock scheme selected. The ADC clock can eventually be divided by the following ratio: 1, 2, 4, 6, 8, 12, 16, 32, 64, 128, 256; using the prescaler configured with bits PRESC[3:0] in the ADCx_CCR register.

Option 2) has the advantage of bypassing the clock domain resynchronizations. This can be useful when the ADC is triggered by a timer and if the application requires that the ADC is precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant time is added by the resynchronizations between the two clock domains).

Figure 88. ADC clock scheme

The diagram illustrates the internal clock scheme for ADC1 and ADC2. On the left, the RCC (Reset and clock controller) provides two main clock signals: HCLK and ADC12_CK. The HCLK signal is connected to the AHB interface within the ADC1 and ADC2 block. The ADC12_CK signal is connected to a clock divider block labeled "/1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256". This divider is controlled by Bits PREC[3:0] of ADCx_CCR. Another clock divider block labeled "/1 or /2 or /4" is also present, controlled by Bits CKMODE[1:0] of ADCx_CCR. Both dividers feed into a multiplexer labeled "Others". The multiplexer is controlled by Bits CKMODE[1:0] of ADCx_CCR. The output of the multiplexer is connected to the Analog ADC1 (master) and Analog ADC2 (slave) blocks. The diagram is labeled MSv50635V1 in the bottom right corner.

Figure 88. ADC clock scheme diagram showing the internal clock architecture of ADC1 and ADC2. The diagram shows the RCC (Reset and clock controller) providing HCLK and ADC12_CK signals. The ADC1 and ADC2 block contains an AHB interface, a clock divider (/1 or /2 or /4) controlled by Bits CKMODE[1:0] of ADCx_CCR, and a clock divider (/1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256) controlled by Bits PREC[3:0] of ADCx_CCR. These dividers feed into a multiplexer (Others) controlled by Bits CKMODE[1:0] of ADCx_CCR. The output of the multiplexer is connected to Analog ADC1 (master) and Analog ADC2 (slave).

Clock ratio constraint between ADC clock and AHB clock

There are generally no constraints to be respected for the ratio between the ADC clock and the AHB clock except if some injected channels are programmed. In this case, it is mandatory to respect the following ratio:

• $F_{HCLK} \geq F_{ADC} / 4$ if the resolution of all channels are 12-bit or 10-bit
• $F_{HCLK} \geq F_{ADC} / 3$ if there are some channels with resolutions equal to 8-bit (and none with lower resolution)
• $F_{HCLK} \geq F_{ADC} / 2$ if there are some channels with resolutions equal to 6-bit

21.4.4 ADC1/2 connectivity

ADC1 and ADC2 are tightly coupled and share some external channels as described in the below figures.

Figure 89. ADC1 connectivity

The diagram illustrates the internal architecture of the ADC1. On the left, external pins are listed: ADC12_INP1, ADC12_INN1, ADC12_INP2, ADC12_INN2, ADC12_INP3, ADC12_INN3, ADC12_INP4, ADC12_INN4, ADC12_INP5, ADC12_INN5, ADC12_INP6, ADC12_INN6, ADC12_INP7, ADC12_INN7, ADC12_INP8, ADC12_INN8, ADC12_INP9, ADC12_INN9, ADC12_INP10, ADC12_INN10, ADC12_INP11, ADC12_INN11, ADC12_INP12, ADC12_INN12, ADC12_INP13, ADC12_INN13, ADC12_INP14, ADC12_INN14, ADC12_INP15, ADC12_INN15, and ADC12_INP16. These are connected to internal channel selection switches. The switches are labeled with V_INP[0] through V_INP[18] and V_INN[0] through V_INN[18]. Channels V_INP[0], V_INP[1], V_INP[2], V_INP[3], V_INP[4], V_INP[5], and V_INP[6] are designated as 'Fast channel'. Channels V_INN[6], V_INP[7], V_INN[7], V_INP[8], V_INN[8], V_INP[9], V_INN[9], V_INP[10], V_INN[10], V_INP[11], V_INN[11], V_INP[12], V_INN[12], V_INP[13], V_INN[13], V_INP[14], V_INN[14], V_INP[15], V_INN[15], V_INP[16], V_INN[16], V_INP[17], V_INN[17], V_INP[18], and V_INN[18] are designated as 'Slow channel'. The selected channels are connected to the positive input (V_INP) and negative input (V_INN) of a SAR ADC1 block. Reference voltages V_REF+, V_REF-, and V_INN are also connected to the SAR ADC1 block. Additional external connections include V_REFINT, V_REF-, V_TS, and V_BAT/3.

Schematic diagram of ADC1 connectivity showing various input channels (V_INP[0] to V_INP[18]) connected to a SAR ADC1 block. The diagram includes labels for external pins like ADC12_INP1, ADC12_INN1, and internal channel types like 'Fast channel' and 'Slow channel'. Reference voltages V_REFINT, V_REF-, V_REF+, and V_INN are also shown.

MSV41967V5

Figure 90. ADC2 connectivity

The diagram illustrates the internal architecture and connectivity of the ADC2 block. On the left, external pins are listed: ADC12_INP1 through ADC12_INP16, ADC12_INN1 through ADC12_INN16, dac_out1, and dac_out2. These pins connect to internal signal lines. The internal lines are labeled with V_INP and V_INN signals, numbered 0 through 18. V_INP[0] and V_INN[0] are connected to V_REF-. V_INP[1] and V_INN[1] are connected to V_REF-. V_INP[2] and V_INN[2] are labeled as 'Fast channel'. V_INP[3] and V_INN[3] are labeled as 'Fast channel'. V_INP[4] and V_INN[4] are labeled as 'Fast channel'. V_INP[5] and V_INN[5] are labeled as 'Fast channel'. V_INP[6] and V_INN[6] are labeled as 'Slow channel'. V_INP[7] and V_INN[7] are labeled as 'Slow channel'. V_INP[8] and V_INN[8] are labeled as 'Slow channel'. V_INP[9] and V_INN[9] are labeled as 'Slow channel'. V_INP[10] and V_INN[10] are labeled as 'Slow channel'. V_INP[11] and V_INN[11] are labeled as 'Slow channel'. V_INP[12] and V_INN[12] are labeled as 'Slow channel'. V_INP[13] and V_INN[13] are labeled as 'Slow channel'. V_INP[14] and V_INN[14] are labeled as 'Slow channel'. V_INP[15] and V_INN[15] are labeled as 'Slow channel'. V_INP[16] and V_INN[16] are labeled as 'Slow channel'. V_INP[17] and V_INN[17] are labeled as 'Slow channel'. V_INP[18] and V_INN[18] are labeled as 'Slow channel'. A 'Channel selection' block, indicated by a dashed vertical line, selects between these internal signals. The selected signal is then sent to a SAR ADC2 block. The SAR ADC2 block has inputs for V_INP and V_INN, and reference inputs for V_REF+ and V_REF-.

ADC2 connectivity diagram showing internal signal paths, channel selection, and external connections to a SAR ADC2 block.

MSV50636V4

21.4.5 Slave AHB interface

The ADCs implement an AHB slave port for control/status register and data access. The features of the AHB interface are listed below:

• Word (32-bit) accesses
• Single cycle response
• Response to all read/write accesses to the registers with zero wait states.

The AHB slave interface does not support split/retry requests, and never generates AHB errors.

21.4.6 ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN)

By default, the ADC is in Deep-power-down mode where its supply is internally switched off to reduce the leakage currents (the reset state of bit DEEPPWD is 1 in the ADC_CR register).

To start ADC operations, it is first needed to exit Deep-power-down mode by setting bit DEEPPWD=0.

When ADC operations are complete, the ADC can be disabled (ADEN=0). It is possible to save power by also disabling the ADC voltage regulator. This is done by writing bit ADVREGEN=0.

Then, to save more power by reducing the leakage currents, it is also possible to re-enter in ADC Deep-power-down mode by setting bit DEEPPWD=1 into ADC_CR register. This is particularly interesting before entering Stop mode.

Note: Writing DEEPPWD=1 automatically disables the ADC voltage regulator and bit ADVREGEN is automatically cleared.

When the internal voltage regulator is disabled (ADVREGEN=0), the internal analog calibration is kept.

In ADC Deep-power-down mode (DEEPPWD=1), the internal analog calibration is lost and it is necessary to either relaunch a calibration or re-apply the calibration factor which was previously saved (refer to Section 21.4.8: Calibration (ADCAL, ADCALDIF, ADC_CALFACT) ).

21.4.7 Single-ended and differential input channels

Channels can be configured to be either single-ended input or differential input by programming DIFSEL[i] bits in the ADC_DIFSEL register. This configuration must be written while the ADC is disabled (ADEN=0). Note that the DIFSEL[i] bits corresponding to single-ended channels are always programmed at 0.

In single-ended input mode, the analog voltage to be converted for channel “i” is the difference between the ADCy_INPx external voltage equal to $V_{INP[i]}$ (positive input) and $V_{REF-}$ (negative input).

In differential input mode, the analog voltage to be converted for channel “i” is the difference between the ADCy_INPx external voltage positive input equal to $V_{INP[i]}$ , and the ADCy_INNx negative input equal to $V_{INN[i]}$ .

The input voltage in differential mode ranges from $V_{REF-}$ to $V_{REF+}$ , which makes a full scale range of $2 \times V_{REF+}$ . When $V_{INP[i]}$ equals $V_{REF-}$ , $V_{INN[i]}$ equals $V_{REF+}$ and the maximum

negative input differential voltage ( $V_{REF-}$ ) corresponds to 0x000 ADC output. When $V_{INP[i]}$ equals $V_{REF+}$ , $V_{INN[i]}$ equals $V_{REF-}$ and the maximum positive input differential voltage ( $V_{REF+}$ ) corresponds to 0xFFF ADC output. When $V_{INP[i]}$ and $V_{INN[i]}$ are connected together, the zero input differential voltage corresponds to 0x800 ADC output.

The ADC sensitivity in differential mode is twice smaller than in single-ended mode.

When ADC is configured as differential mode, both inputs should be biased at $(V_{REF+}) / 2$ voltage. Refer to the device datasheet for the allowed common mode input voltage $V_{CMIN}$ .

The input signals are supposed to be differential (common mode voltage should be fixed).

Internal channels (such as $V_{TS}$ and $V_{REFINT}$ ) are used in single-ended mode only.

For a complete description of how the input channels are connected for each ADC, refer to Section 21.4.4: ADC1/2 connectivity .

Caution: When configuring the channel “i” in differential input mode, its negative input voltage $V_{INN[i]}$ is connected to another channel. As a consequence, this channel is no longer usable in single-ended mode or in differential mode and must never be configured to be converted. Some channels are shared between ADC1/ADC2: this can make the channel on the other ADC unusable. Only exception is interleaved mode for ADC master and the slave.

21.4.8 Calibration (ADCAL, ADCALDIF, ADC_CALFACT)

Each ADC provides an automatic calibration procedure which drives all the calibration sequence including the power-on/off sequence of the ADC. During the procedure, the ADC calculates a calibration factor which is 7-bit wide and which is applied internally to the ADC until the next ADC power-off. During the calibration procedure, the application must not use the ADC and must wait until calibration is complete.

Calibration is preliminary to any ADC operation. It removes the offset error which may vary from chip to chip due to process or bandgap variation.

The calibration factor to be applied for single-ended input conversions is different from the factor to be applied for differential input conversions:

• Write ADCALDIF=0 before launching a calibration which will be applied for single-ended input conversions.
• Write ADCALDIF=1 before launching a calibration which will be applied for differential input conversions.

The calibration is then initiated by software by setting bit ADCAL=1. Calibration can only be initiated when the ADC is disabled (when ADEN=0). ADCAL bit stays at 1 during all the calibration sequence. It is then cleared by hardware as soon the calibration completes. At this time, the associated calibration factor is stored internally in the analog ADC and also in the bits CALFACT_S[6:0] or CALFACT_D[6:0] of ADC_CALFACT register (depending on single-ended or differential input calibration)

The internal analog calibration is kept if the ADC is disabled (ADEN=0). However, if the ADC is disabled for extended periods, then it is recommended that a new calibration cycle is run before re-enabling the ADC.

The internal analog calibration is lost each time the power of the ADC is removed (example, when the product enters in Standby or VBAT mode). In this case, to avoid spending time recalibrating the ADC, it is possible to re-write the calibration factor into the ADC_CALFACT register without recalibrating, supposing that the software has previously saved the calibration factor delivered during the previous calibration.

The calibration factor can be written if the ADC is enabled but not converting (ADEN=1 and ADSTART=0 and JADSTART=0). Then, at the next start of conversion, the calibration factor will automatically be injected into the analog ADC. This loading is transparent and does not add any cycle latency to the start of the conversion. It is recommended to recalibrate when $V_{REF+}$ voltage changed more than 10%.

Software procedure to calibrate the ADC

1. Ensure DEEPPWD=0, ADVREGEN=1 and that ADC voltage regulator startup time has elapsed.
2. Ensure that ADEN=0.
3. Select the input mode for this calibration by setting ADCALDIF=0 (single-ended input) or ADCALDIF=1 (differential input).
4. Set ADCAL=1.
5. Wait until ADCAL=0.
6. The calibration factor can be read from ADC_CALFACT register.

Figure 91. ADC calibration

Timing diagram for ADC calibration showing ADCALDIF, ADCAL, ADC State, and CALFACT_x[6:0] signals over time. It includes a legend for ADCALDIF (0: Single-ended input, 1: Differential input), a timing interval t_CAB, and state transitions for the ADC State (OFF, Startup, Calibrate, OFF).

The figure is a timing diagram illustrating the ADC calibration process. It consists of four horizontal signal lines and a legend.

ADCALDIF: A signal line at the top. A legend indicates that '0' represents 'Single-ended input' and '1' represents 'Differential input'.
ADCAL: A signal line below ADCALDIF. It shows a pulse that goes high when calibration starts and returns low when it ends. The duration of this pulse is labeled $t_{CAB}$ .
ADC State: A state transition diagram showing four states: OFF, Startup, Calibrate, and OFF. The 'Calibrate' state corresponds to the duration of the ADCAL pulse.
CALFACT_x[6:0]: A signal line at the bottom representing the calibration factor. It is shown as '0x00' during the 'Startup' and 'Calibrate' states, and as 'Calibration factor' after the ADC returns to the 'OFF' state.

Below the signal lines, there is a legend for the rising edges of the signals:

A box containing two rising edge symbols: the first is labeled 'by S/W' (software) and the second is labeled 'by H/W' (hardware).
A box labeled 'Indicative timings'.

The diagram is identified by the code MSv30263V2 in the bottom right corner.

Timing diagram for ADC calibration showing ADCALDIF, ADCAL, ADC State, and CALFACT_x[6:0] signals over time. It includes a legend for ADCALDIF (0: Single-ended input, 1: Differential input), a timing interval t_CAB, and state transitions for the ADC State (OFF, Startup, Calibrate, OFF).

Software procedure to re-inject a calibration factor into the ADC

1. Ensure ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing).
2. Write CALFACT_S and CALFACT_D with the new calibration factors.
3. When a conversion is launched, the calibration factor will be injected into the analog ADC only if the internal analog calibration factor differs from the one stored in bits CALFACT_S for single-ended input channel or bits CALFACT_D for differential input channel.

Figure 92. Updating the ADC calibration factor

Timing diagram for updating the ADC calibration factor. It shows the ADC state (Ready, Converting channel), Internal calibration factor[6:0] (F1, F2), Start conversion (hardware or software), WRITE ADC_CALFACT, and CALFACT_S[6:0] signals over time. The diagram illustrates that the internal calibration factor is updated to F2 when the WRITE ADC_CALFACT signal is asserted by software (s/w) while the ADC is in a Ready state. The CALFACT_S[6:0] register is also updated to F2. The diagram includes a legend for 'by s/w' (software) and 'by h/w' (hardware) triggers.

Converting single-ended and differential analog inputs with a single ADC

If the ADC is supposed to convert both differential and single-ended inputs, two calibrations must be performed, one with ADCALDIF=0 and one with ADCALDIF=1. The procedure is the following:

1. Disable the ADC.
2. Calibrate the ADC in single-ended input mode (with ADCALDIF=0). This updates the register CALFACT_S[6:0].
3. Calibrate the ADC in differential input modes (with ADCALDIF=1). This updates the register CALFACT_D[6:0].
4. Enable the ADC, configure the channels and launch the conversions. Each time there is a switch from a single-ended to a differential inputs channel (and vice-versa), the calibration will automatically be injected into the analog ADC.

Figure 93. Mixing single-ended and differential channels

Timing diagram for mixing single-ended and differential channels. It shows the Trigger event, ADC state (RDY, CONV CH 1 to 4), Internal calibration factor[6:0] (F2, F3), CALFACT_S[6:0] (F2), and CALFACT_D[6:0] (F3) signals. The diagram shows that the internal calibration factor automatically switches between F2 (for single-ended channels) and F3 (for differential channels) as the ADC state changes between CONV CH 1 (Single ended) and CONV CH 2 (Differential). The CALFACT_S[6:0] register remains at F2, and the CALFACT_D[6:0] register remains at F3.

21.4.9 ADC on-off control (ADEN, ADDIS, ADRDY)

First of all, follow the procedure explained in Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) .

Once DEEPPWD=0 and ADVREGEN=1, the ADC can be enabled and the ADC needs a stabilization time of $t_{STAB}$ before it starts converting accurately, as shown in Figure 94 . Two control bits enable or disable the ADC:

• ADEN=1 enables the ADC. The flag ADRDY will be set once the ADC is ready for operation.
• ADDIS=1 disables the ADC. ADEN and ADDIS are then automatically cleared by hardware as soon as the analog ADC is effectively disabled.

Regular conversion can then start either by setting ADSTART=1 (refer to Section 21.4.18: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) ) or when an external trigger event occurs, if triggers are enabled.

Injected conversions start by setting JADSTART=1 or when an external injected trigger event occurs, if injected triggers are enabled.

Software procedure to enable the ADC

1. Clear the ADRDY bit in the ADC_ISR register by writing '1'.
2. Set ADEN=1.
3. Wait until ADRDY=1 (ADRDY is set after the ADC startup time). This can be done using the associated interrupt (setting ADRDYIE=1).
4. Clear the ADRDY bit in the ADC_ISR register by writing '1' (optional).

Caution: ADEN bit cannot be set when ADCAL is set and during four ADC clock cycles after the ADCAL bit is cleared by hardware (end of the calibration).

Software procedure to disable the ADC

1. Check that both ADSTART=0 and JADSTART=0 to ensure that no conversion is ongoing. If required, stop any regular and injected conversion ongoing by setting ADSTP=1 and JADSTP=1 and then wait until ADSTP=0 and JADSTP=0.
2. Set ADDIS=1.
3. If required by the application, wait until ADEN=0, until the analog ADC is effectively disabled (ADDIS will automatically be reset once ADEN=0).

Figure 94. Enabling / disabling the ADC

Timing diagram showing the sequence of events for enabling and disabling the ADC. The diagram includes four signal lines: ADEN, ADRDY, ADDIS, and ADC state. ADEN is set by software (S/W) to enable the ADC. ADRDY goes high after a stabilization time tSTAB. ADDIS is set by hardware (H/W) to disable the ADC. The ADC state transitions from OFF to Startup, then RDY, then Converting CH, then RDY, then REQ-OFF, and finally back to OFF.

The diagram illustrates the timing for enabling and disabling the ADC. The ADEN signal is set by software (S/W) to enable the ADC. The ADRDY signal goes high after a stabilization time $t_{STAB}$ . The ADDIS signal is set by hardware (H/W) to disable the ADC. The ADC state transitions from OFF to Startup, then RDY, then Converting CH, then RDY, then REQ-OFF, and finally back to OFF.

Legend:
by S/W $\uparrow$ (Software set)
by H/W $\downarrow$ (Hardware set)

MSV30264V2

Timing diagram showing the sequence of events for enabling and disabling the ADC. The diagram includes four signal lines: ADEN, ADRDY, ADDIS, and ADC state. ADEN is set by software (S/W) to enable the ADC. ADRDY goes high after a stabilization time tSTAB. ADDIS is set by hardware (H/W) to disable the ADC. The ADC state transitions from OFF to Startup, then RDY, then Converting CH, then RDY, then REQ-OFF, and finally back to OFF.

21.4.10 Constraints when writing the ADC control bits

The software is allowed to write the RCC control bits to configure and enable the ADC clock (refer to RCC Section), the DIFSEL[i] control bits in the ADC_DIFSEL register and the control bits ADCAL and ADEN in the ADC_CR register, only if the ADC is disabled (ADEN must be equal to 0).

The software is then allowed to write the control bits ADSTART, JADSTART and ADDIS of the ADC_CR register only if the ADC is enabled and there is no pending request to disable the ADC (ADEN must be equal to 1 and ADDIS to 0).

For all the other control bits of the ADC_CFGR, ADC_SMPRx, ADC_SQRy, ADC_JDRy, ADC_OFRy, ADC_OFCHRy and ADC_IER registers:

• For control bits related to configuration of regular conversions, the software is allowed to write them only if the ADC is enabled (ADEN=1) and if there is no regular conversion ongoing (ADSTART must be equal to 0).
• For control bits related to configuration of injected conversions, the software is allowed to write them only if the ADC is enabled (ADEN=1) and if there is no injected conversion ongoing (JADSTART must be equal to 0).

The software is allowed to write the ADSTP or JADSTP control bits of the ADC_CR register only if the ADC is enabled, possibly converting, and if there is no pending request to disable the ADC (ADSTART or JADSTART must be equal to 1 and ADDIS to 0).

The software can write the register ADC_JSQR at any time, when the ADC is enabled (ADEN=1). Refer to Section 21.6.16: ADC injected sequence register (ADC_JSQR) for additional details.

Note: There is no hardware protection to prevent these forbidden write accesses and ADC behavior may become in an unknown state. To recover from this situation, the ADC must be disabled (clear ADEN=0 as well as all the bits of ADC_CR register).

21.4.11 Channel selection (SQRx, JSQRx)

There are up to 19 multiplexed channels per ADC:

• 5 fast analog inputs coming from GPIO pads (ADCx_INP/INN[1:5])
• Up to 11 slow analog inputs coming from GPIO pads (ADCx_INP/INN[6:16])
• The ADCs are connected to the following internal analog inputs:
- – The internal reference voltage ( $V_{REFINT}$ ) is connected to ADC1_INP0.
- – The internal temperature sensor ( $V_{TS}$ ) is connected to ADC1_INP17.
- – The $V_{BAT}$ monitoring channel ( $V_{BAT}/3$ ) is connected to ADC1_INP18.
- – The DAC1 internal channel 1 is connected to ADC2_INP17.
- – The DAC1 internal channel 2 is connected to ADC2_INP18.

Note: To convert one of the internal analog channels, the corresponding analog sources must first be enabled by programming bits VREFEN, CH17SEL or CH18SEL in the ADCx_CCR registers.

It is possible to organize the conversions in two groups: regular and injected. A group consists of a sequence of conversions that can be done on any channel and in any order. For instance, it is possible to implement the conversion sequence in the following order: ADCx_INP/INN3, ADCx_INP/INN8, ADCx_INP/INN2, ADCx_INN/INP2, ADCx_INP/INN0, ADCx_INP/INN2, ADCx_INP/INN2, ADCx_INP/INN15.

• A regular group is composed of up to 16 conversions. The regular channels and their order in the conversion sequence must be selected in the ADC_SQRy registers. The total number of conversions in the regular group must be written in the L[3:0] bits in the ADC_SQR1 register.
• An injected group is composed of up to 4 conversions. The injected channels and their order in the conversion sequence must be selected in the ADC_JSQR register. The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register.

ADC_SQRy registers must not be modified while regular conversions can occur. For this, the ADC regular conversions must be first stopped by writing ADSTP=1 (refer to Section 21.4.17: Stopping an ongoing conversion (ADSTP, JADSTP) ).

The software is allowed to modify on-the-fly the ADC_JSQR register when JADSTART is set to 1 (injected conversions ongoing) only when the context queue is enabled (JQDIS=0 in ADC_CFGR register). Refer to Section 21.4.21: Queue of context for injected conversions

21.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2)

Before starting a conversion, the ADC must establish a direct connection between the voltage source under measurement and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the embedded capacitor to the input voltage level.

Each channel can be sampled with a different sampling time which is programmable using the SMP[2:0] bits in the ADC_SMPR1 and ADC registers. It is therefore possible to select among the following sampling time values:

• SMP = 000: 2.5 ADC clock cycles
• SMP = 001: 6.5 ADC clock cycles
• SMP = 010: 12.5 ADC clock cycles
• SMP = 011: 24.5 ADC clock cycles
• SMP = 100: 47.5 ADC clock cycles
• SMP = 101: 92.5 ADC clock cycles
• SMP = 110: 247.5 ADC clock cycles
• SMP = 111: 640.5 ADC clock cycles

The total conversion time is calculated as follows:

T_{\text{CONV}} = \text{Sampling time} + 12.5 \text{ ADC clock cycles}

Example:

With $F_{\text{ADC\_CLK}} = 30 \text{ MHz}$ and a sampling time of 2.5 ADC clock cycles:

T_{\text{CONV}} = (2.5 + 12.5) \text{ ADC clock cycles} = 15 \text{ ADC clock cycles} = 500 \text{ ns}

The ADC notifies the end of the sampling phase by setting the status bit EOSMP (only for regular conversion).

Constraints on the sampling time

For each channel, SMP[2:0] bits must be programmed to respect a minimum sampling time as specified in the ADC characteristics section of the datasheets.

I/O analog switches voltage booster

The I/O analog switches resistance increases when the $V_{\text{DDA}}$ voltage is too low. This requires to have the sampling time adapted accordingly (cf datasheet for electrical characteristics). This resistance can be minimized at low $V_{\text{DDA}}$ by enabling an internal voltage booster with BOOSTEN bit in the SYSCFG_CFGR1 register.

SMPPLUS control bit

When a sampling time of 2.5 ADC clock cycles is selected, the total conversion time becomes 15 cycles in 12-bit mode. If the dual interleaved mode is used (see Section : Interleaved mode with independent injected ), the sampling interval cannot be equal to the value specified since an even number of cycles is required for the conversion. The SMPPLUS bit can be used to change the sampling time 2.5 ADC clock cycles into 3.5 ADC clock cycles. In this way, the total conversion time becomes 16 clock cycles, thus making possible to interleave every 8 cycles.

21.4.13 Single conversion mode (CONT=0)

In Single conversion mode, the ADC performs once all the conversions of the channels. This mode is started with the CONT bit at 0 by either:

• Setting the ADSTART bit in the ADC_CR register (for a regular channel)
• Setting the JADSTART bit in the ADC_CR register (for an injected channel)
• External hardware trigger event (for a regular or injected channel)

Inside the regular sequence, after each conversion is complete:

• The converted data are stored into the 16-bit ADC_DR register
• The EOC (end of regular conversion) flag is set
• An interrupt is generated if the EOCIE bit is set

Inside the injected sequence, after each conversion is complete:

• The converted data are stored into one of the four 16-bit ADC_JDRy registers
• The JEOC (end of injected conversion) flag is set
• An interrupt is generated if the JEOCIE bit is set

After the regular sequence is complete:

• The EOS (end of regular sequence) flag is set
• An interrupt is generated if the EOSIE bit is set

After the injected sequence is complete:

• The JEOS (end of injected sequence) flag is set
• An interrupt is generated if the JEOSIE bit is set

Then the ADC stops until a new external regular or injected trigger occurs or until bit ADSTART or JADSTART is set again.

Note: To convert a single channel, program a sequence with a length of 1.

21.4.14 Continuous conversion mode (CONT=1)

This mode applies to regular channels only.

In continuous conversion mode, when a software or hardware regular trigger event occurs, the ADC performs once all the regular conversions of the channels and then automatically restarts and continuously converts each conversions of the sequence. This mode is started with the CONT bit at 1 either by external trigger or by setting the ADSTART bit in the ADC_CR register.

Inside the regular sequence, after each conversion is complete:

• The converted data are stored into the 16-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set

After the sequence of conversions is complete:

• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set

Then, a new sequence restarts immediately and the ADC continuously repeats the conversion sequence.

Note: To convert a single channel, program a sequence with a length of 1.

It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1.

Injected channels cannot be converted continuously. The only exception is when an injected channel is configured to be converted automatically after regular channels in continuous mode (using JAUTO bit), refer to Auto-injection mode section).

21.4.15 Starting conversions (ADSTART, JADSTART)

Software starts ADC regular conversions by setting ADSTART=1.

When ADSTART is set, the conversion starts:

• Immediately: if EXTEN[1:0] = 00 (software trigger)
• At the next active edge of the selected regular hardware trigger: if EXTEN[1:0] is not equal to 00

Software starts ADC injected conversions by setting JADSTART=1.

When JADSTART is set, the conversion starts:

• Immediately, if JEXTEN[1:0] = 00 (software trigger)
• At the next active edge of the selected injected hardware trigger: if JEXTEN[1:0] is not equal to 00

Note: In auto-injection mode (JAUTO=1), use ADSTART bit to start the regular conversions followed by the auto-injected conversions (JADSTART must be kept cleared).

ADSTART and JADSTART also provide information on whether any ADC operation is currently ongoing. It is possible to re-configure the ADC while ADSTART=0 and JADSTART=0 are both true, indicating that the ADC is idle.

ADSTART is cleared by hardware:

• In single mode with software regular trigger (CONT=0, EXTSEL=0x0)
- – At any end of regular conversion sequence (EOS assertion) or at any end of subgroup processing if DISCEN = 1
• In all cases (CONT=x, EXTSEL=x)
- – After execution of the ADSTP procedure asserted by the software.

Note: In continuous mode (CONT=1), ADSTART is not cleared by hardware with the assertion of EOS because the sequence is automatically relaunched.

When a hardware trigger is selected in single mode (CONT=0 and EXTSEL≠0x00), ADSTART is not cleared by hardware with the assertion of EOS to help the software which does not need to reset ADSTART again for the next hardware trigger event. This ensures that no further hardware triggers are missed.

JADSTART is cleared by hardware:

• In single mode with software injected trigger (JEXTSEL = 0x0)
- – At any end of injected conversion sequence (JEOS assertion) or at any end of subgroup processing if JDISCEN = 1
• in all cases (JEXTSEL=x)
- – After execution of the JADSTP procedure asserted by the software.

Note: When the software trigger is selected, ADSTART bit should not be set if the EOC flag is still high.

21.4.16 ADC timing

The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution:

T_{CONV} = T_{SMPL} + T_{SAR} = [2.5 \text{ } |_{min} + 12.5 \text{ } |_{12bit}] \times T_{ADC\_CLK}

T_{CONV} = T_{SMPL} + T_{SAR} = 83.33 \text{ ns } |_{min} + 416.67 \text{ ns } |_{12bit} = 500.0 \text{ ns (for } F_{ADC\_CLK} = 30 \text{ MHz)}

Figure 95. Analog to digital conversion time

Timing diagram for ADC conversion showing ADC state, Analog channel, Internal S/H, ADSTART, EOSMP, EOC, and ADC_DR signals over time. It illustrates the sampling and conversion phases for channels Ch(N) and Ch(N+1).

The diagram shows the timing of an ADC conversion across several signals:

ADC state: Starts in RDY state. It transitions to Sampling Ch(N) when ADSTART is set, then to Converting Ch(N) when EOSMP is set, and finally back to Sampling Ch(N+1) when EOC is set.
Analog channel: Shows Ch(N) being sampled, followed by a hatched transition period, and then Ch(N+1) being sampled.
Internal S/H: Shows Sample AIN(N) during the sampling phase and Hold AIN(N) during the conversion phase.
ADSTART: Set by software to start the conversion sequence.
EOSMP: Set by software to end the sampling phase and start conversion. It is cleared by software after conversion.
EOC: Set by hardware when conversion is complete. It is cleared by software.
ADC_DR: Data register. It contains Data N-1 during the conversion of Ch(N) and updates to Data N when conversion of Ch(N) is complete.

Indicative timings $t_{SMPL}^{(1)}$ and $t_{SAR}^{(2)}$ are shown for the sampling and conversion phases respectively.

Timing diagram for ADC conversion showing ADC state, Analog channel, Internal S/H, ADSTART, EOSMP, EOC, and ADC_DR signals over time. It illustrates the sampling and conversion phases for channels Ch(N) and Ch(N+1).

1. $t_{SMPL}$ depends on SMP[2:0].
2. $t_{SAR}$ depends on RES[2:0].

21.4.17 Stopping an ongoing conversion (ADSTP, JADSTP)

The software can decide to stop regular conversions ongoing by setting ADSTP=1 and injected conversions ongoing by setting JADSTP=1.

Stopping conversions will reset the ongoing ADC operation. Then the ADC can be reconfigured (ex: changing the channel selection or the trigger) ready for a new operation.

Note that it is possible to stop injected conversions while regular conversions are still operating and vice-versa. This allows, for instance, re-configuration of the injected conversion sequence and triggers while regular conversions are still operating (and vice-versa).

When the ADSTP bit is set by software, any ongoing regular conversion is aborted with partial result discarded (ADC_DR register is not updated with the current conversion).

When the JADSTP bit is set by software, any ongoing injected conversion is aborted with partial result discarded (ADC_JDRy register is not updated with the current conversion). The scan sequence is also aborted and reset (meaning that relaunching the ADC would restart a new sequence).

Once this procedure is complete, bits ADSTP/ADSTART (in case of regular conversion), or JADSTP/JADSTART (in case of injected conversion) are cleared by hardware and the software must poll ADSTART (or JADSTART) until the bit is reset before assuming the ADC is completely stopped.

Note: In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (JADSTP must not be used).

Figure 96. Stopping ongoing regular conversions

Timing diagram for Figure 96 showing the state of ADC signals when stopping ongoing regular conversions. The diagram includes ADC state (RDY, Sample Ch(N-1), Convert Ch(N-1), RDY, Sample Ch(N), C, RDY), JADSTART, ADSTART, ADSTP, and ADC_DR signals over time. Triggers are shown at the start of the first and third conversion sequences. ADSTART is set by software and cleared by hardware. ADSTP is set by software and cleared by hardware. ADC_DR contains Data N-2 and Data N-1.

The diagram illustrates the timing for stopping ongoing regular conversions. The ADC state transitions from RDY to Sample Ch(N-1) upon a Trigger, then to Convert Ch(N-1), then back to RDY. A second Trigger occurs while the first conversion is still ongoing (Convert Ch(N-1)). The ADSTART signal is set by software and cleared by hardware. The ADSTP signal is set by software and cleared by hardware. The ADC_DR signal contains Data N-2 and Data N-1. A note indicates that software is not allowed to configure regular conversions selection and triggers.

MSV30533V2

Timing diagram for Figure 96 showing the state of ADC signals when stopping ongoing regular conversions. The diagram includes ADC state (RDY, Sample Ch(N-1), Convert Ch(N-1), RDY, Sample Ch(N), C, RDY), JADSTART, ADSTART, ADSTP, and ADC_DR signals over time. Triggers are shown at the start of the first and third conversion sequences. ADSTART is set by software and cleared by hardware. ADSTP is set by software and cleared by hardware. ADC_DR contains Data N-2 and Data N-1.

Figure 97. Stopping ongoing regular and injected conversions

Timing diagram for Figure 97 showing the state of ADC signals when stopping ongoing regular and injected conversions. The diagram includes ADC state (RDY, Sample Ch(N-1), Convert Ch(N-1), RDY, Sample Ch(M), C, RDY, Sample, RDY), JADSTART, JADSTP, ADC_JDR, ADSTART, ADSTP, and ADC_DR signals over time. Triggers are labeled Regular trigger, Injected trigger, and Regular trigger. JADSTART is set by software and cleared by hardware. JADSTP is set by software and cleared by hardware. ADSTART is set by software and cleared by hardware. ADSTP is set by software and cleared by hardware. ADC_DR contains DATA N-2 and DATA N-1. Notes indicate that software is not allowed to configure injected conversions selection and triggers, and regular conversions selection and triggers.

The diagram illustrates the timing for stopping ongoing regular and injected conversions. The ADC state transitions from RDY to Sample Ch(N-1) upon a Regular trigger, then to Convert Ch(N-1), then back to RDY. An Injected trigger occurs while the first conversion is still ongoing (Convert Ch(N-1)). The ADC state then transitions to Sample Ch(M), C, RDY, Sample, RDY upon another Regular trigger. The JADSTART signal is set by software and cleared by hardware. The JADSTP signal is set by software and cleared by hardware. The ADC_JDR signal contains DATA M-1. The ADSTART signal is set by software and cleared by hardware. The ADSTP signal is set by software and cleared by hardware. The ADC_DR signal contains DATA N-2 and DATA N-1. Notes indicate that software is not allowed to configure injected conversions selection and triggers, and regular conversions selection and triggers.

MS30534V1

Timing diagram for Figure 97 showing the state of ADC signals when stopping ongoing regular and injected conversions. The diagram includes ADC state (RDY, Sample Ch(N-1), Convert Ch(N-1), RDY, Sample Ch(M), C, RDY, Sample, RDY), JADSTART, JADSTP, ADC_JDR, ADSTART, ADSTP, and ADC_DR signals over time. Triggers are labeled Regular trigger, Injected trigger, and Regular trigger. JADSTART is set by software and cleared by hardware. JADSTP is set by software and cleared by hardware. ADSTART is set by software and cleared by hardware. ADSTP is set by software and cleared by hardware. ADC_DR contains DATA N-2 and DATA N-1. Notes indicate that software is not allowed to configure injected conversions selection and triggers, and regular conversions selection and triggers.

21.4.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN)

A conversion or a sequence of conversions can be triggered either by software or by an external event (e.g. timer capture, input pins). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then external events are able to trigger a conversion with the selected polarity.

When the Injected Queue is enabled (bit JQDIS=0), injected software triggers are not possible.

The regular trigger selection is effective once software has set bit ADSTART=1 and the injected trigger selection is effective once software has set bit JADSTART=1.

Any hardware triggers which occur while a conversion is ongoing are ignored.

• If bit ADSTART=0, any regular hardware triggers which occur are ignored.
• If bit JADSTART=0, any injected hardware triggers which occur are ignored.

Table 129 provides the correspondence between the EXTEN[1:0] and JEXTEN[1:0] values and the trigger polarity.

Table 129. Configuring the trigger polarity for regular external triggers

EXTEN[1:0]	Source
00	Hardware Trigger detection disabled, software trigger detection enabled
01	Hardware Trigger with detection on the rising edge
10	Hardware Trigger with detection on the falling edge
11	Hardware Trigger with detection on both the rising and falling edges

Note: The polarity of the regular trigger cannot be changed on-the-fly.

Table 130. Configuring the trigger polarity for injected external triggers

JEXTEN[1:0]	Source
00	– If JQDIS=1 (Queue disabled): Hardware trigger detection disabled, software trigger detection enabled – If JQDIS=0 (Queue enabled), Hardware and software trigger detection disabled
01	Hardware Trigger with detection on the rising edge
10	Hardware Trigger with detection on the falling edge
11	Hardware Trigger with detection on both the rising and falling edges

Note: The polarity of the injected trigger can be anticipated and changed on-the-fly when the queue is enabled (JQDIS=0). Refer to Section 21.4.21: Queue of context for injected conversions .

The EXTSEL and JEXTSEL control bits select which out of 16 possible events can trigger conversion for the regular and injected groups.

A regular group conversion can be interrupted by an injected trigger.

Note:
The regular trigger selection cannot be changed on-the-fly.
The injected trigger selection can be anticipated and changed on-the-fly. Refer to Section 21.4.21: Queue of context for injected conversions on page 643

Each ADC master shares the same input triggers with its ADC slave as described in Figure 98 .

Figure 98. Triggers sharing between ADC master and ADC slave

Figure 98: Triggers sharing between ADC master and ADC slave. The diagram shows two ADC blocks, 'ADC MASTER' and 'ADC SLAVE', sharing external trigger inputs. On the left, 'Regular sequencer triggers' (EXT0, EXT1, ..., EXT15) and 'Injected sequencer triggers' (JEXT0, JEXT1, ..., JEXT15) are shown. The ADC MASTER has two multiplexers: 'External regular trigger' (selecting from EXT0-EXT15 via EXTSEL[3:0]) and 'External injected trigger' (selecting from JEXT0-JEXT15 via JEXTSEL[3:0]). The ADC SLAVE has similar multiplexers. Lines connect the trigger sources to the multiplexers, showing that the master and slave share the same external trigger sources for their respective regular and injected sequences. A small label 'MS35356V1' is in the bottom right corner of the diagram area.

Table 131 to Table 132 give all the possible external triggers of the three ADCs for regular and injected conversions.

Table 131. ADC1 - External triggers for regular channels

Name	Source	Type	EXTSEL[3:0]
EXT0	TIM1_CH1	Internal signal from on-chip timers	0000
EXT1	TIM1_CH2	Internal signal from on-chip timers	0001
EXT2	TIM1_CH3	Internal signal from on-chip timers	0010
EXT3	TIM2_CH2	Internal signal from on-chip timers	0011
EXT4	TIM3_TRGO	Internal signal from on-chip timers	0100
EXT5	TIM4_CH4	Internal signal from on-chip timers	0101
EXT6	EXTI line 11	External pin	0110
EXT7	TIM8_TRGO	Internal signal from on-chip timers	0111
EXT8	TIM8_TRGO2	Internal signal from on-chip timers	1000
EXT9	TIM1_TRGO	Internal signal from on-chip timers	1001

Table 131. ADC1 - External triggers for regular channels (continued)

Name	Source	Type	EXTSEL[3:0]
EXT10	TIM1_TRGO2	Internal signal from on-chip timers	1010
EXT11	TIM2_TRGO	Internal signal from on-chip timers	1011
EXT12	TIM4_TRGO	Internal signal from on-chip timers	1100
EXT13	TIM6_TRGO	Internal signal from on-chip timers	1101
EXT14	TIM15_TRGO	Internal signal from on-chip timers	1110
EXT15	TIM3_CH4	Internal signal from on-chip timers	1111

Table 132. ADC1 - External trigger for injected channels

Name	Source	Type	JEXTSEL[3:0]
JEXT0	TIM1_TRGO	Internal signal from on-chip timers	0000
JEXT1	TIM1_CH4	Internal signal from on-chip timers	0001
JEXT2	TIM2_TRGO	Internal signal from on-chip timers	0010
JEXT3	TIM2_CH1	Internal signal from on-chip timers	0011
JEXT4	TIM3_CH4	Internal signal from on-chip timers	0100
JEXT5	TIM4_TRGO	Internal signal from on-chip timers	0101
JEXT6	EXTI line 15	External pin	0110
JEXT7	TIM8_CH4	Internal signal from on-chip timers	0111
JEXT8	TIM1_TRGO2	Internal signal from on-chip timers	1000
JEXT9	TIM8_TRGO	Internal signal from on-chip timers	1001
JEXT10	TIM8_TRGO2	Internal signal from on-chip timers	1010
JEXT11	TIM3_CH3	Internal signal from on-chip timers	1011
JEXT12	TIM3_TRGO	Internal signal from on-chip timers	1100
JEXT13	TIM3_CH1	Internal signal from on-chip timers	1101
JEXT14	TIM6_TRGO	Internal signal from on-chip timers	1110
JEXT15	TIM15_TRGO	Internal signal from on-chip timers	1111

21.4.19 Injected channel management

Triggered injection mode

To use triggered injection, the JAUTO bit in the ADC_CFGR register must be cleared.

1. Start the conversion of a group of regular channels either by an external trigger or by setting the ADSTART bit in the ADC_CR register.
2. If an external injected trigger occurs, or if the JADSTART bit in the ADC_CR register is set during the conversion of a regular group of channels, the current conversion is

reset and the injected channel sequence switches are launched (all the injected channels are converted once).
1. 3. Then, the regular conversion of the regular group of channels is resumed from the last interrupted regular conversion.
2. 4. If a regular event occurs during an injected conversion, the injected conversion is not interrupted but the regular sequence is executed at the end of the injected sequence.
Figure 99 shows the corresponding timing diagram.

Note: When using triggered injection, one must ensure that the interval between trigger events is longer than the injection sequence. For instance, if the sequence length is 30 ADC clock cycles (that is two conversions with a sampling time of 2.5 clock periods), the minimum interval between triggers must be 31 ADC clock cycles.

Auto-injection mode

If the JAUTO bit in the ADC_CFGR register is set, then the channels in the injected group are automatically converted after the regular group of channels. This can be used to convert a sequence of up to 20 conversions programmed in the ADC_SQRy and ADC_JSQR registers.

In this mode, the ADSTART bit in the ADC_CR register must be set to start regular conversions, followed by injected conversions (JADSTART must be kept cleared). Setting the ADSTP bit aborts both regular and injected conversions (JADSTP bit must not be used).

In this mode, external trigger on injected channels must be disabled.

If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected channels are continuously converted.

Note: It is not possible to use both the auto-injected and discontinuous modes simultaneously. When the DMA is used for exporting regular sequencer's data in JAUTO mode, it is necessary to program it in circular mode (CIRC bit set in DMA_CCRx register). If the CIRC bit is reset (single-shot mode), the JAUTO sequence will be stopped upon DMA Transfer Complete event.

Figure 99. Injected conversion latency

Timing diagram showing injected conversion latency. The diagram displays four signals over time: ADCCLK (a periodic square wave), Injection event (a single pulse), Reset ADC (a pulse that goes high after the injection event), and SOC (Start of Conversion, a pulse that goes high after the Reset ADC pulse). A horizontal double-headed arrow labeled 'max. latency (1)' indicates the time interval between the rising edge of the Injection event and the rising edge of the SOC signal. Vertical dashed lines mark these two rising edges. The signal 'ai16049b' is shown in the bottom right corner.

1. The maximum latency value can be found in the electrical characteristics of the device datasheet.

21.4.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN)

Regular group mode

This mode is enabled by setting the DISCEN bit in the ADC_CFGR register.

It is used to convert a short sequence (subgroup) of $$ n $$ conversions ( $n \leq 8$ ) that is part of the sequence of conversions selected in the ADC_SQRy registers. The value of $$ n $$ is specified by writing to the DISCNUM[2:0] bits in the ADC_CFGR register.

When an external trigger occurs, it starts the next $$ n $$ conversions selected in the ADC_SQRy registers until all the conversions in the sequence are done. The total sequence length is defined by the L[3:0] bits in the ADC_SQR1 register.

Example:

• DISCEN=1, $ n=3 $ , channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10, 11
- – 1st trigger: channels converted are 1, 2, 3 (an EOC event is generated at each conversion).
- – 2nd trigger: channels converted are 6, 7, 8 (an EOC event is generated at each conversion).
- – 3rd trigger: channels converted are 9, 10, 11 (an EOC event is generated at each conversion) and an EOS event is generated after the conversion of channel 11.
- – 4th trigger: channels converted are 1, 2, 3 (an EOC event is generated at each conversion).
- – ...
• DISCEN=0, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10, 11
- – 1st trigger: the complete sequence is converted: channel 1, then 2, 3, 6, 7, 8, 9, 10 and 11. Each conversion generates an EOC event and the last one also generates an EOS event.
- – All the next trigger events will relaunch the complete sequence.

Note: The channel numbers referred to in the above example might not be available on all microcontrollers.

When a regular group is converted in discontinuous mode, no rollover occurs (the last subgroup of the sequence can have less than n conversions).

When all subgroups are converted, the next trigger starts the conversion of the first subgroup. In the example above, the 4th trigger reconverts the channels 1, 2 and 3 in the 1st subgroup.

It is not possible to have both discontinuous mode and continuous mode enabled. In this case (if DISCEN=1, CONT=1), the ADC behaves as if continuous mode was disabled.

Injected group mode

This mode is enabled by setting the JDISCEN bit in the ADC_CFGR register. It converts the sequence selected in the ADC_JSQR register, channel by channel, after an external injected trigger event. This is equivalent to discontinuous mode for regular channels where 'n' is fixed to 1.

When an external trigger occurs, it starts the next channel conversions selected in the ADC_JSQR registers until all the conversions in the sequence are done. The total sequence length is defined by the JL[1:0] bits in the ADC_JSQR register.

Example:

• JDISCEN=1, channels to be converted = 1, 2, 3
- – 1st trigger: channel 1 converted (a JEOC event is generated)
- – 2nd trigger: channel 2 converted (a JEOC event is generated)
- – 3rd trigger: channel 3 converted and a JEOC event + a JEOS event are generated
- – ...

Note: The channel numbers referred to in the above example might not be available on all microcontrollers.

When all injected channels have been converted, the next trigger starts the conversion of the first injected channel. In the example above, the 4th trigger reconverts the 1st injected channel 1.

It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.

21.4.21 Queue of context for injected conversions

A queue of context is implemented to anticipate up to 2 contexts for the next injected sequence of conversions. JQDIS bit of ADC_CFGR register must be reset to enable this feature. Only hardware-triggered conversions are possible when the context queue is enabled.

This context consists of:

• Configuration of the injected triggers (bits JEXTEN[1:0] and JEXTSEL bits in ADC_JSQR register)
• Definition of the injected sequence (bits JSQx[4:0] and JL[1:0] in ADC_JSQR register)

All the parameters of the context are defined into a single register ADC_JSQR and this register implements a queue of 2 buffers, allowing the bufferization of up to 2 sets of parameters:

• The JSQR register can be written at any moment even when injected conversions are ongoing.
• Each data written into the JSQR register is stored into the Queue of context.
• At the beginning, the Queue is empty and the first write access into the JSQR register immediately changes the context and the ADC is ready to receive injected triggers.
• Once an injected sequence is complete, the Queue is consumed and the context changes according to the next JSQR parameters stored in the Queue. This new context is applied for the next injected sequence of conversions.
• A Queue overflow occurs when writing into register JSQR while the Queue is full. This overflow is signaled by the assertion of the flag JQOVF. When an overflow occurs, the write access of JSQR register which has created the overflow is ignored and the queue of context is unchanged. An interrupt can be generated if bit JQOVFIE is set.
• Two possible behaviors are possible when the Queue becomes empty, depending on the value of the control bit JQM of register ADC_CFGR:
- – If JQM=0, the Queue is empty just after enabling the ADC, but then it can never be empty during run operations: the Queue always maintains the last active context and any further valid start of injected sequence will be served according to the last active context.
- – If JQM=1, the Queue can be empty after the end of an injected sequence or if the Queue is flushed. When this occurs, there is no more context in the queue and hardware triggers are disabled. Therefore, any further hardware injected triggers are ignored until the software re-writes a new injected context into JSQR register.
• Reading JSQR register returns the current JSQR context which is active at that moment. When the JSQR context is empty, JSQR is read as 0x0000.
• The Queue is flushed when stopping injected conversions by setting JADSTP=1 or when disabling the ADC by setting ADDIS=1:
- – If JQM=0, the Queue is maintained with the last active context.
- – If JQM=1, the Queue becomes empty and triggers are ignored.

Note: When configured in discontinuous mode (bit JDISCEN=1), only the last trigger of the injected sequence changes the context and consumes the Queue. The 1 ^sttrigger only consumes the queue but others are still valid triggers as shown by the discontinuous mode example below (length = 3 for both contexts):

• 1 ^sttrigger, discontinuous. Sequence 1: context 1 consumed, 1 ^stconversion carried out
• 2 ^ndtrigger, disc. Sequence 1: 2 ^ndconversion.
• 3 ^rdtrigger, discontinuous. Sequence 1: 3 ^rdconversion.
• 4 ^thtrigger, discontinuous. Sequence 2: context 2 consumed, 1 ^stconversion carried out.
• 5 ^thtrigger, discontinuous. Sequence 2: 2 ^ndconversion.
• 6 ^thtrigger, discontinuous. Sequence 2: 3 ^rdconversion.

Behavior when changing the trigger or sequence context

The Figure 100 and Figure 101 show the behavior of the context Queue when changing the sequence or the triggers.

Figure 100. Example of JSQR queue of context (sequence change)

MS30536V2

Timing diagram for Figure 100 showing JSQR queue behavior during sequence changes. It tracks 'Write JSQR', 'JSQR queue', 'Trigger 1', 'ADC J context', and 'ADC state' over time. The queue updates from P1 to P1,P2 and then to P2, P2,P3, and finally P3 as sequences are written. Conversions are shown occurring when the queue is non-empty and the trigger is active.

Parameters:
P1: sequence of 3 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 4 conversions, hardware trigger 1

Figure 101. Example of JSQR queue of context (trigger change)

MS30537V2

Timing diagram for Figure 101 showing JSQR queue behavior during trigger changes. It tracks 'Write JSQR', 'JSQR queue', 'Trigger 1', 'Trigger 2', 'ADC J context', and 'ADC state'. The queue contains P1, P1,P2, P2, P2,P3, and P3. Trigger 1 is active for P1 and P3. Trigger 2 is active for P2. Conversions occur based on the active trigger for the current queue entry. Some triggers are ignored when not active for the current queue entry.

Parameters:
P1: sequence of 2 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 2
P3: sequence of 4 conversions, hardware trigger 1

Queue of context: Behavior when a queue overflow occurs

The Figure 102 and Figure 103 show the behavior of the context Queue if an overflow occurs before or during a conversion.

Figure 102. Example of JSQR queue of context with overflow before conversion

The diagram illustrates the state of the ADC context queue and associated signals over time.
- Write JSQR: Shows pulses for parameters P1, P2, P3, and P4.
- JSQR queue: Starts as EMPTY. P1 is added, then P2 (queue contains P1, P2). When P3 is written, it causes an overflow and is ignored. Later, P1 and P2 are removed, and P4 is added (queue contains P2, P4).
- JQOVF: Goes high when P3 is ignored and is cleared by software (SW).
- Trigger 1: Initiates a conversion sequence.
- ADC J context: Returns the current queue state (e.g., P1, P2) when read.
- ADC state: Transitions from RDY to Conversion1, then Conversion2, and back to RDY.
- JEOS: Goes high when the conversion sequence ends.

Timing diagram for Figure 102 showing JSQR queue behavior with overflow before conversion. The diagram tracks signals: Write JSQR, JSQR queue, JQOVF, Trigger 1, Trigger 2, ADC J context, ADC state, and JEOS. It shows P1, P2, and P4 being added to the queue, while P3 is ignored due to overflow. Conversions are triggered by Trigger 1 and Trigger 2.

1. Parameters:
P1: sequence of 2 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 2
P3: sequence of 3 conversions, hardware trigger 1
P4: sequence of 4 conversions, hardware trigger 1

Figure 103. Example of JSQR queue of context with overflow during conversion

This diagram is similar to Figure 102 but shows an overflow occurring while a conversion is in progress.
- Write JSQR: P1, P2, and P4 are written. P3 is written while the ADC is still processing a previous sequence.
- JSQR queue: P1 and P2 are present. When P3 is written, it overflows and is ignored because the queue is full and a conversion is ongoing.
- JQOVF: Goes high during the conversion and is cleared by SW.
- ADC state: Shows an active conversion sequence (Conversion1, Conversion2) when the overflow occurs.
- ADC J context: Returns the current context (P1, P2) despite the overflow.

Timing diagram for Figure 103 showing JSQR queue behavior with overflow during conversion. Similar to Figure 102, but the overflow of P3 occurs while a conversion sequence is still active. The queue is cleared by software after the overflow.

1. Parameters:
P1: sequence of 2 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 2
P3: sequence of 3 conversions, hardware trigger 1
P4: sequence of 4 conversions, hardware trigger 1

It is recommended to manage the queue overflows as described below:

• After each P context write into JSQR register, flag JQOVF shows if the write has been ignored or not (an interrupt can be generated).
• Avoid Queue overflows by writing the third context (P3) only once the flag JEOS of the previous context P2 has been set. This ensures that the previous context has been consumed and that the queue is not full.

Queue of context: Behavior when the queue becomes empty

Figure 104 and Figure 105 show the behavior of the context Queue when the Queue becomes empty in both cases JQM=0 or 1.

Figure 104. Example of JSQR queue of context with empty queue (case JQM=0)

Timing diagram showing the behavior of the JSQR queue of context when the queue becomes empty (case JQM=0). The diagram illustrates the sequence of events for writing contexts (P1, P2, P3) into the JSQR queue, triggering conversions, and the resulting ADC state.

The diagram shows four horizontal timelines over time:

Write JSQR: Shows pulses for writing contexts P1, P2, and P3. P1 and P2 are written while the queue is empty. P3 is written while P2 is still in the queue.
JSQR queue: Shows the state of the queue. It starts as EMPTY. After P1 is written, it contains P1. After P2 is written, it contains P1, P2. After P1 is consumed, it contains P2. When P3 is written, the queue contains P2 and P3. After P2 is consumed, it contains P3. Annotations indicate: "The queue is not empty and maintains P2 because JQM=0" and "Queue not empty (P3 maintained)".
Trigger 1: Shows a series of pulses that trigger conversions.
ADC J context (returned by reading JQSR): Shows the context returned by the ADC. It starts as EMPTY. It returns P1, then P2, then P3. There is a latency between the write of P3 and its return.
ADC state: Shows the state of the ADC. It starts as RDY. It goes to Conversion1 when P1 is triggered. After the conversion, it returns to RDY. It goes to Conversion1 again when P2 is triggered. After the conversion, it returns to RDY. It goes to Conversion1 again when P3 is triggered. After the conversion, it returns to RDY. The final state shown is Conv.

MS30540V3

Timing diagram showing the behavior of the JSQR queue of context when the queue becomes empty (case JQM=0). The diagram illustrates the sequence of events for writing contexts (P1, P2, P3) into the JSQR queue, triggering conversions, and the resulting ADC state.

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Note: When writing P3, the context changes immediately. However, because of internal resynchronization, there is a latency and if a trigger occurs just after or before writing P3, it can happen that the conversion is launched considering the context P2. To avoid this situation, the user must ensure that there is no ADC trigger happening when writing a new context that applies immediately.

Figure 105. Example of JSQR queue of context with empty queue (case JQM=1)

Timing diagram for Figure 105 showing the JSQR queue behavior when JQM=1. The diagram includes signals for Write JSQR, JSQR queue, Trigger 1, ADC J context, and ADC state. It shows sequences P1, P2, and P3 being added to the queue, and how the queue becomes empty after reading the last context because JQM=1.

The diagram illustrates the following sequence of events:

Write JSQR: P1 is written, then P2, then P3.
JSQR queue: Starts as EMPTY. After writing P1, it contains P1. After writing P2, it contains P1, P2. After P1 is processed, it contains P2. After P2 is processed, it becomes EMPTY. When P3 is written, it contains P3. After P3 is processed, it becomes EMPTY again.
Trigger 1: Hardware triggers occur. The first two are ignored because the queue is not yet populated with the corresponding context. The third trigger occurs while P3 is being processed and is also ignored.
ADC J context (returned by reading JQSR): Returns EMPTY, then P1, then P2, then EMPTY (0x0000) when the queue is empty, then P3, and finally EMPTY.
ADC state: Starts as RDY. It becomes Conversion1 when P1 is processed, then back to RDY. It becomes Conversion1 again when P2 is processed, then back to RDY. It becomes Conversion1 when P3 is processed, then back to RDY.

A note indicates: "Queue becomes empty and triggers are ignored because JQM=1". The diagram is labeled MS30541V1.

Timing diagram for Figure 105 showing the JSQR queue behavior when JQM=1. The diagram includes signals for Write JSQR, JSQR queue, Trigger 1, ADC J context, and ADC state. It shows sequences P1, P2, and P3 being added to the queue, and how the queue becomes empty after reading the last context because JQM=1.

Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Flushing the queue of context

The figures below show the behavior of the context Queue in various situations when the queue is flushed.

Figure 106. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion.

Timing diagram for Figure 106 showing the JSQR queue behavior when JADSTP=1 and JQM=0. It shows how setting JADSTP=1 during an ongoing conversion (P2) flushes the queue, losing P2 and keeping only P1 and P3.

The diagram illustrates the following sequence of events:

Write JSQR: P1 is written, then P2, then P3.
JSQR queue: Starts as EMPTY. After writing P1, it contains P1. After writing P2, it contains P1, P2. When JADSTP is set by software (S/W), the queue is flushed and maintains the last active context, which is P1. P2 is lost. After P1 is processed, the queue contains P3.
JADSTP: Set by S/W during the processing of P2. It is reset by hardware (H/W) after the conversion of P1 is complete.
JADSTART: Reset by H/W after the conversion of P1 is complete. It is set by S/W to start the conversion of P3.
Trigger 1: Hardware trigger occurs to start the conversion of P3.
ADC J context (returned by reading JSQR): Returns EMPTY, then P1. When the queue is flushed, it returns P1. After P1 is processed, it returns P3.
ADC state: Starts as RDY. It becomes Conversion1 when P1 is processed, then back to RDY. When JADSTP is set, the state becomes STP (stop). After P1 is processed, it returns to RDY. It becomes Conversion1 when P3 is processed, then back to RDY.

A note indicates: "Queue is flushed and maintains the last active context (P2 is lost)". The diagram is labeled MS30544V2.

Timing diagram for Figure 106 showing the JSQR queue behavior when JADSTP=1 and JQM=0. It shows how setting JADSTP=1 during an ongoing conversion (P2) flushes the queue, losing P2 and keeping only P1 and P3.

Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Figure 107. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion and a new trigger occurs.

Timing diagram for Figure 107 showing the flushing of the JSQR queue during an ongoing conversion.

This timing diagram illustrates the behavior of the ADC when JADSTP=1 and JQM=0, specifically when JADSTP is set during an ongoing conversion and a new trigger occurs. The diagram shows the following signals and states over time:

Write JSQR: Shows three write pulses for sequences P1, P2, and P3.
JSQR queue: Shows the queue contents: initially EMPTY, then P1, then P1 and P2, then after P2 is lost, only P1 remains, and finally P1 and P3 are present.
JADSTP: Set by software (S/W) before the second trigger. It is reset by hardware (H/W) when the first conversion (P1) is stopped, and then set by S/W again before the third trigger.
JADSTART: Set by software (S/W) to start the first conversion (P1). It is reset by hardware (H/W) when the conversion is stopped, and then set by S/W again to start the third conversion (P3).
Trigger 1: Hardware trigger pulses. The first trigger starts the conversion of P1. The second trigger occurs while P1 is still being converted and causes it to be stopped (ABORTED). The third trigger occurs after the ADC is back in the READY state and starts the conversion of P3.
ADC J context (returned by reading JSQR): Shows the context returned: initially EMPTY, then P1, then after the abort, it becomes EMPTY again, and finally P3 is returned.
ADC state: Shows the state transitions: RDY → Conversion1 (P1) → STOP (ABORTED) → RDY → Conversion1 (P3) → RDY.

A note indicates: "Queue is flushed and maintains the last active context (P2 is lost)". The diagram is labeled MS30543V1.

Timing diagram for Figure 107 showing the flushing of the JSQR queue during an ongoing conversion.

Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Figure 108. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs outside an ongoing conversion

Timing diagram for Figure 108 showing the flushing of the JSQR queue outside an ongoing conversion.

This timing diagram illustrates the behavior of the ADC when JADSTP=1 and JQM=0, specifically when JADSTP is set outside an ongoing conversion. The diagram shows the following signals and states over time:

Write JSQR: Shows three write pulses for sequences P1, P2, and P3.
JSQR queue: Shows the queue contents: initially EMPTY, then P1, then P1 and P2, then after P2 is lost, only P1 remains, and finally P3 is present.
JADSTP: Set by software (S/W) while the ADC is in the READY state. It is reset by hardware (H/W) when the ADC state becomes STOP, and then set by S/W again before the third trigger.
JADSTART: Set by software (S/W) to start the first conversion (P1). It is reset by hardware (H/W) when the conversion is stopped, and then set by S/W again to start the third conversion (P3).
Trigger 1: Hardware trigger pulses. The first trigger starts the conversion of P1. The second trigger occurs while the ADC is in the STOP state (after the first conversion was stopped by JADSTP) and causes the conversion of P3 to start.
ADC J context (returned by reading JSQR): Shows the context returned: initially EMPTY, then P1, then after the stop, it becomes STOP, and finally P3 is returned.
ADC state: Shows the state transitions: RDY → STOP (triggered by JADSTP) → RDY → Conversion1 (P3) → RDY.

A note indicates: "the last active context (P2 is lost)". The diagram is labeled MS30544V1.

Timing diagram for Figure 108 showing the flushing of the JSQR queue outside an ongoing conversion.

Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Figure 109. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1)

Timing diagram for Figure 109 showing the effect of setting JADSTP=1 (JQM=1) on the JSQR queue. The diagram tracks the JSQR queue, JADSTP, JADSTART, Trigger 1, ADC J context, and ADC state over time. It shows that setting JADSTP=1 flushes the queue, losing P2.

The diagram illustrates the state of the ADC's JSQR queue and associated signals when JADSTP=1 (JQM=1). The signals shown are:

Write JSQR: Shows three write operations for sequences P1, P2, and P3.
JSQR queue: Shows the queue state: EMPTY → P1 → P1, P2 → (flushed) → EMPTY → P3 → EMPTY. A note indicates: "Queue is flushed and becomes empty (P2 is lost)".
JADSTP: Set by software (S/W) after P2 is written, and reset by hardware (H/W) when the queue is empty.
JADSTART: Reset by hardware (H/W) when the queue is empty, and set by software (S/W) before starting a conversion.
Trigger 1: A hardware trigger that initiates a conversion. It is ignored when the queue is empty.
ADC J context (returned by reading JSQR): Shows the context returned: EMPTY → P1 → EMPTY (0x0000) → P3 → EMPTY.
ADC state: Shows the state: RDY → Conv1 (Aborted) → STP → RDY → Conversion1 → RDY.

MS30545V1

Timing diagram for Figure 109 showing the effect of setting JADSTP=1 (JQM=1) on the JSQR queue. The diagram tracks the JSQR queue, JADSTP, JADSTART, Trigger 1, ADC J context, and ADC state over time. It shows that setting JADSTP=1 flushes the queue, losing P2.

Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Figure 110. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0)

Timing diagram for Figure 110 showing the effect of setting ADDIS=1 (JQM=0) on the JSQR queue. The diagram tracks the JSQR queue, ADDIS, ADC J context, and ADC state over time. It shows that setting ADDIS=1 flushes the queue but maintains the last active context (P1).

The diagram illustrates the state of the ADC's JSQR queue and associated signals when ADDIS=1 (JQM=0). The signals shown are:

JSQR queue: Shows the queue state: P1, P2 → (flushed) → P1. A note indicates: "Queue is flushed and maintains the last active context (P2 which was not consumed is lost)".
ADDIS: Set by software (S/W) after P2 is written, and reset by hardware (H/W) when the queue is empty.
ADC J context (returned by reading JSQR): Shows the context returned: P1.
ADC state: Shows the state: RDY → REQ-OFF → OFF.

MS30546V1

Timing diagram for Figure 110 showing the effect of setting ADDIS=1 (JQM=0) on the JSQR queue. The diagram tracks the JSQR queue, ADDIS, ADC J context, and ADC state over time. It shows that setting ADDIS=1 flushes the queue but maintains the last active context (P1).

Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Figure 111. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1)

Timing diagram showing the flushing of the JSQR queue. The diagram illustrates four signals over time: JSQR queue, ADDIS, ADC J context, and ADC state. The JSQR queue starts with parameters P1 and P2. When the ADDIS bit is set by software, the queue is flushed and becomes empty (JSQR is read as 0x0000). The ADC J context is then returned by reading the JSQR, showing P1 and an empty context (0x0000). The ADC state transitions from RDY to REQ-OFF and then to OFF. The ADDIS bit is reset by hardware.

Queue is flushed and becomes empty (JSQR is read as 0x0000)

JSQR queue	P1, P2	EMPTY
ADDIS	Set by S/W	Reset by H/W
ADC J context (returned by reading JSQR)	P1	EMPTY (0x0000)
ADC state	RDY	REQ-OFF OFF

MS30547V1

Timing diagram showing the flushing of the JSQR queue. The diagram illustrates four signals over time: JSQR queue, ADDIS, ADC J context, and ADC state. The JSQR queue starts with parameters P1 and P2. When the ADDIS bit is set by software, the queue is flushed and becomes empty (JSQR is read as 0x0000). The ADC J context is then returned by reading the JSQR, showing P1 and an empty context (0x0000). The ADC state transitions from RDY to REQ-OFF and then to OFF. The ADDIS bit is reset by hardware.

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Queue of context: Starting the ADC with an empty queue

The following procedure must be followed to start ADC operation with an empty queue, in case the first context is not known at the time the ADC is initialized. This procedure is only applicable when JQM bit is reset:

5. Write a dummy JSQR with JEXTEN[1:0] not equal to 00 (otherwise triggering a software conversion)
6. Set JADSTART
7. Set JADSTP
8. Wait until JADSTART is reset
9. Set JADSTART.

Disabling the queue

It is possible to disable the queue by setting bit JQDIS=1 into the ADC_CFGR register.

21.4.22 Programmable resolution (RES) - Fast conversion mode

It is possible to perform faster conversion by reducing the ADC resolution.

The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the control bits RES[1:0]. Figure 116 , Figure 117 , Figure 118 and Figure 119 show the conversion result format with respect to the resolution as well as to the data alignment.

Lower resolution allows faster conversion time for applications where high-data precision is not required. It reduces the conversion time spent by the successive approximation steps according to Table 133 .

Table 133. $T_{SAR}$ timings depending on resolution

RES (bits)	$T_{SAR}$ (ADC clock cycles)	$T_{SAR}$ (ns) at $F_{ADC}= 30$ MHz	$T_{CONV}$ (ADC clock cycles) (with Sampling Time= 2.5 ADC clock cycles)	$T_{CONV}$ (ns) at $F_{ADC}= 30$ MHz
12	12.5 ADC clock cycles	416.67 ns	15 ADC clock cycles	500.0 ns
10	10.5 ADC clock cycles	350.0 ns	13 ADC clock cycles	433.33 ns
8	8.5 ADC clock cycles	283.33 ns	11 ADC clock cycles	366.67 ns
6	6.5 ADC clock cycles	216.67 ns	9 ADC clock cycles	300.0 ns

21.4.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP)

The ADC notifies the application for each end of regular conversion (EOC) event and each injected conversion (JEOC) event.

The ADC sets the EOC flag as soon as a new regular conversion data is available in the ADC_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared by the software either by writing 1 to it or by reading ADC_DR.

The ADC sets the JEOC flag as soon as a new injected conversion data is available in one of the ADC_JDRy register. An interrupt can be generated if bit JEOCIE is set. JEOC flag is cleared by the software either by writing 1 to it or by reading the corresponding ADC_JDRy register.

The ADC also notifies the end of Sampling phase by setting the status bit EOSMP (for regular conversions only). EOSMP flag is cleared by software by writing 1 to it. An interrupt can be generated if bit EOSMPIE is set.

21.4.24 End of conversion sequence (EOS, JEOS)

The ADC notifies the application for each end of regular sequence (EOS) and for each end of injected sequence (JEOS) event.

The ADC sets the EOS flag as soon as the last data of the regular conversion sequence is available in the ADC_DR register. An interrupt can be generated if bit EOSIE is set. EOS flag is cleared by the software either by writing 1 to it.

The ADC sets the JEOS flag as soon as the last data of the injected conversion sequence is complete. An interrupt can be generated if bit JEOSIE is set. JEOS flag is cleared by the software either by writing 1 to it.

21.4.25 Timing diagrams example (single/continuous modes, hardware/software triggers)

Figure 112. Single conversions of a sequence, software trigger

The diagram illustrates the timing for single conversions of a sequence. The ADSTART signal is triggered by software (SW) and hardware (HW). The EOC signal pulses for each conversion. The EOS signal pulses at the end of the sequence. The ADC state transitions from RDY to CH1, CH9, CH10, CH17, and back to RDY. The ADC_DR register contains the conversion results: D1, D9, D10, and D17. Reference MS30549V1 is present.

Timing diagram for single conversions of a sequence with a software trigger. It shows the relationship between ADSTART, EOC, EOS, ADC state, and ADC_DR signals over time. The sequence includes channels CH1, CH9, CH10, and CH17. The diagram is labeled with 'by SW' for software trigger and 'by HW' for hardware trigger. Reference MS30549V1 is present.

1. EXTEN[1:0]=00, CONT=0
2. Channels selected = 1,9, 10, 17; AUTDLY=0.

Figure 113. Continuous conversion of a sequence, software trigger

The diagram illustrates the timing for continuous conversion of a sequence. The ADCSTART signal is triggered by software (SW) and hardware (HW). The EOC signal pulses for each conversion. The EOS signal pulses at the end of the sequence. The ADSTP signal is used to stop the conversion. The ADC state transitions from READY to CH1, CH9, CH10, CH17, CH1, CH9, CH10, STP, READY, CH1, CH9, and back to READY. The ADC_DR register contains the conversion results: D1, D9, D10, D17, D1, D9, and D1. Reference MS30550V1 is present.

Timing diagram for continuous conversion of a sequence with a software trigger. It shows the relationship between ADCSTART, EOC, EOS, ADSTP, ADC state, and ADC_DR signals over time. The sequence includes channels CH1, CH9, CH10, and CH17. The diagram is labeled with 'by SW' for software trigger and 'by HW' for hardware trigger. Reference MS30550V1 is present.

1. EXTEN[1:0]=00, CONT=1
2. Channels selected = 1,9, 10, 17; AUTDLY=0.

Figure 114. Single conversions of a sequence, hardware trigger

MS31013V2

Timing diagram for single conversions of a sequence with hardware trigger. It shows signals ADSTART, EOC, EOS, TRGX(1), ADC state(2), and ADC_DR over time. ADSTART is a rising edge that starts the sequence. TRGX(1) is a periodic trigger signal. ADC state shows a sequence of RDY, CH1, CH2, CH3, CH4, READ, CH1, CH2, CH3, CH4, RDY. ADC_DR shows data points D1, D2, D3, D4 corresponding to the channels. Legend indicates: by s/w (software), by h/w (hardware), triggered, ignored, and Indicative timings.

1. TRGX ⁽¹⁾(over-frequency) is selected as trigger source, EXTEN[1:0] = 01, CONT = 0
2. Channels selected = 1, 2, 3, 4; AUTDLY=0.

Figure 115. Continuous conversions of a sequence, hardware trigger

MS31014V2

Timing diagram for continuous conversions of a sequence with hardware trigger. It shows signals ADSTART, EOC, EOS, ADSTP, TRGX(1), ADC(2), and ADC_DR over time. ADSTART is a rising edge that starts the continuous sequence. ADSTP is a rising edge that stops it. TRGX(1) is a periodic trigger signal. ADC(2) state shows a continuous sequence of CH1, CH2, CH3, CH4, CH1, CH2, CH3, CH4, CH1, STOP, RDY. ADC_DR shows data points D1, D2, D3, D4 repeating. Legend indicates: by s/w (software), by h/w (hardware), triggered, ignored, and Not in scale timings.

1. TRGX is selected as trigger source, EXTEN[1:0] = 10, CONT = 1
2. Channels selected = 1, 2, 3, 4; AUTDLY=0.

21.4.26 Data management

Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN)

Data and alignment

At the end of each regular conversion channel (when EOC event occurs), the result of the converted data is stored into the ADC_DR data register which is 16 bits wide.

At the end of each injected conversion channel (when JEOC event occurs), the result of the converted data is stored into the corresponding ADC_JDRy data register which is 16 bits wide.

The ALIGN bit in the ADC_CFGR register selects the alignment of the data stored after conversion. Data can be right- or left-aligned as shown in Figure 116 , Figure 117 , Figure 118 and Figure 119 .

Special case: when left-aligned, the data are aligned on a half-word basis except when the resolution is set to 6-bit. In that case, the data are aligned on a byte basis as shown in Figure 118 and Figure 119 .

Note: Left-alignment is not supported in oversampling mode. When ROVSE and/or JOVSE bit is set, the ALIGN bit value is ignored and the ADC only provides right-aligned data.

Offset

An offset y (y=1,2,3,4) can be applied to a channel by setting the bit OFFSETy_EN=1 into ADC_OF Ry register. The channel to which the offset will be applied is programmed into the bits OFFSETy_CH[4:0] of ADC_OF Ry register. In this case, the converted value is decreased by the user-defined offset written in the bits OFFSETy[11:0]. The result may be a negative value so the read data is signed and the SEXT bit represents the extended sign value.

Note: Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is set, the value of the OFFSETy_EN bit in ADC_OF Ry register is ignored (considered as reset).

Table 136 describes how the comparison is performed for all the possible resolutions for analog watchdog 1.

Table 134. Offset computation versus data resolution

Resolution (bits RES[1:0])	Subtraction between raw converted data and offset		Result	Comments
Resolution (bits RES[1:0])	Raw converted Data, left aligned	Offset	Result	Comments
00: 12-bit	DATA[11:0]	OFFSET[11:0]	Signed 12-bit data	-
01: 10-bit	DATA[11:2],00	OFFSET[11:0]	Signed 10-bit data	The user must configure OFFSET[1:0] to "00"

Table 134. Offset computation versus data resolution (continued)

Resolution (bits RES[1:0])	Subtraction between raw converted data and offset		Result	Comments
Resolution (bits RES[1:0])	Raw converted Data, left aligned	Offset	Result	Comments
10: 8-bit	DATA[11:4],00 00	OFFSET[11:0]	Signed 8-bit data	The user must configure OFFSET[3:0] to “0000”
11: 6-bit	DATA[11:6],00 0000	OFFSET[11:0]	Signed 6-bit data	The user must configure OFFSET[5:0] to “000000”

When reading data from ADC_DR (regular channel) or from ADC_JDRy (injected channel, y=1,2,3,4) corresponding to the channel “i”:

• If one of the offsets is enabled (bit OFFSETy_EN=1) for the corresponding channel, the read data is signed.
• If none of the four offsets is enabled for this channel, the read data is not signed.

Figure 116, Figure 117, Figure 118 and Figure 119 show alignments for signed and unsigned data.

Figure 116. Right alignment (offset disabled, unsigned value)

Diagram showing right alignment for 12-bit, 10-bit, 8-bit, and 6-bit data. Each section shows a 16-bit register layout with bits 15 down to 0. The data bits (D11-D0 for 12-bit, D9-D0 for 10-bit, D7-D0 for 8-bit, D5-D0 for 6-bit) are right-aligned in the lower bits, with the upper bits filled with zeros.

12-bit data
bit15 bit7 bit0

D11

D10

10-bit data
bit15 bit7 bit0

8-bit data
bit15 bit7 bit0

6-bit data
bit15 bit7 bit0

MS31015V1

Diagram showing right alignment for 12-bit, 10-bit, 8-bit, and 6-bit data. Each section shows a 16-bit register layout with bits 15 down to 0. The data bits (D11-D0 for 12-bit, D9-D0 for 10-bit, D7-D0 for 8-bit, D5-D0 for 6-bit) are right-aligned in the lower bits, with the upper bits filled with zeros.

Figure 117. Right alignment (offset enabled, signed value)

Diagram showing right alignment of ADC data for 12-bit, 10-bit, 8-bit, and 6-bit resolutions. Each resolution shows a 16-bit register layout with sign extension (SEXT) and data bits (D11-D0) aligned to the right. Bit 15 is the sign bit, bit 7 is the middle bit, and bit 0 is the least significant bit.

12-bit data
bit15 bit7 bit0

SEXT

D11

D10

10-bit data
bit15 bit7 bit0

SEXT

8-bit data
bit15 bit7 bit0

SEXT

6-bit data
bit15 bit7 bit0

SEXT

MS31016V1

Diagram showing right alignment of ADC data for 12-bit, 10-bit, 8-bit, and 6-bit resolutions. Each resolution shows a 16-bit register layout with sign extension (SEXT) and data bits (D11-D0) aligned to the right. Bit 15 is the sign bit, bit 7 is the middle bit, and bit 0 is the least significant bit.

Figure 118. Left alignment (offset disabled, unsigned value)

Diagram showing left alignment of ADC data for 12-bit, 10-bit, 8-bit, and 6-bit resolutions. Each resolution shows a 16-bit register layout with data bits (D11-D0) aligned to the left and the remaining bits filled with zeros. Bit 15 is the most significant bit, bit 7 is the middle bit, and bit 0 is the least significant bit.

12-bit data
bit15 bit7 bit0

D11

D10

10-bit data
bit15 bit7 bit0

8-bit data
bit15 bit7 bit0

6-bit data
bit15 bit7 bit0

MS31017V1

Diagram showing left alignment of ADC data for 12-bit, 10-bit, 8-bit, and 6-bit resolutions. Each resolution shows a 16-bit register layout with data bits (D11-D0) aligned to the left and the remaining bits filled with zeros. Bit 15 is the most significant bit, bit 7 is the middle bit, and bit 0 is the least significant bit.

Figure 119. Left alignment (offset enabled, signed value)

Diagram showing 12-bit, 10-bit, 8-bit, and 6-bit data alignment in a 16-bit register. Each section shows the mapping of data bits (D15 to D0) into the register, with sign extension (SEXT) for the most significant bit. The 12-bit data uses bits D11-D0, 10-bit uses D9-D0, 8-bit uses D7-D0, and 6-bit uses D5-D0, with the remaining bits filled with zeros or sign-extended values.

12-bit data
bit15 bit7 bit0

SEXT

D11

D10

10-bit data
bit15 bit7 bit0

SEXT

8-bit data
bit15 bit7 bit0

SEXT

6-bit data
bit15 bit7 bit0

SEXT

MS31018V1

Diagram showing 12-bit, 10-bit, 8-bit, and 6-bit data alignment in a 16-bit register. Each section shows the mapping of data bits (D15 to D0) into the register, with sign extension (SEXT) for the most significant bit. The 12-bit data uses bits D11-D0, 10-bit uses D9-D0, 8-bit uses D7-D0, and 6-bit uses D5-D0, with the remaining bits filled with zeros or sign-extended values.

ADC overrun (OVR, OVRMOD)

The overrun flag (OSR) notifies of that a buffer overrun event occurred when the regular converted data has not been read (by the CPU or the DMA) before new converted data became available.

The OVR flag is set if the EOC flag is still 1 at the time when a new conversion completes. An interrupt can be generated if bit OVRIE=1.

When an overrun condition occurs, the ADC is still operating and can continue converting unless the software decides to stop and reset the sequence by setting bit ADSTP=1.

OVR flag is cleared by software by writing 1 to it.

It is possible to configure if data is preserved or overwritten when an overrun event occurs by programming the control bit OVRMOD:

• OVRMOD=0: The overrun event preserves the data register from being overrun: the old data is maintained and the new conversion is discarded and lost. If OVR remains at 1, any further conversions will occur but the result data will be also discarded.
• OVRMOD=1: The data register is overwritten with the last conversion result and the previous unread data is lost. If OVR remains at 1, any further conversions will operate normally and the ADC_DR register will always contain the latest converted data.

Figure 120. Example of overrun (OVR)

Timing diagram showing an overrun (OVR) event in an ADC. The diagram illustrates the relationship between ADSTART, EOC, EOS, OVR, ADSTP, TRGx, ADC state, ADC_DR read access, and ADC_DR values for two OVRMOD settings. An overrun occurs when a new conversion starts before the previous one is read, causing data loss in OVRMOD=0 mode.

The timing diagram shows the following signals and states over time:

ADSTART ⁽¹⁾: Active-low signal that starts the conversion sequence.
EOC : End of Conversion flag, pulses high when a conversion is complete.
EOS : End of Sequence flag, pulses high when the last channel in the sequence is converted.
OVR : Overrun flag, goes high when a new conversion starts before the previous data is read (in OVRMOD=0 mode).
ADSTP : Active-low signal that stops the conversion sequence.
TRGx ⁽¹⁾: Trigger signal that initiates the conversion sequence.
ADC state ⁽²⁾: Shows the sequence of states: RDY, CH1, CH2, CH3, CH4, CH5, CH6, CH7, STOP, RDY.
ADC_DR read access : Shows software read accesses to the data register. In OVRMOD=0, the data for CH5 is overwritten before being read, labeled as "Overrun".
ADC_DR (OVRMOD=0) : Data register values: D1, D2, D3, D4. The value for CH5 is lost.
ADC_DR (OVRMOD=1) : Data register values: D1, D2, D3, D4, D5, D6. The latest conversion (CH5) is retained.

Legend for timing markers:

by s/w (software)
by h/w (hardware)
triggered

Indicative timings

MS31019V1

Timing diagram showing an overrun (OVR) event in an ADC. The diagram illustrates the relationship between ADSTART, EOC, EOS, OVR, ADSTP, TRGx, ADC state, ADC_DR read access, and ADC_DR values for two OVRMOD settings. An overrun occurs when a new conversion starts before the previous one is read, causing data loss in OVRMOD=0 mode.

Note: There is no overrun detection on the injected channels since there is a dedicated data register for each of the four injected channels.

Managing a sequence of conversions without using the DMA

If the conversions are slow enough, the conversion sequence can be handled by the software. In this case the software must use the EOC flag and its associated interrupt to handle each data. Each time a conversion is complete, EOC is set and the ADC_DR register can be read. OVRMOD should be configured to 0 to manage overrun events as an error.

Managing conversions without using the DMA and without overrun

It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). In this case, the OVRMOD bit must be configured to 1 and OVR flag should be ignored by the software. An overrun event will not prevent the ADC from continuing to convert and the ADC_DR register will always contain the latest conversion.

Managing conversions using the DMA

Since converted channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one channel. This avoids the loss of the data already stored in the ADC_DR register.

When the DMA mode is enabled (DMAEN bit set to 1 in the ADC_CFGR register in single ADC mode or MDMA different from 0b00 in dual ADC mode), a DMA request is generated after each conversion of a channel. This allows the transfer of the converted data from the ADC_DR register to the destination location selected by the software.

Despite this, if an overrun occurs (OVR=1) because the DMA could not serve the DMA transfer request in time, the ADC stops generating DMA requests and the data corresponding to the new conversion is not transferred by the DMA. Which means that all the data transferred to the RAM can be considered as valid.

Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten (refer to Section : ADC overrun (OVR, OVRMOD) ).

The DMA transfer requests are blocked until the software clears the OVR bit.

Two different DMA modes are proposed depending on the application use and are configured with bit DMACFG of the ADC_CFGR register in single ADC mode, or with bit DMACFG of the ADC_CCR register in dual ADC mode:

• DMA one shot mode (DMACFG=0).
This mode is suitable when the DMA is programmed to transfer a fixed number of data.
• DMA circular mode (DMACFG=1)
This mode is suitable when programming the DMA in circular mode.

DMA one shot mode (DMACFG=0)

In this mode, the ADC generates a DMA transfer request each time a new conversion data is available and stops generating DMA requests once the DMA has reached the last DMA transfer (when DMA_EOT interrupt occurs - refer to DMA paragraph) even if a conversion has been started again.

When the DMA transfer is complete (all the transfers configured in the DMA controller have been done):

• The content of the ADC data register is frozen.
• Any ongoing conversion is aborted with partial result discarded.
• No new DMA request is issued to the DMA controller. This avoids generating an overrun error if there are still conversions which are started.
• Scan sequence is stopped and reset.
• The DMA is stopped.

DMA circular mode (DMACFG=1)

In this mode, the ADC generates a DMA transfer request each time a new conversion data is available in the data register, even if the DMA has reached the last DMA transfer. This allows configuring the DMA in circular mode to handle a continuous analog input data stream.

21.4.27 Managing conversions using the DFSDM

The ADC conversion results can be transferred directly to the Digital filter for sigma delta modulators (DFSDM).

In this case, the DFSDMCFG bit must be set to 1 and DMAEN bit must be cleared to 0.

The ADC transfers all the 16 bits of the regular data register to the DFSDM and resets the EOC flag once the transfer is complete.

The data format must be 16-bit signed:

ADC_DR[15:12] = sign extended

ADC_DR[11] = sign

ADC_DR[11:0] = data

To obtain 16-bit signed format in 12-bit ADC mode, the software needs to configure the OFFSETy[11:0] to 0x800 after having set OFFSETy_EN to 1.

Only right aligned data format is available for the DFSDM interface (see Figure 117: Right alignment (offset enabled, signed value) ).

21.4.28 Dynamic low-power features

Auto-delayed conversion mode (AUTDLY)

The ADC implements an auto-delayed conversion mode controlled by the AUTDLY configuration bit. Auto-delayed conversions are useful to simplify the software as well as to optimize performance of an application clocked at low frequency where there would be risk of encountering an ADC overrun.

When AUTDLY=1, a new conversion can start only if all the previous data of the same group has been treated:

• For a regular conversion: once the ADC_DR register has been read or if the EOC bit has been cleared (see Figure 121 ).
• For an injected conversion: when the JEOS bit has been cleared (see Figure 122 ).

This is a way to automatically adapt the speed of the ADC to the speed of the system which will read the data.

The delay is inserted after each regular conversion (whatever DISCEN=0 or 1) and after each sequence of injected conversions (whatever JDISCEN=0 or 1).

Note: There is no delay inserted between each conversions of the injected sequence, except after the last one.

During a conversion, a hardware trigger event (for the same group of conversions) occurring during this delay is ignored.

Note: This is not true for software triggers where it remains possible during this delay to set the bits ADSTART or JADSTART to restart a conversion: it is up to the software to read the data before launching a new conversion.

No delay is inserted between conversions of different groups (a regular conversion followed by an injected conversion or conversely):

• If an injected trigger occurs during the automatic delay of a regular conversion, the injected conversion starts immediately (see Figure 122 ).
• Once the injected sequence is complete, the ADC waits for the delay (if not ended) of the previous regular conversion before launching a new regular conversion (see Figure 124 ).

The behavior is slightly different in auto-injected mode (JAUTO=1) where a new regular conversion can start only when the automatic delay of the previous injected sequence of conversion has ended (when JEOS has been cleared). This is to ensure that the software can read all the data of a given sequence before starting a new sequence (see Figure 125 ).

To stop a conversion in continuous auto-injection mode combined with autodelay mode (JAUTO=1, CONT=1 and AUTDLY=1), follow the following procedure:

1. Wait until JEOS=1 (no more conversions are restarted)
2. Clear JEOS,
3. Set ADSTP=1
4. Read the regular data.

If this procedure is not respected, a new regular sequence can restart if JEOS is cleared after ADSTP has been set.

In AUTDLY mode, a hardware regular trigger event is ignored if it occurs during an already ongoing regular sequence or during the delay that follows the last regular conversion of the sequence. It is however considered pending if it occurs after this delay, even if it occurs during an injected sequence of the delay that follows it. The conversion then starts at the end of the delay of the injected sequence.

In AUTDLY mode, a hardware injected trigger event is ignored if it occurs during an already ongoing injected sequence or during the delay that follows the last injected conversion of the sequence.

Figure 121. AUTODLY=1, regular conversion in continuous mode, software trigger

Timing diagram showing ADSTART(1), EOC, EOS, ADSTP, ADC_DR read access, ADC state, and ADC_DR signals over time. The diagram illustrates the sequence of events for a software-triggered continuous conversion with autodelay. It shows the ADC state transitioning from RDY to CH1, DLY, CH2, DLY, CH3, DLY, CH1, DLY, STOP, and back to RDY. Data points D1, D2, D3, and D1 are shown in the ADC_DR register. Triggers are indicated by 'by SW' (software) and 'by HW' (hardware) labels.

The timing diagram shows the following signals and states over time:

ADSTART(1): A signal that goes high to start a conversion (labeled 'by SW') and later goes low.
EOC (End of Conversion): Pulses high when each conversion (CH1, CH2, CH3) is complete.
EOS (End of Sequence): Goes high after the third conversion (CH3) and returns low when ADSTP is set.
ADSTP: A signal that goes high to stop the sequence.
ADC_DR read access: Pulses indicating when data is read from the ADC_DR register.
ADC state: A sequence of states: RDY, CH1, DLY, CH2, DLY, CH3, DLY, CH1, DLY, STOP, RDY.
ADC_DR: Shows data values D1, D2, D3, and D1 being output.

Legend: Indicative timings

MS31020V1

Timing diagram showing ADSTART(1), EOC, EOS, ADSTP, ADC_DR read access, ADC state, and ADC_DR signals over time. The diagram illustrates the sequence of events for a software-triggered continuous conversion with autodelay. It shows the ADC state transitioning from RDY to CH1, DLY, CH2, DLY, CH3, DLY, CH1, DLY, STOP, and back to RDY. Data points D1, D2, D3, and D1 are shown in the ADC_DR register. Triggers are indicated by 'by SW' (software) and 'by HW' (hardware) labels.

1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, CHANNELS = 1,2,3
3. Injected configuration DISABLED

Figure 122. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0; JDISCEN=0)

The timing diagram illustrates the ADC operation with AUTODLY=1. The sequence starts with a regular trigger (by s/w) leading to the RDY state. The first regular conversion sequence consists of CH1, DLY (CH1), CH2, DLY (CH2), and CH5. Data D1 and D2 are produced. An injected trigger (by h/w) occurs during the CH5 conversion and is ignored. After CH5, the regular sequence continues with CH6 (injected, ignored), CH3, DLY (CH3), CH1, DLY (CH1), and CH2. Data D3 and D1 are produced. A second injected trigger (by h/w) occurs during the CH3 conversion and is not ignored, interrupting the regular sequence. The injected sequence consists of CH5, DLY (inj), and CH6, producing data D5 and D6 in ADC_JDR1 and ADC_JDR2 respectively. After the injected sequence, the regular sequence resumes with CH1, DLY (CH1), and CH2, producing data D1. The diagram also shows EOC (End of Conversion) and EOS (End of Sequence) signals, and the ADC_DR read access signal. A legend at the bottom indicates that solid lines represent 'by s/w' triggers and dashed lines represent 'by h/w' triggers.

Timing diagram showing regular and injected ADC conversions with delays (DLY) and triggers. The diagram illustrates the sequence of events when regular conversions are interrupted by injected ones. It includes signals for Regular trigger, ADC state (RDY, CH1, DLY, CH2, CH5, CH6, CH3), EOC, EOS, ADC_DR read access, ADC_DR data (D1, D2, D3, D5, D6), Injected trigger, JEOS, ADC_JDR1, and ADC_JDR2. Annotations indicate 'Ignored' triggers and 'Not ignored (occurs during injected sequence)' triggers. A legend at the bottom shows 'by s/w' and 'by h/w' trigger symbols.

1. AUTODLY=1
2. Regular configuration: EXTEN[1:0]=01 (HW trigger), CONT=0, DISCEN=0, CHANNELS = 1, 2, 3
3. Injected configuration: JEXTEN[1:0]=01 (HW Trigger), JDISCEN=0, CHANNELS = 5,6

Figure 123. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=1, JDISCEN=1)

MS31022V1

Timing diagram showing regular and injected ADC conversions with delays and triggers. The diagram illustrates the sequence of events for regular conversions (CH1, CH2, CH3) and injected conversions (CH5, CH6) triggered by hardware signals. It shows the ADC state (RDY, CH1, DLY, RDY, CH2, DLY, RDY, CH5, RDY, CH6, CH3, DLY, RDY, CH1, DLY, RDY, CH2), EOC, EOS, ADC_DR, read access, ADC_DR, Injected trigger, JEOS, ADC_JDR1, and ADC_JDR2 signals over time. Delays (DLY) are indicated for regular channels and injected channels. Data values D1, D2, D3, D5, and D6 are shown in the ADC_DR and ADC_JDR registers. A legend indicates 'by SW' (software) and 'by HW' (hardware) triggers.

1. AUTODLY=1
2. Regular configuration: EXTEN[1:0]=01 (HW trigger), CONT=0, DISCEN=1, DISCNUM=1, CHANNELS = 1, 2, 3.
3. Injected configuration: JEXTEN[1:0]=01 (HW Trigger), JDISCEN=1, CHANNELS = 5,6

Figure 124. AUTODLY=1, regular continuous conversions interrupted by injected conversions

MS31023V3

Timing diagram for Figure 124 showing regular continuous conversions (CH1, CH2, CH3) with delays (DLY) and injected conversions (CH5, CH6) interrupting the sequence. The diagram includes signals for ADSTART, ADC state, EOC, EOS, ADC_DR read access, ADC_DR, Injected trigger, JEOS, ADC_JDR1, and ADC_JDR2. Data points D1, D2, D3, D5, and D6 are shown. A note indicates that the injected conversion delay is ignored in this mode.

1. AUTODLY=1
2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2, 3
3. Injected configuration: JEXTEN[1:0]=01 (HW Trigger), JDISCEN=0, CHANNELS = 5,6

Figure 125. AUTODLY=1 in auto- injected mode (JAUTO=1)

MS31024V3

Timing diagram for Figure 125 showing regular continuous conversions (CH1, CH2, CH3) with delays (DLY) and injected conversions (CH5, CH6) in auto-injected mode. The diagram includes signals for ADSTART, ADC state, EOC, EOS, ADC_DR read access, ADC_DR, JEOS, ADC_JDR1, and ADC_JDR2. Data points D1, D2, D3, D5, and D6 are shown. A note indicates 'No delay' between regular and injected conversions.

1. AUTODLY=1
2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2
3. Injected configuration: JAUTO=1, CHANNELS = 5,6

21.4.29 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

The three AWD analog watchdogs monitor whether some channels remain within a configured voltage range (window).

Figure 126. Analog watchdog guarded area

Diagram showing the analog watchdog guarded area. A vertical axis represents 'Analog voltage'. Two horizontal lines mark the 'Higher threshold' (HTx) and 'Lower threshold' (LTx). The region between these thresholds is shaded and labeled 'Guarded area'. The diagram is labeled MS45396V1.

AWDx flag and interrupt

An interrupt can be enabled for each of the 3 analog watchdogs by setting AWDxE in the ADC_IER register (x=1,2,3).

AWDx (x=1,2,3) flag is cleared by software by writing 1 to it.

The ADC conversion result is compared to the lower and higher thresholds before alignment.

Description of analog watchdog 1

The AWD analog watchdog 1 is enabled by setting the AWD1EN bit in the ADC_CFGR register. This watchdog monitors whether either one selected channel or all enabled channels ⁽¹⁾remain within a configured voltage range (window).

Table 135 shows how the ADC_CFGR registers should be configured to enable the analog watchdog on one or more channels.

Table 135. Analog watchdog channel selection

Channels guarded by the analog watchdog	AWD1SGL bit	AWD1EN bit	JAWD1EN bit
None	x	0	0
All injected channels	0	0	1
All regular channels	0	1	0
All regular and injected channels	0	1	1
Single ⁽¹⁾injected channel	1	0	1
Single ⁽¹⁾regular channel	1	1	0
Single ⁽¹⁾regular or injected channel	1	1	1

1. Selected by the AWD1CH[4:0] bits. The channels must also be programmed to be converted in the appropriate regular or injected sequence.

The AWD1 analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold.

These thresholds are programmed in bits HT1[11:0] and LT1[11:0] of the ADC_TR1 register for the analog watchdog 1. When converting data with a resolution of less than 12 bits (according to bits RES[1:0]), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned).

Table 136 describes how the comparison is performed for all the possible resolutions for analog watchdog 1.

Table 136. Analog watchdog 1 comparison

Resolution( bit RES[1:0])	Analog watchdog comparison between:		Comments
Resolution( bit RES[1:0])	Raw converted data, left aligned	Thresholds	Comments
00: 12-bit	DATA[11:0]	LT1[11:0] and HT1[11:0]	-
01: 10-bit	DATA[11:2],00	LT1[11:0] and HT1[11:0]	User must configure LT1[1:0] and HT1[1:0] to 00
10: 8-bit	DATA[11:4],0000	LT1[11:0] and HT1[11:0]	User must configure LT1[3:0] and HT1[3:0] to 0000
11: 6-bit	DATA[11:6],000000	LT1[11:0] and HT1[11:0]	User must configure LT1[5:0] and HT1[5:0] to 000000

Description of analog watchdog 2 and 3

The second and third analog watchdogs are more flexible and can guard several selected channels by programming the corresponding bits in AWDxCH[18:0] (x=2,3).

The corresponding watchdog is enabled when any bit of AWDxCH[18:0] (x=2,3) is set.

They are limited to a resolution of 8 bits and only the 8 MSBs of the thresholds can be programmed into HTx[7:0] and LTx[7:0]. Table 137 describes how the comparison is performed for all the possible resolutions.

Table 137. Analog watchdog 2 and 3 comparison

Resolution (bits RES[1:0])	Analog watchdog comparison between:		Comments
Resolution (bits RES[1:0])	Raw converted data, left aligned	Thresholds	Comments
00: 12-bit	DATA[11:4]	LTx[7:0] and HTx[7:0]	DATA[3:0] are not relevant for the comparison
01: 10-bit	DATA[11:4]	LTx[7:0] and HTx[7:0]	DATA[3:2] are not relevant for the comparison
10: 8-bit	DATA[11:4]	LTx[7:0] and HTx[7:0]	-
11: 6-bit	DATA[11:6],00	LTx[7:0] and HTx[7:0]	User must configure LTx[1:0] and HTx[1:0] to 00

ADC _y_AWD _x_OUT signal output generation

Each analog watchdog is associated to an internal hardware signal ADC _y_AWD _x_OUT (y=ADC number, x=watchdog number) which is directly connected to the ETR input (external trigger) of some on-chip timers. Refer to the on-chip timers section to understand how to select the ADC _y_AWD _x_OUT signal as ETR.

ADC _y_AWD _x_OUT is activated when the associated analog watchdog is enabled:

• ADC _y_AWD _x_OUT is set when a guarded conversion is outside the programmed thresholds.
• ADC _y_AWD _x_OUT is reset after the end of the next guarded conversion which is inside the programmed thresholds (It remains at 1 if the next guarded conversions are still outside the programmed thresholds).
• ADC _y_AWD _x_OUT is also reset when disabling the ADC (when setting ADDIS=1). Note that stopping regular or injected conversions (setting ADSTP=1 or JADSTP=1) has no influence on the generation of ADC _y_AWD _x_OUT.

Note: AWD _xflag is set by hardware and reset by software: AWD _xflag has no influence on the generation of ADC _y_AWD _x_OUT (ex: ADC _y_AWD _x_OUT can toggle while AWD _xflag remains at 1 if the software did not clear the flag).

Figure 127. ADC _y_AWD _x_OUT signal generation (on all regular channels)

Timing diagram showing ADC STATE, EOC FLAG, AWDx FLAG, and ADCy_AWDx_OUT signals across seven conversions. The diagram shows how the output signal toggles based on whether conversions are 'inside' or 'outside' thresholds, while the AWDx flag remains high until manually cleared.

The timing diagram illustrates the relationship between the ADC state, End of Conversion (EOC) flag, Watchdog Flag (AWD _x), and the output signal (ADC _y_AWD _x_OUT) during a sequence of seven regular conversions. The conversions are labeled Conversion1 through Conversion7, with their status relative to programmed thresholds indicated as 'inside' or 'outside'.

ADC STATE: Starts in 'RDY' state, then transitions through Conversion1 to Conversion7. Conversion1 is 'inside', Conversion2 is 'outside', Conversion3 is 'inside', Conversion4 is 'outside', Conversion5 is 'outside', Conversion6 is 'outside', and Conversion7 is 'inside'.
EOC FLAG: Pulses high at the end of each conversion (Conversion1 through Conversion7).
AWD _xFLAG: Goes high after Conversion2 (outside) and stays high. It is manually 'cleared by S/W' (Software) after each subsequent 'outside' conversion (Conversions 4, 5, and 6). It remains high until the end of Conversion7 (inside), at which point it goes low.
ADC _y_AWD _x_OUT: Goes high after Conversion2 (outside) and stays high until the end of Conversion7 (inside), where it goes low. It does not toggle back high after the manual clearing of the AWD _xflag.

Legend:

- Converting regular channels 1,2,3,4,5,6,7
- Regular channels 1,2,3,4,5,6,7 are all guarded

MS31025V1

Timing diagram showing ADC STATE, EOC FLAG, AWDx FLAG, and ADCy_AWDx_OUT signals across seven conversions. The diagram shows how the output signal toggles based on whether conversions are 'inside' or 'outside' thresholds, while the AWDx flag remains high until manually cleared.

Figure 128. ADC_y_AWD _x_OUT signal generation (AWD _xflag not cleared by software)

Timing diagram for Figure 128 showing ADC STATE, EOC FLAG, AWDx FLAG, and ADCy_AWDx_OUT signals for regular channels 1-7. The AWDx FLAG is set by Conversion2 and remains high because it is not cleared by software. The ADCy_AWDx_OUT signal is high from Conversion2 to Conversion7.

EOC FLAG: Pulses at the end of each conversion.

AWDx FLAG: Set by Conversion2, not cleared by S/W.

ADC _y_AWD _x_OUT: High from Conversion2 to Conversion7.

- Converting regular channels 1,2,3,4,5,6,7
- Regular channels 1,2,3,4,5,6,7 are all guarded

MS31026V1

Timing diagram for Figure 128 showing ADC STATE, EOC FLAG, AWDx FLAG, and ADCy_AWDx_OUT signals for regular channels 1-7. The AWDx FLAG is set by Conversion2 and remains high because it is not cleared by software. The ADCy_AWDx_OUT signal is high from Conversion2 to Conversion7.

Figure 129. ADC_y_AWD _x_OUT signal generation (on a single regular channel)

Timing diagram for Figure 129 showing ADC STATE, EOC FLAG, EOS FLAG, AWDx FLAG, and ADCy_AWDx_OUT signals for regular channels 1 and 2. Only channel 1 is guarded. The AWDx FLAG is cleared by software. The ADCy_AWDx_OUT signal is high only when Conversion1 is 'inside'.

EOC FLAG: Pulses at the end of each conversion.

EOS FLAG: Pulses at the end of each sequence.

AWDx FLAG: Set by Conversion1 (inside), cleared by S/W.

ADC _y_AWD _x_OUT: High only during Conversion1 (inside).

- Converting regular channels 1 and 2
- Only channel 1 is guarded

MS31027V1

Timing diagram for Figure 129 showing ADC STATE, EOC FLAG, EOS FLAG, AWDx FLAG, and ADCy_AWDx_OUT signals for regular channels 1 and 2. Only channel 1 is guarded. The AWDx FLAG is cleared by software. The ADCy_AWDx_OUT signal is high only when Conversion1 is 'inside'.

Figure 130. ADC_y_AWD _x_OUT signal generation (on all injected channels)

Timing diagram for Figure 130 showing ADC STATE, JEOS FLAG, AWDx FLAG, and ADCy_AWDx_OUT signals for injected channels 1-4. All injected channels are guarded. The AWDx FLAG is cleared by software after each 'inside' conversion. The ADCy_AWDx_OUT signal is high whenever any injected channel is 'inside'.

JEOS FLAG: Pulses at the end of each injected sequence.

AWDx FLAG: Set by Conversion1 (inside), cleared by S/W. Set by Conversion3 (inside), cleared by S/W.

ADC _y_AWD _x_OUT: High during Conversion1 (inside), Conversion3 (inside), and Conversion1 (outside).

- Converting the injected channels 1, 2, 3, 4
- All injected channels 1, 2, 3, 4 are guarded

MS31028V1

Timing diagram for Figure 130 showing ADC STATE, JEOS FLAG, AWDx FLAG, and ADCy_AWDx_OUT signals for injected channels 1-4. All injected channels are guarded. The AWDx FLAG is cleared by software after each 'inside' conversion. The ADCy_AWDx_OUT signal is high whenever any injected channel is 'inside'.

21.4.30 Oversampler

The oversampling unit performs data pre-processing to offload the CPU. It is able to handle multiple conversions and average them into a single data with increased data width, up to 16-bit.

It provides a result with the following form, where N and M can be adjusted:

\text{Result} = \frac{1}{M} \times \sum_{n=0}^{n=N-1} \text{Conversion}(t_n)

It allows to perform by hardware the following functions: averaging, data rate reduction, SNR improvement, basic filtering.

The oversampling ratio N is defined using the OVFS[2:0] bits in the ADC_CFGR2 register, and can range from 2x to 256x. The division coefficient M consists of a right bit shift up to 8 bits, and is defined using the OVSS[3:0] bits in the ADC_CFGR2 register.

The summation unit can yield a result up to 20 bits (256x 12-bit results), which is first shifted right. It is then truncated to the 16 least significant bits, rounded to the nearest value using the least significant bits left apart by the shifting, before being finally transferred into the ADC_DR data register.

Note: If the intermediary result after the shifting exceeds 16-bit, the result is truncated as is, without saturation.

Figure 131. 20-bit to 16-bit result truncation

The diagram illustrates the truncation of a 20-bit raw data to a 16-bit result. The raw data is shown as a 20-bit word with bits 19 to 0. An arrow labeled 'Shifting' indicates a right shift of 4 bits. The resulting 16-bit word has bits 15 to 0. The final step is 'Truncation and rounding', which produces a 16-bit result. The diagram is labeled MS34453V1.

Diagram showing the truncation of a 20-bit raw data to a 16-bit result. The raw data has bits 19-0. After shifting right by 4 bits, the result has bits 15-0. Truncation and rounding are applied to the 16-bit result.

Figure 132 gives a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result.

Figure 132. Numerical example with 5-bit shift and rounding

The diagram shows a numerical example of the processing. The raw 20-bit data is represented as a 5-digit hexadecimal number: 3 B 7 D 7. After a 5-bit right shift and rounding to the nearest value, the final 16-bit result is 1 D B F. The diagram is labeled MS34454V1.

Numerical example showing a 20-bit raw data (3 B 7 D 7) being shifted right by 5 bits and rounded to the nearest value to produce a 16-bit result (1 D B F).

Table 138 gives the data format for the various N and M combinations, for a raw conversion data equal to 0xFFF.

Table 138. Maximum output results versus N and M (gray cells indicate truncation)

Over sampling ratio	Max Raw data	No-shift	1-bit shift	2-bit shift	3-bit shift	4-bit shift	5-bit shift	6-bit shift	7-bit shift	8-bit shift
Over sampling ratio	Max Raw data	OVSS = 0000	OVSS = 0001	OVSS = 0010	OVSS = 0011	OVSS = 0100	OVSS = 0101	OVSS = 0110	OVSS = 0111	OVSS = 1000
2x	0x1FFE	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100	0x0080	0x0040	0x020
4x	0x3FFC	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100	0x0080	0x0040
8x	0x7FF8	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100	0x0080
16x	0xFFF0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100
32x	0x1FFE0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200
64x	0x3FFC0	0xFFC0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400
128x	0x7FF80	0xFF80	0xFFC0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800
256x	0xFFF00	0xFF00	0xFF80	0xFFC0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF

There are no changes for conversion timings in oversampled mode: the sample time is maintained equal during the whole oversampling sequence. A new data is provided every N conversions, with an equivalent delay equal to $N \times T_{\text{CONV}} = N \times (t_{\text{S MPL}} + t_{\text{S AR}})$ . The flags are set as follows:

• The end of the sampling phase (EOSMP) is set after each sampling phase
• The end of conversion (EOC) occurs once every N conversions, when the oversampled result is available
• The end of sequence (EOS) occurs once the sequence of oversampled data is completed (i.e. after N x sequence length conversions total)

ADC operating modes supported when oversampling (single ADC mode)

In oversampling mode, most of the ADC operating modes are maintained:

• Single or continuous mode conversions
• ADC conversions start either by software or with triggers
• ADC stop during a conversion (abort)
• Data read via CPU or DMA with overrun detection
• Low-power modes (AUTDLY)
• Programmable resolution: in this case, the reduced conversion values (as per RES[1:0] bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the same way as 12-bit conversions are

Note: The alignment mode is not available when working with oversampled data. The ALIGN bit in ADC_CFGR1 is ignored and the data are always provided right-aligned.

Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is set, the value of the OFFSETy_EN bit in ADC_OFRy register is ignored (considered as reset).

Analog watchdog

The analog watchdog functionality is maintained (AWDSGL and AWDEN bits), with the following difference:

– The RES[1:0] bits are ignored, comparison is always done using the full 12-bit values HT[11:0] and LT[11:0]
– the comparison is performed on the most significant 12-bit of the 16-bit oversampled results ADC_DR[15:4]

Note: Care must be taken when using high shifting values, this will reduce the comparison range. For instance, if the oversampled result is shifted by 4 bits, thus yielding a 12-bit data right-aligned, the effective analog watchdog comparison can only be performed on 8 bits. The comparison is done between ADC_DR[11:4] and HT[0:7] / LT[0:7], and HT[11:8] / LT[11:8] must be kept reset.

Triggered mode

The averager can also be used for basic filtering purpose. Although not a very powerful filter (slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject constant parasitic frequencies (typically coming from the mains or from a switched mode power supply). For this purpose, a specific discontinuous mode can be enabled with TROVS bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a user and independent from the conversion time itself.

Figure 133 below shows how conversions are started in response to triggers during discontinuous mode.

If the TROVS bit is set, the content of the DISCEN bit is ignored and considered as 1.

Figure 133. Triggered regular oversampling mode (TROVS bit = 1)

Figure 133: Triggered regular oversampling mode (TROVS bit = 1). The diagram illustrates two scenarios for regular oversampling. In the top scenario (CONT=0, DISCEN=1, TROVS=0), a single trigger initiates a sequence of four conversions: Ch(N)0, Ch(N)1, Ch(N)2, and Ch(N)3. The End of Conversion (EOC) flag is set after the fourth conversion. In the bottom scenario (CONT=0, DISCEN=1, TROVS=1), each of the seven triggers initiates a single conversion. The sequence of conversions is Ch(N)0, Ch(N)1, Ch(N)2, Ch(N)3, Ch(N)0, Ch(N)1, and Ch(N)2. The EOC flag is set after the fourth conversion (Ch(N)3).

Injected and regular sequencer management when oversampling

In oversampling mode, it is possible to have differentiated behavior for injected and regular sequencers. The oversampling can be enabled for both sequencers with some limitations if they have to be used simultaneously (this is related to a unique accumulation unit).

Oversampling regular channels only

The regular oversampling mode bit ROVSM defines how the regular oversampling sequence is resumed if it is interrupted by injected conversion:

• In continued mode, the accumulation restarts from the last valid data (prior to the conversion abort request due to the injected trigger). This ensures that oversampling will be complete whatever the injection frequency (providing at least one regular conversion can be complete between triggers);
• In resumed mode, the accumulation restarts from 0 (previous conversion results are ignored). This mode allows to guarantee that all data used for oversampling were converted back-to-back within a single timeslot. Care must be taken to have a injection trigger period above the oversampling period length. If this condition is not respected, the oversampling cannot be complete and the regular sequencer will be blocked.

Figure 134 gives examples for a 4x oversampling ratio.

Figure 134. Regular oversampling modes (4x ratio)

Continued mode: ROVSE = 1, JOVSE = 0, ROVSM = 0, TROVS = X

Resumed mode: ROVSE = 1, JOVSE = 0, ROVSM = 1, TROVS = X

MS34456V1

Figure 134: Regular oversampling modes (4x ratio). The diagram illustrates two scenarios for regular oversampling when interrupted by injected channels. In the top scenario (Continued mode), the regular sequence is Ch(N)0, Ch(N)1, Ch(N)2, Ch(N)3, Ch(M)0, Ch(M)1. An injected trigger occurs before Ch(M)1, causing an abort. Injected channels Ch(J) and Ch(K) are converted, ending with JEOC. After the abort, oversampling is stopped. When the regular sequence resumes, it starts from Ch(M)1, continuing the oversampling accumulation. In the bottom scenario (Resumed mode), the regular sequence is the same. An injected trigger occurs before Ch(M)1, causing an abort. Injected channels Ch(J) and Ch(K) are converted, ending with JEOC. After the abort, oversampling is aborted. When the regular sequence resumes, it restarts from Ch(M)0, restarting the oversampling accumulation from zero.

Oversampling Injected channels only

The Injected oversampling mode bit JOVSE enables oversampling solely for conversions in the injected sequencer.

Oversampling regular and Injected channels

It is possible to have both ROVSE and JOVSE bits set. In this case, the regular oversampling mode is forced to resumed mode (ROVSM bit ignored), as represented on Figure 135 below.

Figure 135. Regular and injected oversampling modes used simultaneously

Timing diagram for Figure 135 showing regular and injected oversampling. Regular channels: Ch(N)0, Ch(N)1, Ch(N)2, Ch(N)3, Ch(M)0, Ch(M)1. Injected channels: Ch(J)0, Ch(J)1, Ch(J)2, Ch(J)3. A trigger starts the regular sequence. After Ch(N)3, an 'Abort' occurs, and oversampling is aborted. Later, after Ch(J)3, a 'JEOC' occurs. When the regular sequence resumes, it starts with Ch(M)0, Ch(M)1, and oversampling is resumed. Configuration: ROVSE = 1, JOVSE = 1, ROVSM = X, TROVS = 0.

Regular channels: Ch(N) ₀| Ch(N) ₁| Ch(N) ₂| Ch(N) ₃| Ch(M) ₀| Ch(M) ₁

Injected channels: Ch(J) ₀| Ch(J) ₁| Ch(J) ₂| Ch(J) ₃

Trigger → Abort → Oversampling aborted

JEOC → Oversampling resumed → Ch(M) ₀| Ch(M) ₁

ROVSE = 1, JOVSE = 1, ROVSM = X, TROVS = 0

MS34457V1

Timing diagram for Figure 135 showing regular and injected oversampling. Regular channels: Ch(N)0, Ch(N)1, Ch(N)2, Ch(N)3, Ch(M)0, Ch(M)1. Injected channels: Ch(J)0, Ch(J)1, Ch(J)2, Ch(J)3. A trigger starts the regular sequence. After Ch(N)3, an 'Abort' occurs, and oversampling is aborted. Later, after Ch(J)3, a 'JEOC' occurs. When the regular sequence resumes, it starts with Ch(M)0, Ch(M)1, and oversampling is resumed. Configuration: ROVSE = 1, JOVSE = 1, ROVSM = X, TROVS = 0.

Triggered regular oversampling with injected conversions

It is possible to have triggered regular mode with injected conversions. In this case, the injected mode oversampling mode must be disabled, and the ROVSM bit is ignored (resumed mode is forced). The JOVSE bit must be reset. The behavior is represented on Figure 136 below.

Figure 136. Triggered regular oversampling with injection

Timing diagram for Figure 136 showing triggered regular oversampling with injection. Regular channels: Ch(N)0, Ch(N)1, Ch(N)2. Injected channels: Ch(J), Ch(K). Triggers start each regular channel. When Ch(N)2 is triggered, an 'Abort' occurs, and the injected sequence Ch(J), Ch(K) is converted. After the injected sequence, the regular sequence resumes with Ch(N)0. Configuration: ROVSE = 1, JOVSE = 0, ROVSM = X, TROVS = 1.

Regular channels: Ch(N) ₀| Ch(N) ₁| Ch(N) ₂

Injected channels: Ch(J) | Ch(K)

Trigger → Trigger → Trigger → Abort → Oversampling resumed → Ch(N) ₀

ROVSE = 1, JOVSE = 0, ROVSM = X, TROVS = 1

MS34458V2

Timing diagram for Figure 136 showing triggered regular oversampling with injection. Regular channels: Ch(N)0, Ch(N)1, Ch(N)2. Injected channels: Ch(J), Ch(K). Triggers start each regular channel. When Ch(N)2 is triggered, an 'Abort' occurs, and the injected sequence Ch(J), Ch(K) is converted. After the injected sequence, the regular sequence resumes with Ch(N)0. Configuration: ROVSE = 1, JOVSE = 0, ROVSM = X, TROVS = 1.

Auto-injected mode

It is possible to oversample auto-injected sequences and have all conversions results stored in registers to save a DMA resource. This mode is available only with both regular and injected oversampling active: JAUTO = 1, ROVSE = 1 and JOVSE = 1, other combinations are not supported. The ROVSM bit is ignored in auto-injected mode. The Figure 137 below shows how the conversions are sequenced.

Figure 137. Oversampling in auto-injected mode

Regular channels $$ N_0 N_1 N_2 N_3 $$

Injected channels $$ I_0 I_1 I_2 I_3 J_0 J_1 J_2 J_3 K_0 K_1 K_2 K_3 L_0 L_1 L_2 L_3 $$

$$ JAUTO = 1, ROVSE = 1, JOVSE = 1, ROVSM = X, TROVS = 0 $$

MS34459V1

Diagram illustrating oversampling in auto-injected mode. It shows a sequence of regular channels (N0, N1, N2, N3) and injected channels (I0, I1, I2, I3, J0, J1, J2, J3, K0, K1, K2, K3, L0, L1, L2, L3). The sequence starts with regular channels, followed by injected channels, and then returns to regular channels. The configuration is JAUTO = 1, ROVSE = 1, JOVSE = 1, ROVSM = X, TROVS = 0. The diagram is labeled MS34459V1.

It is possible to have also the triggered mode enabled, using the TROVS bit. In this case, the ADC must be configured as following: JAUTO = 1, DISCEN = 0, JDISCEN = 0, ROVSE = 1, JOVSE = 1 and TROVSE = 1.

Dual ADC modes supported when oversampling

It is possible to have oversampling enabled when working in dual ADC configuration, for the injected simultaneous mode and regular simultaneous mode. In this case, the two ADCs must be programmed with the very same settings (including oversampling).

All other dual ADC modes are not supported when either regular or injected oversampling is enabled (ROVSE = 1 or JOVSE = 1).

Combined modes summary

The Table 139 below summarizes all combinations, including modes not supported.

Table 139. Oversampler operating modes summary

Regular Oversampling ROVSE	Injected Oversampling JOVSE	Oversampler mode ROVSM 0 = continued 1 = resumed	Triggered Regular mode TROVS	Comment
1	0	0	0	Regular continued mode
1	0	0	1	Not supported
1	0	1	0	Regular resumed mode
1	0	1	1	Triggered regular resumed mode
1	1	0	X	Not supported
1	1	1	0	Injected and regular resumed mode
1	1	1	1	Not supported
0	1	X	X	Injected oversampling

21.4.31 Dual ADC modes

Dual ADC modes can be used in devices with two ADCs or more (see Figure 138 ).

In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADCx master to the ADC slave, depending on the mode selected by the bits DUAL[4:0] in the ADCx_CCR register.

Four possible modes are implemented:

• Injected simultaneous mode
• Regular simultaneous mode
• Interleaved mode
• Alternate trigger mode

It is also possible to use these modes combined in the following ways:

• Injected simultaneous mode + Regular simultaneous mode
• Regular simultaneous mode + Alternate trigger mode
• Injected simultaneous mode + Interleaved mode

In dual ADC mode (when bits DUAL[4:0] in ADCx_CCR register are not equal to zero), the bits CONT, AUTDLY, DISCEN, DISCNUM[2:0], JDISCEN, JQM, JAUTO of the ADC_CFGR register are shared between the master and slave ADC: the bits in the slave ADC are always equal to the corresponding bits of the master ADC.

To start a conversion in dual mode, the user must program the bits EXTEN[1:0], EXTSEL, JEXTEN[1:0], JEXTSEL of the master ADC only, to configure a software or hardware trigger, and a regular or injected trigger. (the bits EXTEN[1:0] and JEXTEN[1:0] of the slave ADC are don't care).

In regular simultaneous or interleaved modes: once the user sets bit ADSTART or bit ADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically set. However, bit ADSTART or bit ADSTP of the slave ADC is not necessary cleared at the same time as the master ADC bit.

In injected simultaneous or alternate trigger modes: once the user sets bit JADSTART or bit JADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically set. However, bit JADSTART or bit JADSTP of the slave ADC is not necessary cleared at the same time as the master ADC bit.

In dual ADC mode, the converted data of the master and slave ADC can be read in parallel, by reading the ADC common data register (ADCx_CDR). The status bits can be also read in parallel by reading the dual-mode status register (ADCx_CSR).

Figure 138. Dual ADC block diagram ⁽¹⁾

The diagram illustrates the internal architecture of a Dual ADC system. On the left, there are two multiplexers for internal analog inputs. The top multiplexer takes inputs from ADCx_INN1, ADCx_INP1, ADCx_INN2, and ADCx_INP2. The bottom multiplexer takes inputs from ADCx_INN16 and ADCx_INP16. These multiplexers feed into the 'Slave ADC' and 'Master ADC' blocks. The 'Slave ADC' block contains 'Regular channels' and 'Injected channels' which output to a 'Regular data register (16-bits)' and 'Injected data registers (4 x16-bits)'. The 'Master ADC' block contains similar 'Regular channels' and 'Injected channels' which also output to their own 'Regular data register (16-bits)' and 'Injected data registers (4 x16-bits)'. Both ADC blocks receive 'Internal triggers' and are connected to a common 'Address/data bus' on the right. The 'Master ADC' also includes a 'Dual mode control' block and two 'Start trigger mux.' blocks (one for the regular group and one for the injected group). The diagram is labeled 'MSV36025V2' in the bottom right corner.

Dual ADC block diagram showing Master ADC and Slave ADC components, including input multiplexers, channel blocks, data registers, and a common address/data bus.

1. External triggers also exist on slave ADC but are not shown for the purposes of this diagram.
2. The ADC common data register (ADCx_CDR) contains both the master and slave ADC regular converted data.

Injected simultaneous mode

This mode is selected by programming bits DUAL[4:0]=00101

This mode converts an injected group of channels. The external trigger source comes from the injected group multiplexer of the master ADC (selected by the JEXTSEL bits in the ADC_JSQR register).

Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel).

In simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the longer of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions.

Regular conversions can be performed on one or all ADCs. In that case, they are independent of each other and are interrupted when an injected event occurs. They are resumed at the end of the injected conversion group.

• At the end of injected sequence of conversion event (JEOS) on the master ADC, the converted data is stored into the master ADC_JDRy registers and a JEOS interrupt is generated (if enabled)
• At the end of injected sequence of conversion event (JEOS) on the slave ADC, the converted data is stored into the slave ADC_JDRy registers and a JEOS interrupt is generated (if enabled)
• If the duration of the master injected sequence is equal to the duration of the slave injected one (like in Figure 139), it is possible for the software to enable only one of the two JEOS interrupt (ex: master JEOS) and read both converted data (from master ADC_JDRy and slave ADC_JDRy registers).

Figure 139. Injected simultaneous mode on 4 channels: dual ADC mode

The diagram illustrates the timing for injected simultaneous mode on 4 channels for dual ADC mode. It shows two horizontal timelines for the MASTER ADC and SLAVE ADC. The MASTER ADC timeline shows four channels: CH1, CH2, CH3, and CH4. The SLAVE ADC timeline shows four channels: CH15, CH14, CH13, and CH12. A 'Trigger' arrow points to the start of the sequences. Below the timelines, a legend indicates that grey boxes represent 'Sampling' and white boxes represent 'Conversion'. An arrow points to the end of the sequences with the text 'End of injected sequence on MASTER and SLAVE ADC'. The diagram is labeled MS31900V1 in the bottom right corner.

Timing diagram showing MASTER ADC and SLAVE ADC conversion sequences. MASTER ADC has channels CH1, CH2, CH3, CH4. SLAVE ADC has channels CH15, CH14, CH13, CH12. A trigger starts the sequence. Legend: Sampling (grey), Conversion (white). End of injected sequence on MASTER and SLAVE ADC is marked at the end of the sequence.

If JDISCEN=1, each simultaneous conversion of the injected sequence requires an injected trigger event to occur.

This mode can be combined with AUTDLY mode:

• Once a simultaneous injected sequence of conversions has ended, a new injected trigger event is accepted only if both JEOS bits of the master and the slave ADC have been cleared (delay phase). Any new injected trigger events occurring during the ongoing injected sequence and the associated delay phase are ignored.
• Once a regular sequence of conversions of the master ADC has ended, a new regular trigger event of the master ADC is accepted only if the master data register (ADC_DR) has been read. Any new regular trigger events occurring for the master ADC during the

ongoing regular sequence and the associated delay phases are ignored.
There is the same behavior for regular sequences occurring on the slave ADC.

Regular simultaneous mode with independent injected

This mode is selected by programming bits DUAL[4:0] = 00110.

This mode is performed on a regular group of channels. The external trigger source comes from the regular group multiplexer of the master ADC (selected by the EXTSEL bits in the ADC_CFGR register). A simultaneous trigger is provided to the slave ADC.

In this mode, independent injected conversions are supported. An injection request (either on master or on the slave) will abort the current simultaneous conversions, which are restarted once the injected conversion is completed.

Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel).

In regular simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the longer conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions.

Software is notified by interrupts when it can read the data:

• At the end of each conversion event (EOC) on the master ADC, a master EOC interrupt is generated (if EOCIE is enabled) and software can read the ADC_DR of the master ADC.
• At the end of each conversion event (EOC) on the slave ADC, a slave EOC interrupt is generated (if EOCIE is enabled) and software can read the ADC_DR of the slave ADC.
• If the duration of the master regular sequence is equal to the duration of the slave one (like in Figure 140 ), it is possible for the software to enable only one of the two EOC interrupt (ex: master EOC) and read both converted data from the Common Data register (ADCx_CDR).

It is also possible to read the regular data using the DMA. Two methods are possible:

• Using two DMA channels (one for the master and one for the slave). In this case bits MDMA[1:0] must be kept cleared.
- – Configure the DMA master ADC channel to read ADC_DR from the master. DMA requests are generated at each EOC event of the master ADC.
- – Configure the DMA slave ADC channel to read ADC_DR from the slave. DMA requests are generated at each EOC event of the slave ADC.
• Using MDMA mode, which leaves one DMA channel free for other uses:
- – Configure MDMA[1:0]=0b10 or 0b11 (depending on resolution).
- – A single DMA channel is used (the one of the master). Configure the DMA master ADC channel to read the common ADC register (ADCx_CDR)
- – A single DMA request is generated each time both master and slave EOC events have occurred. At that time, the slave ADC converted data is available in the upper half-word of the ADCx_CDR 32-bit register and the master ADC converted data is available in the lower half-word of ADCx_CDR register.
- – Both EOC flags are cleared when the DMA reads the ADCx_CDR register.

Note: In MDMA mode (MDMA[1:0]=0b10 or 0b11), the user must program the same number of conversions in the master's sequence as in the slave's sequence. Otherwise, the remaining conversions will not generate a DMA request.

Figure 140. Regular simultaneous mode on 16 channels: dual ADC mode

Diagram illustrating regular simultaneous mode on 16 channels for dual ADC mode. It shows two parallel sequences of 16 channels (CH1 to CH16) for Master ADC and Slave ADC. The Master ADC sequence starts with CH1, CH2, CH3, CH4, ..., CH16. The Slave ADC sequence starts with CH16, CH14, CH13, CH12, ..., CH1. A 'Trigger' arrow points to the start of the Master ADC sequence. A legend indicates that a small square represents 'Sampling' and a larger rectangle represents 'Conversion'. An arrow points to the end of the sequence with the text 'End of regular sequence on MASTER and SLAVE ADC'. The diagram is labeled 'ai16054b' in the bottom right corner.

If DISCEN=1 then each “n” simultaneous conversions of the regular sequence require a regular trigger event to occur (“n” is defined by DISCNUM).

This mode can be combined with AUTDLY mode:

• Once a simultaneous conversion of the sequence has ended, the next conversion in the sequence is started only if the common data register, ADCx_CDR (or the regular data register of the master ADC) has been read (delay phase).
• Once a simultaneous regular sequence of conversions has ended, a new regular trigger event is accepted only if the common data register (ADCx_CDR) has been read (delay phase). Any new regular trigger events occurring during the ongoing regular sequence and the associated delay phases are ignored.

It is possible to use the DMA to handle data in regular simultaneous mode combined with AUTDLY mode, assuming that multi-DMA mode is used: bits MDMA must be set to 0b10 or 0b11.

When regular simultaneous mode is combined with AUTDLY mode, it is mandatory for the user to ensure that:

• The number of conversions in the master’s sequence is equal to the number of conversions in the slave’s.
• For each simultaneous conversions of the sequence, the length of the conversion of the slave ADC is inferior to the length of the conversion of the master ADC. Note that the length of the sequence depends on the number of channels to convert and the sampling time and the resolution of each channels.

Note: This combination of regular simultaneous mode and AUTDLY mode is restricted to the use case when only regular channels are programmed: it is forbidden to program injected channels in this combined mode.

Interleaved mode with independent injected

This mode is selected by programming bits DUAL[4:0] = 00111.

This mode can be started only on a regular group (usually one channel). The external trigger source comes from the regular channel multiplexer of the master ADC.

After an external trigger occurs:

• The master ADC starts immediately.
• The slave ADC starts after a delay of several-ADC clock cycles after the sampling phase of the master ADC has complete.

The minimum delay which separates two conversions in interleaved mode is configured in the DELAY bits in the ADCx_CCR register. This delay starts counting one half cycle after the end of the sampling phase of the master conversion. This way, an ADC cannot start a

conversion if the complementary ADC is still sampling its input (only one ADC can sample the input signal at a given time).

• The minimum possible DELAY is 1 to ensure that there is at least one cycle time between the opening of the analog switch of the master ADC sampling phase and the closing of the analog switch of the slave ADC sampling phase.
• The maximum DELAY is equal to the number of cycles corresponding to the selected resolution. However the user must properly calculate this delay to ensure that an ADC does not start a conversion while the other ADC is still sampling its input.

If the CONT bit is set on both master and slave ADCs, the selected regular channels of both ADCs are continuously converted.

The software is notified by interrupts when it can read the data at the end of each conversion event (EOC) on the slave ADC. A slave and master EOC interrupts are generated (if EOCIE is enabled) and the software can read the ADC_DR of the slave/master ADC.

Note: It is possible to enable only the EOC interrupt of the slave and read the common data register (ADCx_CDR). But in this case, the user must ensure that the duration of the conversions are compatible to ensure that inside the sequence, a master conversion is always followed by a slave conversion before a new master conversion restarts. It is recommended to use the MDMA mode.

It is also possible to have the regular data transferred by DMA. In this case, individual DMA requests on each ADC cannot be used and it is mandatory to use the MDMA mode, as following:

• Configure MDMA[1:0]=0b10 or 0b11 (depending on resolution).
• A single DMA channel is used (the one of the master). Configure the DMA master ADC channel to read the common ADC register (ADCx_CDR).
• A single DMA request is generated each time both master and slave EOC events have occurred. At that time, the slave ADC converted data is available in the upper half-word of the ADCx_CDR 32-bit register and the master ADC converted data is available in the lower half-word of ADCx_CDR register.
• Both EOC flags are cleared when the DMA reads the ADCx_CDR register.

Figure 141. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode

Timing diagram for dual ADC interleaved mode. The diagram shows the timing of sampling and conversion for a Master ADC and a Slave ADC. The Master ADC starts sampling at 0.5 ADCCLK cycles, followed by conversion. The Slave ADC is triggered and starts sampling at 0.5 ADCCLK cycles, followed by conversion. The diagram indicates that the Master ADC conversion is followed by the Slave ADC conversion, and the process repeats. The total duration for one full cycle (Master sampling + Master conversion + Slave sampling + Slave conversion) is 4 ADCCLK cycles. The diagram also shows the 'End of conversion on master and slave ADC'.

The diagram illustrates the timing for dual ADC interleaved mode. The Master ADC and Slave ADC both have a sampling phase (grey box) and a conversion phase (white box) for channel CH1. The Master ADC starts sampling at 0.5 ADCCLK cycles, followed by conversion. The Slave ADC is triggered and starts sampling at 0.5 ADCCLK cycles, followed by conversion. The diagram shows that the Master ADC conversion is followed by the Slave ADC conversion, and the process repeats. The total duration for one full cycle (Master sampling + Master conversion + Slave sampling + Slave conversion) is 4 ADCCLK cycles. The diagram also shows the 'End of conversion on master and slave ADC'.

Legend:

Sampling (grey box)
Conversion (white box)

Timing details:

0.5 ADCCLK cycle: Master ADC sampling phase.
0.5 ADCCLK cycle: Slave ADC sampling phase (triggered).
4 ADCCLK cycles: Total duration for one full cycle (Master sampling + Master conversion + Slave sampling + Slave conversion).
End of conversion on master and slave ADC: The point where both conversions are complete.

MSV31030V3

Timing diagram for dual ADC interleaved mode. The diagram shows the timing of sampling and conversion for a Master ADC and a Slave ADC. The Master ADC starts sampling at 0.5 ADCCLK cycles, followed by conversion. The Slave ADC is triggered and starts sampling at 0.5 ADCCLK cycles, followed by conversion. The diagram indicates that the Master ADC conversion is followed by the Slave ADC conversion, and the process repeats. The total duration for one full cycle (Master sampling + Master conversion + Slave sampling + Slave conversion) is 4 ADCCLK cycles. The diagram also shows the 'End of conversion on master and slave ADC'.

Figure 142. Interleaved mode on 1 channel in single conversion mode: dual ADC mode

Timing diagram for Figure 142 showing interleaved mode on 1 channel in single conversion mode. It illustrates the Master ADC and Slave ADC conversion sequences. The Slave ADC is triggered, and then the Master ADC starts. The diagram shows two conversion cycles. Each cycle consists of a sampling phase (grey) and a conversion phase (white) for CH1. The Master ADC's conversion starts 0.5 ADCCLK cycles after the Slave ADC's conversion starts. Both conversions end after 4 ADCCLK cycles. A legend indicates that grey boxes represent Sampling and white boxes represent Conversion. The diagram is labeled MSV31031V3.

If DISCEN=1, each “n” simultaneous conversions (“n” is defined by DISCNUM) of the regular sequence require a regular trigger event to occur.

In this mode, injected conversions are supported. When injection is done (either on master or on slave), both the master and the slave regular conversions are aborted and the sequence is restarted from the master (see Figure 143 below).

Figure 143. Interleaved conversion with injection

Timing diagram for Figure 143 showing interleaved conversion with injection. It illustrates the Master ADC (ADC1) and Slave ADC (ADC2) conversion sequences. The Master ADC is converting CH1, CH1, CH1. The Slave ADC is converting CH2, CH2, CH2. An injected trigger occurs, causing the Master ADC to convert CH11. The Slave ADC's conversion is aborted. After the injection, the Master ADC resumes with CH1, CH1, CH1. The Slave ADC resumes with CH2, CH2, CH0. A legend indicates that grey boxes represent Sampling and white boxes represent Conversion. The diagram is labeled MS34460V1.

Alternate trigger mode

This mode is selected by programming bits DUAL[4:0] = 01001.

This mode can be started only on an injected group. The source of external trigger comes from the injected group multiplexer of the master ADC.

This mode is only possible when selecting hardware triggers: JEXTEN[1:0] must not be 00.

Injected discontinuous mode disabled (JDISCEN=0 for both ADC)

1. When the 1st trigger occurs, all injected master ADC channels in the group are converted.
2. When the 2nd trigger occurs, all injected slave ADC channels in the group are converted.
3. And so on.

A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in the group have been converted.

A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the group have been converted.

JEOC interrupts, if enabled, can also be generated after each injected conversion.

If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts by converting the injected channels of the master ADC in the group.

Figure 144. Alternate trigger: injected group of each ADC

Timing diagram showing the sequence of events for Master and Slave ADCs under alternate trigger mode. The diagram illustrates four trigger events and the resulting conversion sequences and interrupt signals (JEOC, JEOS) for both Master and Slave ADCs. A legend indicates that grey boxes represent sampling and white boxes represent conversion.

The diagram illustrates the timing of injected group conversions for a Master ADC and a Slave ADC under alternate trigger mode. The sequence of events is as follows:

1st trigger: Initiates conversion of injected channels on the Master ADC. JEOC on master ADC is generated after the first conversion, and JEOC, JEOS on master ADC are generated after the last conversion.
2nd trigger: Initiates conversion of injected channels on the Slave ADC. JEOC on slave ADC is generated after the first conversion, and JEOC, JEOS on slave ADC are generated after the last conversion.
3rd trigger: Initiates conversion of injected channels on the Master ADC again. JEOC on master ADC is generated after the first conversion, and JEOC, JEOS on master ADC are generated after the last conversion.
4th trigger: Initiates conversion of injected channels on the Slave ADC again. JEOC on slave ADC is generated after the first conversion, and JEOC, JEOS on slave ADC are generated after the last conversion.

Legend:

Grey box: Sampling
White box: Conversion

ai16059-m

Timing diagram showing the sequence of events for Master and Slave ADCs under alternate trigger mode. The diagram illustrates four trigger events and the resulting conversion sequences and interrupt signals (JEOC, JEOS) for both Master and Slave ADCs. A legend indicates that grey boxes represent sampling and white boxes represent conversion.

Note: Regular conversions can be enabled on one or all ADCs. In this case the regular conversions are independent of each other. A regular conversion is interrupted when the ADC has to perform an injected conversion. It is resumed when the injected conversion is finished.

The time interval between 2 trigger events must be greater than or equal to 1 ADC clock period. The minimum time interval between 2 trigger events that start conversions on the same ADC is the same as in the single ADC mode.

Injected discontinuous mode enabled (JDISCEN=1 for both ADC)

If the injected discontinuous mode is enabled for both master and slave ADCs:

• When the 1st trigger occurs, the first injected channel of the master ADC is converted.
• When the 2nd trigger occurs, the first injected channel of the slave ADC is converted.
• And so on.

A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in the group have been converted.

A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the group have been converted.

JEOC interrupts, if enabled, can also be generated after each injected conversions.

If another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts.

Figure 145. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode

Timing diagram showing the sequence of triggers and conversions for Master and Slave ADCs in discontinuous mode. The diagram illustrates the flow between sampling and conversion phases for 4 injected channels. Triggers 1, 3, 5, and 7 start the Master ADC sequence, while triggers 2, 4, 6, and 8 start the Slave ADC sequence. JEOC and JEOS interrupts are shown occurring at the end of each sequence.

The diagram illustrates the timing of two ADCs, MASTER ADC and SLAVE ADC, in discontinuous mode with 4 injected channels each. The sequence of events is as follows:

1st trigger: MASTER ADC starts sampling and conversion of its first injected channel.
2nd trigger: SLAVE ADC starts sampling and conversion of its first injected channel. Simultaneously, the MASTER ADC completes its conversion (JEOC on master ADC).
3rd trigger: MASTER ADC starts sampling and conversion of its second injected channel. Simultaneously, the SLAVE ADC completes its conversion (JEOC on master ADC).
4th trigger: SLAVE ADC starts sampling and conversion of its second injected channel. Simultaneously, the MASTER ADC completes its conversion (JEOC on master ADC).
5th trigger: MASTER ADC starts sampling and conversion of its third injected channel. Simultaneously, the SLAVE ADC completes its conversion (JEOC on master ADC).
6th trigger: SLAVE ADC starts sampling and conversion of its third injected channel. Simultaneously, the MASTER ADC completes its conversion (JEOC on master ADC).
7th trigger: MASTER ADC starts sampling and conversion of its fourth injected channel. Simultaneously, the SLAVE ADC completes its conversion (JEOC on master ADC).
8th trigger: SLAVE ADC starts sampling and conversion of its fourth injected channel. Simultaneously, the MASTER ADC completes its conversion (JEOC, JEOS on master ADC).

The diagram uses a legend where a shaded rectangle represents 'Sampling' and a white rectangle represents 'Conversion'. The identifier 'ai16060V2-m' is present in the bottom right corner.

Timing diagram showing the sequence of triggers and conversions for Master and Slave ADCs in discontinuous mode. The diagram illustrates the flow between sampling and conversion phases for 4 injected channels. Triggers 1, 3, 5, and 7 start the Master ADC sequence, while triggers 2, 4, 6, and 8 start the Slave ADC sequence. JEOC and JEOS interrupts are shown occurring at the end of each sequence.

Combined regular/injected simultaneous mode

This mode is selected by programming bits DUAL[4:0] = 00001.

It is possible to interrupt the simultaneous conversion of a regular group to start the simultaneous conversion of an injected group.

Note: In combined regular/injected simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the long conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions.

Combined regular simultaneous + alternate trigger mode

This mode is selected by programming bits DUAL[4:0]=00010.

It is possible to interrupt the simultaneous conversion of a regular group to start the alternate trigger conversion of an injected group. Figure 146 shows the behavior of an alternate trigger interrupting a simultaneous regular conversion.

The injected alternate conversion is immediately started after the injected event. If a regular conversion is already running, in order to ensure synchronization after the injected conversion, the regular conversion of all (master/slave) ADCs is stopped and resumed synchronously at the end of the injected conversion.

Note: In combined regular simultaneous + alternate trigger mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the long conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions.

Figure 146. Alternate + regular simultaneous

The diagram shows four horizontal timelines for ADC MASTER reg, ADC MASTER inj, ADC SLAVE reg, and ADC SLAVE inj. - ADC MASTER reg: CH1, CH2, CH3 | CH3, CH4 | CH4, CH5 - ADC MASTER inj: CH1 (starts during CH3 of master reg) - ADC SLAVE reg: CH4, CH6, CH7 | CH7, CH8 | CH8, CH9 - ADC SLAVE inj: CH1 (starts during CH8 of slave reg) - 1st trigger: points to the start of CH3 in master reg. - 2nd trigger: points to the start of CH1 in slave inj. - A label 'synchronization not lost' is present near the 2nd trigger.

Timing diagram for Figure 146 showing ADC MASTER and ADC SLAVE regular and injected conversion sequences. The diagram illustrates that synchronization is not lost when a trigger occurs during an injected conversion.

If a trigger occurs during an injected conversion that has interrupted a regular conversion, the alternate trigger is served. Figure 147 shows the behavior in this case (note that the 6th trigger is ignored because the associated alternate conversion is not complete).

Figure 147. Case of trigger occurring during injected conversion

The diagram shows four horizontal timelines for ADC MASTER reg, ADC MASTER inj, ADC SLAVE reg, and ADC SLAVE inj. - ADC MASTER reg: CH1, CH2, CH3 | CH3, CH4 | CH4, CH5 | CH5, CH6 - ADC MASTER inj: CH14 (starts during CH3, CH4, and CH5 of master reg) - ADC SLAVE reg: CH7, CH8, CH9 | CH9, CH10 | CH10, CH11 | CH11, CH12 - ADC SLAVE inj: CH15 (starts during CH9, CH10, and CH11 of slave reg) - 1st trigger: points to the start of CH3 in master reg. - 2nd trigger: points to the start of CH15 in slave inj. - 3rd trigger: points to the start of CH4 in master reg. - 4th trigger: points to the start of CH15 in slave inj. - 5th trigger: points to the start of CH5 in master reg. - 6th trigger (ignored): points to the start of CH12 in slave reg, but is ignored because CH15 is still active.

Timing diagram for Figure 147 showing multiple triggers occurring during injected conversions. The 6th trigger is ignored because the associated alternate conversion is not complete.

Combined injected simultaneous plus interleaved

This mode is selected by programming bits DUAL[4:0]=00011

It is possible to interrupt an interleaved conversion with a simultaneous injected event.

In this case the interleaved conversion is interrupted immediately and the simultaneous injected conversion starts. At the end of the injected sequence the interleaved conversion is resumed. When the interleaved regular conversion resumes, the first regular conversion which is performed is always the master's one. Figure 148, Figure 149 and Figure 150 show the behavior using an example.

Caution: In this mode, it is mandatory to use the Common Data Register to read the regular data with a single read access. On the contrary, master-slave data coherency is not guaranteed.

Figure 148. Interleaved single channel CH0 with injected sequence CH11, CH12

Timing diagram for Figure 148 showing interleaved single channel CH0 with injected sequence CH11, CH12. It illustrates ADC1 (master) and ADC2 (slave) conversion sequences, sampling, and conversion phases. An injected trigger interrupts the master sequence, causing conversions to be aborted. The slave sequence resumes after the injected sequence. A legend indicates Sampling (light gray) and Conversion (dark gray) phases.

ADC1 (master): CH0 | CH0 | CH0 | ...

ADC2 (slave): CH0 | CH0 | CH0 | ...

read CDR (after first CH0 conversion)

read CDR (after second CH0 conversion)

Conversions aborted (due to injected trigger)

Injected trigger

CH11 | CH11

CH12 | CH12

Resume (always restart with the master)

Legend:
Sampling (light gray)
Conversion (dark gray)

MS34461V1

Timing diagram for Figure 148 showing interleaved single channel CH0 with injected sequence CH11, CH12. It illustrates ADC1 (master) and ADC2 (slave) conversion sequences, sampling, and conversion phases. An injected trigger interrupts the master sequence, causing conversions to be aborted. The slave sequence resumes after the injected sequence. A legend indicates Sampling (light gray) and Conversion (dark gray) phases.

Figure 149. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 1: Master interrupted first

Timing diagram for Figure 149 (case 1) showing two interleaved channels (CH1, CH2) with an injected sequence (CH11, CH12) where the master is interrupted first. It shows ADC1 (master) and ADC2 (slave) sequences. The master's conversion of CH1 is interrupted by the injected sequence. The slave's conversion of CH2 completes. After the injected sequence, the master resumes its conversion. A legend indicates Sampling and Conversion phases.

ADC1 (master): CH1 | CH1 | CH1 | ...

ADC2 (slave): CH2 | CH2 | CH2 | ...

read CDR (after first CH2 conversion)

read CDR (after second CH2 conversion)

Conversions aborted (due to injected trigger)

Injected trigger

CH11 | CH11

CH12 | CH12

Resume (always restart with the master)

Legend:
Sampling (light gray)
Conversion (dark gray)

MS34462V1

Timing diagram for Figure 149 (case 1) showing two interleaved channels (CH1, CH2) with an injected sequence (CH11, CH12) where the master is interrupted first. It shows ADC1 (master) and ADC2 (slave) sequences. The master's conversion of CH1 is interrupted by the injected sequence. The slave's conversion of CH2 completes. After the injected sequence, the master resumes its conversion. A legend indicates Sampling and Conversion phases.

Figure 150. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 2: Slave interrupted first

Timing diagram for Figure 150 (case 2) showing two interleaved channels (CH1, CH2) with an injected sequence (CH11, CH12) where the slave is interrupted first. It shows ADC1 (master) and ADC2 (slave) sequences. The slave's conversion of CH2 is interrupted by the injected sequence. The master's conversion of CH1 completes. After the injected sequence, the slave resumes its conversion. A legend indicates Sampling and Conversion phases.

ADC1 (master): CH1 | CH1 | CH1 | ...

ADC2 (slave): CH2 | CH2 | CH2 | ...

read CDR (after first CH1 conversion)

read CDR (after second CH1 conversion)

Conversions aborted (due to injected trigger)

Injected trigger

CH11 | CH11

CH12 | CH12

Resume (always restart with the master)

Legend:
Sampling (light gray)
Conversion (dark gray)

MS34463V2

Timing diagram for Figure 150 (case 2) showing two interleaved channels (CH1, CH2) with an injected sequence (CH11, CH12) where the slave is interrupted first. It shows ADC1 (master) and ADC2 (slave) sequences. The slave's conversion of CH2 is interrupted by the injected sequence. The master's conversion of CH1 completes. After the injected sequence, the slave resumes its conversion. A legend indicates Sampling and Conversion phases.

DMA requests in dual ADC mode

In all dual ADC modes, it is possible to use two DMA channels (one for the master, one for the slave) to transfer the data, like in single mode (refer to Figure 151: DMA Requests in regular simultaneous mode when MDMA=0b00 ).

Figure 151. DMA Requests in regular simultaneous mode when MDMA=0b00

Timing diagram showing DMA requests in regular simultaneous mode when MDMA=0b00. The diagram illustrates the sequence of events for two ADCs (Master and Slave) triggered by external signals. The Master ADC (CH1) and Slave ADC (CH2) are triggered simultaneously. The Master ADC generates an EOC (End of Conversion) signal, which triggers a DMA request. The Slave ADC generates an EOC signal, which triggers a DMA request. The DMA controller reads the Master ADC data (ADC_DR) and the Slave ADC data (ADC_DR). The diagram shows two conversion cycles. The first cycle shows the Master ADC (CH1) being triggered, generating an EOC signal, and a DMA request being generated. The DMA controller reads the Master ADC data (ADC_DR). The Slave ADC (CH2) is also triggered, generating an EOC signal, and a DMA request being generated. The DMA controller reads the Slave ADC data (ADC_DR). The second cycle shows the same sequence of events. The diagram is labeled 'Configuration where each sequence contains only one conversion' and 'MSV31032V2'.

Configuration where each sequence contains only one conversion

MSV31032V2

Timing diagram showing DMA requests in regular simultaneous mode when MDMA=0b00. The diagram illustrates the sequence of events for two ADCs (Master and Slave) triggered by external signals. The Master ADC (CH1) and Slave ADC (CH2) are triggered simultaneously. The Master ADC generates an EOC (End of Conversion) signal, which triggers a DMA request. The Slave ADC generates an EOC signal, which triggers a DMA request. The DMA controller reads the Master ADC data (ADC_DR) and the Slave ADC data (ADC_DR). The diagram shows two conversion cycles. The first cycle shows the Master ADC (CH1) being triggered, generating an EOC signal, and a DMA request being generated. The DMA controller reads the Master ADC data (ADC_DR). The Slave ADC (CH2) is also triggered, generating an EOC signal, and a DMA request being generated. The DMA controller reads the Slave ADC data (ADC_DR). The second cycle shows the same sequence of events. The diagram is labeled 'Configuration where each sequence contains only one conversion' and 'MSV31032V2'.

In simultaneous regular and interleaved modes, it is also possible to save one DMA channel and transfer both data using a single DMA channel. For this MDMA bits must be configured in the ADCx_CCR register:

MDMA=0b10: A single DMA request is generated each time both master and slave EOC events have occurred. At that time, two data items are available and the 32-bit register ADCx_CDR contains the two half-words representing two ADC-converted data items. The slave ADC data take the upper half-word and the master ADC data take the lower half-word. This mode is used in interleaved mode and in regular simultaneous mode when resolution is 10-bit or 12-bit.

Example:

Interleaved dual mode: a DMA request is generated each time 2 data items are available:

1st DMA request: ADCx_CDR[31:0] = SLV_ADC_DR[15:0] | MST_ADC_DR[15:0]

2nd DMA request: ADCx_CDR[31:0] = SLV_ADC_DR[15:0] | MST_ADC_DR[15:0]

Figure 152. DMA requests in regular simultaneous mode when MDMA=0b10

Timing diagram for Figure 152 showing regular simultaneous mode. It displays two sequences of conversions. In each sequence, a 'Trigger' signal initiates a conversion on 'ADC Master regular' (CH1) and 'ADC Slave regular' (CH2) simultaneously. The 'ADC Slave EOC' (End of Conversion) signal for CH2 goes high when the conversion is complete. The 'DMA request from ADC Master' signal goes high at the EOC of CH2. The 'DMA request from ADC Slave' signal remains low throughout. A vertical line separates the two sequences. Below the diagram, text indicates 'Configuration where each sequence contains only one conversion'. The code MSv31033V2 is in the bottom right corner.

Configuration where each sequence contains only one conversion

MSv31033V2

Timing diagram for Figure 152 showing regular simultaneous mode. It displays two sequences of conversions. In each sequence, a 'Trigger' signal initiates a conversion on 'ADC Master regular' (CH1) and 'ADC Slave regular' (CH2) simultaneously. The 'ADC Slave EOC' (End of Conversion) signal for CH2 goes high when the conversion is complete. The 'DMA request from ADC Master' signal goes high at the EOC of CH2. The 'DMA request from ADC Slave' signal remains low throughout. A vertical line separates the two sequences. Below the diagram, text indicates 'Configuration where each sequence contains only one conversion'. The code MSv31033V2 is in the bottom right corner.

Figure 153. DMA requests in interleaved mode when MDMA=0b10

Timing diagram for Figure 153 showing interleaved mode. It displays two sequences of conversions. In each sequence, a 'Trigger' signal initiates a conversion on 'ADC Master regular' (CH1). After a 'Delay', the 'ADC Slave regular' (CH2) conversion begins. The 'ADC Master EOC' signal goes high when the CH1 conversion is complete. The 'DMA request from ADC Master' signal goes high at the EOC of CH1. The 'DMA request from ADC Slave' signal remains low throughout. A vertical line separates the two sequences. Below the diagram, text indicates 'Configuration where each sequence contains only one conversion'. The code MSv31034V2 is in the bottom right corner.

Configuration where each sequence contains only one conversion

MSv31034V2

Timing diagram for Figure 153 showing interleaved mode. It displays two sequences of conversions. In each sequence, a 'Trigger' signal initiates a conversion on 'ADC Master regular' (CH1). After a 'Delay', the 'ADC Slave regular' (CH2) conversion begins. The 'ADC Master EOC' signal goes high when the CH1 conversion is complete. The 'DMA request from ADC Master' signal goes high at the EOC of CH1. The 'DMA request from ADC Slave' signal remains low throughout. A vertical line separates the two sequences. Below the diagram, text indicates 'Configuration where each sequence contains only one conversion'. The code MSv31034V2 is in the bottom right corner.

Note: When using MDMA mode, the user must take care to configure properly the duration of the master and slave conversions so that a DMA request is generated and served for reading both data (master + slave) before a new conversion is available.

• MDMA=0b11: This mode is similar to the MDMA=0b10. The only differences are that on each DMA request (two data items are available), two bytes representing two ADC converted data items are transferred as a half-word.

This mode is used in interleaved and regular simultaneous mode when resolution is 6-bit or when resolution is 8-bit and data is not signed (offsets must be disabled for all the involved channels).

Example:

Interleaved dual mode: a DMA request is generated each time 2 data items are available:

1st DMA request: ADCx_CDR[15:0] = SLV_ADC_DR[7:0] | MST_ADC_DR[7:0]

2nd DMA request: ADCx_CDR[15:0] = SLV_ADC_DR[7:0] | MST_ADC_DR[7:0]

Overrun detection

In dual ADC mode (when DUAL[4:0] is not equal to b00000), if an overrun is detected on one of the ADCs, the DMA requests are no longer issued to ensure that all the data transferred to the RAM are valid (this behavior occurs whatever the MDMA configuration). It may happen that the EOC bit corresponding to one ADC remains set because the data register of this ADC contains valid data.

DMA one shot mode/ DMA circular mode when MDMA mode is selected

When MDMA mode is selected (0b10 or 0b11), bit DMACFG of the ADCx_CCR register must also be configured to select between DMA one shot mode and circular mode, as explained in section Section : Managing conversions using the DMA (bits DMACFG of master and slave ADC_CFGR are not relevant).

Stopping the conversions in dual ADC modes

The user must set the control bits ADSTP/JADSTP of the master ADC to stop the conversions of both ADC in dual ADC mode. The other ADSTP control bit of the slave ADC has no effect in dual ADC mode.

Once both ADC are effectively stopped, the bits ADSTART/JADSTART of the master and slave ADCs are both cleared by hardware.

21.4.32 Temperature sensor

The temperature sensor can be used to measure the junction temperature (T _j) of the device. The temperature sensor is internally connected to the ADC input channels which are used to convert the sensor output voltage to a digital value. When not in use, the sensor can be put in power down mode. It support the temperature range –40 to 125 °C.

Figure 154 shows the block diagram of connections between the temperature sensor and the ADC.

The temperature sensor output voltage changes linearly with temperature. The offset of this line varies from chip to chip due to process variation (up to 45 °C from one chip to another).

The uncalibrated internal temperature sensor is more suited for applications that detect temperature variations instead of absolute temperatures. To improve the accuracy of the temperature sensor measurement, calibration values are stored in system memory for each device by ST during production.

During the manufacturing process, the calibration data of the temperature sensor and the internal voltage reference are stored in the system memory area. The user application can then read them and use them to improve the accuracy of the temperature sensor or the internal reference (refer to the datasheet for additional information).

The temperature sensor is internally connected to the ADC input channel which is used to convert the sensor's output voltage to a digital value. Refer to the electrical characteristics section of the device datasheet for the sampling time value to be applied when converting the internal temperature sensor.

When not in use, the sensor can be put in power-down mode.

Figure 154 shows the block diagram of the temperature sensor.

Figure 154. Temperature sensor channel block diagram

Figure 154. Temperature sensor channel block diagram. The diagram shows a 'Temperature sensor' block connected to a multiplexer. The multiplexer is controlled by a 'CH17SEL control bit' and its output is labeled 'VTS'. This output is connected to the 'ADC input' of an 'ADCx' block. The 'ADCx' block outputs 'Converted data' to an 'Address/data bus' block. A small label 'MSV37243V3' is in the bottom right corner of the diagram area.

Reading the temperature

To use the sensor:

1. Select the ADC input channels that is connected to $V_{TS}$ .
2. Program with the appropriate sampling time (refer to electrical characteristics section of the device datasheet).
3. Set the CH17SEL bit in the ADCx_CCR register to wake up the temperature sensor from power-down mode.
4. Start the ADC conversion.
5. Read the resulting $V_{TS}$ data in the ADC data register.
6. Calculate the actual temperature using the following formula:

\text{Temperature (in } ^\circ\text{C)} = \frac{\text{TS\_CAL2\_TEMP} - \text{TS\_CAL1\_TEMP}}{\text{TS\_CAL2} - \text{TS\_CAL1}} \times (\text{TS\_DATA} - \text{TS\_CAL1}) + 30 \ ^\circ\text{C}

Where:

• TS_CAL2 is the temperature sensor calibration value acquired at TS_CAL2_TEMP.
• TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP.
• TS_DATA is the actual temperature sensor output value converted by ADC.

Refer to the device datasheet for more information about TS_CAL1 and TS_CAL2 calibration points.

Note: The sensor has a startup time after waking from power-down mode before it can output $V_{TS}$ at the correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADEN and CH17SEL bits should be set at the same time.

The above formula is given for TS_DATA measurement done with the same $V_{REF+}$ voltage as TS_CAL1/TS_CAL2 values. If $V_{REF+}$ is different, the formula must be adapted. For example if $V_{REF+} = 3.3\text{ V}$ and TS_CAL data are acquired at $V_{REF+} = 3.0\text{ V}$ , TS_DATA must be replaced by $TS\_DATA \times (3.3/3.0)$ .

21.4.33 $V_{BAT}$ supply monitoring

The CH18SEL bit in the ADCx_CCR register is used to switch to the battery voltage. As the $V_{BAT}$ voltage could be higher than $V_{DDA}$ , to ensure the correct operation of the ADC, the $V_{BAT}$ pin is internally connected to a bridge divider by 3. This bridge is automatically enabled when CH18SEL is set, to connect $V_{BAT}/3$ to the ADC input channels. As a consequence, the converted digital value is one third of the $V_{BAT}$ voltage. To prevent any unwanted consumption on the battery, it is recommended to enable the bridge divider only when needed, for ADC conversion.

Refer to the electrical characteristics of the device datasheet for the sampling time value to be applied when converting the $V_{BAT}/3$ voltage.

The figure below shows the block diagram of the $V_{BAT}$ sensing feature.

Figure 155. $V_{BAT}$ channel block diagram

Block diagram of the VBAT channel sensing feature. It shows a switch controlled by the CH18SEL bit connecting the VBAT pin to a voltage divider. The divider consists of two resistors in series, with the midpoint labeled VBAT/3. This midpoint is connected to a multiplexer, which is also controlled by the CH18SEL bit. The output of the multiplexer is connected to the ADC input of the ADCx block. The ADCx block is connected to an Address/data bus. The bottom of the voltage divider is connected to ground.

1. The CH18SEL bit must be set to enable the conversion of internal channel for $V_{BAT}/3$ .

21.4.34 Monitoring the internal voltage reference

It is possible to monitor the internal voltage reference ( $V_{REFINT}$ ) to have a reference point for evaluating the ADC $V_{REF+}$ voltage level.

The internal voltage reference is internally connected to the input channel 0 of the ADC1 (ADC1_INP0).

Refer to the electrical characteristics section of the product datasheet for the sampling time value to be applied when converting the internal voltage reference voltage.

Figure 156 shows the block diagram of the $V_{REFINT}$ sensing feature.

Figure 156. $V_{REFINT}$ channel block diagram

Block diagram showing the internal power block outputting V_REFINT into a multiplexer controlled by the VREFEN control bit, which then feeds into the ADC input of the ADCx block.

graph LR
    IPB[Internal power block] -- V_REFINT --> MUX{ }
    VREFEN[VREFEN control bit] --> MUX
    MUX --> ADC_IN[ADC input]
    subgraph ADCx
    ADC_IN
    end

MSV34467V5

Block diagram showing the internal power block outputting V_REFINT into a multiplexer controlled by the VREFEN control bit, which then feeds into the ADC input of the ADCx block.

1. The VREFEN bit into ADCx_CCR register must be set to enable the conversion of internal channels ( $V_{REFINT}$ ).

Calculating the actual $V_{REF+}$ voltage using the internal reference voltage

The power supply voltage applied to the device may be subject to variations or not precisely known. When $V_{DDA}$ is connected to $V_{REF+}$ , it is possible to compute the actual $V_{DDA}$ voltage using the embedded internal reference voltage ( $V_{REFINT}$ ). $V_{REFINT}$ and its calibration data, acquired by the ADC during the manufacturing process at $V_{DDA\_Charac}$ , can be used to evaluate the actual $V_{DDA}$ voltage level.

The following formula gives the actual $V_{REF+}$ voltage supplying the device:

V_{REF+} = V_{REF+\_Charac} \times VREFINT\_CAL / VREFINT\_DATA

Where:

• $V_{REF+\_Charac}$ is the value of $V_{REF+}$ voltage characterized at $V_{REFINT}$ during the manufacturing process. It is specified in the device datasheet.
• $VREFINT\_CAL$ is the $V_{REFINT}$ calibration value
• $VREFINT\_DATA$ is the actual $V_{REFINT}$ output value converted by ADC

Converting a supply-relative ADC measurement to an absolute voltage value

The ADC is designed to deliver a digital value corresponding to the ratio between $V_{REF+}$ and the voltage applied on the converted channel.

For most applications $V_{DDA}$ value is unknown and ADC converted values are right-aligned. In this case, it is necessary to convert this ratio into a voltage independent from $V_{DDA}$ :

V_{\text{CHANNELx}} = \frac{V_{\text{REF+}}}{\text{FULL\_SCALE}} \times \text{ADC\_DATA}

By replacing $V_{\text{REF+}}$ by the formula provided above, the absolute voltage value is given by the following formula

V_{\text{CHANNELx}} = \frac{V_{\text{REF+\_Charac}} \times \text{VREFINT\_CAL} \times \text{ADC\_DATA}}{\text{VREFINT\_DATA} \times \text{FULL\_SCALE}}

For applications where $V_{\text{REF+}}$ is known and ADC converted values are right-aligned, the absolute voltage value can be obtained by using the following formula:

V_{\text{CHANNELx}} = \frac{V_{\text{REF+}}}{\text{FULL\_SCALE}} \times \text{ADC\_DATA}

Where:

– $V_{\text{REF+\_Charac}}$ is the value of $V_{\text{REF+}}$ voltage characterized at $V_{\text{REFINT}}$ during the manufacturing process.
– $\text{VREFINT\_CAL}$ is the $V_{\text{REFINT}}$ calibration value
– $\text{ADC\_DATA}$ is the value measured by the ADC on channel x (right-aligned)
– $\text{VREFINT\_DATA}$ is the actual $V_{\text{REFINT}}$ output value converted by the ADC
– $\text{FULL\_SCALE}$ is the maximum digital value of the ADC output. For example with 12-bit resolution, it will be $2^{12} - 1 = 4095$ or with 8-bit resolution, $$ 2^8 - 1 = 255 $$ .

Note: If ADC measurements are done using an output format other than 16-bit right-aligned, all the parameters must first be converted to a compatible format before the calculation is done.

21.5 ADC interrupts

For each ADC, an interrupt can be generated:

• After ADC power-up, when the ADC is ready (flag ADRDY)
• On the end of any conversion for regular groups (flag EOC)
• On the end of a sequence of conversion for regular groups (flag EOS)
• On the end of any conversion for injected groups (flag JEOC)
• On the end of a sequence of conversion for injected groups (flag JEOS)
• When an analog watchdog detection occurs (flag AWD1, AWD2 and AWD3)
• When the end of sampling phase occurs (flag EOSMP)
• When the data overrun occurs (flag OVR)
• When the injected sequence context queue overflows (flag JQOVF)

Separate interrupt enable bits are available for flexibility.

Table 140. ADC interrupts per each ADC

Interrupt event	Event flag	Enable control bit
ADC ready	ADRDY	ADRDYIE
End of conversion of a regular group	EOC	EOCIE
End of sequence of conversions of a regular group	EOS	EOSIE
End of conversion of a injected group	JEOC	JEOCIE
End of sequence of conversions of an injected group	JEOS	JEOSIE
Analog watchdog 1 status bit is set	AWD1	AWD1IE
Analog watchdog 2 status bit is set	AWD2	AWD2IE
Analog watchdog 3 status bit is set	AWD3	AWD3IE
End of sampling phase	EOSMP	EOSMPIE
Overrun	OVR	OVRIE
Injected context queue overflows	JQOVF	JQOVFIE

21.6 ADC registers (for each ADC)

Refer to Section 1.2 on page 86 for a list of abbreviations used in register descriptions.

21.6.1 ADC interrupt and status register (ADC_ISR)

Address offset: 0x00

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	JQOVF	AWD3	AWD2	AWD1	JEOS	JEOC	OVR	EOS	EOC	EOSMP	ADRDY
					rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 JQOVF: Injected context queue overflow

This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to Section 21.4.21: Queue of context for injected conversions for more information.

0: No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software)

1: Injected context queue overflow has occurred

Bit 9 AWD3: Analog watchdog 3 flag

This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT3[7:0] and HT3[7:0] of ADC_TR3 register. It is cleared by software writing 1 to it.

0: No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software)

1: Analog watchdog 3 event occurred

Bit 8 AWD2: Analog watchdog 2 flag

This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT2[7:0] and HT2[7:0] of ADC_TR2 register. It is cleared by software writing 1 to it.

0: No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software)

1: Analog watchdog 2 event occurred

Bit 7 AWD1: Analog watchdog 1 flag

This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT1[11:0] and HT1[11:0] of ADC_TR1 register. It is cleared by software writing 1 to it.

0: No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software)

1: Analog watchdog 1 event occurred

Bit 6 JEOS: Injected channel end of sequence flag

This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it.

0: Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)

1: Injected conversions complete

Bit 5 JEOC: Injected channel end of conversion flag

This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register

0: Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)

1: Injected channel conversion complete

Bit 4 OVR: ADC overrun

This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it.

0: No overrun occurred (or the flag event was already acknowledged and cleared by software)

1: Overrun has occurred

Bit 3 EOS: End of regular sequence flag

This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it.

0: Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software)

1: Regular Conversions sequence complete

Bit 2 EOC: End of conversion flag

This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register

0: Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)

1: Regular channel conversion complete

Bit 1 EOSMP: End of sampling flag

This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase.

0: not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)

1: End of sampling phase reached

Bit 0 ADRDY: ADC ready

This bit is set by hardware after the ADC has been enabled (bit ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests.

It is cleared by software writing 1 to it.

0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)

1: ADC is ready to start conversion

21.6.2 ADC interrupt enable register (ADC_IER)

Address offset: 0x04

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	JQOVF IE	AWD3IE	AWD2IE	AWD1IE	JEOSIE	JEOCIE	OVR IE	EOSIE	EOCIE	EOSMP IE	ADRDI IE
					rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 JQOVFIE: Injected context queue overflow interrupt enable

This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt.

0: Injected Context Queue Overflow interrupt disabled

1: Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit is set.

Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Bit 9 AWD3IE: Analog watchdog 3 interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.

0: Analog watchdog 3 interrupt disabled

1: Analog watchdog 3 interrupt enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bit 8 AWD2IE: Analog watchdog 2 interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.

0: Analog watchdog 2 interrupt disabled

1: Analog watchdog 2 interrupt enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bit 7 AWD1IE: Analog watchdog 1 interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt.

0: Analog watchdog 1 interrupt disabled

1: Analog watchdog 1 interrupt enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bit 6 JEOSIE: End of injected sequence of conversions interrupt enable

This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt.

0: JEOS interrupt disabled

1: JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.

Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Bit 5 JEOCIE: End of injected conversion interrupt enable

This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt.
0: JEOC interrupt disabled.

1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.

Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).

Bit 4 OVRRIE: Overrun interrupt enable

This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion.

0: Overrun interrupt disabled

1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 3 EOSIE: End of regular sequence of conversions interrupt enable

This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt.

0: EOS interrupt disabled

1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 2 EOCIE: End of regular conversion interrupt enable

This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt.

0: EOC interrupt disabled.

1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 1 EOSMPIE: End of sampling flag interrupt enable for regular conversions

This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions.

0: EOSMP interrupt disabled.

1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 0 ADRDYIE: ADC ready interrupt enable

This bit is set and cleared by software to enable/disable the ADC Ready interrupt.

0: ADRDY interrupt disabled

1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

21.6.3 ADC control register (ADC_CR)

Address offset: 0x08

Reset value: 0x2000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADCAL L	ADCAL LDIF	DEEP PWD	ADVREG EN	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
rs	rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	JADST P	ADSTP	JADST ART	ADSTA RT	ADDIS	ADEN
										rs	rs	rs	rs	rs	rs

Bit 31 ADCAL: ADC calibration

This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for single-ended or differential inputs mode.

It is cleared by hardware after calibration is complete.

0: Calibration complete

1: Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress.

Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN=0.

The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing)

Bit 30 ADCALDIF: Differential mode for calibration

This bit is set and cleared by software to configure the single-ended or differential inputs mode for the calibration.

0: Writing ADCAL will launch a calibration in single-ended inputs mode.

1: Writing ADCAL will launch a calibration in differential inputs mode.

Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

Bit 29 DEEPPWD: Deep-power-down enable

This bit is set and cleared by software to put the ADC in Deep-power-down mode.

0: ADC not in Deep-power down

1: ADC in Deep-power-down (default reset state)

Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

Bit 28 ADVREGEN: ADC voltage regulator enable

This bit is set by software to enable the ADC voltage regulator.

Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time.

0: ADC Voltage regulator disabled

1: ADC Voltage regulator enabled.

For more details about the ADC voltage regulator enable and disable sequences, refer to Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) .

The software can program this bit field only when the ADC is disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

Bits 27:6 Reserved, must be kept at reset value.

Bit 5 JADSTP: ADC stop of injected conversion command

This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command).

It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command).

0: No ADC stop injected conversion command ongoing

1: Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in progress.

Note: The software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC)

In Auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP)

Bit 4 ADSTP: ADC stop of regular conversion command

This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command).

It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command).

0: No ADC stop regular conversion command ongoing

1: Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in progress.

Note: The software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC).

In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP).

Bit 3 JADSTART: ADC start of injected conversion

This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN[1:0], a conversion will start immediately (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration).

It is cleared by hardware:

– in single conversion mode when software trigger is selected (JEXTSEL=0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag.
– in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware.

0: No ADC injected conversion is ongoing.

1: Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually converting an injected channel.

Note: The software is allowed to set JADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC).

In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)

Bit 2 ADSTART: ADC start of regular conversion

This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN[1:0], a conversion will start immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration).

It is cleared by hardware:

– in single conversion mode when software trigger is selected (EXTSEL=0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag.
– in all cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware.

0: No ADC regular conversion is ongoing.

1: Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually converting a regular channel.

Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC)

In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)

Bit 1 ADDIS: ADC disable command

This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state).

It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time).

0: no ADDIS command ongoing

1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.

Note: The software is allowed to set ADDIS only when ADEN=1 and both ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)

Bit 0 ADEN: ADC enable control

This bit is set by software to enable the ADC. The ADC will be effectively ready to operate once the flag ADRDY has been set.

It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.

0: ADC is disabled (OFF state)

1: Write 1 to enable the ADC.

Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator)

21.6.4 ADC configuration register (ADC_CFGR)

Address offset: 0x0C

Reset value: 0x8000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
JQDIS	AWD1CH[4:0]						JAUTO	JAWD1EN	AWD1EN	AWD1SGL	JQM	JDISCEN	DISCNUM[2:0]		DISCEN
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	AUT DLY	CONT	OVR MOD	EXTEN[1:0]		EXTSE L3	EXTSE L2	EXTSE L1	EXTSE L0	ALIGN	RES[1:0]		DFSD MCFG	DMA CFG	DMA EN
	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 JQDIS: Injected Queue disable

These bits are set and cleared by software to disable the Injected Queue mechanism :

0: Injected Queue enabled

1: Injected Queue disabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no regular nor injected conversion is ongoing).

A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared.

Bits 30:26 AWD1CH[4:0]: Analog watchdog 1 channel selection

These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog.

00000: ADC analog input channel 0 monitored by AWD1 (available on ADC1 only)

00001: ADC analog input channel 1 monitored by AWD1

.....

10010: ADC analog input channel 18 monitored by AWD1

others: reserved, must not be used

Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to the reset value.

The channel selected by AWD1CH must be also selected into the SQ Ri or JSQRi registers.

The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bit 25 JAUTO: Automatic injected group conversion

This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion.

0: Automatic injected group conversion disabled

1: Automatic injected group conversion enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no regular nor injected conversion is ongoing).

When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit JAUTO of the slave ADC is no more writable and its content is equal to the bit JAUTO of the master ADC.

Bit 24 JAWD1EN: Analog watchdog 1 enable on injected channels

This bit is set and cleared by software

0: Analog watchdog 1 disabled on injected channels

1: Analog watchdog 1 enabled on injected channels

Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Bit 23 AWD1EN: Analog watchdog 1 enable on regular channels

This bit is set and cleared by software

0: Analog watchdog 1 disabled on regular channels

1: Analog watchdog 1 enabled on regular channels

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 22 AWD1SGL: Enable the watchdog 1 on a single channel or on all channels

This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels

0: Analog watchdog 1 enabled on all channels

1: Analog watchdog 1 enabled on a single channel

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bit 21 JQM: JSQR queue mode

This bit is set and cleared by software.

It defines how an empty Queue is managed.

0: JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR.

1: JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence.

Refer to Section 21.4.21: Queue of context for injected conversions for more information.

Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing).

When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit JQM of the slave ADC is no more writable and its content is equal to the bit JQM of the master ADC.

Bit 20 JDISCEN: Discontinuous mode on injected channels

This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group.

0: Discontinuous mode on injected channels disabled

1: Discontinuous mode on injected channels enabled

Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing).

It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.

When dual mode is enabled (bits DUAL of ADCx_CCR register are not equal to zero), the bit JDISCEN of the slave ADC is no more writable and its content is equal to the bit JDISCEN of the master ADC.

Bits 19:17 DISCNUM[2:0]: Discontinuous mode channel count

These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger.

000: 1 channel

001: 2 channels

...

111: 8 channels

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bits DISCNUM[2:0] of the slave ADC are no more writable and their content is equal to the bits DISCNUM[2:0] of the master ADC.

Bit 16 DISCEN: Discontinuous mode for regular channels

This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels.

0: Discontinuous mode for regular channels disabled

1: Discontinuous mode for regular channels enabled

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1.

It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.

The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit DISCEN of the slave ADC is no more writable and its content is equal to the bit DISCEN of the master ADC.

Bit 15 Reserved, must be kept at reset value. Bit 14 AUTDLY: Delayed conversion mode

This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.

0: Auto-delayed conversion mode off

1: Auto-delayed conversion mode on

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the master ADC.

Bit 13 CONT: Single / continuous conversion mode for regular conversions

This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared.

0: Single conversion mode

1: Continuous conversion mode

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1.

The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit CONT of the slave ADC is no more writable and its content is equal to the bit CONT of the master ADC.

Bit 12 OVRMOD: Overrun mode

This bit is set and cleared by software and configure the way data overrun is managed.

0: ADC_DR register is preserved with the old data when an overrun is detected.

1: ADC_DR register is overwritten with the last conversion result when an overrun is detected.

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection for regular channels

These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group.

00: Hardware trigger detection disabled (conversions can be launched by software)

01: Hardware trigger detection on the rising edge

10: Hardware trigger detection on the falling edge

11: Hardware trigger detection on both the rising and falling edges

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bits 9:6 EXTSEL[3:0]: External trigger selection for regular group

These bits select the external event used to trigger the start of conversion of a regular group:

0000: Event 0

0001: Event 1

0010: Event 2

0011: Event 3

0100: Event 4

0101: Event 5

0110: Event 6

0111: Event 7

...

1111: Event 15

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 5 ALIGN: Data alignment

This bit is set and cleared by software to select right or left alignment. Refer to Section : Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN)

0: Right alignment

1: Left alignment

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bits 4:3 RES[1:0]: Data resolution

These bits are written by software to select the resolution of the conversion.

00: 12-bit

01: 10-bit

10: 8-bit

11: 6-bit

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bit 2 DFSDMCFG : DFSDM mode configuration

This bit is set and cleared by software to enable the DFSDM mode. It is effective only when DMAEN=0.

0: DFSDM mode disabled

1: DFSDM mode enabled

Note: To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART= 0 and JADSTART= 0.

Bit 1 DMACFG : Direct memory access configuration

This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN=1.

0: DMA One Shot mode selected

1: DMA Circular mode selected

For more details, refer to Section : Managing conversions using the DMA

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

In dual-ADC modes, this bit is not relevant and replaced by control bit DMACFG of the ADCx_CCR register.

Bit 0 DMAEN : Direct memory access enable

This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA to manage automatically the converted data. For more details, refer to Section : Managing conversions using the DMA .

0: DMA disabled

1: DMA enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

In dual-ADC modes, this bit is not relevant and replaced by control bits MDMA[1:0] of the ADCx_CCR register.

21.6.5 ADC configuration register 2 (ADC_CFGR2)

Address offset: 0x10

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	ROVSM	TROVS	OVSS[3:0]				OVSR[2:0]			JOVSE	ROVSE
					rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:17 Reserved, must be kept at reset value.

Bits 16:11 Reserved, must be kept at reset value.

Bit 10 ROVSM: Regular Oversampling mode

This bit is set and cleared by software to select the regular oversampling mode.

0: Continued mode: When injected conversions are triggered, the oversampling is temporarily stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)

1: Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).

Bit 9 TROVS: Triggered Regular Oversampling

This bit is set and cleared by software to enable triggered oversampling

0: All oversampled conversions for a channel are done consecutively following a trigger

1: Each oversampled conversion for a channel needs a new trigger

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).

Bits 8:5 OVSS[3:0]: Oversampling shift

This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result.

0000: No shift

0001: Shift 1-bit

0010: Shift 2-bits

0011: Shift 3-bits

0100: Shift 4-bits

0101: Shift 5-bits

0110: Shift 6-bits

0111: Shift 7-bits

1000: Shift 8-bits

Other codes reserved

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing).

Bits 4:2 OVSR[2:0] : Oversampling ratio

This bitfield is set and cleared by software to define the oversampling ratio.

000: 2x
001: 4x
010: 8x
011: 16x
100: 32x
101: 64x
110: 128x
111: 256x

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing).

Bit 1 JOVSE : Injected Oversampling Enable

This bit is set and cleared by software to enable injected oversampling.

0: Injected Oversampling disabled
1: Injected Oversampling enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)

Bit 0 ROVSE : Regular Oversampling Enable

This bit is set and cleared by software to enable regular oversampling.

0: Regular Oversampling disabled
1: Regular Oversampling enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)

21.6.6 ADC sample time register 1 (ADC_SMPR1)

Address offset: 0x14

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SMPPLUS	Res.	SMP9[2:0]			SMP8[2:0]			SMP7[2:0]			SMP6[2:0]			SMP5[2:1]
rw		rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMP5[0]	SMP4[2:0]			SMP3[2:0]			SMP2[2:0]			SMP1[2:0]			SMP0[2:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 SMPPLUS : Addition of one clock cycle to the sampling time.

1: 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers.

0: The sampling time remains set to 2.5 ADC clock cycles remains

To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART= 0 and JADSTART= 0.

Bit 30 Reserved, must be kept at reset value.

Bits 29:0 SMP[9:0][2:0] : Channel x sampling time selection

These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged.

000: 2.5 ADC clock cycles
001: 6.5 ADC clock cycles
010: 12.5 ADC clock cycles
011: 24.5 ADC clock cycles
100: 47.5 ADC clock cycles
101: 92.5 ADC clock cycles
110: 247.5 ADC clock cycles
111: 640.5 ADC clock cycles

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.

21.6.7 ADC sample time register 2 (ADC_SMPR2)

Address offset: 0x18

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	SMP18[2:0]			SMP17[2:0]			SMP16[2:0]			SMP15[2:1]
					rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMP15[0]	SMP14[2:0]			SMP13[2:0]			SMP12[2:0]			SMP11[2:0]			SMP10[2:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:0 SMP[18:10][2:0] : Channel x sampling time selection

These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged.

000: 2.5 ADC clock cycles
001: 6.5 ADC clock cycles
010: 12.5 ADC clock cycles
011: 24.5 ADC clock cycles
100: 47.5 ADC clock cycles
101: 92.5 ADC clock cycles
110: 247.5 ADC clock cycles
111: 640.5 ADC clock cycles

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.

21.6.8 ADC watchdog threshold register 1 (ADC_TR1)

Address offset: 0x20

Reset value: 0x0FFF 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	HT1[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	LT1[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT1[11:0] : Analog watchdog 1 higher threshold

These bits are written by software to define the higher threshold for the analog watchdog 1.

Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 LT1[11:0] : Analog watchdog 1 lower threshold

These bits are written by software to define the lower threshold for the analog watchdog 1.

Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

21.6.9 ADC watchdog threshold register 2 (ADC_TR2)

Address offset: 0x24

Reset value: 0x00FF 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	HT2[7:0]
								rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	LT2[7:0]
								rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 HT2[7:0] : Analog watchdog 2 higher threshold

These bits are written by software to define the higher threshold for the analog watchdog 2.

Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 LT2[7:0] : Analog watchdog 2 lower threshold

These bits are written by software to define the lower threshold for the analog watchdog 2.

Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

21.6.10 ADC watchdog threshold register 3 (ADC_TR3)

Address offset: 0x28

Reset value: 0x00FF 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	HT3[7:0]
								rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	LT3[7:0]
								rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 HT3[7:0] : Analog watchdog 3 higher threshold

These bits are written by software to define the higher threshold for the analog watchdog 3.

Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 LT3[7:0] : Analog watchdog 3 lower threshold

These bits are written by software to define the lower threshold for the analog watchdog 3.

This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data.

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

21.6.11 ADC regular sequence register 1 (ADC_SQR1)

Address offset: 0x30

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	SQ4[4:0]				Res.	SQ3[4:0]				Res.	SQ2[4]
			rw	rw	rw	rw	rw		rw	rw	rw	rw	rw		rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ2[3:0]				Res.	SQ1[4:0]				Res.	Res.	L[3:0]
rw	rw	rw	rw		rw	rw	rw	rw	rw			rw	rw	rw	rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ4[4:0] : 4th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 4th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 23 Reserved, must be kept at reset value.

Bits 22:18 SQ3[4:0] : 3rd conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 3rd in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 17 Reserved, must be kept at reset value.

Bits 16:12 SQ2[4:0] : 2nd conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 2nd in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 11 Reserved, must be kept at reset value.

Bits 10:6 SQ1[4:0] : 1st conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 1st in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bits 5:4 Reserved, must be kept at reset value.

Bits 3:0 L[3:0] : Regular channel sequence length

These bits are written by software to define the total number of conversions in the regular channel conversion sequence.

0000: 1 conversion

0001: 2 conversions

...

1111: 16 conversions

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Note: Some channels are not connected physically and must not be selected for conversion.

21.6.12 ADC regular sequence register 2 (ADC_SQR2)

Address offset: 0x34

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	SQ9[4:0]				Res.	SQ8[4:0]				Res.	SQ7[4]
			rw	rw	rw	rw	rw		rw	rw	rw	rw	rw		rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ7[3:0]				Res.	SQ6[4:0]				Res.	SQ5[4:0]
rw	rw	rw	rw		rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ9[4:0] : 9th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 9th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 23 Reserved, must be kept at reset value.

Bits 22:18 SQ8[4:0] : 8th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 8th in the regular conversion sequence

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 17 Reserved, must be kept at reset value.

Bits 16:12 SQ7[4:0] : 7th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 7th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 11 Reserved, must be kept at reset value.

Bits 10:6 SQ6[4:0] : 6th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 6th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 5 Reserved, must be kept at reset value.

Bits 4:0 SQ5[4:0] : 5th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 5th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Note: Some channels are not connected physically and must not be selected for conversion.

21.6.13 ADC regular sequence register 3 (ADC_SQR3)

Address offset: 0x38

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	SQ14[4:0]				Res.	SQ13[4:0]				Res.	SQ12[4]
			rw	rw	rw	rw	rw		rw	rw	rw	rw	rw		rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ12[3:0]				Res.	SQ11[4:0]				Res.	SQ10[4:0]
rw	rw	rw	rw		rw	rw	rw	rw	rw		rw	rw	rw	rw	rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ14[4:0] : 14th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 14th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 23 Reserved, must be kept at reset value.

Bits 22:18 SQ13[4:0] : 13th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 13th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 17 Reserved, must be kept at reset value.

Bits 16:12 SQ12[4:0] : 12th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 12th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 11 Reserved, must be kept at reset value.

Bits 10:6 SQ11[4:0] : 11th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 11th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 5 Reserved, must be kept at reset value.

Bits 4:0 SQ10[4:0] : 10th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 10th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Note: Some channels are not connected physically and must not be selected for conversion.

21.6.14 ADC regular sequence register 4 (ADC_SQR4)

Address offset: 0x3C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	SQ16[4:0]					Res.	SQ15[4:0]
					rw	rw	rw	rw	rw		rw	rw	rw	rw	rw

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:6 SQ16[4:0] : 16th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 16th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 5 Reserved, must be kept at reset value.

Bits 4:0 SQ15[4:0] : 15th conversion in regular sequence

These bits are written by software with the channel number (0 to 18) assigned as the 15th in the regular conversion sequence.

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Note: Some channels are not connected physically and must not be selected for conversion.

21.6.15 ADC regular data register (ADC_DR)

Address offset: 0x40

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA[15:0]
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RDATA[15:0] : Regular data converted

These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in Section 21.4.26: Data management .

21.6.16 ADC injected sequence register (ADC_JSQR)

Address offset: 0x4C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	JSQ4[4:0]					Res.	JSQ3[4:0]					Res.	JSQ2[4:2]
	rw	rw	rw	rw	rw		rw	rw	rw	rw	rw		rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JSQ2[1:0]		Res.	JSQ1[4:0]					JEXTEN[1:0]		JEXTSEL[3:0]				JL[1:0]
rw	rw		rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:26 JSQ4[4:0] : 4th conversion in the injected sequence

These bits are written by software with the channel number (0 to 18) assigned as the 4th in the injected conversion sequence.

Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Bit 25 Reserved, must be kept at reset value.

Bits 24:20 JSQ3[4:0] : 3rd conversion in the injected sequence

These bits are written by software with the channel number (0 to 18) assigned as the 3rd in the injected conversion sequence.

Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Bit 19 Reserved, must be kept at reset value.

Bits 18:14 JSQ2[4:0] : 2nd conversion in the injected sequence

These bits are written by software with the channel number (0 to 18) assigned as the 2nd in the injected conversion sequence.

Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Bit 13 Reserved, must be kept at reset value.

Bits 12:8 JSQ1[4:0] : 1st conversion in the injected sequence

These bits are written by software with the channel number (0 to 18) assigned as the 1st in the injected conversion sequence.

Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Bits 7:6 JEXTEN[1:0] : External Trigger Enable and Polarity Selection for injected channels

These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group.

00: If JQDIS=0 (queue enabled), Hardware and software trigger detection disabled

00: If JQDIS=1 (queue disabled), Hardware trigger detection disabled (conversions can be launched by software)

01: Hardware trigger detection on the rising edge

10: Hardware trigger detection on the falling edge

11: Hardware trigger detection on both the rising and falling edges

Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).

If JQM=1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Section 21.4.21: Queue of context for injected conversions )

Bits 5:2 JEXTSEL[3:0] : External Trigger Selection for injected group

These bits select the external event used to trigger the start of conversion of an injected group:

0000: Event 0

0001: Event 1

0010: Event 2

0011: Event 3

0100: Event 4

0101: Event 5

0110: Event 6

0111: Event 7

...

1111: Event 15

Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Bits 1:0 JL[1:0] : Injected channel sequence length

These bits are written by software to define the total number of conversions in the injected channel conversion sequence.

00: 1 conversion

01: 2 conversions

10: 3 conversions

11: 4 conversions

Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).

Note: Some channels are not connected physically and must not be selected for conversion.

21.6.17 ADC offset y register (ADC_OFRy)

Address offset: $$ 0x60 + 0x04 * (y - 1) $$ , ( $$ y = 1 $$ to $$ 4 $$ )

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSETy_EN	OFFSETy_CH[4:0]					Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	OFFSETy[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 OFFSETy_EN : Offset y enable

This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0].

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Bits 30:26 OFFSETy_CH[4:0] : Channel selection for the data offset y

These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[11:0] will apply.

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Some channels are not connected physically and must not be selected for the data offset y.

Bits 25:12 Reserved, must be kept at reset value.

Bits 11:0 OFFSETy[11:0] : Data offset y for the channel programmed into bits OFFSETy_CH[4:0]

These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion).

Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction.

Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[11:0] which is subtracted when converting channel 4.

21.6.18 ADC injected channel y data register (ADC_JDRy)

Address offset: $$ 0x80 + 0x04 * (y - 1) $$ , ( $$ y = 1 $$ to $$ 4 $$ )

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 JDATA[15:0] : Injected data
These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in Section 21.4.26: Data management .

21.6.19 ADC analog watchdog 2 configuration register (ADC_AWD2CR)

Address offset: 0xA0

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	AWD2CH[18:16]
													rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD2CH[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD2CH[18:0] : Analog watchdog 2 channel selection

These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2.
$$ AWD2CH[i] = 0 $$ : ADC analog input channel i is not monitored by AWD2
$$ AWD2CH[i] = 1 $$ : ADC analog input channel i is monitored by AWD2
When $$ AWD2CH[18:0] = 000..0 $$ , the analog watchdog 2 is disabled

Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers.

The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Some channels are not connected physically and must not be selected for the analog watchdog.

21.6.20 ADC analog watchdog 3 configuration register (ADC_AWD3CR)

Address offset: 0xA4

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	AWD3CH[18:16]
													rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD3CH[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD3CH[18:0] : Analog watchdog 3 channel selection

These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3.

AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3

AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3

When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled

Note: The channels selected by AWD3CH must be also selected into the SQRI or JSQRI registers.

The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).

Some channels are not connected physically and must not be selected for the analog watchdog.

21.6.21 ADC differential mode selection register (ADC_DIFSEL)

Address offset: 0xB0

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DIFSEL[18:16]
													rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DIFSEL[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	r

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 DIFSEL[18:0] : Differential mode for channels 18 to 0.

These bits are set and cleared by software. They allow to select if a channel is configured as single-ended or differential mode.

DIFSEL[i] = 0: ADC analog input channel is configured in single ended mode

DIFSEL[i] = 1: ADC analog input channel i is configured in differential mode

Note: The DIFSEL bits corresponding to channels that are either connected to a single-ended I/O port or to an internal channel must be kept their reset value (single-ended input mode).

The software is allowed to write these bits only when the ADC is disabled (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

21.6.22 ADC calibration factors (ADC_CALFACT)

Address offset: 0xB4

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CALFACT_D[6:0]
									rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CALFACT_S[6:0]
									rw	rw	rw	rw	rw	rw	rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 CALFACT_D[6:0] : Calibration Factors in differential mode

These bits are written by hardware or by software.

Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors.

Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new differential calibration is launched.

Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:0 CALFACT_S[6:0] : Calibration Factors In single-ended mode

These bits are written by hardware or by software.

Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors.

Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).

21.7 ADC common registers

These registers define the control and status registers common to master and slave ADCs:

21.7.1 ADC common status register (ADC_CSR)

Address offset: 0x00 (this offset address is relative to the master ADC base address + 0x300)

Reset value: 0x0000 0000

This register provides an image of the status bits of the different ADCs. Nevertheless it is read-only and does not allow to clear the different status bits. Instead each status bit must be cleared by writing 0 to it in the corresponding ADC_ISR register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	JQOVF_ SLV	AWD3_ SLV	AWD2_ SLV	AWD1_ SLV	JEOS_ SLV	JEOC_ SLV	OVR_ SLV	EOS_ SLV	EOC_ SLV	EOSMP_ SLV	ADRDY_ SLV
					r	r	r	r	r	r	r	r	r	r	r

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	JQOVF_ MST	AWD3_ MST	AWD2_ MST	AWD1_ MST	JEOS_ MST	JEOC_ MST	OVR_ MST	EOS_ MST	EOC_ MST	EOSMP_ MST	ADRDY_ MST
					r	r	r	r	r	r	r	r	r	r	r

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 JQOVF_
SLV : Injected Context Queue Overflow flag of the slave ADC

This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.

Bit 25 AWD3_
SLV : Analog watchdog 3 flag of the slave ADC

This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.

Bit 24 AWD2_
SLV : Analog watchdog 2 flag of the slave ADC

This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.

Bit 23 AWD1_
SLV : Analog watchdog 1 flag of the slave ADC

This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.

Bit 22 JEOS_
SLV : End of injected sequence flag of the slave ADC

This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.

Bit 21 JEOC_
SLV : End of injected conversion flag of the slave ADC

This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.

Bit 20 OVR_
SLV : Overrun flag of the slave ADC

This bit is a copy of the OVR bit in the corresponding ADC_ISR register.

Bit 19 EOS_
SLV : End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register.

Bit 18 EOC_
SLV : End of regular conversion of the slave ADC

This bit is a copy of the EOC bit in the corresponding ADC_ISR register.

Bit 17 EOSMP_
SLV : End of Sampling phase flag of the slave ADC

This bit is a copy of the EOSMP2 bit in the corresponding ADC_ISR register.

Bit 16 ADRDY_
SLV : Slave ADC ready

This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.

Bits 15:11 Reserved, must be kept at reset value.

Bit 10 JQOVF_
MST : Injected Context Queue Overflow flag of the master ADC

This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.

Bit 9 AWD3_
MST : Analog watchdog 3 flag of the master ADC

This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.

Bit 8 AWD2_
MST : Analog watchdog 2 flag of the master ADC

This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.

Bit 7 AWD1_
MST : Analog watchdog 1 flag of the master ADC

This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.

Bit 6 JEOS_
MST : End of injected sequence flag of the master ADC

This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.

Bit 5 JEOC_MST : End of injected conversion flag of the master ADC

This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.

Bit 4 OVR_MST : Overrun flag of the master ADC

This bit is a copy of the OVR bit in the corresponding ADC_ISR register.

Bit 3 EOS_MST : End of regular sequence flag of the master ADC

This bit is a copy of the EOS bit in the corresponding ADC_ISR register.

Bit 2 EOC_MST : End of regular conversion of the master ADC

This bit is a copy of the EOC bit in the corresponding ADC_ISR register.

Bit 1 EOSMP_MST : End of Sampling phase flag of the master ADC

This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.

Bit 0 ADRDY_MST : Master ADC ready

This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.

21.7.2 ADC common control register (ADC_CCR)

Address offset: 0x08 (this offset address is relative to the master ADC base address + 0x300)

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	CH18SEL	CH17SEL	VREFEN	PRESC[3:0]				CKMODE[1:0]
							rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MDMA[1:0]	DMA CFG	Res.	DELAY[3:0]				Res.	Res.	Res.	DUAL[4:0]
rw	rw	rw		rw	rw	rw	rw				rw	rw	rw	rw	rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 CH18SEL : CH18 selection

This bit is set and cleared by software to control channel 18.

0: V _BATchannel disabled.

1: V _BATchannel enabled

Bit 23 CH17SEL : CH17 selection

This bit is set and cleared by software to control channel 17.

0: Temperature sensor channel disabled

1: Temperature sensor channel enabled

Bit 22 VREFEN : V _REFINTenable

This bit is set and cleared by software to enable/disable the V _REFINTchannel.

0: V _REFINTchannel disabled

1: V _REFINTchannel enabled

Bits 21:18 PRESC[3:0] : ADC prescaler

These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs.

0000: input ADC clock not divided
0001: input ADC clock divided by 2
0010: input ADC clock divided by 4
0011: input ADC clock divided by 6
0100: input ADC clock divided by 8
0101: input ADC clock divided by 10
0110: input ADC clock divided by 12
0111: input ADC clock divided by 16
1000: input ADC clock divided by 32
1001: input ADC clock divided by 64
1010: input ADC clock divided by 128
1011: input ADC clock divided by 256
other: reserved

Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.

Bits 17:16 CKMODE[1:0] : ADC clock mode

These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs):

00: CK_ADCx (x=123) (Asynchronous clock mode), generated at product level (refer to Section 6: Reset and clock control (RCC) )
01: HCLK/1 (Synchronous clock mode). This configuration must be enabled only if the AHB clock prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register) and if the system clock has a 50% duty cycle.
10: HCLK/2 (Synchronous clock mode)
11: HCLK/4 (Synchronous clock mode)

In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion.

Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

Bits 15:14 MDMA[1:0] : Direct memory access mode for dual ADC mode

This bitfield is set and cleared by software. Refer to the DMA controller section for more details.

00: MDMA mode disabled
01: Enable dual interleaved mode to output to the master channel of DFSDM interface both Master and the Slave result (16-bit data width)
10: MDMA mode enabled for 12 and 10-bit resolution
11: MDMA mode enabled for 8 and 6-bit resolution

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 13 DMACFG : DMA configuration (for dual ADC mode)

This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN=1.

0: DMA One Shot mode selected
1: DMA Circular mode selected

For more details, refer to Section : Managing conversions using the DMA

Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).

Bit 12 Reserved, must be kept at reset value.

Bits 11:8 DELAY : Delay between 2 sampling phases

These bits are set and cleared by software. These bits are used in dual interleaved modes.

Refer to Table 141 for the value of ADC resolution versus DELAY bits values.

Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 DUAL[4:0] : Dual ADC mode selection

These bits are written by software to select the operating mode.

All the ADCs independent:

00000: Independent mode

00001 to 01001: Dual mode, master and slave ADCs working together

00001: Combined regular simultaneous + injected simultaneous mode

00010: Combined regular simultaneous + alternate trigger mode

00011: Combined Interleaved mode + injected simultaneous mode

00100: Reserved

00101: Injected simultaneous mode only

00110: Regular simultaneous mode only

00111: Interleaved mode only

01001: Alternate trigger mode only

All other combinations are reserved and must not be programmed

Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

Table 141. DELAY bits versus ADC resolution

DELAY bits	12-bit resolution	10-bit resolution	8-bit resolution	6-bit resolution
0000	$1 * T_{ADC\_CLK}$	$1 * T_{ADC\_CLK}$	$1 * T_{ADC\_CLK}$	$1 * T_{ADC\_CLK}$
0001	$2 * T_{ADC\_CLK}$	$2 * T_{ADC\_CLK}$	$2 * T_{ADC\_CLK}$	$2 * T_{ADC\_CLK}$
0010	$3 * T_{ADC\_CLK}$	$3 * T_{ADC\_CLK}$	$3 * T_{ADC\_CLK}$	$3 * T_{ADC\_CLK}$
0011	$4 * T_{ADC\_CLK}$	$4 * T_{ADC\_CLK}$	$4 * T_{ADC\_CLK}$	$4 * T_{ADC\_CLK}$
0100	$5 * T_{ADC\_CLK}$	$5 * T_{ADC\_CLK}$	$5 * T_{ADC\_CLK}$	$5 * T_{ADC\_CLK}$
0101	$6 * T_{ADC\_CLK}$	$6 * T_{ADC\_CLK}$	$6 * T_{ADC\_CLK}$	$6 * T_{ADC\_CLK}$
0110	$7 * T_{ADC\_CLK}$	$7 * T_{ADC\_CLK}$	$7 * T_{ADC\_CLK}$	$6 * T_{ADC\_CLK}$
0111	$8 * T_{ADC\_CLK}$	$8 * T_{ADC\_CLK}$	$8 * T_{ADC\_CLK}$	$6 * T_{ADC\_CLK}$
1000	$9 * T_{ADC\_CLK}$	$9 * T_{ADC\_CLK}$	$8 * T_{ADC\_CLK}$	$6 * T_{ADC\_CLK}$
1001	$10 * T_{ADC\_CLK}$	$10 * T_{ADC\_CLK}$	$8 * T_{ADC\_CLK}$	$6 * T_{ADC\_CLK}$
1010	$11 * T_{ADC\_CLK}$	$10 * T_{ADC\_CLK}$	$8 * T_{ADC\_CLK}$	$6 * T_{ADC\_CLK}$
1011	$12 * T_{ADC\_CLK}$	$10 * T_{ADC\_CLK}$	$8 * T_{ADC\_CLK}$	$6 * T_{ADC\_CLK}$
others	$12 * T_{ADC\_CLK}$	$10 * T_{ADC\_CLK}$	$8 * T_{ADC\_CLK}$	$6 * T_{ADC\_CLK}$

21.7.3 ADC common regular data register for dual mode (ADC_CDR)

Address offset: 0x0C (this offset address is relative to the master ADC base address + 0x300)

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDATA_SLV[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDATA_MST[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:16 RDATA_SLV[15:0] : Regular data of the slave ADC

In dual mode, these bits contain the regular data of the slave ADC. Refer to Section 21.4.31: Dual ADC modes .

The data alignment is applied as described in Section : Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN)

Bits 15:0 RDATA_MST[15:0] : Regular data of the master ADC.

In dual mode, these bits contain the regular data of the master ADC. Refer to Section 21.4.31: Dual ADC modes .

The data alignment is applied as described in Section : Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN)

In MDMA=0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0].

21.8 ADC register map

The following table summarizes the ADC registers.

Table 142. ADC global register map ⁽¹⁾

Offset	Register
0x000 - 0x0B4	Master ADC1
0x0B8 - 0x0FC	Reserved
0x100 - 0x1B4	Slave ADC2
0x1B8 - 0x2FC	Reserved
0x300 - 0x30C	Master and slave ADCs common registers

1. Reserved area highlighted in gray.

Table 143. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC)

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	ADC_ISR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	JQOVF	AWD3	AWD2	AWD1	JEOS	JEOC	OVR	EOS	EOC	EOSMP	ADRDY
0x00	Reset value																							0	0	0	0	0	0	0	0	0	0	0
0x04	ADC_IER	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	JQOVFIE	AWD3IE	AWD2IE	AWD1IE	JEOSIE	JEOCIE	OVRIE	EOSIE	EOCIE	EOSMPIE	ADRDYIE
0x04	Reset value																						0	0	0	0	0	0	0	0	0	0	0
0x08	ADC_CR	ADCAL	ADCALDIF	DEEPPWD	ADVREGEN	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	JADSTP	ADSTP	JADSTART	ADSTART	ADDIS	ADEN
0x08	Reset value	0	0	1	0																							0	0	0	0	0	0
0x0C	ADC_CFGR	JQDIS	AWD1CH[4:0]					JAUTO	JAWD1EN	AWD1EN	AWD1SGL	JQM	JDISCEN	DISCNUM [2:0]			DISCEN	Res.	AUTDLY	CONT	OVRMOD	EXTEN[1:0]		EXTSEL3	EXTSEL2	EXTSEL1	EXTSEL0	ALIGN	RES [1:0]		DFSDMCFG	DMACFG	DMAEN
0x0C	Reset value	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x10	ADC_CFGR2	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ROVSM	TROVS	OVSS[3:0]				OVSR [2:0]			JOVSE	ROVSE
0x10	Reset value																						0	0	0	0	0	0	0	0	0	0	0
0x14	ADC_SMPR1	SMPPLUS	Res.	SMP9 [2:0]			SMP8 [2:0]			SMP7 [2:0]			SMP6 [2:0]			SMP5 [2:0]			SMP4 [2:0]			SMP3 [2:0]			SMP2 [2:0]			SMP1 [2:0]			SMP0 [2:0]
0x14	Reset value	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x18	ADC_SMPR2	Res.	Res.	Res.	Res.	Res.	SMP18 [2:0]			SMP17 [2:0]			SMP16 [2:0]			SMP15 [2:0]			SMP14 [2:0]			SMP13 [2:0]			SMP12 [2:0]			SMP11 [2:0]			SMP10 [2:0]
0x18	Reset value						0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x1C	Reserved	Res.
0x20	ADC_TR1	Res.	Res.	Res.	Res.	HT1[11:0]												Res.	Res.	Res.	Res.	LT1[11:0]
0x20	Reset value					1	1	1	1	1	1	1	1	1	1	1	1					0	0	0	0	0	0	0	0	0	0	0	0
0x24	ADC_TR2	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	HT2[7:0]								Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	LT2[7:0]
0x24	Reset value									1	1	1	1	1	1	1	1									0	0	0	0	0	0	0	0
0x28	ADC_TR3	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	HT3[7:0]								Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	LT3[7:0]
0x28	Reset value									1	1	1	1	1	1	1	1									0	0	0	0	0	0	0	0
0x2C	Reserved	Res.
0x30	ADC_SQR1	Res.	Res.	Res.	SQ4[4:0]					Res.	SQ3[4:0]					Res.	SQ2[4:0]					Res.	SQ1[4:0]					Res.	L[3:0]
0x30	Reset value				0	0	0	0	0		0	0	0	0	0		0	0	0	0	0		0	0	0	0	0		0	0	0	0
0x34	ADC_SQR2	Res.	Res.	Res.	SQ9[4:0]					Res.	SQ8[4:0]					Res.	SQ7[4:0]					Res.	SQ6[4:0]					Res.	SQ5[4:0]
0x34	Reset value				0	0	0	0	0		0	0	0	0	0		0	0	0	0	0		0	0	0	0	0		0	0	0	0	0
0x38	ADC_SQR3	Res.	Res.	Res.	SQ14[4:0]					Res.	SQ13[4:0]					Res.	SQ12[4:0]					Res.	SQ11[4:0]					Res.	SQ10[4:0]
0x38	Reset value				0	0	0	0	0		0	0	0	0	0		0	0	0	0	0		0	0	0	0	0		0	0	0	0	0
0x3C	ADC_SQR4	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SQ16[4:0]					Res.	SQ15[4:0]
0x3C	Reset value																						0	0	0	0	0		0	0	0	0	0
0x40	ADC_DR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	regular RDATA[15:0]
0x40	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Table 143. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) (continued)

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x44-0x48	Reserved	Res.
0x4C	ADC_JSQR	Res.	JSQ4[4:0]					Res.	JSQ3[4:0]					Res.	JSQ2[4:0]					Res.	JSQ1[4:0]					JEXTEN[1:0]		JEXTSEL[3:0]				JL[1:0]
0x4C	Reset value		0	0	0	0	0		0	0	0	0	0		0	0	0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x50-0x5C	Reserved	Res.
0x60	ADC_OFR1	OFFSET1_EN	OFFSET1_CH[4:0]					Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET1[11:0]
0x60	Reset value	0	0	0	0	0	0															0	0	0	0	0	0	0	0	0	0	0	0
0x64	ADC_OFR2	OFFSET2_EN	OFFSET2_CH[4:0]					Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET2[11:0]
0x64	Reset value	0	0	0	0	0	0															0	0	0	0	0	0	0	0	0	0	0	0
0x68	ADC_OFR3	OFFSET3_EN	OFFSET3_CH[4:0]					Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET3[11:0]
0x68	Reset value	0	0	0	0	0	0															0	0	0	0	0	0	0	0	0	0	0	0
0x6C	ADC_OFR4	OFFSET4_EN	OFFSET4_CH[4:0]					Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET4[11:0]
0x6C	Reset value	0	0	0	0	0	0															0	0	0	0	0	0	0	0	0	0	0	0
0x70-0x7C	Reserved	Res.
0x80	ADC_JDR1	Res.																JDATA1[15:0]
0x80	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x84	ADC_JDR2	Res.																JDATA2[15:0]
0x84	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x88	ADC_JDR3	Res.																JDATA3[15:0]
0x88	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x8C	ADC_JDR4	Res.																JDATA4[15:0]
0x8C	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x8C-0x9C	Reserved	Res.
0xA0	ADC_AWD2CR	Res.													AWD2CH[18:0]
0xA0	Reset value														0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0xA4	ADC_AWD3CR	Res.													AWD3CH[18:0]
0xA4	Reset value														0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0xA8-0xAC	Reserved	Res.

Table 143. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) (continued)

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1
0xB0	ADC_DIFSEL	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	DIFSEL[18:0]
0xB0	Reset value														0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0xB4	ADC_CALFACT	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	CALFACT_D[6:0]																	CALFACT_S[6:0]
0xB4	Reset value										0	0	0	0	0	0	0															0

Table 144. ADC register map and reset values (master and slave ADC common registers) offset = 0x300

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	ADC_CSR	Res	Res	Res	Res	Res	JQOVF_SLV	AWD3_SLV	AWD2_SLV	AWD1_SLV	JEOS_SLV	JEOC_SLV	OVR_SLV	EoS_SLV	EOC_SLV	EOSMP_SLV	ADRDY_SLV	slave ADC2															master ADC1
0x00	Reset value						0	0	0	0	0	0	0	0	0	0	0															0
0x04	Reserved	Res.
0x08	ADC_CCR	Res	Res	Res	Res	Res	Res	Res	CH18SEL	CH17SEL	VREFEN	PRESC[3:0]																				CKMODE[1:0]	MDMA[1:0]	DMACFG	Res	DELAY[3:0]		DUAL[4:0]
0x08	Reset value								0	0	0	0	0	0	0	0	0						0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x0C	ADC_CDR	RDATA_SLV[15:0]																														RDATA_MST[15:0]
0x0C	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Refer to Section 2.2 on page 93 for the register boundary addresses.

21. Analog-to-digital converters (ADC)

21.1 Introduction

21.2 ADC main features

21.3 ADC implementation

21.4 ADC functional description

21.4.1 ADC block diagram

21.4.2 ADC pins and internal signals

21.4.3 ADC clocks

Dual clock domain architecture

Clock ratio constraint between ADC clock and AHB clock

21.4.4 ADC1/2 connectivity

21.4.5 Slave AHB interface

21.4.6 ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN)

21.4.7 Single-ended and differential input channels

21.4.8 Calibration (ADCAL, ADCALDIF, ADC_CALFACT)

21.4.9 ADC on-off control (ADEN, ADDIS, ADRDY)

Software procedure to enable the ADC

Software procedure to disable the ADC

21.4.10 Constraints when writing the ADC control bits

21.4.11 Channel selection (SQRx, JSQRx)

21.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2)

Constraints on the sampling time

I/O analog switches voltage booster

SMPPLUS control bit

21.4.13 Single conversion mode (CONT=0)

21.4.14 Continuous conversion mode (CONT=1)

21.4.15 Starting conversions (ADSTART, JADSTART)

21.4.16 ADC timing

21.4.17 Stopping an ongoing conversion (ADSTP, JADSTP)

21.4.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN)

21.4.19 Injected channel management

Triggered injection mode

Auto-injection mode

21.4.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN)

Regular group mode

Injected group mode

21.4.21 Queue of context for injected conversions

Behavior when changing the trigger or sequence context

Queue of context: Behavior when the queue becomes empty

Queue of context: Starting the ADC with an empty queue

Disabling the queue

21.4.22 Programmable resolution (RES) - Fast conversion mode

21.4.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP)

21.4.24 End of conversion sequence (EOS, JEOS)

21.4.26 Data management

Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN)

Data and alignment

Offset

Managing a sequence of conversions without using the DMA

Managing conversions without using the DMA and without overrun

Managing conversions using the DMA

DMA one shot mode (DMACFG=0)

DMA circular mode (DMACFG=1)

21.4.27 Managing conversions using the DFSDM

21.4.28 Dynamic low-power features

Auto-delayed conversion mode (AUTDLY)

21.4.29 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)

AWDx flag and interrupt

Description of analog watchdog 1

Description of analog watchdog 2 and 3

ADC y _AWD x _OUT signal output generation

21.4.30 Oversampler

ADC operating modes supported when oversampling (single ADC mode)

Analog watchdog

Triggered mode

Injected and regular sequencer management when oversampling

Oversampling regular channels only

Oversampling Injected channels only

Oversampling regular and Injected channels

Triggered regular oversampling with injected conversions

Auto-injected mode

Dual ADC modes supported when oversampling

Combined modes summary

21.4.31 Dual ADC modes

Injected simultaneous mode

Regular simultaneous mode with independent injected

Combined injected simultaneous plus interleaved

DMA requests in dual ADC mode

Example:

Overrun detection

ADC _y_AWD _x_OUT signal output generation

21.4.33 $V_{BAT}$ supply monitoring

Calculating the actual $V_{REF+}$ voltage using the internal reference voltage