13. Chrom-ART Accelerator controller (DMA2D)

13.1 DMA2D introduction

The Chrom-ART Accelerator (DMA2D) is a specialized DMA dedicated to image manipulation. It can perform the following operations:

• Filling a part or the whole of a destination image with a specific color
• Copying a part or the whole of a source image into a part or the whole of a destination image
• Copying a part or the whole of a source image into a part or the whole of a destination image with a pixel format conversion
• Blending a part and/or two complete source images with different pixel format and copy the result into a part or the whole of a destination image with a different color format.

All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel with indexed or direct color mode. The DMA2D has its own dedicated memories for CLUTs (color look-up tables).

13.2 DMA2D main features

The main DMA2D features are:

• Single AHB master bus architecture.
• AHB slave programming interface supporting 8/16/32-bit accesses (except for CLUT accesses which are 32-bit).
• User programmable working area size
• User programmable offset for sources and destination areas expressed in pixels or bytes
• User programmable sources and destination addresses on the whole memory space
• Up to 2 sources with blending operation
• Alpha value can be modified (source value, fixed value or modulated value)
• User programmable source and destination color format
• Up to 11 color formats supported from 4-bit up to 32-bit per pixel with indirect or direct color coding
• 2 internal memories for CLUT storage in indirect color mode
• Automatic CLUT loading or CLUT programming via the CPU
• User programmable CLUT size
• Internal timer to control AHB bandwidth
• 6 operating modes: register-to-memory, memory-to-memory, memory-to-memory with pixel format conversion, memory-to-memory with pixel format conversion and blending, memory-to memory with pixel format conversion, blending and fixed color foreground, and memory-to memory with pixel format conversion, blending and fixed color background.

• Area filling with a fixed color
• Copy from an area to another
• Copy with pixel format conversion between source and destination images
• Copy from two sources with independent color format and blending
• Output buffer byte swapping to support refresh of displays through parallel interface
• Abort and suspend of DMA2D operations
• Watermark interrupt on a user programmable destination line
• Interrupt generation on bus error or access conflict
• Interrupt generation on process completion

13.3 DMA2D functional description

13.3.1 DMA2D block diagram

The DMA2D controller performs direct memory transfer. As an AHB master, it can take the control of the AHB bus matrix to initiate AHB transactions.

The DMA2D can operate in the following modes:

• Register-to-memory
• Memory-to-memory
• Memory-to-memory with Pixel Format Conversion
• Memory-to-memory with Pixel Format Conversion and Blending
• Memory-to memory with pixel format conversion, blending and fixed color foreground
• Memory-to memory with pixel format conversion, blending and fixed color background

The AHB slave port is used to program the DMA2D controller.

The block diagram of the DMA2D is shown in Figure 35: DMA2D block diagram .

Figure 35. DMA2D block diagram

Figure 35. DMA2D block diagram. The diagram shows the internal architecture of the DMA2D controller. At the top, an 'AHB MASTER' interface is connected to a bus. Below it, the 'FG PFC' (Foreground Pixel Format Converter) block contains 'Color mode', '8-bit α', and an 'Expander' that outputs 'α' and 'RGB' data. This is followed by 'FG FIFO', 'CLUT itf', and '256x32-bit RAM'. Below this, the 'BG PFC' (Background Pixel Format Converter) block is identical in structure. In the center, a 'BLENDER' block takes 'α', 'Red', 'Green', and 'Blue' inputs. To the right, the 'OUT PFC' block contains 'Color mode' and a 'Converter' (supporting 32/24/16-bit formats) which outputs to 'OUT FIFO' and 'Color'. At the bottom, an 'AHB SLAVE' interface is connected to the bus. The diagram is labeled 'MS30439V1' in the bottom right corner.

13.3.2 DMA2D control

The DMA2D controller is configured through the DMA2D Control Register (DMA2D_CR) which allows selecting:

The user application can perform the following operations:

• Select the operating mode
• Enable/disable the DMA2D interrupt
• Start/suspend/abort ongoing data transfers

13.3.3 DMA2D foreground and background FIFOs

The DMA2D foreground (FG) FG FIFO and background (BG) FIFO fetch the input data to be copied and/or processed.

The FIFOs fetch the pixels according to the color format defined in their respective pixel format converter (PFC).

They are programmed through a set of control registers:

• DMA2D foreground memory address register (DMA2D_FGMAR)
• DMA2D foreground offset register (DMA2D_FGOR)
• DMA2D background memory address register (DMA2D_BGMAR)
• DMA2D background offset register (DMA2D_BGBOR)
• DMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)

When the DMA2D operates in register-to-memory mode, none of the FIFOs is activated.

When the DMA2D operates in memory-to-memory mode (no pixel format conversion nor blending operation), only the FG FIFO is activated and acts as a buffer.

When the DMA2D operates in memory-to-memory operation with pixel format conversion (no blending operation), the BG FIFO is not activated.

13.3.4 DMA2D foreground and background pixel format converter (PFC)

DMA2D foreground pixel format converter (PFC) and background pixel format converter perform the pixel format conversion to generate a 32-bit per pixel value. The PFC can also modify the alpha channel.

The first stage of the converter converts the color format. The original color format of the foreground pixel and background pixels are configured through the CM[3:0] bits of the DMA2D_FGPFCCR and DMA2D_BGPFCCR, respectively.

The supported input formats are given in Table 63: Supported color mode in input .

Table 63. Supported color mode in input

CM[3:0]	Color mode
0000	ARGB8888
0001	RGB888
0010	RGB565
0011	ARGB1555
0100	ARGB4444
0101	L8
0110	AL44
0111	AL88
1000	L4
1001	A8
1010	A4

The color format are coded as follows:

• Alpha value field: transparency
0xFF value corresponds to an opaque pixel and 0x00 to a transparent one.
• R field for Red
• G field for Green
• B field for Blue
• L field: luminance

This field is the index to a CLUT to retrieve the three/four RGB/ARGB components.

If the original format was direct color mode (ARGB/RGB), then the extension to 8-bit per channel is performed by copying the MSBs into the LSBs. This ensures a perfect linearity of the conversion.

If the original format is indirect color mode (L/AL), a CLUT is required and each pixel format converter is associated with a 256 entry 32-bit CLUT.

If the original format does not include an alpha channel, the alpha value is automatically set to 0xFF (opaque).

For the specific alpha mode A4 and A8, no color information is stored nor indexed. The color to be used for the image generation is fixed and is defined in the DMA2D_FGCOLR for foreground pixels and in the DMA2D_BGCOLR register for background pixels.

The order of the fields in the system memory is defined in Table 64: Data order in memory .

Table 64. Data order in memory

Color Mode	@ + 3	@ + 2	@ + 1	@ + 0
ARGB8888	A ₀[7:0]	R ₀[7:0]	G ₀[7:0]	B ₀[7:0]
RGB888	B ₁[7:0]	R ₀[7:0]	G ₀[7:0]	B ₀[7:0]
	G ₂[7:0]	B ₂[7:0]	R ₁[7:0]	G ₁[7:0]
	R ₃[7:0]	G ₃[7:0]	B ₃[7:0]	R ₂[7:0]
RGB565	R ₁[4:0]G ₁[5:3]	G ₁[2:0]B ₁[4:0]	R ₀[4:0]G ₀[5:3]	G ₀[2:0]B ₀[4:0]
ARGB1555	A ₁[0]R ₁[4:0]G ₁[4:3]	G ₁[2:0]B ₁[4:0]	A ₀[0]R ₀[4:0]G ₀[4:3]	G ₀[2:0]B ₀[4:0]
ARGB4444	A ₁[3:0]R ₁[3:0]	G ₁[3:0]B ₁[3:0]	A ₀[3:0]R ₀[3:0]	G ₀[3:0]B ₀[3:0]
L8	L ₃[7:0]	L ₂[7:0]	L ₁[7:0]	L ₀[7:0]
AL44	A ₃[3:0]L ₃[3:0]	A ₂[3:0]L ₂[3:0]	A ₁[3:0]L ₁[3:0]	A ₀[3:0]L ₀[3:0]
AL88	A ₁[7:0]	L ₁[7:0]	A ₀[7:0]	L ₀[7:0]
L4	L ₇[3:0]L ₆[3:0]	L ₅[3:0]L ₄[3:0]	L ₃[3:0]L ₂[3:0]	L ₁[3:0]L ₀[3:0]
A8	A ₃[7:0]	A ₂[7:0]	A ₁[7:0]	A ₀[7:0]
A4	A ₇[3:0]A ₆[3:0]	A ₅[3:0]A ₄[3:0]	A ₃[3:0]A ₂[3:0]	A ₁[3:0]A ₀[3:0]

The 24-bit RGB888 aligned on 32-bit is supported through the ARGB8888 mode.

Once the 32-bit value is generated, the alpha channel can be modified according to the AM[1:0] field of the DMA2D_FGPFCCR/DMA2D_BGPFCCR registers as shown in Table 65: Alpha mode configuration .

The alpha channel can be:

• kept as it is (no modification),
• replaced by the ALPHA[7:0] value of DMA2D_FGPFCCR/DMA2D_BGPFCCR,
• or replaced by the original alpha value multiplied by the ALPHA[7:0] value of DMA2D_FGPFCCR/DMA2D_BGPFCCR divided by 255.

Table 65. Alpha mode configuration

AM[1:0]	Alpha mode
00	No modification
01	Replaced by value in DMA2D_xxPFCCR
10	Replaced by original value multiplied by the value in DMA2D_xxPFCCR / 255
11	Reserved

Note: To support the alternate format, the incoming alpha value can be inverted setting the AI bit of the DMA2D_FGPFCCR/DMA2D_BGPFCCR registers. This applies also to the Alpha value stored in the DMA2D_FGPFCCR/DMA2D_BGPFCCR and in the CLUT.

The R and B fields can also be swapped setting the RBS bit of the DMA2D_FGPFCCR/DMA2D_BGPFCCR registers. This applies also to the RGB order used in the CLUT and in the DMA2D_FGCOLR/DMA2D_BGCOLR registers.

13.3.5 DMA2D foreground and background CLUT interface

The CLUT interface manages the CLUT memory access and the automatic loading of the CLUT.

Three kinds of accesses are possible:

• CLUT read by the PFC during pixel format conversion operation
• CLUT accessed through the AHB slave port when the CPU is reading or writing data into the CLUT
• CLUT written through the AHB master port when an automatic loading of the CLUT is performed

The CLUT memory loading can be done in two different ways:

• Automatic loading

The following sequence must be followed to load the CLUT:

a) Program the CLUT address into the DMA2D_FGCMAR register (foreground CLUT) or DMA2D_BGCMAR register (background CLUT)
b) Program the CLUT size in the CS[7:0] field of the DMA2D_FGPFCCR register (foreground CLUT) or DMA2D_BGPFCCR register (background CLUT).
c) Set the START bit of the DMA2D_FGPFCCR register (foreground CLUT) or DMA2D_BGPFCCR register (background CLUT) to start the transfer. During this automatic loading process, the CLUT is not accessible by the CPU. If a conflict

occurs, a CLUT access error interrupt is raised assuming CAEIE is set to '1' in DMA2D_CR.

Manual loading

The application has to program the CLUT manually through the DMA2D AHB slave port to which the local CLUT memory is mapped. The foreground CLUT is located at address offset 0x0400 and the background CLUT at address offset 0x0800.

The CLUT format is 24 or 32 bits. It is configured through the CCM bit of the DMA2D_FGPFCCR register (foreground CLUT) or DMA2D_BGPFCCR register (background CLUT) as shown in Table 66: Supported CLUT color mode .

Table 66. Supported CLUT color mode

CCM	CLUT color mode
0	32-bit ARGB8888
1	24-bit RGB888

The way the CLUT data are organized in the system memory is specified in Table 67: CLUT data order in system memory .

Table 67. CLUT data order in system memory

CLUT Color Mode	@ + 3	@ + 2	@ + 1	@ + 0
ARGB8888	A ₀[7:0]	R ₀[7:0]	G ₀[7:0]	B ₀[7:0]
RGB888	B ₁[7:0]	R ₀[7:0]	G ₀[7:0]	B ₀[7:0]
	G ₂[7:0]	B ₂[7:0]	R ₁[7:0]	G ₁[7:0]
	R ₃[7:0]	G ₃[7:0]	B ₃[7:0]	R ₂[7:0]

13.3.6 DMA2D blender

The DMA2D blender blends the source pixels by pair to compute the resulting pixel.

The blending is performed according to the following equation:

\text{with } \alpha_{\text{Mult}} = \frac{\alpha_{\text{FG}} \cdot \alpha_{\text{BG}}}{255}

\alpha_{\text{OUT}} = \alpha_{\text{FG}} + \alpha_{\text{BG}} - \alpha_{\text{Mult}}

C_{\text{OUT}} = \frac{C_{\text{FG}} \cdot \alpha_{\text{FG}} + C_{\text{BG}} \cdot \alpha_{\text{BG}} - C_{\text{BG}} \cdot \alpha_{\text{Mult}}}{\alpha_{\text{OUT}}} \quad \text{with } C = R \text{ or } G \text{ or } B

Division is rounded to the nearest lower integer

No configuration register is required by the blender. The blender usage depends on the DMA2D operating mode defined in MODE[2:0] field of the DMA2D_CR register.

13.3.7 DMA2D output PFC

The output PFC performs the pixel format conversion from 32 bits to the output format defined in the CM[2:0] field of the DMA2D output pixel format converter configuration register (DMA2D_OPFCCR).

The supported output formats are given in Table 68: Supported color mode in output .

Table 68. Supported color mode in output

CM[2:0]	Color mode
000	ARGB8888
001	RGB888
010	RGB565
011	ARGB1555
100	ARGB4444

Note: To support the alternate format, the calculated alpha value is inverted setting the AI bit of the DMA2D_OPFCCR registers. This applies also to the Alpha value used in the DMA2D_OCOLR.

The R and B fields can also be swapped setting the RBS bit of the DMA2D_OPFCCR registers. This applies also to the RGB order used in the DMA2D_OCOLR.

13.3.8 DMA2D output FIFO

The output FIFO programs the pixels according to the color format defined in the output PFC.

The destination area is defined through a set of control registers:

• DMA2D output memory address register (DMA2D_OMAR)
• DMA2D output offset register (DMA2D_OOR)
• DMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)

If the DMA2D operates in register-to-memory mode, the configured output rectangle is filled by the color specified in the DMA2D output color register (DMA2D_OCOLR) which contains a fixed 32-bit, 24-bit or 16-bit value. The format is selected by the CM[2:0] field of the DMA2D_OPFCCR register.

The data are stored into the memory in the order defined in Table 69: Data order in memory

Table 69. Data order in memory

Color Mode	@ + 3	@ + 2	@ + 1	@ + 0
ARGB8888	A ₀[7:0]	R ₀[7:0]	G ₀[7:0]	B ₀[7:0]
RGB888	B ₁[7:0]	R ₀[7:0]	G ₀[7:0]	B ₀[7:0]
	G ₂[7:0]	B ₂[7:0]	R ₁[7:0]	G ₁[7:0]
	R ₃[7:0]	G ₃[7:0]	B ₃[7:0]	R ₂[7:0]
RGB565	R ₁[4:0]G ₁[5:3]	G ₁[2:0]B ₁[4:0]	R ₀[4:0]G ₀[5:3]	G ₀[2:0]B ₀[4:0]

Table 69. Data order in memory (continued)

Color Mode	@ + 3	@ + 2	@ + 1	@ + 0
ARGB1555	A ₁[0]R ₁[4:0]G ₁[4:3]	G ₁[2:0]B ₁[4:0]	A ₀[0]R ₀[4:0]G ₀[4:3]	G ₀[2:0]B ₀[4:0]
ARGB4444	A ₁[3:0]R ₁[3:0]	G ₁[3:0]B ₁[3:0]	A ₀[3:0]R ₀[3:0]	G ₀[3:0]B ₀[3:0]

The RGB888 aligned on 32-bit is supported through the ARGB8888 mode.

13.3.9 DMA2D output FIFO byte reordering

The output FIFO bytes is reordered to support display frame buffer update through a parallel interface (F(S)MC) directly from the DMA2D.

The reordering of bytes can be done using:

• RBS bit to swap Red and Blue component
• SB bit to swap byte two by two in the output FIFO

When the byte swapping is activated (SB field of the DMA2D_OPFCR is set), the number of pixel per line (PL field of the DMA2D_NLR) must be even and the output memory address (MA field of the DMA2D_OMAR) must be even, and the output line offset computed in bytes (resulting from LOM field of DMA2D_CR and LO field of DMA2D_OOR values) must be even. If not a configuration error is detected.

Table 70. Standard data order in memory

Color Mode	@ + 3	@ + 2	@ + 1	@ + 0
RGB888	B ₁[7:0]	R ₀[7:0]	G ₀[7:0]	B ₀[7:0]
	G ₂[7:0]	B ₂[7:0]	R ₁[7:0]	G ₁[7:0]
	R ₃[7:0]	G ₃[7:0]	B ₃[7:0]	R ₂[7:0]
RGB565	R ₁[4:0]G ₁[5:3]	G ₁[2:0]B ₁[4:0]	R ₀[4:0]G ₀[5:3]	G ₀[2:0]B ₀[4:0]

16-bit mode (RGB565)

This mode is supported without byte reordering by the DMA2D.

Figure 36. Intel 8080 16-bit mode (RGB565)

The diagram shows a 16-bit data bus (D15 to D0) connected to a sequence of color components. The components are grouped into three color groups: Red (R4, R3, R2, R1, R0), Green (G5, G4, G3, G2, G1, G0), and Blue (B4, B3, B2, B1, B0). Each component is represented by a colored box. Arrows indicate the mapping from the data bus to the color components: D15 to R4, D14 to R3, D13 to R2, D12 to R1, D11 to R0, D10 to G5, D9 to G4, D8 to G3, D7 to G2, D6 to G1, D5 to G0, D4 to B4, D3 to B3, D2 to B2, D1 to B1, D0 to B0. The entire sequence of components is labeled '64K colors'.

Diagram illustrating the Intel 8080 16-bit mode (RGB565) data bus mapping. The Data Bus (D15 to D0) is mapped to Colors (R4 to B0) via a 16-bit Data bus. The colors are grouped into 64K colors. The mapping is: D15 to R4, D14 to R3, D13 to R2, D12 to R1, D11 to R0, D10 to G5, D9 to G4, D8 to G3, D7 to G2, D6 to G1, D5 to G0, D4 to B4, D3 to B3, D2 to B2, D1 to B1, D0 to B0.

18/24-bit mode (RGB888)

This mode needs data reordering.

1. The Red and the Blue have to be swapped (setting the RBS bit)
2. The MSB and the LSB bytes of a half-word as to be swapped (setting the SB bit)

Figure 37. Intel 8080 18/24-bit mode (RGB888)

The diagram illustrates the data bus and color mapping for two pixels in Intel 8080 18/24-bit mode (RGB888). The 'Transfer Order' is divided into two 16-bit data segments. The 'Data Bus' is shown as a sequence of bytes from D15 down to D0. The 'Colors' are mapped to these bytes: the first pixel's colors (R7-R0, G7-G0, B7-B0) are mapped to the first 16-bit data segment, and the second pixel's colors (R7-R0, G7-G0, B7-B0) are mapped to the second 16-bit data segment. The text '16.7M colors' is present between the two pixels. The diagram is labeled 'MSv42079V2' in the bottom right corner.

Diagram of Intel 8080 18/24-bit mode (RGB888) showing data bus and color mapping for two pixels.

Table 71. Output FIFO byte reordering steps

Steps	@ + 3	@ + 2	@ + 1	@ + 0
Original data ordering	B ₁[7:0]	R ₀[7:0]	G ₀[7:0]	B ₀[7:0]
	G ₂[7:0]	B ₂[7:0]	R ₁[7:0]	G ₁[7:0]
	R ₃[7:0]	G ₃[7:0]	B ₃[7:0]	R ₂[7:0]
Setting the RBS bit
Data ordering after red and blue swap (RBS set)	R ₁[7:0]	B ₀[7:0]	G ₀[7:0]	R ₀[7:0]
	G ₂[7:0]	R ₂[7:0]	B ₁[7:0]	G ₁[7:0]
	B ₃[7:0]	G ₃[7:0]	R ₃[7:0]	B ₂[7:0]
Setting the SB bit
Data ordering after byte swapping (SB set)	B ₀[7:0]	R ₁[7:0]	R ₀[7:0]	G ₀[7:0]
	R ₂[7:0]	G ₂[7:0]	G ₁[7:0]	B ₁[7:0]
	G ₃[7:0]	B ₃[7:0]	B ₂[7:0]	R ₃[7:0]

13.3.10 DMA2D AHB master port timer

An 8-bit timer is embedded into the AHB master port to provide an optional limitation of the bandwidth on the crossbar.

This timer is clocked by the AHB clock and counts a dead time between two consecutive accesses. This limits the bandwidth usage.

The timer enabling and the dead time value are configured through the AHB master port timer configuration register (DMA2D_AMPTCR).

13.3.11 DMA2D transactions

DMA2D transactions consist of a sequence of a given number of data transfers. The number of data and the width can be programmed by software.

Each DMA2D data transfer is composed of up to 4 steps:

1. Data loading from the memory location pointed by the DMA2D_FGMAR register and pixel format conversion as defined in DMA2D_FGCR.
2. Data loading from a memory location pointed by the DMA2D_BGMAR register and pixel format conversion as defined in DMA2D_BGCR.
3. Blending of all retrieved pixels according to the alpha channels resulting of the PFC operation on alpha values.
4. Pixel format conversion of the resulting pixels according to the DMA2D_OCR register and programming of the data to the memory location addressed through the DMA2D_OMAR register.

13.3.12 DMA2D configuration

Both source and destination data transfers can target peripherals and memories in the whole 4 Gbyte memory area, at addresses ranging between 0x0000 0000 and 0xFFFF FFFF.

The DMA2D can operate in any of the four following modes selected through MODE[2:0] bits of the DMA2D_CR register:

• Register-to-memory
• Memory-to-memory
• Memory-to-memory with PFC
• Memory-to-memory with PFC and blending
• Memory-to-memory with PFC, blending and fixed FG color
• Memory-to-memory with PFC, blending and fixed BG color

Register-to-memory

The register-to-memory mode is used to fill a user defined area with a predefined color.

The color format is set in the DMA2D_OPFCCR.

The DMA2D does not perform any data fetching from any source. It just writes the color defined in the DMA2D_OCOLR register to the area located at the address pointed by the DMA2D_OMAR and defined in the DMA2D_NLR and DMA2D_OOR.

Memory-to-memory

In memory-to-memory mode, the DMA2D does not perform any graphical data transformation. The foreground input FIFO acts as a buffer and the data are transferred from the source memory location defined in DMA2D_FGMAR to the destination memory location pointed by DMA2D_OMAR.

The color mode programmed in the CM[3:0] bits of the DMA2D_FGPFCCR register defines the number of bits per pixel for both input and output.

The size of the area to be transferred is defined by the DMA2D_NLR and DMA2D_FGOR registers for the source, and by DMA2D_NLR and DMA2D_OOR registers for the destination.

Memory-to-memory with PFC

In this mode, the DMA2D performs a pixel format conversion of the source data and stores them in the destination memory location.

The size of the areas to be transferred are defined by the DMA2D_NLR and DMA2D_FGOR registers for the source, and by DMA2D_NLR and DMA2D_OOR registers for the destination.

Data are fetched from the location defined in the DMA2D_FGMAR register and processed by the foreground PFC. The original pixel format is configured through the DMA2D_FGPFCCR register.

If the original pixel format is direct color mode, then the color channels are all expanded to 8 bits.

If the pixel format is indirect color mode, the associated CLUT has to be loaded into the CLUT memory.

The CLUT loading can be done automatically by following the sequence below:

1. Set the CLUT address into the DMA2D_FGCMAR.
2. Set the CLUT size in the CS[7:0] bits of the DMA2D_FGPFCCR register.
3. Set the CLUT format (24 or 32 bits) in the CCM bit of the DMA2D_FGPFCCR register.
4. Start the CLUT loading by setting the START bit of the DMA2D_FGPFCCR register.

Once the CLUT loading is complete, the CTCIF flag of the DMA2D_IFR register is raised, and an interrupt is generated if the CTCIE bit is set in DMA2D_CR. The automatic CLUT loading process can not work in parallel with classical DMA2D transfers.

The CLUT can also be filled by the CPU or by any other master through the APB port. The access to the CLUT is not possible when a DMA2D transfer is ongoing and uses the CLUT (indirect color format).

In parallel to the color conversion process, the alpha value is added or changed depending on the value programmed in the DMA2D_FGPFCCR register. If the original image does not have an alpha channel, a default alpha value of 0xFF is automatically added to obtain a fully opaque pixel. The alpha value is modified according to the AM[1:0] bits of the DMA2D_FGPFCCR register:

• It can be unchanged.
• It can be replaced by the value defined in the ALPHA[7:0] value of the DMA2D_FGPFCCR register.
• It can be replaced by the original value multiplied by the ALPHA[7:0] value of the DMA2D_FGPFCCR register divided by 255.

The resulting 32-bit data are encoded by the OUT PFC into the format specified by the CM[2:0] field of the DMA2D_OPFCCR register. The output pixel format cannot be the indirect mode since no CLUT generation process is supported.

The processed data are written into the destination memory location pointed by DMA2D_OMAR.

Memory-to-memory with PFC and blending

In this mode, 2 sources are fetched in the foreground FIFO and background FIFO from the memory locations defined by DMA2D_FGMAR and DMA2D_BGMAR.

The two pixel format converters have to be configured as described in the memory-to-memory mode. Their configurations can be different as each pixel format converter are independent and have their own CLUT memory.

Once each pixel has been converted into 32 bits by their respective PFCs, they are blended according to the equation below:

\text{with } \alpha_{\text{Mult}} = \frac{\alpha_{\text{FG}} \cdot \alpha_{\text{BG}}}{255}

\alpha_{\text{OUT}} = \alpha_{\text{FG}} + \alpha_{\text{BG}} - \alpha_{\text{Mult}}

C_{\text{OUT}} = \frac{C_{\text{FG}} \cdot \alpha_{\text{FG}} + C_{\text{BG}} \cdot \alpha_{\text{BG}} - C_{\text{BG}} \cdot \alpha_{\text{Mult}}}{\alpha_{\text{OUT}}} \quad \text{with } C = R \text{ or } G \text{ or } B

Division are rounded to the nearest lower integer

The resulting 32-bit pixel value is encoded by the output PFC according to the specified output format, and the data are written into the destination memory location pointed by DMA2D_OMAR.

Memory-to-memory with PFC, blending and fixed color FG

In this mode, only 1 source is fetched in the background FIFO from the memory location defined by DMA2D_BGMAR.

The value of the foreground color is given by the DMA2D_FGCOLR register and the alpha value is set to 0xFF (opaque).

The alpha value can be replaced or modified according to the AM[1:0] and ALPHA[7:0] fields of the DMA2D_FGPFCR.

Once each pixel has been converted into 32 bits by their respective PFCs, they are blended together, and the resulting 32-bit pixel value is encoded by the output PFC according to the specified output format, and the data are written into the destination memory location pointed by DMA2D_OMAR.

Memory-to-memory with PFC, blending and fixed color BG

In this mode, only 1 source is fetched in the foreground FIFO from the memory location defined by DMA2D_FGMAR.

The value of the background color is given by the DMA2D_BGCOLR register and the alpha value is set to 0xFF (opaque).

The alpha value can be replaced or modified according to the AM[1:0] and ALPHA[7:0] fields of the DMA2D_BGPFCR.

Configuration error detection

The DMA2D checks that the configuration is correct before any transfer. The configuration error interrupt flag is set by hardware when a wrong configuration is detected when a new transfer/automatic loading starts. An interrupt is then generated if the CEIE bit of the DMA2D_CR is set.

The wrong configurations that can be detected are listed below:

• Foreground CLUT automatic loading: MA bits of DMA2D_FGCMAR are not aligned with CCM of DMA2D_FGPFCCR.
• Background CLUT automatic loading: MA bits of DMA2D_BGCMAR are not aligned with CCM of DMA2D_BGPFCCR
• Memory transfer (except in register-to-memory mode and except in memory-to-memory mode with blending and fixed color FG): MA bits of DMA2D_FGMAR are not aligned with CM of DMA2D_FGPFCCR
• Memory transfer (except in register-to-memory mode and except in memory-to-memory mode with blending and fixed color FG): CM bits of DMA2D_FGPFCCR are invalid
• Memory transfer (except in register-to-memory mode and except in memory-to-memory mode with blending and fixed color FG): PL bits of DMA2D_NLR are odd while CM of DMA2D_FGPFCCR is A4 or L4
• Memory transfer (except in register-to-memory mode and except in memory-to-memory mode with blending and fixed color FG): LO bits of DMA2D_FGOR are odd while CM of DMA2D_FGPFCCR is A4 or L4 and LOM bit of the DMA2D_CR is pixel mode
• Memory transfer (only in blending mode and except in memory-to-memory mode with blending and fixed color FG): MA bits of DMA2D_BGMAR are not aligned with the CM of DMA2D_BGPFCCR
• Memory transfer: (only in blending mode and in blending with fixed color FG mode) CM bits of DMA2D_BGPFCCR are invalid
• Memory transfer (only in blending mode and in blending with fixed color FG mode): PL bits of DMA2D_NLR odd while CM of DMA2D_BGPFCCR is A4 or L4
• Memory transfer (only in blending mode and in blending with fixed color FG mode): LO bits of DMA2D_BGOR are odd while CM of DMA2D_BGPFCCR is A4 or L4 and LOM bit of the DMA2D_CR is pixel mode
• Memory transfer (except in memory to memory mode): MA bits of DMA2D_OMAR are not aligned with CM bits of DMA2D_OPFCCR.
• Memory transfer (except in memory to memory mode): CM bits of DMA2D_OPFCCR are invalid
• Memory transfer with byte swapping: PL bits of DMA2D_NLR are odd or MA bits of the DMA2D_OMAR are odd or LO in bytes (resulting from LOM bit of the DMA2D_CR and LO bits of DMA2D_OOR values) are odd while SB bit of DMA2D_OPFCCR is set
• Memory transfer: NL bits of DMA2D_NLR = 0

• Memory transfer: PL bits of DMA2D_NLR = 0
• Memory transfer: MODE bits of DMA2D_CR are invalid

13.3.13 DMA2D transfer control (start, suspend, abort and completion)

Once the DMA2D is configured, the transfer can be launched by setting the START bit of the DMA2D_CR register. Once the transfer is completed, the START bit is automatically reset and the TCIF flag of the DMA2D_ISR register is raised. An interrupt can be generated if the TCIE bit of the DMA2D_CR is set.

The user application can suspend the DMA2D at any time by setting the SUSP bit of the DMA2D_CR register. The transaction can then be aborted by setting the ABORT bit of the DMA2D_CR register or can be restarted by resetting the SUSP bit of the DMA2D_CR register.

The user application can abort at any time an ongoing transaction by setting the ABORT bit of the DMA2D_CR register. In this case, the TCIF flag is not raised.

Automatic CLUT transfers can also be aborted or suspended by using the ABORT or the SUSP bit of the DMA2D_CR register.

13.3.14 Watermark

A watermark can be programmed to generate an interrupt when the last pixel of a given line has been written to the destination memory area.

The line number is defined in the LW[15:0] field of the DMA2D_LWR register.

When the last pixel of this line has been transferred, the TWIF flag of the DMA2D_ISR register is raised and an interrupt is generated if the TWIE bit of the DMA2D_CR is set.

13.3.15 Error management

Two kind of errors can be triggered:

• AHB master port errors signaled by the TEIF flag of the DMA2D_ISR register.
• Conflicts caused by CLUT access (CPU trying to access the CLUT while a CLUT loading or a DMA2D transfer is ongoing) signalled by the CAEIF flag of the DMA2D_ISR register.

Both flags are associated to their own interrupt enable flag in the DMA2D_CR register to generate an interrupt if need be (TEIE and CAEIE).

13.3.16 AHB dead time

To limit the AHB bandwidth usage, a dead time between two consecutive AHB accesses can be programmed.

This feature can be enabled by setting the EN bit in the DMA2D_AMTCR register.

The dead time value is stored in the DT[7:0] field of the DMA2D_AMTCR register. This value represents the guaranteed minimum number of cycles between two consecutive transactions on the AHB bus.

The update of the dead time value while the DMA2D is running is taken into account for the next AHB transfer.

13.4 DMA2D interrupts

An interrupt can be generated on the following events:

• Configuration error
• CLUT transfer complete
• CLUT access error
• Transfer watermark reached
• Transfer complete
• Transfer error

Separate interrupt enable bits are available for flexibility.

Table 72. DMA2D interrupt requests

Interrupt event	Event flag	Enable control bit
Configuration error	CEIF	CEIE
CLUT transfer complete	CTCIF	CTCIE
CLUT access error	CAEIF	CAEIE
Transfer watermark	TWF	TWIE
Transfer complete	TCIF	TCIE
Transfer error	TEIF	TEIE

13.5 DMA2D registers

13.5.1 DMA2D control register (DMA2D_CR)

Address offset: 0x0000

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MODE[2:0]
													rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	CEIE	CTCIE	CAEIE	TWIE	TCIE	TEIE	Res.	LOM	Res.	Res.	Res.	ABORT	SUSP	START
		rw	rw	rw	rw	rw	rw		rw				rs	rw	rs

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:16 MODE[2:0] : DMA2D mode

These bits are set and cleared by software. They cannot be modified while a transfer is ongoing.

000: Memory-to-memory (FG fetch only)

001: Memory-to-memory with PFC (FG fetch only with FG PFC active)

010: Memory-to-memory with blending (FG and BG fetch with PFC and blending)

011: Register-to-memory (no FG nor BG, only output stage active)

100: Memory-to-memory with Blending and fixed color FG (BG fetch only with FG and BG PFC active)

101: Memory-to-memory with Blending and fixed color BG (BG fetch only with FG and BG PFC active)

others: meaningless

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 CEIE : Configuration Error Interrupt Enable