9. System configuration controller (SYSCFG)

9.1 SYSCFG main features

The STM32L4+ Series devices feature a set of configuration registers. The main purposes of the system configuration controller are the following:

• • Remapping memory areas
• • Managing the external interrupt line connection to the GPIOs
• • Managing robustness feature
• • Setting SRAM2 write protection and software erase
• • Configuring FPU interrupts
• • Enabling the firewall
• • Enabling /disabling \( I^2C \) Fast-mode Plus driving capability on some I/Os and voltage booster for I/Os analog switches.

9.2 SYSCFG registers

9.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)

This register is used for specific configurations on memory remap.

Address offset: 0x00

Reset value: 0x0000 000X (X is the memory mode selected by the BOOT0 pin and BOOT1 option bit)

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 FB_MODE : Flash Bank mode selection

For 2 Mbytes devices:

0: Flash Bank 1 mapped at 0x0800 0000 (and aliased @0x0000 0000 ⁽¹⁾ )
and Flash Bank 2 mapped at 0x0810 0000 (and aliased at 0x0010 0000)

1: Flash Bank 2 mapped at 0x0800 0000 (and aliased @0x0000 0000 ⁽¹⁾ )
and Flash Bank 1 mapped at 0x0810 0000 (and aliased at 0x0010 0000)

For 1 Mbyte devices:

0: Flash Bank 1 mapped at 0x0800 0000 (and aliased @0x0000 0000 ⁽¹⁾ )
and Flash Bank 2 mapped at 0x0808 0000 (and aliased at 0x0008 0000)

1: Flash Bank2 mapped at 0x0800 0000 (and aliased @0x0000 0000 ⁽¹⁾ )
and Flash Bank 1 mapped at 0x0808 0000 (and aliased at 0x0008 0000)

For 512 Kbytes devices:

0: Flash Bank 1 mapped at 0x0800 0000 (and aliased @0x0000 0000 ⁽¹⁾ )
and Flash Bank 2 mapped at 0x0804 0000 (and aliased at 0x0004 0000)

1: Flash Bank2 mapped at 0x0800 0000 (and aliased @0x0000 0000 ⁽¹⁾ )
and Flash Bank 1 mapped at 0x0804 0000 (and aliased at 0x0004 0000)

Bits 7:3 Reserved, must be kept at reset value.

Bits 2:0 MEM_MODE : Memory mapping selection

These bits control the memory internal mapping at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the BOOT pin and the option bit setting. After reset these bits take the value selected by BOOT0 pin (or option bit depending on nSWBOOT0 option bit) and BOOT1 option bit.

000: Main Flash memory mapped at 0x00000000 ⁽¹⁾ .

001: System Flash memory mapped at 0x00000000.

010: FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.

011: SRAM1 mapped at 0x00000000.

100: OCTOSPI1 memory mapped at 0x00000000

101: OCTOSPI2 memory mapped at 0x00000000

111: Reserved

1. When BFB2 bit is set, the system memory remains aliased at @0x0000 0000.

Note: When the FSMC is remapped at address 0x0000 0000, only the first two regions of Bank 1 memory controller (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) can be remapped. In remap mode, the CPU can access the external memory via ICode bus instead of System bus which boosts up the performance.

9.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1)

Address offset: 0x04

Reset value: 0x7C00 0001

Bits 31:26 FPU_IE[5..0] : Floating point unit interrupts enable bits

FPU_IE[5]: Inexact interrupt enable

FPU_IE[4]: Input denormal interrupt enable

FPU_IE[3]: Overflow interrupt enable

FPU_IE[2]: underflow interrupt enable

FPU_IE[1]: Divide-by-zero interrupt enable

FPU_IE[0]: Invalid operation interrupt enable

Bits 25:24 Reserved, must be kept at reset value.

Bit 23 I2C4_FMP : Fast-mode Plus driving capability activation

This bit enables the Fm+ driving mode on I2C4 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C4 pins selected through AF selection bits

1: Fm+ mode is enabled on I2C4 pins selected through AF selection bits.

Bit 22 I2C3_FMP : I2C3 Fast-mode Plus driving capability activation

This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C3 pins selected through AF selection bits

1: Fm+ mode is enabled on I2C3 pins selected through AF selection bits.

Bit 21 I2C2_FMP : I2C2 Fast-mode Plus driving capability activation

This bit enables the Fm+ driving mode on I2C2 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C2 pins selected through AF selection bits

1: Fm+ mode is enabled on I2C2 pins selected through AF selection bits.

Bit 20 I2C1_FMP : I2C1 Fast-mode Plus driving capability activation

This bit enables the Fm+ driving mode on I2C1 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C1 pins selected through AF selection bits

1: Fm+ mode is enabled on I2C1 pins selected through AF selection bits.

Bit 19 I2C_PB9_FMP : Fast-mode Plus (Fm+) driving capability activation on PB9

This bit enables the Fm+ driving mode for PB9.

0: PB9 pin operates in standard mode.

1: Fm+ mode enabled on PB9 pin, and the Speed control is bypassed.

Bit 18 I2C_PB8_FMP : Fast-mode Plus (Fm+) driving capability activation on PB8

This bit enables the Fm+ driving mode for PB8.

0: PB8 pin operates in standard mode.

1: Fm+ mode enabled on PB8 pin, and the Speed control is bypassed.

Bit 17 I2C_PB7_FMP : Fast-mode Plus (Fm+) driving capability activation on PB7

This bit enables the Fm+ driving mode for PB7.

0: PB7 pin operates in standard mode.

1: Fm+ mode enabled on PB7 pin, and the Speed control is bypassed.

Bit 16 I2C_PB6_FMP : Fast-mode Plus (Fm+) driving capability activation on PB6

This bit enables the Fm+ driving mode for PB6.

0: PB6 pin operates in standard mode.

1: Fm+ mode enabled on PB6 pin, and the Speed control is bypassed.

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 ANASWVDD : GPIO analog switch control voltage selection when at least one analog peripheral supplied by V _DDA is enabled (COMP, OPAMP, VREFBUF, ADC,...).

0: I/O analog switches supplied by V _DDA or booster when booster is ON

1: I/O analog switches supplied by V _DD .

Refer to Table 45 for bit 9 setting.

Note: if all analog peripherals are disabled then ANASWVDD is bypassed and analog switches are only supplied by VDD

Bit 8 BOOSTEN : I/O analog switch voltage booster enable when at least one analog peripheral supplied by V _DDA is enabled (COMP, OPAMP, VREFBUF, ADC,...)

0: I/O analog switches are supplied by V _DDA voltage. This is the recommended configuration when using the ADC in high V _DDA voltage operation.

1: I/O analog switches are supplied by a dedicated voltage booster (supplied by V _DD ). This is the recommended configuration when using the ADC in low V _DDA voltage operation

Note: if all analog peripherals are disabled then BOOSTEN is bypassed and voltage booster is disabled

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 FWDIS : Firewall disable

This bit is cleared by software to protect the access to the memory segments according to the Firewall configuration. Once enabled, the firewall cannot be disabled by software. Only a system reset set the bit.

0: Firewall protection enabled

1: Firewall protection disabled

Table 45 describes when the bit 9 (ANASWVDD) and the bit 8 (BOOSTEN) should be set or reset depending on the voltage settings.

Table 45. BOOSTEN and ANASWVDD set/reset (when at least one analog peripheral supplied by VDDA is enabled)

9.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)

Address offset: 0x08

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 EXTI3[3:0] : EXTI 3 configuration bits

These bits are written by software to select the source input for the EXTI3 external interrupt.

0000: PA[3] pin
0001: PB[3] pin
0010: PC[3] pin
0011: PD[3] pin
0100: PE[3] pin
0101: PF[3] pin
0110: PG[3] pin
0111: PH[3] pin
1000: PI[3] pin

Bits 11:8 EXTI2[3:0] : EXTI 2 configuration bits

These bits are written by software to select the source input for the EXTI2 external interrupt.

0000: PA[2] pin
0001: PB[2] pin
0010: PC[2] pin
0011: PD[2] pin
0100: PE[2] pin
0101: PF[2] pin
0110: PG[2] pin
0111: PH[2] pin
1000: PI[2] pin

Bits 7:4 EXTI1[3:0] : EXTI 1 configuration bits

These bits are written by software to select the source input for the EXTI1 external interrupt.

0000: PA[1] pin
0001: PB[1] pin
0010: PC[1] pin
0011: PD[1] pin
0100: PE[1] pin
0101: PF[1] pin
0110: PG[1] pin
0111: PH[1] pin
1000: PI[1] pin

Bits 3:0 EXTI0[3:0] : EXTI 0 configuration bits

These bits are written by software to select the source input for the EXTI0 external interrupt.

0000: PA[0] pin
0001: PB[0] pin
0010: PC[0] pin
0011: PD[0] pin
0100: PE[0] pin
0101: PF[0] pin
0110: PG[0] pin
0111: PH[0] pin
1000: PI[0] pin

9.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 EXTI7[3:0] : EXTI 7 configuration bits

These bits are written by software to select the source input for the EXTI7 external interrupt.

• 0000: PA[7] pin
• 0001: PB[7] pin
• 0010: PC[7] pin
• 0011: PD[7] pin
• 0100: PE[7] pin
• 0101: PF[7] pin
• 0110: PG[7] pin
• 0111: PH[7] pin
• 1000: PI[7] pin

These bits are written by software to select the source input for the EXTI6 external interrupt.

0000: PA[6] pin
0001: PB[6] pin
0010: PC[6] pin
0011: PD[6] pin
0100: PE[6] pin
0101: PF[6] pin
0110: PG[6] pin
0111: PH[6] pin
1000: PI[6] pin

These bits are written by software to select the source input for the EXTI5 external interrupt.

0000: PA[5] pin
0001: PB[5] pin
0010: PC[5] pin
0011: PD[5] pin
0100: PE[5] pin
0101: PF[5] pin
0110: PG[5] pin
0111: PH[5] pin
1000: PI[5] pin

These bits are written by software to select the source input for the EXTI4 external interrupt.

0000: PA[4] pin
0001: PB[4] pin
0010: PC[4] pin
0011: PD[4] pin
0100: PE[4] pin
0101: PF[4] pin
0110: PG[4] pin
0111: PH[4] pin
1000: PI[4] pin

Note: Some of the I/O pins mentioned in the above register may not be available on small packages.

9.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)

Address offset: 0x10

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 EXTI11[3:0] : EXTI 11 configuration bits

These bits are written by software to select the source input for the EXTI11 external interrupt.

0000: PA[11] pin
0001: PB[11] pin
0010: PC[11] pin
0011: PD[11] pin
0100: PE[11] pin
0101: PF[11] pin
0110: PG[11] pin
0111: PH[11] pin
1000: PI[11] pin

Bits 11:8 EXTI10[3:0] : EXTI 10 configuration bits

These bits are written by software to select the source input for the EXTI10 external interrupt.

0000: PA[10] pin
0001: PB[10] pin
0010: PC[10] pin
0011: PD[10] pin
0100: PE[10] pin
0101: PF[10] pin
0110: PG[10] pin
0111: PH[10] pin
1000: PI[10] pin

Bits 7:4 EXTI9[3:0] : EXTI 9 configuration bits

These bits are written by software to select the source input for the EXTI9 external interrupt.

0000: PA[9] pin
0001: PB[9] pin
0010: PC[9] pin
0011: PD[9] pin
0100: PE[9] pin
0101: PF[9] pin
0110: PG[9] pin
0111: PH[9] pin
1000: PI[9] pin

Bits 3:0 EXTI8[3:0] : EXTI 8 configuration bits

These bits are written by software to select the source input for the EXTI8 external interrupt.

0000: PA[8] pin
0001: PB[8] pin
0010: PC[8] pin
0011: PD[8] pin
0100: PE[8] pin
0101: PF[8] pin
0110: PG[8] pin
0111: PH[8] pin
1000: PI[8] pin

Note: Some of the I/O pins mentioned in the above register may not be available on small packages.

9.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)

Address offset: 0x14

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 EXTI15[3:0] : EXTI 15 configuration bits

These bits are written by software to select the source input for the EXTI15 external interrupt.

• 0000: PA[15] pin
• 0001: PB[15] pin
• 0010: PC[15] pin
• 0011: PD[15] pin
• 0100: PE[15] pin
• 0101: PF[15] pin
• 0110: PG[15] pin
• 0111: PH[15] pin
• 1000: Reserved

These bits are written by software to select the source input for the EXTI14 external interrupt.

0000: PA[14] pin
0001: PB[14] pin
0010: PC[14] pin
0011: PD[14] pin
0100: PE[14] pin
0101: PF[14] pin
0110: PG[14] pin
0111: PH[14] pin
1000: Reserved

These bits are written by software to select the source input for the EXTI13 external interrupt.

0000: PA[13] pin
0001: PB[13] pin
0010: PC[13] pin
0011: PD[13] pin
0100: PE[13] pin
0101: PF[13] pin
0110: PG[13] pin
0111: PH[13] pin
1000: Reserved

These bits are written by software to select the source input for the EXTI12 external interrupt.

0000: PA[12] pin
0001: PB[12] pin
0010: PC[12] pin
0011: PD[12] pin
0100: PE[12] pin
0101: PF[12] pin
0110: PG[12] pin
0111: PH[12] pin
1000: Reserved

Note: Some of the I/O pins mentioned in the above register may not be available on small packages.

9.2.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR)

Address offset: 0x18

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value

Bit 1 SRAM2BSY : SRAM2 busy by erase operation

0: No SRAM2 erase operation is on going.

1: SRAM2 erase operation is on going.

Bit 0 SRAM2ER : SRAM2 Erase

Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at the end of the SRAM2 erase operation.

Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register.

9.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x1C

System reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value

Bit 8 SPF : SRAM2 parity error flag

This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing '1'.

0: No SRAM2 parity error detected

1: SRAM2 parity error detected

Bits 7:4 Reserved, must be kept at reset value

Bit 3 ECCL : ECC Lock

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Flash ECC error connection to TIM1/8/15/16/17 Break input.

0: ECC error disconnected from TIM1/8/15/16/17 Break input.

1: ECC error connected to TIM1/8/15/16/17 Break input.

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.

0: PVD interrupt disconnected from TIM1/8/15/16/17 Break input. PVDE and PLS[2:0] bits can be programmed by the application.

1: PVD interrupt connected to TIM1/8/15/16/17 Break input, PVDE and PLS[2:0] bits are read only.

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break inputs.

0: SRAM2 parity error signal disconnected from TIM1/8/15/16/17 Break inputs

1: SRAM2 parity error signal connected to TIM1/8/15/16/17 Break inputs

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of Cortex ^® -M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input

0: Cortex ^® -M4 LOCKUP output disconnected from TIM1/8/15/16/17 Break inputs

1: Cortex ^® -M4 LOCKUP output connected to TIM1/8/15/16/17 Break inputs

9.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR)

Address offset: 0x20

System reset value: 0x0000 0000

Bits 31:0 P _x WP (x = 0 to 31): SRAM2 page x write protection

These bits are set by software and cleared only by a system reset.

0: Write protection of SRAM2 page x is disabled.

1: Write protection of SRAM2 page x is enabled.

9.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR)

Address offset: 0x24

System reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value

Bits 7:0 KEY[7:0] : SRAM2 write protection key for software erase

The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register.

1. 1. Write "0xCA" into Key[7:0]
2. 2. Write "0x53" into Key[7:0]

Writing a wrong key reactivates the write protection.

9.2.11 SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2)

Address offset: 0x28

System reset value: 0x0000 0000

Bits 31:0 PxWP (x= 32 to 63): SRAM2 page x write protection

These bits are set by software and cleared only by a system reset.

0: Write protection of SRAM2 page x is disabled.

1: Write protection of SRAM2 page x is enabled.

9.2.12 SYSCFG register map

The following table gives the SYSCFG register map and the reset values.

Table 46. SYSCFG register map and reset values

Refer to Section 2.2 on page 93 for the register boundary addresses.