5. Power control (PWR)

5.1 Power supplies

The STM32L4+ Series devices require a 1.71 V to 3.6 V operating supply voltage ( \( V_{DD} \) ). Several peripherals are supplied through independent power domains: \( V_{DDA} \) , \( V_{DDIO2} \) , \( V_{DDUSB} \) , \( V_{DDDSI} \) . Those supplies must not be provided without a valid operating supply on the \( V_{DD} \) pin.

• • \( V_{DD} = 1.71 \text{ V to } 3.6 \text{ V} \)

\( V_{DD} \) is the external power supply for the I/Os, the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins.

• • \( V_{DDA} = 1.62 \text{ V (ADCs/COMPs) / } 1.8 \text{ V (DACs/OPAMPs) / } 2.4 \text{ V (VREFBUF) to } 3.6 \text{ V} \)

\( V_{DDA} \) is the external analog power supply for A/D converters, D/A converters, voltage reference buffer, operational amplifiers and comparators. The \( V_{DDA} \) voltage level is independent from the \( V_{DD} \) voltage. \( V_{DDA} \) should be preferably connected to \( V_{DD} \) when these peripherals are not used.

• • \( V_{DD12} = 1.05 \text{ to } 1.32 \text{ V} \)

\( V_{DD12} \) is the external power supply bypassing the internal regulator when connected to an external SMPS. It is provided externally through \( V_{DD12} \) pins and only available on packages with the external SMPS supply option. \( V_{DD12} \) does not require any external decoupling capacitance and cannot support any external load.

• • \( V_{DDUSB} = 3.0 \text{ V to } 3.6 \text{ V} \)

\( V_{DDUSB} \) is the external independent power supply for USB transceivers. The \( V_{DDUSB} \) voltage level is independent from the \( V_{DD} \) voltage. \( V_{DDUSB} \) should be preferably connected to \( V_{DD} \) when the USB is not used.

The \( V_{DDUSB} \) power supply may not be present as a dedicated pin, but to be internally bonded to \( V_{DD} \) . For such devices, \( V_{DD} \) has to respect the \( V_{DDUSB} \) supply range when the USB is used.

• • \( V_{DDIO2} = 1.08 \text{ V to } 3.6 \text{ V} \)

\( V_{DDIO2} \) is the external power supply for 14 I/Os (Port G[15:2]). The \( V_{DDIO2} \) voltage level is independent from the \( V_{DD} \) voltage and should preferably be connected to \( V_{DD} \) when PG[15:2] are not used.

• • \( V_{DDDSI} \) is an independent DSI power supply dedicated to the DSI regulator and the MIPI DPHY. This supply must be connected to the global \( V_{DD} \) .

• • \( V_{CAPDSI} \) pin is the output of the DSI regulator (1.2 V) which must be connected externally to \( V_{DD12DSI} \) .

• • \( V_{DD12DSI} \) pin is used to supply the MIPI D-PHY, and to supply the clock and data lanes pins. An external capacitor of 2.2 uF must be connected on \( V_{DD12DSI} \) pin.

• • \( V_{BAT} = 1.55 \text{ V to } 3.6 \text{ V} \)

\( V_{BAT} \) is the power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when \( V_{DD} \) is not present. \( V_{BAT} \) is internally bonded to VDD for small packages without dedicated pin.

• • \( V_{REF-} \) , \( V_{REF+} \)

\( V_{REF+} \) is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage reference buffer when enabled.

When \( V_{DDA} < 2\text{ V} \) , \( V_{REF+} \) must be equal to \( V_{DDA} \) .

When \( V_{DDA} \geq 2\text{ V} \) , \( V_{REF+} \) must be between 2 V and \( V_{DDA} \) .

\( V_{REF+} \) can be grounded when ADC and DAC are not active.

The internal voltage reference buffer supports two output voltages, which are configured with VRS bit in the VREFBUF_CSR register:

• – \( V_{REF+} \) around 2.048 V. This requires \( V_{DDA} \) equal to or higher than 2.4 V.
• – \( V_{REF+} \) around 2.5 V. This requires \( V_{DDA} \) equal to or higher than 2.8 V.

\( V_{REF-} \) and \( V_{REF+} \) pins are not available on all packages. When not available on the package, they are bonded to \( V_{SSA} \) and \( V_{DDA} \) , respectively.

When the \( V_{REF+} \) is double-bonded with \( V_{DDA} \) in a package, the internal voltage reference buffer is not available and must be kept disable (refer to related device datasheet for packages pinout description).

\( V_{REF-} \) must always be equal to \( V_{SSA} \) .

An embedded linear voltage regulator is used to supply the internal digital power \( V_{CORE} \) . \( V_{CORE} \) is the power supply for digital peripherals and memories.

Figure 9. STM32L4P5xx/Q5xx, STM32L4S5xx/R5xx and STM32L4S7xx/L4R7xx power supply overview

Figure 10. STM32L4S9xx/L4R9xx power supply overview

5.1.1 Independent analog peripherals supply

To improve ADC and DAC conversion accuracy and to extend the supply flexibility, the analog peripherals have an independent power supply which can be separately filtered and shielded from noise on the PCB.

• • The analog peripherals voltage supply input is available on a separate V _DDA pin.
• • An isolated supply ground connection is provided on V _SSA pin.

The V _DDA supply voltage can be different from V _DD . The presence of V _DDA must be checked before enabling any of the analog peripherals supplied by V _DDA (A/D converter, D/A converter, comparators, operational amplifiers, voltage reference buffer).

The V _DDA supply can be monitored by the Peripheral Voltage Monitoring, and compared with two thresholds (1.65 V for PVM3 or 2.2 V for PVM4), refer to Section 5.2.3: Peripheral Voltage Monitoring (PVM) for more details.

When a single supply is used, V _DDA can be externally connected to V _DD through the external filtering circuit in order to ensure a noise-free V _DDA reference voltage.

ADC and DAC reference voltage

To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to \( V_{REF+} \) a separate reference voltage lower than \( V_{DDA} \) . \( V_{REF+} \) is the highest voltage, represented by the full scale value, for an analog input (ADC) or output (DAC) signal.

\( V_{REF+} \) can be provided either by an external reference or by an internal buffered voltage reference (VREFBUF).

The internal voltage reference is enabled by setting the ENVR bit in the Section 23.3.1: VREFBUF control and status register (VREFBUF_CSR) . The voltage reference is set to 2.5 V when the VRS bit is set and to 2.048 V when the VRS bit is cleared. The internal voltage reference can also provide the voltage to external components through \( V_{REF+} \) pin. Refer to the device datasheet and to Section 23: Voltage reference buffer (VREFBUF) for further information.

5.1.2 Independent I/O supply rail

Some I/Os from Port G (PG[15:2]) are supplied from a separate supply rail. The power supply for this rail can range from 1.08 V to 3.6 V and is provided externally through the \( V_{DDIO2} \) pin. The \( V_{DDIO2} \) voltage level is completely independent from \( V_{DD} \) or \( V_{DDA} \) . The \( V_{DDIO2} \) pin is available only for some packages. Refer to the pinout diagrams or tables in the related device datasheet(s) for I/O list(s).

After reset, the I/Os supplied by \( V_{DDIO2} \) are logically and electrically isolated and therefore are not available. The isolation must be removed before using any I/O from PG[15:2], by setting the IOSV bit in the PWR_CR2 register, once the \( V_{DDIO2} \) supply is present.

The \( V_{DDIO2} \) supply is monitored by the Peripheral Voltage Monitoring (PVM2) and compared with the internal reference voltage ( \( 3/4 V_{REFINT} \) , around 0.9V), refer to Section 5.2.3: Peripheral Voltage Monitoring (PVM) for more details.

5.1.3 Independent USB transceivers supply

The USB transceivers are supplied from a separate \( V_{DDUSB} \) power supply pin. \( V_{DDUSB} \) range is from 3.0 V to 3.6 V and is completely independent from \( V_{DD} \) or \( V_{DDA} \) .

After reset, the USB features supplied by \( V_{DDUSB} \) are logically and electrically isolated and therefore are not available. The isolation must be removed before using the USB OTG peripheral, by setting the USV bit in the PWR_CR2 register, once the \( V_{DDUSB} \) supply is present.

The \( V_{DDUSB} \) supply is monitored by the Peripheral Voltage Monitoring (PVM1) and compared with the internal reference voltage ( \( V_{REFINT} \) , around 1.2 V), refer to Section 5.2.3: Peripheral Voltage Monitoring (PVM) for more details.

5.1.4 Independent DSI supply

The DSI (Display Serial Interface) sub-system uses several power supply pins which are independent from the other supply pins:

• • \( VDDDSI \) is an independent DSI power supply dedicated for DSI Regulator and MIPI D-PHY. This supply must be connected to global \( V_{DD} \) .
• • \( VCAPDSI \) pin is the output of DSI Regulator (1.2V) which must be connected externally to \( VDD12DSI \) .
• • \( VDD12DSI \) pin is used to supply the MIPI D-PHY, and to supply clock and data lanes

pins. An external capacitor of 2.2 uF must be connected on VDD12DSI pin.

• • VSSDSI pin is an isolated supply ground used for DSI sub-system.

If DSI functionality is not used at all, then:

• • VDDDSI pin must be connected to global VDD.
• • VCAPDSI pin must be connected externally to VDD12DSI but the external capacitor is no more needed. If the VDD12DSI is not available on a package, the VCAPDSI to be kept floating.
• • VSSDSI pin must be grounded.

Note: VDDDSI and VDD12DSI pins are not available on all packages. When not available, they are bonded to VDD and VCAPDSI, respectively.

5.1.5 Battery backup domain

To retain the content of the Backup registers and supply the RTC function when \( V_{DD} \) is turned off, the VBAT pin can be connected to an optional backup voltage supplied by a battery or by another source.

The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 I/Os, allowing the RTC to operate even when the main power supply is turned off. The switch to the \( V_{BAT} \) supply is controlled by the power-down reset embedded in the Reset block.

Warning: During \( t_{RSTTEMPO} \) (temporization at \( V_{DD} \) startup) or after a PDR has been detected, the power switch between \( V_{BAT} \) and \( V_{DD} \) remains connected to \( V_{BAT} \) .
During the startup phase, if \( V_{DD} \) is established in less than \( t_{RSTTEMPO} \) (refer to the datasheet for the value of \( t_{RSTTEMPO} \) ) and \( V_{DD} > V_{BAT} + 0.6 \) V, a current may be injected into \( V_{BAT} \) through an internal diode connected between \( V_{DD} \) and the power switch ( \( V_{BAT} \) ).
If the power supply/battery connected to the VBAT pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the VBAT pin.

If no external battery is used in the application, it is recommended to connect \( V_{BAT} \) externally to \( V_{DD} \) with a 100 nF external ceramic decoupling capacitor.

When the backup domain is supplied by \( V_{DD} \) (analog switch connected to \( V_{DD} \) ), the following pins are available:

• • PC13, PC14 and PC15, which can be used as GPIO pins
• • PC13, PC14 and PC15, which can be configured by RTC or LSE (refer to Section 46.3: RTC functional description on page 1544 )
• • PA0/RTC_TAMP2 and PE6/RTC_TAMP3 when they are configured by the RTC as tamper pins

Note: Due to the fact that the analog switch can transfer only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive a LED).

When the backup domain is supplied by \( V_{BAT} \) (analog switch connected to \( V_{BAT} \) because \( V_{DD} \) is not present), the following functions are available:

• • PC13, PC14 and PC15 can be controlled only by RTC or LSE (refer to Section 46.3: RTC functional description )
• • PA0/RTC_TAMP2 and PE6/RTC_TAMP3 when they are configured by the RTC as tamper pins

Backup domain access

After a system reset, the backup domain (RTC registers and backup registers) is protected against possible unwanted write accesses. To enable access to the backup domain, proceed as follows:

1. 1. Enable the power interface clock by setting the PWREN bits in the Section 6.4.19: APB1 peripheral clock enable register 1 (RCC_APB1ENR1)
2. 2. Set the DBP bit in the Power control register 1 (PWR_CR1) to enable access to the backup domain
3. 3. Select the RTC clock source in the Backup domain control register (RCC_BDCR) .
4. 4. Enable the RTC clock by setting the RTCEN [15] bit in the Backup domain control register (RCC_BDCR) .

VBAT battery charging

When \( V_{DD} \) is present, It is possible to charge the external battery on VBAT through an internal resistance.

The VBAT charging is done either through a 5 k \( \Omega \) resistor or through a 1.5 k \( \Omega \) resistor depending on the VBRS bit value in the PWR_CR4 register.

The battery charging is enabled by setting VBE bit in the PWR_CR4 register. It is automatically disabled in VBAT mode.

5.1.6 Voltage regulator

Two embedded linear voltage regulators supply all the digital circuitries, except for the Standby circuitry and the backup domain. The main regulator output voltage ( \( V_{CORE} \) ) can be programmed by software to two different power ranges (Range 1 and Range 2) in order to optimize the consumption depending on the system's maximum operating frequency (refer to Section 6.2.9: Clock source frequency versus voltage scaling and to Section 3.3.3: Read access latency ).

The voltage regulators are always enabled after a reset. Depending on the application modes, the \( V_{CORE} \) supply is provided either by the main regulator (MR) or by the low-power regulator (LPR).

• • In Run, Sleep and Stop 0 modes, both regulators are enabled and the main regulator (MR) supplies full power to the \( V_{CORE} \) domain (core, memories and digital peripherals).
• • In Low-power run and Low-power sleep modes, the main regulator is off and the low-power regulator (LPR) supplies low-power to the \( V_{CORE} \) domain, preserving the contents of the registers, SRAM1, SRAM2 and SRAM3.
• • In Stop 1 and Stop 2 modes, the main regulator is off and the low-power regulator (LPR) supplies low-power to the \( V_{CORE} \) domain, preserving the contents of the registers, SRAM1, SRAM2 and SRAM3.
• • In Standby mode, the SRAM2 content can be fully or partially (see note below)

preserved (depending on RRS[1:0] bits in the PWR_CR3 register). The main regulator (MR) is off and the low-power regulator (LPR) provides the supply only to SRAM2. The core, digital peripherals (except Standby circuitry and backup domain) and SRAM1 are powered off.

Note: For STM32L4Rxxx and STM32L4Sxxx devices it is only possible to preserve the full SRAM2 content depending on RRS bit in the PWR_CR3 register. For STM32L4P5xx and STM32L4Q5xx devices it is possible to preserve the full (64 Kbytes) or partial (4 Kbytes) SRAM2 content depending on RRS[1:0] bits in the PWR_CR3 register.

• • In Standby mode, both regulators are powered off. The contents of the registers, SRAM1, SRAM2 and SRAM3 is lost except for the Standby circuitry and the backup domain.
• • In Shutdown mode, both regulators are powered off. When exiting from Shutdown mode, a power-on reset is generated. Consequently, the contents of the registers, SRAM1, SRAM2 and SRAM3 is lost, except for the backup domain.

5.1.7 VDD12 domain

VDD12 is intended to be connected with external SMPS (switched-mode power supply) to generate the V _CORE logic supply in Run, Sleep and Stop 0 modes only.

VDD12 pins correspond to the internal V _CORE powering the digital part of Core, RAMs, FLASH and peripherals. This significantly improves the power consumption with a gain from 50% or more depending of the SMPS performances.

The main benefit occurs in Run and Sleep modes whereas in Stop 0 mode, the gain is less significant.

The figure below shows a schematic to understand how the internal regulator stops supplying V _CORE when an external voltage VDD12 is provided.

As VDD12 shares the same pin as output of the internal regulator, applying a slightly higher voltage (typically +50 mV) on the VDD12 blocks, the PMOS and the regulator consumption is negligible.

Figure 11. Internal main regulator overview

A switch, controlled by the chosen GPIO, is inserted between the SMPS output and VDD12.

There are two possible states:

• • Connected: Switch is closed so SMPS powers VDD12
• • Disconnected: Switch is open and VDD12 is disconnected from SMPS output

Proper software management through GPIOs to enable/disable SMPS and to connect/disconnect SMPS through the switch, is required to conform with the rules described below. See also Section 5.1.8: Dynamic voltage scaling management .

It is mandatory to respect the following rules to avoid any damage or instability on either digital parts or internal regulators:

• • In Run, Sleep and Stop 0 modes, VDD12 can be connected and should respect
  • – \( VDD12 < 1.32\text{ V} \)
  • – \( VDD12 \geq V_{CORE} + 50\text{ mV} \) giving for main regulator
    Range 1 boost mode, \( V_{CORE} = 1.28\text{ V} \) so VDD12 should be greater than 1.33 V, but this cannot match previous rule \( VDD12 < 1.32\text{ V} \) , so it is not a functional use case with an external SMPS.
    Range 1 normal mode, \( V_{CORE} = 1.2\text{ V} \) so VDD12 should be greater than 1.25 V.
    Range 2, \( V_{CORE} = 1.0\text{ V} \) so VDD12 should be greater than 1.05 V
  • – \( VDD12 \geq 1.08\text{ V} \) in Range 2 when \( 80\text{ MHz} \geq \text{SYSCLK frequency} \geq 26\text{ MHz} \)
  • – \( VDD12 \geq 1.14\text{ V} \) in Range 2 when \( \text{SYSCLK frequency} > 80\text{ MHz} \)
• • In all other modes, such as LPRun, LPSleep, Stop 1, Stop 2, Standby and Shutdown modes, VDD12 must be disconnected from SMPS output. This means that the pin must be connected to an high impedance output:
  • – VDD12 connected to HiZ (voltage is provided by internal regulators)
• • Transitions of VDD12 from connected to disconnected is only allowed when \( \text{SYSCLK frequency} \leq 26\text{ MHz} \) to avoid too big voltage drop on main regulator side.

Note: In case of asynchronous reset while having the \( VDD12 \leq 1.25\text{ V} \) , VDD12 should switch to HiZ in less than regulator switching time from Range 2 to Range 1 ( \( \sim 1\text{ us} \) ).

Note: On STM32L4P5xx and STM32L4Q5xx devices, VDD12 Range 2 is extended down to 1.00 V for better efficiency, thus following formula applies when bit EXT_SMPS_ON in the Power control register 4 (PWR_CR4) is set:
Range 2, \( V_{CORE} = 0.95\text{ V} \) so VDD12 should be greater than 1.00 V

Note: For more details on VDD12 management, refer to AN4978 “Design recommendations for STM32L4xxxx with external SMPS, for ultra-low-power applications with high performance”.

5.1.8 Dynamic voltage scaling management

The dynamic voltage scaling is a power management technique which consists in increasing or decreasing the voltage used for the digital peripherals ( \( V_{CORE} \) ), according to the application performance and power consumption needs.

Dynamic voltage scaling to increase \( V_{CORE} \) is known as overvolting. It allows to improve the device performance.

Dynamic voltage scaling to decrease \( V_{CORE} \) is known as undervolting. It is performed to save power, particularly in laptop and other mobile devices where the energy comes from a battery and is thus limited.

• • Range 1: High-performance range.

In Range1, the main regulator operates in two modes following the R1MODE bit in the PWR_CR5 register:

• • Main regulator Range 1 normal mode: provides a typical output voltage at 1.2 V. It is used when the system clock frequency is up to 80 MHz. The Flash access time for read access is minimum, write and erase operations are possible.
• • Main regulator Range 1 boost mode: provides a typical output voltage at 1.28 V. It is used when the system clock frequency is up to 120 MHz. The Flash access time for read access is minimum, write and erase operations are possible. To optimize the power consumption it is recommended to select the range1 boost mode when the system clock frequency is greater than 80 MHz. See Table 24 .

Table 24. Range 1 boost mode configuration

• • Range 2: Low-power range.

The main regulator provides a typical output voltage at 1.0 V. The system clock frequency can be up to 26 MHz. The Flash access time for a read access is increased as compared to Range 1; write and erase operations are not possible.

Voltage scaling is selected through the VOS bit in the PWR_CR1 register.

The sequence to go from Range 1 (Normal/Boost) to Range 2 is:

1. 1. In case of switching from Range 1 boost mode to Range 2, the system clock must be divided by 2 using the AHB prescaler before switching to a lower system frequency for at least 1us and then reconfigure the AHB prescaler.:
2. 2. Reduce the system frequency to a value lower than 26 MHz
3. 3. Adjust number of wait states according new frequency target in Range 2 (LATENCY bits in the FLASH_ACR).
4. 4. Program the VOS bits to “10” in the PWR_CR1 register.

The sequence to go from Range 2 to Range 1 (normal/boost mode) is:

1. 1. Program the VOS bits to “01” in the PWR_CR1 register.
2. 2. Wait until the VOSF flag is cleared in the PWR_SR2 register.
3. 3. Adjust number of wait states according new frequency target in Range 1 (LATENCY bits in the FLASH_ACR).
4. 4. Increase the system frequency by following below procedure:
   • – If the system frequency is \( 26\text{ MHz} < \text{SYSCLK} \leq 80\text{ MHz} \) :
     • - Select the Range 1 normal mode by setting R1MODE bit in the PWR_CR5 register.
     • - Configure and switch to PLL for a new system frequency.
   • – If the system frequency is \( \text{SYSCLK} > 80\text{ MHz} \) :
     • - The system clock must be divided by 2 using the AHB prescaler before switching to a higher system frequency.
     • - Select the Range 1 boost mode by clearing the R1MODE bit is in the PWR_CR5 register,
     • - Configure and switch to PLL for a new system frequency.
     • - Wait for at least 1us and then reconfigure the AHB prescaler to get the needed HCLK clock frequency.

The sequence to switch from Range1 normal mode to Range1 boost mode is:

1. 1. The system clock must be divided by 2 using the AHB prescaler before switching to a higher system frequency.
2. 2. Clear the R1MODE bit is in the PWR_CR5 register,
3. 3. Adjust the number of wait states according to the new frequency target in range1 boost mode
4. 4. Configure and switch to new system frequency.
5. 5. Wait for at least 1 1us and then reconfigure the AHB prescaler to get the needed HCLK clock frequency.

The sequence to switch from Range1 boost mode to Range1 normal mode is:

1. 1. Set the R1MODE bit is in the PWR_CR5 register.
2. 2. Adjust the number of wait states according new frequency target in Range1 default mode
3. 3. Configure and switch to new system frequency.

When supplying VDD12 with an external SMPS, three states can be configured:

• • SMPS Range 1: main regulator is in normal Range 1, \( V_{\text{CORE}} \) is supplied by external SMPS and higher than 1.25 V. SYSCLK frequency can be up to 120 MHz.
• • SMPS Range 2 high: main regulator is in Range 2, \( V_{\text{CORE}} \) is supplied by external SMPS and higher than
  • – 1.08 V when \( \text{SYSCLK frequency} \leq 80\text{ MHz} \)
  • – 1.14 V when \( \text{SYSCLK frequency} > 80\text{ MHz} \)
• • SMPS Range 2 low: main regulator is in Range 2, \( V_{\text{CORE}} \) is supplied by external SMPS and higher than 1.05 V. Max SYSCLK frequency is 26 MHz without Flash write/erase operations.

In order to match the upper rules described in Section 5.1.7: VDD12 domain , the transition sequences can only be one of the following:

• • Range 1 to SMPS Range 1:
  1. 1. Start SMPS converter (if not always enabled by HW).
  2. 2. Check that SMPS converter output is at the correct level, like \( 1.25\text{ V} \leq \text{VDD12} < 1.32\text{ V} \) .
  3. 3. Connect VDD12 to external SMPS converter through the switch.


• • Range 2 to SMPS Range 2 low and high:
  1. 1. Start SMPS (if not always enabled by HW).
  2. 2. Check that SMPS output is at the correct level like \( 1.05\text{ V} \leq \text{VDD12} < 1.32\text{ V} \) .
  3. 3. Connect VDD12 to external SMPS converter through the switch.
     • – If \( 1.08\text{ V} \leq \text{VDD12} \) (like SMPS Range 2 high), then the following steps can be applied:
       1. 1. Set register FLASH_CFGR bit LVEN to 1.
       2. 2. Adjust the number of wait states in the FLASH_ACR (up to max frequency of Range 1 refer to Section 3.3.3: Read access latency ).
       3. 3. Increase the system frequency up to the maximum allowed value for voltage Range 1 (like 80 MHz when \( 1.08\text{ V} < \text{VDD12} < 1.14\text{ V} \) or 120 MHz when \( \text{VDD12} > 1.14\text{ V} \) ).


• • SMPS Range 1 to Range 1 or SMPS Range 2 low and high to Range 2:
  1. 1. If in Range 1, reduce the system frequency to a value lower or equal to 26 MHz.
  2. 2. Adjust number of wait states according new frequency target corresponding to voltage range (LATENCY bits in the FLASH_ACR).
  3. 3. Set register FLASH_CFGR bit LVEN to 0.
  4. 4. Disconnect VDD12 by opening the switch.
  5. 5. Stop SMPS (if required and not kept always enabled).

5.2 Power supply supervisor

5.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR)

The device has an integrated power-on reset (POR) / power-down reset (PDR), coupled with a brown-out reset (BOR) circuitry. The BOR is active in all power modes except Shutdown mode, and cannot be disabled.

Five BOR thresholds can be selected through option bytes.

During power-on, the BOR keeps the device under reset until the supply voltage \( V_{\text{DD}} \) reaches the specified \( V_{\text{BORx}} \) threshold. When \( V_{\text{DD}} \) drops below the selected threshold, a device reset is generated. When \( V_{\text{DD}} \) is above the \( V_{\text{BORx}} \) upper limit, the device reset is released and the system can start.

For more details on the brown-out reset thresholds, refer to the electrical characteristics section in the datasheet.

Figure 12. Brown-out reset waveform

1. 1. The reset temporization \( t_{RSTTEMPO} \) is present only for the BOR lowest threshold ( \( V_{BOR0} \) ).

5.2.2 Programmable voltage detector (PVD)

You can use the PVD to monitor the \( V_{DD} \) power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register 2 (PWR_CR2) .

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the Power status register 2 (PWR_SR2) , to indicate if \( V_{DD} \) is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The rising/falling edge sensitivity of the EXTI Line16 should be configured according to PVD output behavior i.e. if the EXTI line 16 is configured to rising edge sensitivity, the interrupt will be generated when \( V_{DD} \) drops below the PVD threshold. As an example the service routine could perform emergency shutdown tasks.

Figure 13. PVD thresholds

5.2.3 Peripheral Voltage Monitoring (PVM)

Only \( V_{DD} \) is monitored by default, as it is the only supply required for all system-related functions. The other supplies ( \( V_{DDA} \) , \( V_{DDIO2} \) and \( V_{DDUSB} \) ) can be independent from \( V_{DD} \) and can be monitored with four Peripheral Voltage Monitoring (PVM).

Each of the four PVMx (x=1, 2, 3, 4) is a comparator between a fixed threshold \( V_{PVMx} \) and the selected power supply. PVMOx flags indicate if the independent power supply is higher or lower than the PVMx threshold: PVMOx flag is cleared when the supply voltage is above the PVMx threshold, and is set when the supply voltage is below the PVMx threshold.

Each PVM output is connected to an EXTI line and can generate an interrupt if enabled through the EXTI registers. The PVMx output interrupt is generated when the independent power supply drops below the PVMx threshold and/or when it rises above the PVMx threshold, depending on EXTI line rising/falling edge configuration.

Each PVM can remain active in Stop 0, Stop 1 and Stop 2 modes, and the PVM interrupt can wake up from the Stop mode.

Table 25. PVM features

The independent supplies ( \( V_{DDA} \) , \( V_{DDIO2} \) and \( V_{DDUSB} \) ) are not considered as present by default, and a logical and electrical isolation is applied to ignore any information coming from the peripherals supplied by these dedicated supplies.

• • If these supplies are shorted externally to \( V_{DD} \) , the application should assume they are available without enabling any Peripheral Voltage Monitoring.
• • If these supplies are independent from \( V_{DD} \) , the Peripheral Voltage Monitoring (PVM) can be enabled to confirm whether the supply is present or not.

The following sequence must be done before using the USB OTG peripheral:

1. 1. If \( V_{DDUSB} \) is independent from \( V_{DD} \) :
   1. a) Enable the PVM1 by setting PVME1 bit in the Power control register 2 (PWR_CR2) .
   2. b) Wait for the PVM1 wakeup time
   3. c) Wait until PVMO1 bit is cleared in the Power status register 2 (PWR_SR2) .
   4. d) Optional: Disable the PVM1 for consumption saving.
2. 2. Set the USV bit in the Power control register 2 (PWR_CR2) to remove the \( V_{DDUSB} \) power isolation.

The following sequence must be done before using any I/O from PG[15:2]:

1. 1. If \( V_{DDIO2} \) is independent from \( V_{DD} \) :
   1. a) Enable the PWM2 by setting PVME2 bit in the Power control register 2 (PWR_CR2) .
   2. b) Wait for the PWM2 wakeup time
   3. c) Wait until PVMO2 bit is cleared in the Power status register 2 (PWR_SR2) .
   4. d) Optional: Disable the PWM2 for consumption saving.
2. 2. Set the IOSV bit in the Power control register 2 (PWR_CR2) to remove the \( V_{DDIO2} \) power isolation.

The following sequence must be done before using any of these analog peripherals: analog to digital converters, digital to analog converters, comparators, operational amplifiers, voltage reference buffer:

1. 1. If \( V_{DDA} \) is independent from \( V_{DD} \) :
   1. a) Enable the PWM3 (or PWM4) by setting PVME3 (or PVME4) bit in the Power control register 2 (PWR_CR2) .
   2. b) Wait for the PWM3 (or PWM4) wakeup time
   3. c) Wait until PVMO3 (or PVMO4) bit is cleared in the Power status register 2 (PWR_SR2) .
   4. d) Optional: Disable the PWM3 (or PWM4) for consumption saving.
2. 2. Enable the analog peripheral, which automatically removes the \( V_{DDA} \) isolation.

5.3 Low-power modes

By default, the microcontroller is in Run mode after a system or a power Reset. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources.

The device features seven low-power modes:

• • Sleep mode: CPU clock off, all peripherals including Cortex ^® -M4 core peripherals such as NVIC, SysTick, etc. can run and wake up the CPU when an interrupt or an event occurs. Refer to Section 5.3.4: Sleep mode .
• • Low-power run mode: This mode is achieved when the system clock frequency is reduced below 2 MHz. The code is executed from the SRAM or the Flash memory. The regulator is in low-power mode to minimize the regulator's operating current. Refer to Section 5.3.2: Low-power run mode (LP run) .
• • Low-power sleep mode: This mode is entered from the Low-power run mode: Cortex ^® -M4 is off. Refer to Section 5.3.5: Low-power sleep mode (LP sleep) .
• • Stop 0, Stop 1 and Stop 2 modes: SRAM1, SRAM2, SRAM3 and all registers content are retained. All clocks in the \( V_{CORE} \) domain are stopped, the PLL, the MSI, the HSI16 and the HSE are disabled. The LSI and the LSE can be kept running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with the wakeup capability can enable the HSI16 RC during the Stop mode to detect their wakeup condition.

In Stop 2 mode, most of the \( V_{CORE} \) domain is put in a lower leakage mode. To further reduce the current consumption during Stop 2, it is possible to switch OFF the SRAM3:

• – Stop 2 mode with SRAM3 content lost when the RRSTP bit is cleared in

PWR_CR1 register (default setting).

Stop 2 mode with SRAM3 retention when the RRSTP bit is set in PWR_CR1 register.

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, which allows the fastest wakeup time but with much higher consumption. The active peripherals and wakeup sources are the same as in Stop 1 mode.

The system clock, when exiting from Stop 0, Stop 1 or Stop 2 mode, can be either MSI up to 48 MHz or HSI16, depending on the software configuration.

Refer to Section 5.3.6: Stop 0 mode and Section 5.3.8: Stop 2 mode .

• • Standby mode: \( V_{\text{CORE}} \) domain is powered off. However, it is possible to preserve the SRAM2 contents:

For STM32L4Rxxx and STM32L4Sxxx devices:

• • – Standby mode with SRAM2 retention when the bit RRS is set in PWR_CR3 register. In this case, SRAM2 is supplied by the low-power regulator.
  • – Standby mode when the bit RRS is cleared in PWR_CR3 register. In this case the main regulator and the low-power regulator are powered off.

For STM32L4P5xx and STM32L4Q5xx devices:

• • – Standby mode with full or only the upper 4 Kbytes of SRAM2 retention when the RRS[1:0] bits are set to '01' or '10' respectively in the PWR_CR3 register. In this case, the SRAM2 is supplied by the low-power regulator.
  • – Standby mode when the RRS[1:0] bits are cleared in PWR_CR3 register. In this case the main regulator and the low-power regulator are powered off.

All clocks in the \( V_{\text{CORE}} \) domain are stopped, the PLL, the MSI, the HSI16 and the HSE are disabled. The LSI and the LSE can be kept running.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The system clock, when exiting Standby modes, is MSI from 1 MHz up to 8 MHz.

Refer to Section 5.3.9: Standby mode .

• • Shutdown mode: \( V_{\text{CORE}} \) domain is powered off. All clocks in the \( V_{\text{CORE}} \) domain are stopped, the PLL, the MSI, the HSI16, the LSI and the HSE are disabled. The LSE can be kept running. The system clock, when exiting the Shutdown mode, is MSI at 4 MHz. In this mode, the supply voltage monitoring is disabled and the product behavior is not guaranteed in case of a power voltage drop. Refer to Section 5.3.10: Shutdown mode .

In addition, the power consumption in Run mode can be reduced by one of the following means:

• • Slowing down the system clocks
• • Gating the clocks to the APB and AHB peripherals when they are unused.

Figure 14. Low-power modes possible transitions

graph TD
    LPSM[Low power sleep mode] <--> LPRM[Low power run mode]
    LPRM <--> RM[Run mode]
    LPRM --> SDM[Shutdown mode]
    LPRM --> SBM[Standby mode]
    SM[Sleep mode] <--> RM
    SM <--> LPRM
    S1M[Stop 1 mode] <--> RM
    S1M <--> LPRM
    S1M <--> SM
    S0M[Stop 0 mode] <--> RM
    S0M <--> S1M
    S2M[Stop 2 mode] <--> RM
    RM <--> SDM
    RM <--> SBM
    SBM <--> SDM
    S2M --> SDM
    S2M --> SBM

Table 26. Low-power mode summary

Table 26. Low-power mode summary (continued)

1. Refer to Table 27: Functionalities depending on the working mode .

2. SRAM2 4 Kbytes retention in Standby mode is only available for STM32L4P5xx and STM32L4Q5xx devices.

Table 27. Functionalities depending on the working mode ⁽¹⁾ (continued)

1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available. Wakeup highlighted in gray.
2. The Flash can be configured in Power-down mode. By default, it is not in Power-down mode.
3. The SRAM clock can be gated on or off.
4. For STM32L4Rxxx and STM32L4Sxxx, SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register. For STM32L4P5xx and STM32L4Q5xx, 4 Kbytes or full SRAM2 content is preserved depending on RRS[1:0] bits configuration in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore.
6. PSSI is available only on STM32L4P5xx and STM32L4Q5xx devices.
7. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.
8. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
9. Only for STM32L4P5xx and STM32L4Q5xx devices.

1. 10. Voltage scaling Range 1 only.
2. 11. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
3. 12. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
4. 13. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

Debug mode

By default, the debug connection is lost if the application puts the MCU in Stop 0, Stop1, Stop 2, Standby or Shutdown mode while the debug features are used. This is due to the fact that the Cortex ^® -M4 core is no longer clocked.

However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to Section 57.16.1: Debug support for low-power modes .

5.3.1 Run mode

Slowing down system clocks

In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down the peripherals before entering the Sleep mode.

For more details, refer to Section 6.4.3: Clock configuration register (RCC_CFGR) .

Peripheral clock gating

In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped at any time to reduce the power consumption.

To further reduce the power consumption in Sleep mode, the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.

The peripheral clock gating is controlled by the RCC_AHBxENR and RCC_APBxENR registers.

Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in the RCC_AHBxSMENR and RCC_APBxSMENR registers.

5.3.2 Low-power run mode (LP run)

To further reduce the consumption when the system is in Run mode, the regulator can be configured in low-power mode. In this mode, the system frequency should not exceed 2 MHz.

Please refer to the product datasheet for more details on voltage regulator and peripherals operating conditions.

I/O states in Low-power run mode

In Low-power run mode, all I/O pins keep the same state as in Run mode.

Entering the Low-power run mode

To enter the Low-power run mode, proceed as follows:

1. 1. Optional: Jump into the SRAM and power-down the Flash by setting the RUN_PD bit in the Flash access control register (FLASH_ACR) .
2. 2. Decrease the system clock frequency below 2 MHz.
3. 3. Force the regulator in low-power mode by setting the LPR bit in the PWR_CR1 register.

Refer to Table 28: Low-power run on how to enter the Low-power run mode.

Exiting the Low-power run mode

To exit the Low-power run mode, proceed as follows:

1. 1. Force the regulator in main mode by clearing the LPR bit in the PWR_CR1 register.
2. 2. Wait until REGLPF bit is cleared in the PWR_SR2 register.
3. 3. Increase the system clock frequency.

Refer to Table 28: Low-power run on how to exit the Low-power run mode.

Table 28. Low-power run

5.3.3 Low-power modes

Entering low-power mode

Low-power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M4 System Control register is set on Return from ISR.

Entering Low-power mode through WFI or WFE will be executed only if no interrupt is pending or no event is pending.

Exiting low-power mode

From Sleep modes, and Stop modes the MCU exit low-power mode depending on the way the low-power mode was entered:

• • If the WFI instruction or Return from ISR was used to enter the low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device.
• • If the WFE instruction is used to enter the low-power mode, the MCU exits the low-power mode as soon as an event occurs. The wakeup event can be generated either by:
  • – NVIC IRQ interrupt.
    • - When SEVONPEND = 0 in the Cortex®-M4 System Control register. By enabling an interrupt in the peripheral control register and in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral

IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.

• - When SEVONPEND = 1 in the Cortex ^® -M4 System Control register.

By enabling an interrupt in the peripheral control register and optionally in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

All NVIC interrupts will wakeup the MCU, even the disabled ones. Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.

• – Event

Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set.

It may be necessary to clear the interrupt flag in the peripheral.

From Standby modes, and Shutdown modes the MCU exit low-power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs (see Figure 456: RTC block diagrams ).

After waking up from Standby or Shutdown mode, program execution restarts in the same way as after a Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).

5.3.4 Sleep mode

I/O states in Sleep mode

In Sleep mode, all I/O pins keep the same state as in Run mode.

Entering the Sleep mode

The Sleep mode is entered according Section : Entering low-power mode , when the SLEEPDEEP bit in the Cortex ^® -M4 System Control register is clear.

Refer to Table 29: Sleep for details on how to enter the Sleep mode.

Exiting the Sleep mode

The Sleep mode is exit according Section : Exiting low-power mode .

Refer to Table 29: Sleep for more details on how to exit the Sleep mode.

Table 29. Sleep

5.3.5 Low-power sleep mode (LP sleep)

Please refer to the product datasheet for more details on voltage regulator and peripherals operating conditions.

I/O states in Low-power sleep mode

In Low-power sleep mode, all I/O pins keep the same state as in Run mode.

Entering the Low-power sleep mode

The Low-power sleep mode is entered from Low-power run mode according to Section : Entering low-power mode , when the SLEEPDEEP bit in the Cortex®-M4 System Control register is clear.

Refer to Table 30: Low-power sleep for details on how to enter the Low-power sleep mode.

Exiting the Low-power sleep mode

The low-power Sleep mode is exit according to Section : Exiting low-power mode . When exiting the Low-power sleep mode by issuing an interrupt or an event, the MCU is in Low-power run mode.

Refer to Table 30: Low-power sleep for details on how to exit the Low-power sleep mode.

Table 30. Low-power sleep

5.3.6 Stop 0 mode

The Stop 0 mode is based on the Cortex®-M4 DeepSleep mode combined with the peripheral clock gating. The voltage regulator is configured in main regulator mode. In Stop 0 mode, all clocks in the V _CORE domain are stopped; the PLL, the MSI, the HSI16 and the HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx (x=1,2,3), U(S)ARTx(x=1,2...5) and LPUART) can switch on the HSI16 to receive a frame, and switch off the HSI16 after receiving the frame if it is not a wakeup frame. In this case, the HSI16 clock is propagated only to the peripheral requesting it.

SRAM1, SRAM2, SRAM3 and register contents are preserved.

The BOR is always available in Stop 0 mode. The consumption is increased when thresholds higher than V _BOR0 are used.

I/O states in Stop 0 mode

In the Stop 0 mode, all I/O pins keep the same state as in the Run mode.

Entering the Stop 0 mode

The Stop 0 mode is entered according Section : Entering low-power mode , when the SLEEPDEEP bit in the Cortex®-M4 System Control register is set.

Refer to Table 31: Stop 0 mode for details on how to enter the Stop 0 mode.

If Flash memory programming is ongoing, the Stop 0 mode entry is delayed until the memory access is finished.

If an access to the APB domain is ongoing, The Stop 0 mode entry is delayed until the APB access is finished.

In Stop 0 mode, the following features can be selected by programming individual control bits:

• • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started, it cannot be stopped except by a Reset. See Section 44.3: IWDG functional description .
• • real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR)
• • Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status register (RCC_CSR) .
• • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR) .

Several peripherals can be used in Stop 0 mode and can add consumption if they are enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LPTIM1, LPTIM2, I2Cx (x=1,2,3,4) U(S)ARTx(x=1,2...5), LPUART.

The DACx (x=1,2), the OPAMPs and the comparators can be used in Stop 0 mode, the PVMx (x=1,2,3,4) and the PVD as well. If they are not needed, they must be disabled by software to save their power consumptions.

The ADCx (x=1,2,3), temperature sensor and VREFBUF buffer can consume power during the Stop 0 mode, unless they are disabled before entering this mode.

Exiting the Stop 0 mode

The Stop 0 mode is exit according Section : Entering low-power mode .

Refer to Table 31: Stop 0 mode for details on how to exit Stop 0 mode.

When exiting Stop 0 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is selected as system clock if the bit STOPWUCK is set in Clock configuration register (RCC_CFGR) . The MSI oscillator is selected as system clock if the bit STOPWUCK is cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The MSI selection allows wakeup at higher frequency, up to 48 MHz.

When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop 0 mode with HSI16. By keeping the internal regulator ON during Stop 0 mode, the consumption is higher although the startup time is reduced.

When exiting the Stop 0 mode, the MCU is either in Run mode (Range 1 or Range 2 depending on VOS bit in PWR_CR1) or in Low-power run mode if the bit LPR is set in the PWR_CR1 register.

Table 31. Stop 0 mode

5.3.7 Stop 1 mode

The Stop 1 mode is the same as Stop 0 mode except that the main regulator is OFF, and only the low-power regulator is ON. Stop 1 mode can be entered from Run mode and from Low-power run mode.

Refer to Table 32: Stop 1 mode for details on how to enter and exit Stop 1 mode.

Table 32. Stop 1 mode

5.3.8 Stop 2 mode

The Stop 2 mode is based on the Cortex®-M4 DeepSleep mode combined with peripheral clock gating. In Stop 2 mode, all clocks in the V _CORE domain are stopped, the PLL, the MSI, the HSI16 and the HSE oscillators are disabled. Some peripherals with wakeup capability (I2C3 and LPUART) can switch on the HSI16 to receive a frame, and switch off the HSI16 after receiving the frame if it is not a wakeup frame. In this case the HSI16 clock is propagated only to the peripheral requesting it.

SRAM1, SRAM2, SRAM3 and register contents are preserved. The SRAM3 content is preserved or lost following the RRSTP bit configuration in the PWR_CR1 register. By default, after reset, the RRSTP bit is reset thus the SRAM3 content is lost during Stop 2.

The BOR is always available in Stop 2 mode. The consumption is increased when thresholds higher than V _BOR0 are used.

Note: The comparators outputs, the LPUART outputs and the LPTIM1 outputs are forced to low speed (OSPEEDy=00) during the Stop 2 mode.

I/O states in Stop 2 mode

In the Stop 2 mode, all I/O pins keep the same state as in the Run mode.

Entering Stop 2 mode

The Stop 2 mode is entered according Section : Entering low-power mode , when the SLEEPDEEP bit in the Cortex ^® -M4 System Control register is set.

Refer to Table 33: Stop 2 mode for details on how to enter the Stop 2 mode.

Stop 2 mode can only be entered from Run mode. It is not possible to enter Stop 2 mode from the Low-power run mode.

If Flash memory programming is ongoing, the Stop 2 mode entry is delayed until the memory access is finished.

If an access to the APB domain is ongoing, The Stop 2 mode entry is delayed until the APB access is finished.

In Stop 2 mode, the following features can be selected by programming individual control bits:

• • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See Section 44.3: IWDG functional description in Section 44: Independent watchdog (IWDG) .
• • Real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR)
• • Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status register (RCC_CSR) .
• • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR) .

Several peripherals can be used in Stop 2 mode and can add consumption if they are enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LPTIM1, I2C3, LPUART.

The comparators can be used in Stop 2 mode, the PWMx (x=1,2,3,4) and the PVD as well. If they are not needed, they must be disabled by software to save their power consumptions.

The ADCx, OPAMPx, DACx, temperature sensor and VREFBUF buffer can consume power during Stop 2 mode, unless they are disabled before entering this mode.

All the peripherals which cannot be enabled in Stop 2 mode must be either disabled by clearing the Enable bit in the peripheral itself, or put under reset state by setting the corresponding bit in the AHB1 peripheral reset register (RCC_AHB1RSTR) , AHB2 peripheral reset register (RCC_AHB2RSTR) , AHB3 peripheral reset register (RCC_AHB3RSTR) , APB1 peripheral reset register 1 (RCC_APB1RSTR1) , APB1 peripheral reset register 2 (RCC_APB1RSTR2) , APB2 peripheral reset register (RCC_APB2RSTR) .

Exiting Stop 2 mode

The Stop 2 mode is exit according Section : Exiting low-power mode .

Refer to Table 33: Stop 2 mode for details on how to exit Stop 2 mode.

When exiting Stop 2 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is selected as system clock if the bit STOPWUCK is set in Clock configuration register (RCC_CFGR) . The MSI oscillator is selected as system clock if the bit STOPWUCK is cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The MSI selection allows wakeup at higher frequency, up to 48 MHz.

When exiting the Stop 2 mode, the MCU is in Run mode (Range 1 or Range 2 depending on VOS bit in PWR_CR1).

Table 33. Stop 2 mode

5.3.9 Standby mode

The Standby mode allows to achieve the lowest power consumption with BOR. It is based on the Cortex®-M4 DeepSleep mode, with the voltage regulators disabled (except when

SRAM2 content is preserved). The PLL, the HSI16, the MSI and the HSE oscillators are also switched off.

SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry (see Figure 9 ). SRAM2 content can be partially (only for STM32L4P5xx and STM32L4Q5xx) or fully preserved depending on RRS[1:0] bits configuration in PWR_CR3 register. In this case the Low-power regulator is ON and provides the supply to SRAM2 only.

The BOR is always available in Standby mode. The consumption is increased when thresholds higher than \( V_{BOR0} \) are used.

I/O states in Standby mode

In the Standby mode, the IO's are by default in floating state. If the APC bit of PWR_CR3 register has been set, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx registers ( \( x=A,B,C,D,E,F,G,H \) )), or with a pull-down (refer to PWR_PDCRx registers ( \( x=A,B,C,D,E,F,G,H \) )), or can be kept in analog state if none of the PWR_PUCRx or PWR_PDCRx register has been set. The pull-down configuration has highest priority over pull-up configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same IO.

Some I/Os (listed in Section 8.3.1: General-purpose I/O (GPIO) ) are used for JTAG/SW debug and can only be configured to their respective reset pull-up or pull-down state during Standby mode setting their respective bit in the PWR_PUCRx or PWR_PDCRx registers to '1', or will be configured to floating state if the bit is kept at '0'.

The RTC outputs on PC13 are functional in Standby mode. PC14 and PC15 used for LSE are also functional. 5 wakeup pins (WKUPx, \( x=1,2...5 \) ) and the 3 RTC tampers are available.

Entering Standby mode

The Standby mode is entered according Section : Entering low-power mode , when the SLEEPDEEP bit in the Cortex ^® -M4 System Control register is set.

Refer to Table 34: Standby mode for details on how to enter Standby mode.

In Standby mode, the following features can be selected by programming individual control bits:

• • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See Section 44.3: IWDG functional description in Section 44: Independent watchdog (IWDG) .
• • real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR)
• • Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status register (RCC_CSR).
• • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR)

Exiting Standby mode

The Standby mode is exited according Section : Entering low-power mode . The SBF status flag in the Power control register 3 (PWR_CR3) indicates that the MCU was in Standby mode. All registers are reset after wakeup from Standby except for Power control register 3 (PWR_CR3) .

Refer to Table 34: Standby mode for more details on how to exit Standby mode.

When exiting Standby mode, I/O's that were configured with pull-up or pull-down during Standby through registers PWR_PUCRx or PWR_PDCRx will keep this configuration upon exiting Standby mode until the bit APC of PWR_CR3 register has been cleared. Once the bit APC is cleared, they will be either configured to their reset values or to the pull-up/pull-down state according the GPIOx_PUPDR registers. The content of the PWR_PUCRx or PWR_PDCRx registers however is not lost and can be re-used for a sub-sequent entering into Standby mode.

Some I/Os (listed in Section 8.3.1: General-purpose I/O (GPIO) ) are used for JTAG/SW debug and have internal pull-up or pull-down activated after reset so will be configured at this reset value as well when exiting Standby mode.

For IO's, with a pull-up or pull-down pre-defined after reset (some JTAG/SW IO's) or with GPIOx_PUPDR programming done after exiting from Standby, in case those programming is different from the PWR_PUCRx or PWR_PDCRx programmed value during Standby, both a pull-down and pull-up will be applied until the bit APC is cleared, releasing the PWR_PUCRx or PWR_PDCRx programmed value.

Table 34. Standby mode

5.3.10 Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. It is based on the DeepSleep mode, with the voltage regulator disabled. The V _CORE domain is consequently powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off.

SRAM1, SRAM2, SRAM3 and register contents are lost except for registers in the Backup domain. The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.

I/O states in Shutdown mode

In the Shutdown mode, I/Os are by default in floating state. If the APC bit of PWR_CR3 register has been set, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx registers (x=A,B,C,D,E,F,G,H), or with a pull-down (refer to PWR_PDCRx registers (x=A,B,C,D,E,F,G,H)), or can be kept in analog state if none of the PWR_PUCRx or PWR_PDCRx register has been set. The pull-down configuration has highest priority over pull-up configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same IO. However this configuration is lost when exiting the Shutdown mode due to the power-on reset.

Some I/Os (listed in Section 8.3.1: General-purpose I/O (GPIO) ) are used for JTAG/SW debug and can only be configured to their respective reset pull-up or pull-down state during Standby mode setting their respective bit in the PWR_PUCRx or PWR_PDCRx registers to '1', or will be configured to floating state if the bit is kept at '0'.

The RTC outputs on PC13 are functional in Shutdown mode. PC14 and PC15 used for LSE are also functional. 5 wakeup pins (WKUPx, x=1,2...5) and the 3 RTC tampers are available.

Entering Shutdown mode

The Shutdown mode is entered according to Entering low-power mode , when the SLEEPDEEP bit in the Cortex ^® -M4 System Control register is set.

Refer to Table 35: Shutdown mode for details on how to enter Shutdown mode.

In Shutdown mode, the following features can be selected by programming individual control bits:

• • real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR). Caution: in case of VDD power-down the RTC content will be lost.
• • external 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR)

Exiting Shutdown mode

The Shutdown mode is exited according to Section : Exiting low-power mode . A power-on reset occurs when exiting from Shutdown mode. All registers (except for the ones in the Backup domain) are reset after wakeup from Shutdown.

Refer to Table 35: Shutdown mode for more details on how to exit Shutdown mode.

When exiting Shutdown mode, I/Os that were configured with pull-up or pull-down during Shutdown through registers PWR_PUCRx or PWR_PDCRx will lose their configuration and

will be configured in floating state or to their pull-up pull-down reset value (for some I/Os listed in Section 8.3.1: General-purpose I/O (GPIO) ).

Table 35. Shutdown mode

5.3.11 Auto-wakeup from low-power mode

The RTC can be used to wakeup the MCU from low-power mode without depending on an external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for waking up from Stop (0, 1 or 2) or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR) :

• • Low-power 32.768 kHz external crystal oscillator (LSE OSC)
  This clock source provides a precise time base with very low-power consumption.
• • Low-power internal RC Oscillator (LSI)
  This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC Oscillator is designed to add minimum power consumption.

To wakeup from Stop mode with an RTC alarm event (or RTC SSRU event which is only available on STM32L4P5xx and STM32L4Q5xx devices), it is necessary to:

• • Configure the EXTI Line 18 to be sensitive to rising edge
• • Configure the RTC to generate the RTC alarm

To wakeup from Standby mode, there is no need to configure the EXTI Line 18.

To wakeup from Stop mode with an RTC wakeup event, it is necessary to:

• • Configure the EXTI Line 20 to be sensitive to rising edge
• • Configure the RTC to generate the RTC alarm

To wakeup from Standby mode, there is no need to configure the EXTI Line 20.

5.4 PWR registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

5.4.1 Power control register 1 (PWR_CR1)

Address offset: 0x00

Reset value: 0x0000 0200 (This register is reset after wakeup from Standby mode)

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 LPR : Low-power run

When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR).

Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead.

Bits 13:11 Reserved, must be kept at reset value.

Bits 10:9 VOS : Voltage scaling range selection

• 00: Cannot be written (forbidden by hardware)
• 01: Range 1
• 10: Range 2
• 11: Cannot be written (forbidden by hardware)

Bit 8 DBP : Disable backup domain write protection

In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers.

• 0: Access to RTC and Backup registers disabled
• 1: Access to RTC and Backup registers enabled

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 RRSTP : SRAM3 retention in Stop 2 mode

0: SRAM3 is powered off in Stop 2 mode (SRAM3 content is lost)

1: SRAM3 is powered in Stop 2 mode (RAM3 content is kept).

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 LPMS[2:0] : Low-power mode selection

These bits select the low-power mode entered when CPU enters the Deepsleep mode.

000: Stop 0 mode

001: Stop 1 mode

010: Stop 2 mode

011: Standby mode

1xx: Shutdown mode

Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered instead of Stop 2.

In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3.

5.4.2 Power control register 2 (PWR_CR2)

Address offset: 0x04

Reset value: 0x0000 0000 (This register is reset when exiting the Standby mode)

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 USV : V _DDUSB USB supply valid

This bit is used to validate the V _DDUSB supply for electrical and logical isolation purpose.

Setting this bit is mandatory to use the USB OTG_FS peripheral. If V _DDUSB is not always present in the application, the PVM can be used to determine whether this supply is ready or not.

0: V _DDUSB is not present. Logical and electrical isolation is applied to ignore this supply.

1: V _DDUSB is valid.

Bit 9 IOSV : V _DDIO2 Independent I/Os supply valid

This bit is used to validate the V _DDIO2 supply for electrical and logical isolation purpose.

Setting this bit is mandatory to use PG[15:2]. If V _DDIO2 is not always present in the application, the PVM can be used to determine whether this supply is ready or not.

0: V _DDIO2 is not present. Logical and electrical isolation is applied to ignore this supply.

1: V _DDIO2 is valid.

Bit 8 Reserved, must be kept at reset value.

Bit 7 PVME4 : Peripheral voltage monitoring 4 enable: V _DDA vs. 2.2V

0: PWM4 (V _DDA monitoring vs. 2.2V threshold) disable.

1: PWM4 (V _DDA monitoring vs. 2.2V threshold) enable.

Bit 6 PVME3 : Peripheral voltage monitoring 3 enable: \( V_{DDA} \) vs. 1.62V

0: PVM3 ( \( V_{DDA} \) monitoring vs. 1.62V threshold) disable.

1: PVM3 ( \( V_{DDA} \) monitoring vs. 1.62V threshold) enable.

Bit 5 PVME2 : Peripheral voltage monitoring 2 enable: \( V_{DDIO2} \) vs. 0.9V

0: PVM2 ( \( V_{DDIO2} \) monitoring vs. 0.9V threshold) disable.

1: PVM2 ( \( V_{DDIO2} \) monitoring vs. 0.9V threshold) enable.

Bit 4 PVME1 : Peripheral voltage monitoring 1 enable: \( V_{DDUSB} \) vs. 1.2V

0: PVM1 ( \( V_{DDUSB} \) monitoring vs. 1.2V threshold) disable.

1: PVM1 ( \( V_{DDUSB} \) monitoring vs. 1.2V threshold) enable.

Bits 3:1 PLS[2:0] : Power voltage detector level selection.

These bits select the voltage threshold detected by the power voltage detector:

000: \( V_{PVD0} \) around 2.0 V

001: \( V_{PVD1} \) around 2.2 V

010: \( V_{PVD2} \) around 2.4 V

011: \( V_{PVD3} \) around 2.5 V

100: \( V_{PVD4} \) around 2.6 V

101: \( V_{PVD5} \) around 2.8 V

110: \( V_{PVD6} \) around 2.9 V

111: External input analog voltage \( PVD\_IN \) (compared internally to \( VREFINT \) )

Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register.

These bits are reset only by a system reset.

Bit 0 PVDE : Power voltage detector enable

0: Power voltage detector disable.

1: Power voltage detector enable.

Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register.

This bit is reset only by a system reset.

5.4.3 Power control register 3 (PWR_CR3)

Address offset: 0x08

Reset value: 0x0000 8000 (This register is not reset when exiting Standby modes and with the PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 EIWUL : Enable internal wakeup line

0: Internal wakeup line disable.

1: Internal wakeup line enable.

Bits 14:13 Reserved, must be kept at reset value.

Bit 12 DSIPDEN : Enable Pull-down activation on DSI pins

1: Pull-Down is enabled on DSI pins.

0: Pull-Down is disabled on DSI pins.

Bit 11 ENULP : Enable ULP sampling

When this bit is set, the BORL, BORH and PVD are periodically sampled instead continuous monitoring to reduce power consumption. Fast supply drop between two sample/compare phases is not detected in this mode. This bit has impact only on STOP2, Standby and shutdown low power modes.

Note: Available on STM32L4P5xx and STM32L4Q5xx only.

Bit 10 APC : Apply pull-up and pull-down configuration

When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os, instead the I/Os will be in floating mode during Standby or configured according GPIO controller GPIOx_PUPDR register during Run mode.

Bit 9:8 RRS[1:0] : SRAM2 retention in Standby mode

For STM32L4Rxxx and STM32L4Sxxx devices bit 9 is reserved

0: SRAM2 is powered off in Standby mode (SRAM2 content is lost).

1: SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept).

For STM32L4P5xx and STM32L4Q5xx devices:

00: SRAM2 is powered off in Standby mode (SRAM2 content is lost).

01: Full SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 full content is kept).

10: Only 4 Kbytes of SRAM2 is powered by the low-power regulator in Standby mode (4 Kbytes of SRAM2 content is kept)

11: reserved.

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 EWUP5 : Enable Wakeup pin WKUP5

When this bit is set, the external wakeup pin WKUP5 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP5 bit in the PWR_CR4 register.

Bit 3 EWUP4 : Enable Wakeup pin WKUP4

When this bit is set, the external wakeup pin WKUP4 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register.

Bit 2 EWUP3 : Enable Wakeup pin WKUP3

When this bit is set, the external wakeup pin WKUP3 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register.

Bit 1 EWUP2 : Enable Wakeup pin WKUP2

When this bit is set, the external wakeup pin WKUP2 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register.

Bit 0 EWUP1 : Enable Wakeup pin WKUP1

When this bit is set, the external wakeup pin WKUP1 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register.

5.4.4 Power control register 4 (PWR_CR4)

Address offset: 0x0C

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with the PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 EXT_SMPS_ON : external SMPS on.

This bit informs the internal regulator about external SMPS switch status to decrease regulator output to 0.95 V in Range 2, allowing the external SMPS output down to 1.00 V.

0: the external SMPS switch is open.

1: the external SMPS switch is closed, internal regulator output is set to 0.95 V.

Note: This bit is only available on STM32L4P5xx and STM32L4Q5xx devices.

Bits 12:10 Reserved, must be kept at reset value.

Bit 9 VBR : V _BAT battery charging resistor selection

0: Charge V _BAT through a 5 kOhms resistor

1: Charge V _BAT through a 1.5 kOhms resistor

Bit 8 VBE : V _BAT battery charging enable

0: V _BAT battery charging disable

1: V _BAT battery charging enable

Bits 7:5 Reserved, must be kept at reset value.

This bit defines the polarity used for an event detection on external wake-up pin, WKUP5

0: Detection on high level (rising edge)

1: Detection on low level (falling edge)

This bit defines the polarity used for an event detection on external wake-up pin, WKUP4

0: Detection on high level (rising edge)

1: Detection on low level (falling edge)

This bit defines the polarity used for an event detection on external wake-up pin, WKUP3

0: Detection on high level (rising edge)

1: Detection on low level (falling edge)

This bit defines the polarity used for an event detection on external wake-up pin, WKUP2

0: Detection on high level (rising edge)

1: Detection on low level (falling edge)

This bit defines the polarity used for an event detection on external wake-up pin, WKUP1

0: Detection on high level (rising edge)

1: Detection on low level (falling edge)

5.4.5 Power status register 1 (PWR_SR1)

Address offset: 0x10

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with the PWRRST bit in the RCC_APB1RSTR1 register)

Access: 2 additional APB cycles are needed to read this register vs. a standard APB read.

Bits 31:16 Reserved, must be kept at reset value.

This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared.

Bit 14 Reserved, must be kept at reset value.

Bit 13 EXT_SMPS_RDY : External SMPS ready

This bit informs the state of regulator transition from Range 1 to Range 2

0: Internal regulator not ready in Range 2, the external SMPS cannot be connected

1: Internal regulator ready in Range 2, the external SMPS can be connected

Note: This bit is only available on STM32L4P5xx and STM32L4Q5xx devices.

Bits 12:9 Reserved, must be kept at reset value.

Bit 8 SBF : Standby flag

This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset.

0: The device did not enter the Standby mode

1: The device entered the Standby mode

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 WUF5 : Wakeup flag 5

This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by writing '1' in the CWUF5 bit of the PWR_SCR register.

Bit 3 WUF4 : Wakeup flag 4

This bit is set when a wakeup event is detected on wakeup pin, WKUP4. It is cleared by writing '1' in the CWUF4 bit of the PWR_SCR register.

Bit 2 WUF3 : Wakeup flag 3

This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by writing '1' in the CWUF3 bit of the PWR_SCR register.

Bit 1 WUF2 : Wakeup flag 2

This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by writing '1' in the CWUF2 bit of the PWR_SCR register.

Bit 0 WUF1 : Wakeup flag 1

This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by writing '1' in the CWUF1 bit of the PWR_SCR register.

5.4.6 Power status register 2 (PWR_SR2)

Address offset: 0x14

Reset value: 0x0000 0000 (This register is partially reset when exiting Standby/Shutdown modes)

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 PVMO4 : Peripheral voltage monitoring output: \( V_{DDA} \) vs. 2.2 V

0: \( V_{DDA} \) voltage is above PWM4 threshold (around 2.2 V).

1: \( V_{DDA} \) voltage is below PWM4 threshold (around 2.2 V).

Note: PVMO4 is cleared when PWM4 is disabled (PVME4 = 0). After enabling PWM4, the PWM4 output is valid after the PWM4 wakeup time.

Bit 14 PVMO3 : Peripheral voltage monitoring output: \( V_{DDA} \) vs. 1.62 V

0: \( V_{DDA} \) voltage is above PWM3 threshold (around 1.62 V).

1: \( V_{DDA} \) voltage is below PWM3 threshold (around 1.62 V).

Note: PVMO3 is cleared when PWM3 is disabled (PVME3 = 0). After enabling PWM3, the PWM3 output is valid after the PWM3 wakeup time.

Bit 13 PVMO2 : Peripheral voltage monitoring output: \( V_{DDIO2} \) vs. 0.9 V

0: \( V_{DDIO2} \) voltage is above PWM2 threshold (around 0.9 V).

1: \( V_{DDIO2} \) voltage is below PWM2 threshold (around 0.9 V).

Note: PVMO2 is cleared when PWM2 is disabled (PVME2 = 0). After enabling PWM2, the PWM2 output is valid after the PWM2 wakeup time.

Bit 12 PVMO1 : Peripheral voltage monitoring output: \( V_{DDUSB} \) vs. 1.2 V

0: \( V_{DDUSB} \) voltage is above PWM1 threshold (around 1.2 V).

1: \( V_{DDUSB} \) voltage is below PWM1 threshold (around 1.2 V).

Note: PVMO1 is cleared when PWM1 is disabled (PVME1 = 0). After enabling PWM1, the PWM1 output is valid after the PWM1 wakeup time.

Bit 11 PVDO : Power voltage detector output

0: \( V_{DD} \) is above the selected PVD threshold

1: \( V_{DD} \) is below the selected PVD threshold

Bit 10 VOSF : Voltage scaling flag

A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register.

0: The regulator is ready in the selected voltage range

1: The regulator output voltage is changing to the required voltage level

Bit 9 REGLPF : Low-power regulator flag

This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency.

This bit is cleared by hardware when the regulator is ready.

0: The regulator is ready in main mode (MR)

1: The regulator is in low-power mode (LPR)

Bit 8 REGLPS : Low-power regulator started

This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wakeup from Standby mode time may be increased.

0: The low-power regulator is not ready

1: The low-power regulator is ready

Bits 7:0 Reserved, must be kept at reset value.

5.4.7 Power status clear register (PWR_SCR)

Address offset: 0x18

Reset value: 0x0000 0000

Access: 3 additional APB cycles are needed to write this register vs. a standard APB write.

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 CSBF : Clear standby flag
Setting this bit clears the SBF flag in the PWR_SR1 register.

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 CWUF5 : Clear wakeup flag 5
Setting this bit clears the WUF5 flag in the PWR_SR1 register.

Bit 3 CWUF4 : Clear wakeup flag 4
Setting this bit clears the WUF4 flag in the PWR_SR1 register.

Bit 2 CWUF3 : Clear wakeup flag 3
Setting this bit clears the WUF3 flag in the PWR_SR1 register.

Bit 1 CWUF2 : Clear wakeup flag 2
Setting this bit clears the WUF2 flag in the PWR_SR1 register.

Bit 0 CWUF1 : Clear wakeup flag 1
Setting this bit clears the WUF1 flag in the PWR_SR1 register.

5.4.8 Power Port A pull-up control register (PWR_PUCRA)

Address offset: 0x20.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 PU15 : Port A pull-up bit 15

When set, this bit activates the pull-up on PA[15] when APC bit is set in PWR_CR3 register.
If the corresponding PD15 bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.

Bit 14 Reserved, must be kept at reset value.

Bits 13:0 PUy : Port A pull-up bit y (y=0...13)

When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

5.4.9 Power Port A pull-down control register (PWR_PDCRA)

Address offset: 0x24.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 PD14 : Port A pull-down bit 14

When set, this bit activates the pull-down on PA[14] when APC bit is set in PWR_CR3 register.

Bit 13 Reserved, must be kept at reset value.

Bits 12:0 PDy : Port A pull-down bit y (y=0..12)

When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.

5.4.10 Power Port B pull-up control register (PWR_PUCRB)

Address offset: 0x28.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port B pull-up bit y (y=0..15)

When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

5.4.11 Power Port B pull-down control register (PWR_PDCRB)

Address offset: 0x2C.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:5 PDy : Port B pull-down bit y (y=5..15)

When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.

Bit 4 Reserved, must be kept at reset value.

Bits 3:0 PDy : Port B pull-down bit y (y=0..3)

When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.

5.4.12 Power Port C pull-up control register (PWR_PUCRC)

Address offset: 0x30.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port C pull-up bit y (y=0..15)

When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register.

The pull-up is not activated if the corresponding PDy bit is also set.

5.4.13 Power Port C pull-down control register (PWR_PDCRC)

Address offset: 0x34.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port C pull-down bit y (y=0..15)

When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.

5.4.14 Power Port D pull-up control register (PWR_PUCRD)

Address offset: 0x38.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port D pull-up bit y (y=0..15)

When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register.

The pull-up is not activated if the corresponding PDy bit is also set.

5.4.15 Power Port D pull-down control register (PWR_PDCRD)

Address offset: 0x3C.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port D pull-down bit y (y=0..15)

When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.

5.4.16 Power Port E pull-up control register (PWR_PUCRE)

Address offset: 0x20.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port E pull-up bit y (y=0..15)

When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register.

The pull-up is not activated if the corresponding PDy bit is also set.

5.4.17 Power Port E pull-down control register (PWR_PDCRE)

Address offset: 0x44.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port E pull-down bit y (y=0..15)

When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.

5.4.18 Power Port F pull-up control register (PWR_PUCRF)

Address offset: 0x48.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port F pull-up bit y (y=0..15)

When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register.

The pull-up is not activated if the corresponding PDy bit is also set.

5.4.19 Power Port F pull-down control register (PWR_PDCRF)

Address offset: 0x4C.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port F pull-down bit y (y=0..15)

When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.

5.4.20 Power Port G pull-up control register (PWR_PUCRG)

Address offset: 0x50.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port G pull-up bit y (y=0..15)

When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register.

The pull-up is not activated if the corresponding PDy bit is also set.

5.4.21 Power Port G pull-down control register (PWR_PDCRG)

Address offset: 0x54.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port G pull-down bit y (y=0..15)

When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.

5.4.22 Power Port H pull-up control register (PWR_PUCRH)

Address offset: 0x58.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port H pull-up bit y (y=0..15)

When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

5.4.23 Power Port H pull-down control register (PWR_PDCRH)

Address offset: 0x5C.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port H pull-down bit x (y =15..0)

When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register.

5.4.24 Power Port I pull-up control register (PWR_PUCRI)

Address offset: 0x60.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 11:0 PUy : Port I pull-up bit y (y=0..11)

When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register.

The pull-up is not activated if the corresponding PDy bit is also set.

5.4.25 Power Port I pull-down control register (PWR_PDCRI)

Address offset: 0x64.

Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 11:0 PDy : Port I pull-down bit y (y=0..11)

When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register.

5.4.26 PWR control register (PWR_CR5)

Address offset: 0x80.

Reset value: 0x0000 0100 (This register is not reset after a wakeup from Standby mode)

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 R1MODE : Main regulator Range 1 mode

This bit is only valid for the main regulator in Range 1 and has no effect on Range 2. It is recommended to reset this bit when the system frequency is greater than 80 MHz. Refer to Table 24: Range 1 boost mode configuration .

0: Main regulator in Range 1 boost mode.

1: Main regulator in Range 1 normal mode.

Bits 7:0 Reserved, must be kept at reset value.

5.4.27 PWR register map and reset value table

Table 36. PWR register map and reset values

Table 36. PWR register map and reset values (continued)

1. The availability of this bit/bitfield depends on product part numbers. For additional information refer to Section 1.4: Availability of peripherals .

Refer to Section 2.2 on page 93 for the register boundary addresses.