2. System and memory overview

2.1 System architecture

The main system consists of 32-bit multilayer AHB bus matrix that interconnects:

• • Up to nine masters:
  • – Cortex ^® -M4 with FPU core I-bus
  • – Cortex ^® -M4 with FPU core D-bus
  • – Cortex ^® -M4 with FPU core S-bus
  • – DMA1
  • – DMA2
  • – DMA2D (Chrom-Art Accelerator ^™ ) memory bus
  • – LCD-TFT controller DMA-bus
  • – SDMMC1 bus
  • – SDMMC2 bus
    (only for STM32L4P5xx and STM32L4Q5xx devices)
  • – GFXMMU (Chrom-GRC ^™ ) bus
    (only for STM32L4Sxxx and STM32L4R5xxx devices)
• • Up to eleven slaves:
  • – Internal Flash memory on the I-Code bus
  • – Internal Flash memory on D-Code bus
  • – Internal SRAM1
    (192 Kbytes for STM32L4Rxxx and STM32Sxxx devices and
    128 Kbytes for STM32L4P5xx and STM32Q5xx devices)
  • – Internal SRAM2 (64 Kbytes)
  • – Internal SRAM3
    (384 Kbytes for STM32L4Rxxx and STM32L4Sxxx devices and
    128 Kbytes for STM32L4P5xx and STM32L4Q5xx devices)
  • – GFXMMU (Chrom-GRC ^™ )
    (only for STM32L4Rxxx and STM32L4Sxxx devices)
  • – AHB1 peripherals including AHB to APB bridges and APB peripherals (connected to APB1 and APB2)
  • – AHB2 peripherals
  • – Flexible memory controller (FMC)
  • – OCTOSPI1
  • – OCTOSPI2

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. This architecture is shown in Figure 1 :

Figure 1. System architecture for STM32L4Rxxx and STM32L4Sxxx

Figure 2. System architecture for STM32L4P5xx and STM32L4Q5xx

2.1.1 I-bus

This bus connects the instruction bus of the Cortex®-M4 core to the BusMatrix. This bus is used by the core to fetch instructions. The target of this bus is a memory containing code (either internal Flash memory, internal SRAM or external memories through the FMC or OCTOSPIs).

2.1.2 D-bus

This bus connects the data bus of the Cortex®-M4 core to the BusMatrix. This bus is used by the core for literal load and debug access. The target of this bus is a memory containing code (either internal Flash memory, internal SRAM or external memories through the FMC or OCTOSPIs).

2.1.3 S-bus

This bus connects the system bus of the Cortex®-M4 core to the BusMatrix. This bus is used by the core to access data located in a peripheral or SRAM area. The targets of this bus are the internal SRAM, the AHB1 peripherals including the APB1 and APB2

peripherals, the AHB2 peripherals and the external memories through the OCTOSPI or the FMC.

The SRAM2 is also accessible on this bus to allow continuous mapping with SRAM1 and SRAM3.

2.1.4 DMA-bus

This bus connects the AHB master interface of the DMA to the BusMatrix. The targets of this bus are the SRAM1, SRAM2 and SRAM3, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the external memories through the OCTOSPI or the FMC.

2.1.5 DMA2D-bus

This bus connects the AHB master interface of the DMA2D to the BusMatrix. The targets of this bus are the SRAM1, SRAM2 and SRAM3 and external memories through the OCTOSPI or the FMC.

2.1.6 LCD-TFT controller DMA bus

This bus connects the LCD controller DMA master interface to the BusMatrix. The targets of this bus are data memories: internal SRAMs (SRAM1, SRAM2, SRAM3), internal Flash memory or external memories through FMC or OCTOSPI.

2.1.7 SDMMC1 controller DMA bus

This bus connects the SDMMC1 DMA master interface to the BusMatrix. This bus is used only by the SDMMC1 DMA to load/store data from/to memory. The targets of this bus are data memories: internal SRAMs (SRAM1, SRAM2, SRAM3), internal Flash memory or external memories through FMC or OCTOSPI.

2.1.8 SDMMC2 controller DMA bus (only for STM32L4P5xx and STM32L4Q5xx devices)

This bus connects the SDMMC2 DMA master interface to the BusMatrix. This bus is used only by the SDMMC2 DMA to load/store data from/to memory. The targets of this bus are data memories: internal SRAMs (SRAM1, SRAM2, SRAM3), internal Flash memory or external memories through FMC or OCTOSPI.

2.1.9 GFXMMU-bus (only for STM32L4Rxxx and STM32L4Sxxx devices)

This bus connects the GFXMMU (Chrom-GRC™) AHB master interface to the BusMatrix. The targets of this bus are data memories: internal SRAMs (SRAM1, SRAM2, SRAM3), internal Flash memory or external memories through FMC or OCTOSPI.

2.1.10 BusMatrix

The BusMatrix manages the access arbitration between masters. The arbitration uses a Round Robin algorithm.

For STM32L4Rxxx and STM32L4Sxxx devices, the BusMatrix is composed of

• • up to nine masters:
  • – CPU AHB system bus, D-Code bus, I-Code bus, DMA1, DMA2, DMA2D, SDMMC1, LCD-TFT and GFXMMU
• • up to eleven slaves:
  • – FLASH, SRAM1, SRAM2, SRAM3, AHB1 (including APB1 and APB2), AHB2, GFXMMU, OCTOSTPI1, OCTOSPI2 and FMC

For STM32L4P5xx and STM32Q5xx devices, the BusMatrix is composed of:

• • nine masters:
  • – CPU AHB system bus, D-Code bus, I-Code bus, DMA1, DMA2, DMA2D, SDMMC1, SDMMC2 and LCD-TFT
• • ten slaves:
  • – FLASH, SRAM1, SRAM2, SRAM3, AHB1 (including APB1 and APB2), AHB2, OCTOSTPI1, OCTOSPI2 and FMC.

AHB/APB bridges

The two AHB/APB bridges provide full synchronous connections between the AHB and the two APB buses, allowing flexible selection of the peripheral frequency.

Refer to Section 2.2.2: Memory map and register boundary addresses on page 94 for the address mapping of the peripherals connected to this bridge.

After each device reset, all peripheral clocks are disabled (except for the SRAM1/2 and Flash memory interface). Before using a peripheral you have to enable its clock in the RCC_AHBxENR and the RCC_APBxENR registers.

Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

2.2 Memory organization

2.2.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

The addressable memory space is divided into eight main blocks, of 512 Mbytes each.

2.2.2 Memory map and register boundary addresses

Figure 3. Memory map for STM32L4Rxxx and STM32L4Sxxx

Figure 4. Memory map for STM32L4P5xx and STM32L4Q5xx

All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved” (highlighted in gray). For the detailed mapping of available memory and register areas, refer to the following tables.

The following tables give the boundary addresses of the peripherals available in the devices.

Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary addresses

Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary addresses (continued)

Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary addresses (continued)

Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary addresses (continued)

Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary addresses (continued)

Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary addresses (continued)

2.3 Bit banding

The Cortex ^® -M4 with FPU memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.

In the STM32L4+ Series devices both the peripheral registers and the SRAM1 are mapped to a bit-band region, so that single bit-band write and read operations are allowed. The operations are only available for Cortex ^® -M4 with FPU accesses, and not from other bus masters (such as DMA).

A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is:

where:

• – bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit
• – bit_band_base is the starting address of the alias region
• – byte_offset is the number of the byte in the bit-band region that contains the targeted bit
• – bit_number is the bit position (0-7) of the targeted bit

Example

The following example shows how to map bit 2 of the byte located at SRAM1 address 0x20000300 to the alias region:

Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit 2 of the byte at SRAM1 address 0x20000300.

Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM1 address 0x20000300 (0x01: bit set; 0x00: bit reset).

For more information on bit-banding, refer to the Cortex®-M4 programming manual (see Related documents on page 1 ).

2.4 Embedded SRAM

The STM32L4Rxxx and STM32L4Sxxx devices feature up to 640 Kbytes SRAM:

• • 192 Kbytes SRAM1
• • 64 Kbytes SRAM2
• • 384 Kbytes SRAM3

The STM32L4P5xx and STM32L4Q5xx devices feature up to 320 Kbytes SRAM:

• • 128 Kbytes SRAM1
• • 64 Kbytes SRAM2
• • 128 Kbytes SRAM3

These SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). These memories can be addressed at maximum system clock frequency without wait state and thus by both CPU and DMA.

The CPU can access the SRAM1 through the system bus or through the ICode/DCode buses when boot from SRAM1 is selected or when physical remap is selected ( Section 9.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller). To get the maximum performance on SRAM1 execution, physical remap should be selected (boot or software selection).

Execution can be performed from SRAM2 with maximum performance without any remap thanks to access through ICode bus.

The SRAM2 is aliased at address 0x2003 0000 for STM32L4Rxxx and STM32L4Sxxx devices and at address 0x2002 0000 for STM32L4P5xx and STM32L4Q5xx devices,

offering a continuous address space with the SRAM1 and SRAM3.

2.4.1 SRAM2 parity check

The user can enable the SRAM2 parity check using the option bit SRAM2_PE in the user option byte (refer to Section 3.4.1: Option bytes description ).

The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in order to increase memory robustness, as required for instance by Class B or SIL norms.

The parity bits are computed and stored when writing into the SRAM2. Then, they are automatically checked when reading. If one bit fails, an NMI is generated. The same error can also be linked to the BRK_IN Break input of TIM1/TIM8/TIM15/TIM16/TIM17, with the SPL control bit in the SYSCFG configuration register 2 (SYSCFG_CFGR2) . The SRAM2 Parity Error flag (SPF) is available in the SYSCFG configuration register 2 (SYSCFG_CFGR2) .

Note: When enabling the RAM parity check, it is advised to initialize by software the whole RAM memory at the beginning of the code, to avoid getting parity errors when reading non-initialized locations.

2.4.2 SRAM2 Write protection

The SRAM2 can be write protected with a page granularity of 1 Kbyte.

Table 3. SRAM2 organization

Table 3. SRAM2 organization (continued)

The write protection can be enabled in SYSCFG SRAM2 write protection register (SYSCFG_SWPR) in the SYSCFG block. This is a register with write '1' once mechanism, which means by writing '1' on a bit it will setup the write protection for that page of SRAM and it can be removed/cleared by a system reset only.

2.4.3 SRAM2 Read protection

The SRAM2 is protected with the Read protection (RDP). Refer to Section 3.5.1: Read protection (RDP) for more details.

2.4.4 SRAM2 Erase

The SRAM2 can be erased with a system reset using the option bit SRAM2_RST in the user option byte (refer to Section 3.4.1: Option bytes description ).

The SRAM2 erase can also be requested by software by setting the bit SRAM2ER in the SYSCFG SRAM2 control and status register (SYSCFG_SCSR) .

2.5 Flash memory overview

The Flash memory is composed of two distinct physical areas:

• • The main Flash memory block. It contains the application program and user data if necessary.
• • The information block. It is composed of three parts:
  • – Option bytes for hardware and memory protection user configuration.
  • – System memory that contains the ST proprietary code.
  • – OTP (one-time programmable) area

The Flash interface implements instruction access and data access based on the AHB protocol. It also implements the logic necessary to carry out the Flash memory operations

(program/erase) controlled through the Flash registers Refer to Section 3: Embedded Flash memory (FLASH) for more details.

2.6 Boot configuration

2.6.1 Boot configuration

Three different boot modes can be selected through the BOOT0 pin or the nBOOT0 bit into the FLASH_OPTR register (if the nSWBOOT0 bit is cleared into the FLASH_OPTR register), and nBOOT1 bit in FLASH_OPTR register, as shown in the following table.

Table 4. Boot modes

1. 1. A Flash empty check mechanism is implemented to force the boot from system Flash if the first Flash memory location is not programmed (0xFFFF FFFF) and if the boot selection was configured to boot from the main Flash.

The values on both BOOT0 pin (coming from the pin or the option bit) and nBOOT1 bit are latched upon reset release. It is up to the user to set nBOOT1 and BOOT0 to select the required boot mode.

The BOOT0 pin or user option bit (depending on the nSWBOOT0 bit value in the FLASH_OPTR register), and nBOOT1 bit are also re-sampled when exiting from Standby mode. Consequently, they must be kept in the required Boot mode configuration in Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.

Depending on the selected boot mode, main Flash memory, system memory or SRAM1 is accessible as follows:

• • Boot from main Flash memory: the main Flash memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space

(0x0800 0000). In other words, the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000.

• • Boot from system memory: the system memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x1FFF 0000).
• • Boot from the embedded SRAM1: the SRAM1 is aliased in the boot memory space (0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).

PH3/BOOT0 GPIO is configured in:

• • Input mode during the complete reset phase if the option bit nSWBOOT0 is set into the FLASH_OPTR register and then switches automatically in analog mode after reset is released (BOOT0 pin).
• • Input mode from the reset phase to the completion of the option byte loading if the bit nSWBOOT0 is cleared into the FLASH_OPTR register (BOOT0 value coming from the option bit). It switches then automatically to the analog mode even if the reset phase is not complete.

Note: When the device boots from SRAM, in the application initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and the offset register. When booting from the main Flash memory, the application software can either boot from bank 1 or from bank 2. By default, boot from bank 1 is selected. To select boot from Flash memory bank 2, set the BFB2 bit in the user option bytes. When this bit is set and the boot pins are in the boot from main Flash memory configuration, the device boots from system memory, and the boot loader jumps to execute the user application programmed in Flash memory bank 2. For further details, please refer to AN2606.

Physical remap

Once the boot pins mode is selected, the application software can modify the memory accessible in the code area (in this way the code can be executed through the ICode bus in place of the System bus). This modification is performed by programming the SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller.

The following memories can thus be remapped:

• • Main Flash memory
• • System memory
• • Embedded SRAM1 (192 Kbytes for STM32L4Rxxx and STM32L4Sxxx devices and 128 Kbytes for STM32L4P5xx and STM32L4Q5xx devices)
• • FSMC bank 1 (NOR/PSRAM 1 and 2)
• • OctoSPI (OCTOSPI1 or OSCTOSPI2) memory

Table 5. Memory mapping versus boot mode/physical remap ⁽¹⁾

1. 1. Reserved areas highlighted in gray.
2. 2. When the FSMC is remapped at address 0x0000 0000, only the first two regions of bank 1 memory controller (bank 1 NOR/PSRAM 1 and NOR/PSRAM 2) can be remapped. When the OCTOSPI is remapped at address 0x0000 0000, only 128 Mbytes are remapped. In remap mode, the CPU can access the external memory via ICode bus instead of system bus, which boosts up the performance.
3. 3. Even when aliased in the boot memory space, the related memory is still accessible at its original memory space.
4. 4. 2 Mbytes for STM32L4Rxxx and STM32L4Sxxx devices and 1 Mbyte for STM32L4P5xx and STM32L4Q5xx devices.
5. 5. 192 Kbytes for STM32L4Rxxx and STM32L4Sxxx devices and 128 Kbytes for STM32L4P5xx and STM32L4Q5xx devices.

Embedded boot loader

The embedded boot loader is located in the system memory, programmed by ST during production. Refer to AN2606 STM32 microcontroller system memory boot mode.