RM0432-STM32L4+

This reference manual targets application developers. It provides complete information on how to use the STM32L4+ Series microcontrollers memory and peripherals.

The STM32L4+ Series is a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics, refer to the corresponding datasheets.

For information on the Arm ® Cortex ® -M4 core, refer to the Cortex ® -M4 Technical Reference Manual.

STM32L4+ Series microcontrollers include ST state-of-the-art patented technology.

Contents

3.1Introduction .....114
3.2FLASH main features .....114
3.3FLASH functional description .....115
3.3.1Flash memory organization .....115
3.3.2Error code correction (ECC) .....120
3.3.3Read access latency .....122
3.3.4Adaptive real-time memory accelerator (ART Accelerator) .....123
3.3.5Flash program and erase operations .....126
3.3.6Flash main memory erase sequences .....127
3.3.7Flash main memory programming sequences .....128
3.3.8Read-while-write (RWW) available only in Dual-bank mode .....132
3.4FLASH option bytes .....134
3.4.1Option bytes description .....134
3.4.2Option bytes programming .....141
3.5FLASH memory protection .....144
3.5.1Read protection (RDP) .....144
3.5.2Proprietary code readout protection (PCROP) .....147
3.5.3Write protection (WRP) .....149
3.6FLASH interrupts .....150
3.7FLASH registers .....151
3.7.1Flash access control register (FLASH_ACR) .....151
3.7.2Flash Power-down key register (FLASH_PDKEYR) .....152
3.7.3Flash key register (FLASH_KEYR) .....153
3.7.4Flash option key register (FLASH_OPTKEYR) .....153
3.7.5Flash status register (FLASH_SR) .....154
3.7.6Flash control register (FLASH_CR) .....156
3.7.7Flash ECC register (FLASH_ECCR) .....158
3.7.8Flash option register (FLASH_OPTR) .....160
3.7.9Flash PCROP1 Start address register (FLASH_PCROP1SR) .....162
3.7.10Flash PCROP1 End address register (FLASH_PCROP1ER) .....163
3.7.11Flash WRP1 area A address register (FLASH_WRP1AR) .....163
3.7.12Flash WRP2 area A address register (FLASH_WRP2AR) .....164
3.7.13Flash PCROP2 Start address register (FLASH_PCROP2SR) .....165
3.7.14Flash PCROP2 End address register (FLASH_PCROP2ER) .....165
3.7.15Flash WRP1 area B address register (FLASH_WRP1BR) .....166
3.7.16Flash WRP2 area B address register (FLASH_WRP2BR) .....166

3.7.17 Flash configuration register (FLASH_CFGR) . . . . . 167

3.7.18 FLASH register map . . . . . 168

4 Firewall (FW) . . . . . 170

4.1 Introduction . . . . . 170

4.2 Firewall main features . . . . . 170

4.3 Firewall functional description . . . . . 171

4.3.1 Firewall AMBA bus snoop . . . . . 171

4.3.2 Functional requirements . . . . . 171

4.3.3 Firewall segments . . . . . 172

4.3.4 Segment accesses and properties . . . . . 173

4.3.5 Firewall initialization . . . . . 174

4.3.6 Firewall states . . . . . 175

4.4 Firewall registers . . . . . 177

4.4.1 Code segment start address (FW_CSSA) . . . . . 177

4.4.2 Code segment length (FW_CSL) . . . . . 177

4.4.3 Non-volatile data segment start address (FW_NVDSSA) . . . . . 178

4.4.4 Non-volatile data segment length (FW_NVDLSL) . . . . . 178

4.4.5 Volatile data segment start address (FW_VDSSA) . . . . . 179

4.4.6 Volatile data segment length (FW_VDSL) . . . . . 179

4.4.7 Configuration register (FW_CR) . . . . . 180

4.4.8 Firewall register map . . . . . 182

5 Power control (PWR) . . . . . 183

5.1 Power supplies . . . . . 183

5.1.1 Independent analog peripherals supply . . . . . 185

5.1.2 Independent I/O supply rail . . . . . 186

5.1.3 Independent USB transceivers supply . . . . . 186

5.1.4 Independent DSI supply . . . . . 186

5.1.5 Battery backup domain . . . . . 187

5.1.6 Voltage regulator . . . . . 188

5.1.7 VDD12 domain . . . . . 189

5.1.8 Dynamic voltage scaling management . . . . . 190

5.2 Power supply supervisor . . . . . 193

5.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) . . . . . 193

5.2.2 Programmable voltage detector (PVD) . . . . . 194

5.2.3Peripheral Voltage Monitoring (PVM) .....195
5.3Low-power modes .....196
5.3.1Run mode .....204
5.3.2Low-power run mode (LP run) .....204
5.3.3Low-power modes .....205
5.3.4Sleep mode .....206
5.3.5Low-power sleep mode (LP sleep) .....207
5.3.6Stop 0 mode .....208
5.3.7Stop 1 mode .....210
5.3.8Stop 2 mode .....211
5.3.9Standby mode .....213
5.3.10Shutdown mode .....216
5.3.11Auto-wakeup from low-power mode .....217
5.4PWR registers .....218
5.4.1Power control register 1 (PWR_CR1) .....218
5.4.2Power control register 2 (PWR_CR2) .....219
5.4.3Power control register 3 (PWR_CR3) .....220
5.4.4Power control register 4 (PWR_CR4) .....222
5.4.5Power status register 1 (PWR_SR1) .....223
5.4.6Power status register 2 (PWR_SR2) .....224
5.4.7Power status clear register (PWR_SCR) .....225
5.4.8Power Port A pull-up control register (PWR_PUCRA) .....226
5.4.9Power Port A pull-down control register (PWR_PDCRA) .....227
5.4.10Power Port B pull-up control register (PWR_PUCRB) .....227
5.4.11Power Port B pull-down control register (PWR_PDCRB) .....228
5.4.12Power Port C pull-up control register (PWR_PUCRC) .....228
5.4.13Power Port C pull-down control register (PWR_PDCRC) .....229
5.4.14Power Port D pull-up control register (PWR_PUCRD) .....229
5.4.15Power Port D pull-down control register (PWR_PDCRD) .....230
5.4.16Power Port E pull-up control register (PWR_PUCRE) .....230
5.4.17Power Port E pull-down control register (PWR_PDCRE) .....231
5.4.18Power Port F pull-up control register (PWR_PUCRF) .....231
5.4.19Power Port F pull-down control register (PWR_PDCRF) .....232
5.4.20Power Port G pull-up control register (PWR_PUCRG) .....232
5.4.21Power Port G pull-down control register (PWR_PDCRG) .....233
5.4.22Power Port H pull-up control register (PWR_PUCRH) .....233
5.4.23Power Port H pull-down control register (PWR_PDCRH) .....234
6.4.6PLLSAI2 configuration register (RCC_PLLSAI2CFGR) . . . . .271
6.4.7Clock interrupt enable register (RCC_CIER) . . . . .273
6.4.8Clock interrupt flag register (RCC_CIFR) . . . . .275
6.4.9Clock interrupt clear register (RCC_CICR) . . . . .276
6.4.10AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .278
6.4.11AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .279
6.4.12AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . .281
6.4.13APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . .282
6.4.14APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . .284
6.4.15APB2 peripheral reset register (RCC_APB2RSTR) . . . . .285
6.4.16AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .287
6.4.17AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .288
6.4.18AHB3 peripheral clock enable register(RCC_AHB3ENR) . . . . .290
6.4.19APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . .291
6.4.20APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . .293
6.4.21APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .295
6.4.22AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR) . . . . .		296
6.4.23AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR) . . . . .		298
6.4.24AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR) . . . . .		300
6.4.25APB1 peripheral clocks enable in Sleep and Stop modes register 1
(RCC_APB1SMENR1) . . . . .		301
6.4.26APB1 peripheral clocks enable in Sleep and Stop modes register 2
(RCC_APB1SMENR2) . . . . .		304
6.4.27APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR) . . . . .		305
6.4.28Peripherals independent clock configuration register (RCC_CCIPR) .306
6.4.29Backup domain control register (RCC_BDCR) . . . . .309
6.4.30Control/status register (RCC_CSR) . . . . .311
6.4.31Clock recovery RC register (RCC_CRRRCR) . . . . .313
6.4.32Peripherals independent clock configuration register (RCC_CCIPR2)314
6.4.33OCTOSPI delay configuration register (RCC_DLYCFGR) . . . . .316
6.4.34RCC register map . . . . .317
7Clock recovery system (CRS) . . . . .322
7.1Introduction . . . . .322
7.2CRS main features . . . . .322
7.3CRS implementation . . . . .322
7.4CRS functional description . . . . .323
7.4.1CRS block diagram . . . . .323
7.4.2Synchronization input . . . . .323
7.4.3Frequency error measurement . . . . .324
7.4.4Frequency error evaluation and automatic trimming . . . . .325
7.4.5CRS initialization and configuration . . . . .325
7.5CRS low-power modes . . . . .326
7.6CRS interrupts . . . . .326
7.7CRS registers . . . . .327
7.7.1CRS control register (CRS_CR) . . . . .327
7.7.2CRS configuration register (CRS_CFGR) . . . . .328
7.7.3CRS interrupt and status register (CRS_ISR) . . . . .329
7.7.4CRS interrupt flag clear register (CRS_ICR) . . . . .331
7.7.5CRS register map . . . . .332
8General-purpose I/Os (GPIO) . . . . .333
8.1Introduction . . . . .333
8.2GPIO main features . . . . .333
8.3GPIO functional description . . . . .333
8.3.1General-purpose I/O (GPIO) . . . . .336
8.3.2I/O pin alternate function multiplexer and mapping . . . . .336
8.3.3I/O port control registers . . . . .337
8.3.4I/O port data registers . . . . .337
8.3.5I/O data bitwise handling . . . . .337
8.3.6GPIO locking mechanism . . . . .338
8.3.7I/O alternate function input/output . . . . .338
8.3.8External interrupt/wakeup lines . . . . .338
8.3.9Input configuration . . . . .339
8.3.10Output configuration . . . . .339
8.3.11Alternate function configuration . . . . .340
8.3.12Analog configuration . . . . .341
8.3.13Using the HSE or LSE oscillator pins as GPIOs . . . . .341
8.3.14Using the GPIO pins in the RTC supply domain . . . . .341
8.3.15Using PH3 as GPIO . . . . .342
8.4GPIO registers . . . . .342
8.4.1GPIO port mode register (GPIOx_MODER)
(x = A to I) .....		342
8.4.2GPIO port output type register (GPIOx_OTYPER)
(x = A to I) .....		343
8.4.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to I) .....		343
8.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to I) .....		344
8.4.5GPIO port input data register (GPIOx_IDR)
(x = A to I) .....		344
8.4.6GPIO port output data register (GPIOx_ODR)
(x = A to I) .....		345
8.4.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to I) .....		345
8.4.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to I) .....		345
8.4.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to I) .....		347
8.4.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to I) .....		347
8.4.11GPIO port bit reset register (GPIOx_BRR) (x = A to I) .....348
8.4.12GPIO register map .....349
9System configuration controller (SYSCFG) .....351
9.1SYSCFG main features .....351
9.2SYSCFG registers .....351
9.2.1SYSCFG memory remap register (SYSCFG_MEMRMP) .....351
9.2.2SYSCFG configuration register 1 (SYSCFG_CFGR1) .....352
9.2.3SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) .....		354
9.2.4SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) .....		356
9.2.5SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) .....		357
9.2.6SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) .....		359
9.2.7SYSCFG SRAM2 control and status register (SYSCFG_SCSR) .....360
9.2.8SYSCFG configuration register 2 (SYSCFG_CFGR2) .....361
9.2.9SYSCFG SRAM2 write protection register (SYSCFG_SWPR) .....362
9.2.10SYSCFG SRAM2 key register (SYSCFG_SKR) .....362
9.2.11SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2) .....363

9.2.12 SYSCFG register map . . . . . 364

10        Peripherals interconnect matrix . . . . . 366

10.1    Introduction . . . . . 366

10.2    Connection summary . . . . . 366

10.3    Interconnection details . . . . . 367

10.3.1    From timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15/TIM16/TIM17) to timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15) . . . . . 367

10.3.2    From timer (TIM1/TIM2/TIM3/TIM4/TIM6/TIM8/TIM15) and EXTI to ADC (ADC1) . . . . . 368

10.3.3    From ADC to timer (TIM1/TIM8) . . . . . 369

10.3.4    From timer (TIM2/TIM4/TIM5/TIM6/TIM7/TIM8/LPTIM1/LPTIM2) and EXTI to DAC (internal channel 1 and channel 2) . . . . . 369

10.3.5    From timer (TIM1/TIM3/TIM4/TIM6/TIM7/TIM8/TIM16/LPTIM1/LPTIM2) and EXTI to DFSDM1 . . . . . 369

10.3.6    From DFSDM1 to timer (TIM1/TIM8/TIM15/TIM16/TIM17) . . . . . 370

10.3.7    From HSE, LSE, LSI, MSI, MCO, RTC to timer (TIM2/TIM15/TIM16/TIM17) . . . . . 370

10.3.8    From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2) . . . . . 371

10.3.9    From timer (TIM1/TIM2/TIM3/TIM8/TIM15) to comparators (COMP1/COMP2) . . . . . 371

10.3.10    From ADC (ADC1) to ADC (ADC2) . . . . . 371

10.3.11    From USB to timer (TIM2) . . . . . 372

10.3.12    From internal analog source to ADC and OPAMP (OPAMP1/OPAMP2) . . . . . 372

10.3.13    From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17) . . . . . 373

10.3.14    From system errors to timers (TIM1/TIM8/TIM15/TIM16/TIM17) . . . . . 373

10.3.15    From timers (TIM16/TIM17) to IRTIM . . . . . 374

10.3.16    From ADC (ADC1/ADC2) to DFSDM . . . . . 374

11        Direct memory access controller (DMA) . . . . . 375

11.1    Introduction . . . . . 375

11.2    DMA main features . . . . . 375

11.3    DMA implementation . . . . . 376

11.3.1    DMA1 and DMA2 . . . . . 376

11.3.2    DMA request mapping . . . . . 376

11.4    DMA functional description . . . . . 376

11.4.1    DMA block diagram . . . . . 376

11.4.2DMA pins and internal signals . . . . .378
11.4.3DMA transfers . . . . .378
11.4.4DMA arbitration . . . . .379
11.4.5DMA channels . . . . .379
11.4.6DMA data width, alignment and endianness . . . . .383
11.4.7DMA error management . . . . .384
11.5DMA interrupts . . . . .385
11.6DMA registers . . . . .385
11.6.1DMA interrupt status register (DMA_ISR) . . . . .385
11.6.2DMA interrupt flag clear register (DMA_IFCR) . . . . .388
11.6.3DMA channel x configuration register (DMA_CCRx) . . . . .389
11.6.4DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . .392
11.6.5DMA channel x peripheral address register (DMA_CPARx) . . . . .392
11.6.6DMA channel x memory address register (DMA_CMARx) . . . . .393
11.6.7DMA register map . . . . .393
12DMA request multiplexer (DMAMUX) . . . . .396
12.1Introduction . . . . .396
12.2DMAMUX main features . . . . .397
12.3DMAMUX implementation . . . . .397
12.3.1DMAMUX instantiation . . . . .397
12.3.2DMAMUX mapping . . . . .397
12.4DMAMUX functional description . . . . .403
12.4.1DMAMUX block diagram . . . . .403
12.4.2DMAMUX signals . . . . .404
12.4.3DMAMUX channels . . . . .404
12.4.4DMAMUX request line multiplexer . . . . .404
12.4.5DMAMUX request generator . . . . .407
12.5DMAMUX interrupts . . . . .408
12.6DMAMUX registers . . . . .409
12.6.1DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR) . . . . .		409
12.6.2DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR) . . . . .		410
12.6.3DMAMUX request line multiplexer interrupt clear flag register
(DMAMUX_CFR) . . . . .		410
13.5.8DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . .437
13.5.9DMA2D foreground color register (DMA2D_FGCOLR) . . . . .439
13.5.10DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . .440
13.5.11DMA2D background color register (DMA2D_BGCOLR) . . . . .442
13.5.12DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . .		442
13.5.13DMA2D background CLUT memory address register
(DMA2D_BGCMAR) . . . . .		443
13.5.14DMA2D output PFC control register (DMA2D_OPFCCR) . . . . .443
13.5.15DMA2D output color register (DMA2D_OCOLR) . . . . .444
13.5.16DMA2D output memory address register (DMA2D_OMAR) . . . . .446
13.5.17DMA2D output offset register (DMA2D_OOR) . . . . .446
13.5.18DMA2D number of line register (DMA2D_NLR) . . . . .447
13.5.19DMA2D line watermark register (DMA2D_LWR) . . . . .447
13.5.20DMA2D AHB master timer configuration register (DMA2D_AMTCR) . . . . .448
13.5.21DMA2D foreground CLUT (DMA2D_FGCLUT[y]) . . . . .448
13.5.22DMA2D background CLUT (DMA2D_BGCLUT[y]) . . . . .449
13.5.23DMA2D register map . . . . .450
14Chrom-GRC (GFXMMU) . . . . .452
14.1Introduction . . . . .452
14.2GFXMMU main features . . . . .452
14.3GFXMMU functional and architectural description . . . . .453
14.3.1Virtual memory . . . . .453
14.3.2MMU architecture . . . . .455
14.4GFXMMU interrupts . . . . .459
14.5GFXMMU registers . . . . .460
14.5.1GFXMMU configuration register (GFXMMU_CR) . . . . .460
14.5.2GFXMMU status register (GFXMMU_SR) . . . . .461
14.5.3GFXMMU flag clear register (GFXMMU_FCR) . . . . .461
14.5.4GFXMMU default value register (GFXMMU_DVR) . . . . .462
14.5.5GFXMMU buffer 0 configuration register (GFXMMU_B0CR) . . . . .462
14.5.6GFXMMU buffer 1 configuration register (GFXMMU_B1CR) . . . . .463
14.5.7GFXMMU buffer 2 configuration register (GFXMMU_B2CR) . . . . .463
14.5.8GFXMMU buffer 3 configuration register (GFXMMU_B3CR) . . . . .464
14.5.9GFXMMU LUT entry x low (GFXMMU_LUTxL) . . . . .464
14.5.10GFXMMU LUT entry x high (GFXMMU_LUTxH) . . . . .464
14.5.11GFXMMU register map .....466
15Nested vectored interrupt controller (NVIC) .....467
15.1NVIC main features .....467
15.2SysTick calibration value register .....467
15.3Interrupt and exception vectors .....468
16Extended interrupts and events controller (EXTI) .....476
16.1Introduction .....476
16.2EXTI main features .....476
16.3EXTI functional description .....476
16.3.1EXTI block diagram .....477
16.3.2Wakeup event management .....477
16.3.3Peripherals asynchronous Interrupts .....478
16.3.4Hardware interrupt selection .....478
16.3.5Hardware event selection .....478
16.3.6Software interrupt/event selection .....478
16.4EXTI interrupt/event line mapping .....478
16.5EXTI registers .....481
16.5.1Interrupt mask register 1 (EXTI_IMR1) .....481
16.5.2Event mask register 1 (EXTI_EM1) .....481
16.5.3Rising trigger selection register 1 (EXTI_RTSR1) .....481
16.5.4Falling trigger selection register 1 (EXTI_FTSR1) .....482
16.5.5Software interrupt event register 1 (EXTI_SWIER1) .....483
16.5.6Pending register 1 (EXTI_PR1) .....484
16.5.7Interrupt mask register 2 (EXTI_IMR2) .....484
16.5.8Event mask register 2 (EXTI_EM2) .....485
16.5.9Rising trigger selection register 2 (EXTI_RTSR2) .....485
16.5.10Falling trigger selection register 2 (EXTI_FTSR2) .....486
16.5.11Software interrupt event register 2 (EXTI_SWIER2) .....486
16.5.12Pending register 2 (EXTI_PR2) .....487
16.5.13EXTI register map .....488
17Cyclic redundancy check calculation unit (CRC) .....489
17.1Introduction .....489
17.2CRC main features .....489
17.3CRC functional description . . . . .490
17.3.1CRC block diagram . . . . .490
17.3.2CRC internal signals . . . . .490
17.3.3CRC operation . . . . .490
17.4CRC registers . . . . .492
17.4.1CRC data register (CRC_DR) . . . . .492
17.4.2CRC independent data register (CRC_IDR) . . . . .492
17.4.3CRC control register (CRC_CR) . . . . .493
17.4.4CRC initial value (CRC_INIT) . . . . .494
17.4.5CRC polynomial (CRC_POL) . . . . .494
17.4.6CRC register map . . . . .495
18Flexible static memory controller (FSMC) . . . . .496
18.1Introduction . . . . .496
18.2FMC main features . . . . .496
18.3FMC implementation . . . . .497
18.4FMC block diagram . . . . .497
18.5AHB interface . . . . .498
18.5.1Supported memories and transactions . . . . .498
18.6External device address mapping . . . . .499
18.6.1NOR/PSRAM address mapping . . . . .500
18.6.2NAND Flash memory address mapping . . . . .501
18.7NOR Flash/PSRAM controller . . . . .502
18.7.1External memory interface signals . . . . .503
18.7.2Supported memories and transactions . . . . .505
18.7.3General timing rules . . . . .506
18.7.4NOR Flash/PSRAM controller asynchronous transactions . . . . .507
18.7.5Synchronous transactions . . . . .525
18.7.6NOR/PSRAM controller registers . . . . .532
18.8NAND Flash controller . . . . .540
18.8.1External memory interface signals . . . . .541
18.8.2NAND Flash supported memories and transactions . . . . .543
18.8.3Timing diagrams for NAND Flash memory . . . . .543
18.8.4NAND Flash operations . . . . .544
18.8.5NAND Flash prewait functionality . . . . .545
19.7.6OCTOSPI status register (OCTOSPI_SR) . . . . .590
19.7.7OCTOSPI flag clear register (OCTOSPI_FCR) . . . . .591
19.7.8OCTOSPI data length register (OCTOSPI_DLR) . . . . .591
19.7.9OCTOSPI address register (OCTOSPI_AR) . . . . .592
19.7.10OCTOSPI data register (OCTOSPI_DR) . . . . .593
19.7.11OCTOSPI polling status mask register (OCTOSPI_PSMKR) . . . . .593
19.7.12OCTOSPI polling status match register (OCTOSPI_PSMAR) . . . . .594
19.7.13OCTOSPI polling interval register (OCTOSPI_PIR) . . . . .594
19.7.14OCTOSPI communication configuration register (OCTOSPI_CCR) . . . . .595
19.7.15OCTOSPI timing configuration register (OCTOSPI_TCR) . . . . .597
19.7.16OCTOSPI instruction register (OCTOSPI_IR) . . . . .598
19.7.17OCTOSPI alternate bytes register (OCTOSPI_ABR) . . . . .598
19.7.18OCTOSPI low-power timeout register (OCTOSPI_LPTR) . . . . .599
19.7.19OCTOSPI wrap communication configuration register
(OCTOSPI_WPCCR) . . . . .		599
19.7.20OCTOSPI wrap timing configuration register (OCTOSPI_WPTCR) . . . . .601
19.7.21OCTOSPI wrap instruction register (OCTOSPI_WPIR) . . . . .602
19.7.22OCTOSPI wrap alternate bytes register (OCTOSPI_WPABR) . . . . .602
19.7.23OCTOSPI write communication configuration register
(OCTOSPI_WCCR) . . . . .		603
19.7.24OCTOSPI write timing configuration register (OCTOSPI_WTCR) . . . . .605
19.7.25OCTOSPI write instruction register (OCTOSPI_WIR) . . . . .605
19.7.26OCTOSPI write alternate bytes register (OCTOSPI_WABR) . . . . .606
19.7.27OCTOSPI HyperBus latency configuration register
(OCTOSPI_HLCR) . . . . .		606
19.7.28OCTOSPI register map . . . . .607
20OCTOSPI I/O manager (OCTOSPIM) . . . . .610
20.1Introduction . . . . .610
20.2OCTOSPIM main features . . . . .610
20.3OCTOSPIM implementation . . . . .610
20.4OCTOSPIM functional description . . . . .610
20.4.1OCTOSPIM block diagram . . . . .610
20.4.2OCTOSPIM matrix . . . . .612
20.4.3OCTOSPIM multiplexed mode . . . . .612
20.5OCTOSPIM registers . . . . .614
20.5.1OCTOSPIM control register (OCTOSPIM_CR) . . . . .614
20.5.2OCTOSPIM Port n configuration register (OCTOSPIM_PnCR) . . . . .614
20.5.3OCTOSPIM register map . . . . .616
21Analog-to-digital converters (ADC) . . . . .617
21.1Introduction . . . . .617
21.2ADC main features . . . . .618
21.3ADC implementation . . . . .619
21.4ADC functional description . . . . .620
21.4.1ADC block diagram . . . . .620
21.4.2ADC pins and internal signals . . . . .621
21.4.3ADC clocks . . . . .622
21.4.4ADC1/2 connectivity . . . . .624
21.4.5Slave AHB interface . . . . .626
21.4.6ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) . . . . .626
21.4.7Single-ended and differential input channels . . . . .626
21.4.8Calibration (ADCAL, ADCALDIF, ADC_CALFACT) . . . . .627
21.4.9ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .630
21.4.10Constraints when writing the ADC control bits . . . . .631
21.4.11Channel selection (SQRx, JSQRx) . . . . .632
21.4.12Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .633
21.4.13Single conversion mode (CONT=0) . . . . .634
21.4.14Continuous conversion mode (CONT=1) . . . . .634
21.4.15Starting conversions (ADSTART, JADSTART) . . . . .635
21.4.16ADC timing . . . . .636
21.4.17Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .636
21.4.18Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . .638
21.4.19Injected channel management . . . . .640
21.4.20Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .642
21.4.21Queue of context for injected conversions . . . . .643
21.4.22Programmable resolution (RES) - Fast conversion mode . . . . .651
21.4.23End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . . . .652
21.4.24End of conversion sequence (EOS, JEOS) . . . . .652
21.4.25Timing diagrams example (single/continuous modes, hardware/software triggers) . . . . .653
21.4.26Data management . . . . .655
21.4.27Managing conversions using the DFSDM . . . . .660
21.4.28Dynamic low-power features . . . . .661
21.4.29Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . .666
21.4.30Oversampler . . . . .670
21.4.31Dual ADC modes . . . . .676
21.4.32Temperature sensor . . . . .689
21.4.33VBAT supply monitoring . . . . .691
21.4.34Monitoring the internal voltage reference . . . . .692
21.5ADC interrupts . . . . .693
21.6ADC registers (for each ADC) . . . . .695
21.6.1ADC interrupt and status register (ADC_ISR) . . . . .695
21.6.2ADC interrupt enable register (ADC_IER) . . . . .697
21.6.3ADC control register (ADC_CR) . . . . .699
21.6.4ADC configuration register (ADC_CFGR) . . . . .702
21.6.5ADC configuration register 2 (ADC_CFGR2) . . . . .706
21.6.6ADC sample time register 1 (ADC_SMPR1) . . . . .708
21.6.7ADC sample time register 2 (ADC_SMPR2) . . . . .709
21.6.8ADC watchdog threshold register 1 (ADC_TR1) . . . . .710
21.6.9ADC watchdog threshold register 2 (ADC_TR2) . . . . .711
21.6.10ADC watchdog threshold register 3 (ADC_TR3) . . . . .711
21.6.11ADC regular sequence register 1 (ADC_SQR1) . . . . .712
21.6.12ADC regular sequence register 2 (ADC_SQR2) . . . . .713
21.6.13ADC regular sequence register 3 (ADC_SQR3) . . . . .714
21.6.14ADC regular sequence register 4 (ADC_SQR4) . . . . .715
21.6.15ADC regular data register (ADC_DR) . . . . .716
21.6.16ADC injected sequence register (ADC_JSQR) . . . . .716
21.6.17ADC offset y register (ADC_OFRy) . . . . .718
21.6.18ADC injected channel y data register (ADC_JDRy) . . . . .719
21.6.19ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . .719
21.6.20ADC analog watchdog 3 configuration register (ADC_AWD3CR) . . . . .720
21.6.21ADC differential mode selection register (ADC_DIFSEL) . . . . .720
21.6.22ADC calibration factors (ADC_CALFACT) . . . . .721
21.7ADC common registers . . . . .721
21.7.1ADC common status register (ADC_CSR) . . . . .721
21.7.2ADC common control register (ADC_CCR) . . . . .723
21.7.3ADC common regular data register for dual mode (ADC_CDR) . . . . .726
22.7.10Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . .757
22.7.11Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . .758
22.7.12DAC channel1 data output register (DAC_DOR1) . . . . .758
22.7.13DAC channel2 data output register (DAC_DOR2) . . . . .759
22.7.14DAC status register (DAC_SR) . . . . .759
22.7.15DAC calibration control register (DAC_CCR) . . . . .761
22.7.16DAC mode control register (DAC_MCR) . . . . .761
22.7.17DAC channel1 sample and hold sample time register (DAC_SHSR1) . . . . .763
22.7.18DAC channel2 sample and hold sample time register (DAC_SHSR2) . . . . .763
22.7.19DAC sample and hold time register (DAC_SHHR) . . . . .764
22.7.20DAC sample and hold refresh time register (DAC_SHRR) . . . . .764
22.7.21DAC register map . . . . .766
23Voltage reference buffer (VREFBUF) . . . . .768
23.1Introduction . . . . .768
23.2VREFBUF functional description . . . . .768
23.3VREFBUF registers . . . . .769
23.3.1VREFBUF control and status register (VREFBUF_CSR) . . . . .769
23.3.2VREFBUF calibration control register (VREFBUF_CCR) . . . . .770
23.3.3VREFBUF register map . . . . .770
24Digital camera interface (DCMI) . . . . .771
24.1Introduction . . . . .771
24.2DCMI main features . . . . .771
24.3DCMI functional description . . . . .771
24.3.1DCMI block diagram . . . . .772
24.3.2DCMI pins . . . . .772
24.3.3DCMI clocks . . . . .772
24.3.4DCMI DMA interface . . . . .773
24.3.5DCMI physical interface . . . . .773
24.3.6DCMI synchronization . . . . .775
24.3.7DCMI capture modes . . . . .777
24.3.8DCMI crop feature . . . . .778
24.3.9DCMI JPEG format . . . . .779
24.3.10DCMI FIFO .....779
24.3.11DCMI data format description .....780
24.4DCMI interrupts .....782
24.5DCMI registers .....783
24.5.1DCMI control register (DCMI_CR) .....783
24.5.2DCMI status register (DCMI_SR) .....785
24.5.3DCMI raw interrupt status register (DCMI_RIS) .....786
24.5.4DCMI interrupt enable register (DCMI_IER) .....787
24.5.5DCMI masked interrupt status register (DCMI_MIS) .....788
24.5.6DCMI interrupt clear register (DCMI_ICR) .....789
24.5.7DCMI embedded synchronization code register (DCMI_ESCR) .....789
24.5.8DCMI embedded synchronization unmask register (DCMI_ESUR) ..791
24.5.9DCMI crop window start (DCMI_CWSTRT) .....791
24.5.10DCMI crop window size (DCMI_CWSIZE) .....792
24.5.11DCMI data register (DCMI_DR) .....792
24.5.12DCMI register map .....794
25Parallel synchronous slave interface (PSSI) applied
to STM32L4P5xx and STM32LQ5xx only .....		795
25.1Introduction .....795
25.2PSSI main features .....795
25.3PSSI functional description .....795
25.3.1PSSI block diagram .....796
25.3.2PSSI pins and internal signals .....796
25.3.3PSSI clock .....797
25.3.4PSSI data management .....797
25.3.5PSSI optional control signals .....799
25.4PSSI interrupts .....802
25.5PSSI registers .....803
25.5.1PSSI control register (PSSI_CR) .....803
25.5.2PSSI status register (PSSI_SR) .....805
25.5.3PSSI raw interrupt status register (PSSI_RIS) .....805
25.5.4PSSI interrupt enable register (PSSI_IER) .....806
25.5.5PSSI masked interrupt status register (PSSI_MIS) .....806
25.5.6PSSI interrupt clear register (PSSI_ICR) .....807
25.5.7PSSI data register (PSSI_DR) .....808
25.5.8PSSI register map .....808
26Comparator (COMP) .....810
26.1Introduction .....810
26.2COMP main features .....810
26.3COMP functional description .....811
26.3.1COMP block diagram .....811
26.3.2COMP pins and internal signals .....811
26.3.3COMP reset and clocks .....812
26.3.4Comparator LOCK mechanism .....812
26.3.5Window comparator .....813
26.3.6Hysteresis .....813
26.3.7Comparator output blanking function .....814
26.3.8COMP power and speed modes .....815
26.4COMP low-power modes .....815
26.5COMP interrupts .....815
26.6COMP registers .....816
26.6.1Comparator 1 control and status register (COMP1_CSR) .....816
26.6.2Comparator 2 control and status register (COMP2_CSR) .....818
26.6.3COMP register map .....821
27Operational amplifiers (OPAMP) .....822
27.1Introduction .....822
27.2OPAMP main features .....822
27.3OPAMP functional description .....822
27.3.1OPAMP reset and clocks .....822
27.3.2Initial configuration .....823
27.3.3Signal routing .....823
27.3.4OPAMP modes .....824
27.3.5Calibration .....827
27.4OPAMP low-power modes .....829
27.5OPAMP registers .....830
27.5.1OPAMP1 control/status register (OPAMP1_CSR) .....830
27.5.2OPAMP1 offset trimming register in normal mode (OPAMP1_OTR) ..831
27.5.3OPAMP1 offset trimming register in low-power mode
(OPAMP1_LPOTR) .....		831
28.7.4DFSDM channel y watchdog filter data register (DFSDM_CHyWDATR) .....869
28.7.5DFSDM channel y data input register (DFSDM_CHyDATINR) .....869
28.7.6DFSDM channel y delay register (DFSDM_CHyDLYR) .....870
28.8DFSDM filter x module registers (x=0..3) .....871
28.8.1DFSDM filter x control register 1 (DFSDM_FLTxCR1) .....871
28.8.2DFSDM filter x control register 2 (DFSDM_FLTxCR2) .....874
28.8.3DFSDM filter x interrupt and status register (DFSDM_FLTxISR) .....875
28.8.4DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) .....877
28.8.5DFSDM filter x injected channel group selection register (DFSDM_FLTxJCHGR) .....878
28.8.6DFSDM filter x control register (DFSDM_FLTxFCR) .....878
28.8.7DFSDM filter x data register for injected group (DFSDM_FLTxJDATAR) .....879
28.8.8DFSDM filter x data register for the regular channel (DFSDM_FLTxRDATAR) .....880
28.8.9DFSDM filter x analog watchdog high threshold register (DFSDM_FLTxAWHTR) .....881
28.8.10DFSDM filter x analog watchdog low threshold register (DFSDM_FLTxAWLTR) .....881
28.8.11DFSDM filter x analog watchdog status register (DFSDM_FLTxAWSR) .....882
28.8.12DFSDM filter x analog watchdog clear flag register (DFSDM_FLTxAWCFR) .....883
28.8.13DFSDM filter x extremes detector maximum register (DFSDM_FLTxEXMAX) .....883
28.8.14DFSDM filter x extremes detector minimum register (DFSDM_FLTxEXMIN) .....884
28.8.15DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) ..884
28.8.16DFSDM register map .....885
29LCD-TFT display controller (LTDC) .....895
29.1Introduction .....895
29.2LTDC main features .....895
29.3LTDC implementation .....895
29.4LTDC functional description .....896
29.4.1LTDC block diagram .....896
29.4.2LTDC pins and external signal interface .....896
29.4.3LTDC reset and clocks .....897
29.5LTDC programmable parameters . . . . .898
29.5.1LTDC global configuration parameters . . . . .898
29.5.2Layer programmable parameters . . . . .901
29.6LTDC interrupts . . . . .906
29.7LTDC programming procedure . . . . .907
29.8LTDC registers . . . . .908
29.8.1LTDC synchronization size configuration register (LTDC_SSCR) . . . . .908
29.8.2LTDC back porch configuration register (LTDC_BPCR) . . . . .909
29.8.3LTDC active width configuration register (LTDC_AWCR) . . . . .910
29.8.4LTDC total width configuration register (LTDC_TWCR) . . . . .911
29.8.5LTDC global control register (LTDC_GCR) . . . . .911
29.8.6LTDC shadow reload configuration register (LTDC_SRCR) . . . . .913
29.8.7LTDC background color configuration register (LTDC_BCCR) . . . . .913
29.8.8LTDC interrupt enable register (LTDC_IER) . . . . .914
29.8.9LTDC interrupt status register (LTDC_ISR) . . . . .915
29.8.10LTDC Interrupt clear register (LTDC_ICR) . . . . .915
29.8.11LTDC line interrupt position configuration register (LTDC_LIPCR) . . . . .916
29.8.12LTDC current position status register (LTDC_CPSR) . . . . .916
29.8.13LTDC current display status register (LTDC_CDSR) . . . . .917
29.8.14LTDC layer x control register (LTDC_LxCR) . . . . .917
29.8.15LTDC layer x window horizontal position configuration register
(LTDC_LxWHPCR) . . . . .		918
29.8.16LTDC layer x window vertical position configuration register
(LTDC_LxWVPCR) . . . . .		919
29.8.17LTDC layer x color keying configuration register
(LTDC_LxCKCR) . . . . .		920
29.8.18LTDC layer x pixel format configuration register
(LTDC_LxPFCR) . . . . .		920
29.8.19LTDC layer x constant alpha configuration register
(LTDC_LxCACR) . . . . .		921
29.8.20LTDC layer x default color configuration register
(LTDC_LxDCCR) . . . . .		922
29.8.21LTDC layer x blending factors configuration register
(LTDC_LxBFCR) . . . . .		923
29.8.22LTDC layer x color frame buffer address register
(LTDC_LxCFBAR) . . . . .		924
29.8.23LTDC layer x color frame buffer length register
(LTDC_LxCFBLR) . . . . .		924
29.8.24LTDC layer x color frame buffer line number register
(LTDC_LxCFBLNR) . . . . .		925
29.8.25LTDC layer x CLUT write register (LTDC_LxCLUTWR)926
29.8.26LTDC register map926
30DSI Host (DSI) applied to STM32L4R9xx and STM32L4S9xx only930
30.1Introduction930
30.2Standard and references930
30.3DSI Host main features931
30.4DSI Host functional description932
30.4.1General description932
30.4.2DSI Host pins and internal signals932
30.4.3Supported resolutions and frame rates933
30.4.4System level architecture933
30.5Functional description: video mode on LTDC interface936
30.5.1Video transmission mode937
30.5.2Updating the LTDC interface configuration in video mode939
30.6Functional description: adapted command mode on LTDC interface941
30.7Functional description: APB slave generic interface945
30.7.1Packet transmission using the generic interface945
30.8Functional description: timeout counters949
30.8.1Contention error detection timeout counters949
30.8.2Peripheral response timeout counters950
30.9Functional description: transmission of commands955
30.9.1Transmission of commands in video mode955
30.9.2Transmission of commands in low-power mode957
30.9.3Transmission of commands in high-speed961
30.9.4Read command transmission961
30.9.5Clock lane in low-power mode962
30.10Functional description: virtual channels964
30.11Functional description: video mode pattern generator965
30.11.1Color bar pattern965
30.11.2Color coding967
30.11.3BER testing pattern967
30.11.4Video mode pattern generator resolution968
30.12Functional description: D-PHY management969
30.12.1D-PHY configuration969
30.12.2Special D-PHY operations . . . . .971
30.12.3Special low-power D-PHY functions . . . . .971
30.12.4DSI PLL control . . . . .971
30.12.5Regulator control . . . . .973
30.13Functional description: interrupts and errors . . . . .973
30.13.1DSI Wrapper interrupts . . . . .973
30.13.2DSI Host interrupts and errors . . . . .973
30.14Programing procedure . . . . .981
30.14.1Programing procedure overview . . . . .981
30.14.2Configuring the D-PHY parameters . . . . .981
30.14.3Configuring the DSI Host timing . . . . .982
30.14.4Configuring flow control and DBI interface . . . . .983
30.14.5Configuring the DSI Host LTDC interface . . . . .983
30.14.6Configuring the video mode . . . . .984
30.14.7Configuring the adapted command mode . . . . .988
30.14.8Configuring the video mode pattern generator . . . . .988
30.14.9Managing ULPM . . . . .989
30.15DSI Host registers . . . . .992
30.15.1DSI Host version register (DSI_VR) . . . . .992
30.15.2DSI Host control register (DSI_CR) . . . . .992
30.15.3DSI Host clock control register (DSI_CCR) . . . . .992
30.15.4DSI Host LTDC VCID register (DSI_LVCIDR) . . . . .993
30.15.5DSI Host LTDC color coding register (DSI_LCOLCR) . . . . .993
30.15.6DSI Host LTDC polarity configuration register (DSI_LPCR) . . . . .994
30.15.7DSI Host low-power mode configuration register (DSI_LPMCR) . . . . .994
30.15.8DSI Host protocol configuration register (DSI_PCR) . . . . .995
30.15.9DSI Host generic VCID register (DSI_GVCIDR) . . . . .996
30.15.10DSI Host mode configuration register (DSI_MCR) . . . . .996
30.15.11DSI Host video mode configuration register (DSI_VMCR) . . . . .996
30.15.12DSI Host video packet configuration register (DSI_VPCR) . . . . .998
30.15.13DSI Host video chunks configuration register (DSI_VCCR) . . . . .998
30.15.14DSI Host video null packet configuration register (DSI_VNPCR) . . . . .999
30.15.15DSI Host video HSA configuration register (DSI_VHSACR) . . . . .999
30.15.16DSI Host video HBP configuration register (DSI_VHBPCR) . . . . .1000
30.15.17DSI Host video line configuration register (DSI_VLCR) . . . . .1000
30.15.18DSI Host video VSA configuration register (DSI_VVSACR) . . . . .1000
30.15.19DSI Host video VBP configuration register (DSI_VVBPCR) . . . . .1001
30.15.20 DSI Host video VFP configuration register (DSI_VVFPCCR) . . . . .1001
30.15.21 DSI Host video VA configuration register (DSI_VVACR) . . . . .1001
30.15.22 DSI Host LTDC command configuration register (DSI_LCCR) . . . . .1002
30.15.23 DSI Host command mode configuration register (DSI_CMCCR) . . . . .1002
30.15.24 DSI Host generic header configuration register (DSI_GHCCR) . . . . .1004
30.15.25 DSI Host generic payload data register (DSI_GPDR) . . . . .1005
30.15.26 DSI Host generic packet status register (DSI_GPSR) . . . . .1005
30.15.27 DSI Host timeout counter configuration register 0 (DSI_TCCR0) . . . . .1006
30.15.28 DSI Host timeout counter configuration register 1 (DSI_TCCR1) . . . . .1007
30.15.29 DSI Host timeout counter configuration register 2 (DSI_TCCR2) . . . . .1007
30.15.30 DSI Host timeout counter configuration register 3 (DSI_TCCR3) . . . . .1007
30.15.31 DSI Host timeout counter configuration register 4 (DSI_TCCR4) . . . . .1008
30.15.32 DSI Host timeout counter configuration register 5 (DSI_TCCR5) . . . . .1008
30.15.33 DSI Host clock lane configuration register (DSI_CLCR) . . . . .1009
30.15.34 DSI Host clock lane timer configuration register (DSI_CLTCR) . . . . .1009
30.15.35 DSI Host data lane timer configuration register (DSI_DLTCR) . . . . .1010
30.15.36 DSI Host PHY control register (DSI_PCTLR) . . . . .1010
30.15.37 DSI Host PHY configuration register (DSI_PCONFR) . . . . .1011
30.15.38 DSI Host PHY ULPS control register (DSI_PUCR) . . . . .1011
30.15.39 DSI Host PHY TX triggers configuration register (DSI_PTTCCR) . . . . .1012
30.15.40 DSI Host PHY status register (DSI_PSR) . . . . .1012
30.15.41 DSI Host interrupt and status register 0 (DSI_ISR0) . . . . .1013
30.15.42 DSI Host interrupt and status register 1 (DSI_ISR1) . . . . .1015
30.15.43 DSI Host interrupt enable register 0 (DSI_IER0) . . . . .1016
30.15.44 DSI Host interrupt enable register 1 (DSI_IER1) . . . . .1018
30.15.45 DSI Host force interrupt register 0 (DSI_FIR0) . . . . .1020
30.15.46 DSI Host force interrupt register 1 (DSI_FIR1) . . . . .1021
30.15.47 DSI Host video shadow control register (DSI_VSCR) . . . . .1022
30.15.48 DSI Host LTDC current VCID register (DSI_LCVCIDR) . . . . .1023
30.15.49 DSI Host LTDC current color coding register (DSI_LCCCR) . . . . .1023
30.15.50 DSI Host low-power mode current configuration register
(DSI_LPMCCR) . . . . .		1024
30.15.51 DSI Host video mode current configuration register
(DSI_VMCCR) . . . . .		1024
30.15.52 DSI Host video packet current configuration register
(DSI_VPCCR) . . . . .		1025
30.15.53 DSI Host video chunks current configuration register
(DSI_VCCCR) . . . . .		1026

30.15.54 DSI Host video null packet current configuration register (DSI_VNPCCR) . . . . . 1026

30.15.55 DSI Host video HSA current configuration register (DSI_VHSACCR) . . . . . 1027

30.15.56 DSI Host video HBP current configuration register (DSI_VHBPCCR) . . . . . 1027

30.15.57 DSI Host video line current configuration register (DSI_VLCCR) . . . . . 1027

30.15.58 DSI Host video VSA current configuration register (DSI_VVSACCR) . . . . . 1028

30.15.59 DSI Host video VBP current configuration register (DSI_VVBPCCR) . . . . . 1028

30.15.60 DSI Host video VFP current configuration register (DSI_VVFPCCR) . . . . . 1029

30.15.61 DSI Host video VA current configuration register (DSI_VVACCR) . . . . . 1029

30.16 DSI Wrapper registers . . . . . 1030

30.16.1 DSI Wrapper configuration register (DSI_WCFGR) . . . . . 1030

30.16.2 DSI Wrapper control register (DSI_WCR) . . . . . 1031

30.16.3 DSI Wrapper interrupt enable register (DSI_WIER) . . . . . 1031

30.16.4 DSI Wrapper interrupt and status register (DSI_WISR) . . . . . 1032

30.16.5 DSI Wrapper interrupt flag clear register (DSI_WIFCR) . . . . . 1033

30.16.6 DSI Wrapper PHY configuration register 0 (DSI_WPCR0) . . . . . 1034

30.16.7 DSI Wrapper PHY configuration register 1 (DSI_WPCR1) . . . . . 1036

30.16.8 DSI Wrapper PHY configuration register 2 (DSI_WPCR2) . . . . . 1038

30.16.9 DSI Wrapper PHY configuration register 3 (DSI_WPCR3) . . . . . 1039

30.16.10 DSI Wrapper PHY configuration register 4 (DSI_WPCR4) . . . . . 1039

30.16.11 DSI Wrapper regulator and PLL control register (DSI_WRPCR) . . . . . 1040

30.16.12 DSI register map . . . . . 1041

31 Touch sensing controller (TSC) . . . . . 1047

31.1 Introduction . . . . . 1047

31.2 TSC main features . . . . . 1047

31.3 TSC functional description . . . . . 1048

31.3.1 TSC block diagram . . . . . 1048

31.3.2 Surface charge transfer acquisition overview . . . . . 1048

31.3.3 Reset and clocks . . . . . 1050

31.3.4 Charge transfer acquisition sequence . . . . . 1051

31.3.5 Spread spectrum feature . . . . . 1052

31.3.6 Max count error . . . . . 1052

31.3.7Sampling capacitor I/O and channel I/O mode selection . . . . .1053
31.3.8Acquisition mode . . . . .1054
31.3.9I/O hysteresis and analog switch control . . . . .1054
31.4TSC low-power modes . . . . .1055
31.5TSC interrupts . . . . .1055
31.6TSC registers . . . . .1056
31.6.1TSC control register (TSC_CR) . . . . .1056
31.6.2TSC interrupt enable register (TSC_IER) . . . . .1058
31.6.3TSC interrupt clear register (TSC_ICR) . . . . .1059
31.6.4TSC interrupt status register (TSC_ISR) . . . . .1060
31.6.5TSC I/O hysteresis control register (TSC_IOHCR) . . . . .1060
31.6.6TSC I/O analog switch control register (TSC_IOASCR) . . . . .1061
31.6.7TSC I/O sampling control register (TSC_IOSCR) . . . . .1061
31.6.8TSC I/O channel control register (TSC_IOCCR) . . . . .1062
31.6.9TSC I/O group control status register (TSC_IOGCSR) . . . . .1062
31.6.10TSC I/O group x counter register (TSC_IOGxCR) . . . . .1063
31.6.11TSC register map . . . . .1064
32True random number generator (RNG) applied to
STM32L4Rxxx and STM32L4Sxxx only . . . . .		1066
32.1Introduction . . . . .1066
32.2RNG main features . . . . .1066
32.3RNG functional description . . . . .1067
32.3.1RNG block diagram . . . . .1067
32.3.2RNG internal signals . . . . .1067
32.3.3Random number generation . . . . .1068
32.3.4RNG initialization . . . . .1070
32.3.5RNG operation . . . . .1071
32.3.6RNG clocking . . . . .1072
32.3.7Error management . . . . .1072
32.3.8RNG low-power usage . . . . .1073
32.4RNG interrupts . . . . .1074
32.5RNG processing time . . . . .1074
32.6RNG entropy source validation . . . . .1074
32.6.1Introduction . . . . .1074
32.6.2Validation conditions . . . . .1074
34.3AES implementation . . . . .1095
34.4AES functional description . . . . .1095
34.4.1AES block diagram . . . . .1095
34.4.2AES internal signals . . . . .1095
34.4.3AES cryptographic core . . . . .1096
34.4.4AES procedure to perform a cipher operation . . . . .1101
34.4.5AES decryption round key preparation . . . . .1104
34.4.6AES ciphertext stealing and data padding . . . . .1105
34.4.7AES task suspend and resume . . . . .1105
34.4.8AES basic chaining modes (ECB, CBC) . . . . .1106
34.4.9AES counter (CTR) mode . . . . .1111
34.4.10AES Galois/counter mode (GCM) . . . . .1113
34.4.11AES Galois message authentication code (GMAC) . . . . .1118
34.4.12AES counter with CBC-MAC (CCM) . . . . .1120
34.4.13AES data registers and data swapping . . . . .1125
34.4.14AES key registers . . . . .1127
34.4.15AES initialization vector registers . . . . .1127
34.4.16AES DMA interface . . . . .1128
34.4.17AES error management . . . . .1129
34.5AES interrupts . . . . .1130
34.6AES processing latency . . . . .1131
34.7AES registers . . . . .1131
34.7.1AES control register (AES_CR) . . . . .1131
34.7.2AES status register (AES_SR) . . . . .1134
34.7.3AES data input register (AES_DINR) . . . . .1135
34.7.4AES data output register (AES_DOUTR) . . . . .1135
34.7.5AES key register 0 (AES_KEYR0) . . . . .1136
34.7.6AES key register 1 (AES_KEYR1) . . . . .1137
34.7.7AES key register 2 (AES_KEYR2) . . . . .1137
34.7.8AES key register 3 (AES_KEYR3) . . . . .1137
34.7.9AES initialization vector register 0 (AES_IVR0) . . . . .1138
34.7.10AES initialization vector register 1 (AES_IVR1) . . . . .1138
34.7.11AES initialization vector register 2 (AES_IVR2) . . . . .1138
34.7.12AES initialization vector register 3 (AES_IVR3) . . . . .1139
34.7.13AES key register 4 (AES_KEYR4) . . . . .1139
34.7.14AES key register 5 (AES_KEYR5) . . . . .1139

34.7.15 AES key register 6 (AES_KEYR6) . . . . . 1140

34.7.16 AES key register 7 (AES_KEYR7) . . . . . 1140

34.7.17 AES suspend registers (AES_SUSPxR) . . . . . 1140

34.7.18 AES register map . . . . . 1141

35 Hash processor (HASH) . . . . . 1143

35.1 Introduction . . . . . 1143

35.2 HASH main features . . . . . 1143

35.3 HASH implementation . . . . . 1144

35.4 HASH functional description . . . . . 1144

35.4.1 HASH block diagram . . . . . 1144

35.4.2 HASH internal signals . . . . . 1145

35.4.3 About secure hash algorithms . . . . . 1145

35.4.4 Message data feeding . . . . . 1145

35.4.5 Message digest computing . . . . . 1147

35.4.6 Message padding . . . . . 1148

35.4.7 HMAC operation . . . . . 1150

35.4.8 HASH suspend/resume operations . . . . . 1152

35.4.9 HASH DMA interface . . . . . 1154

35.4.10 HASH error management . . . . . 1154

35.5 HASH interrupts . . . . . 1154

35.6 HASH processing time . . . . . 1155

35.7 HASH registers . . . . . 1156

35.7.1 HASH control register (HASH_CR) . . . . . 1156

35.7.2 HASH data input register (HASH_DIN) . . . . . 1158

35.7.3 HASH start register (HASH_STR) . . . . . 1159

35.7.4 HASH digest registers . . . . . 1160

35.7.5 HASH interrupt enable register (HASH_IMR) . . . . . 1161

35.7.6 HASH status register (HASH_SR) . . . . . 1162

35.7.7 HASH context swap registers . . . . . 1162

35.7.8 HASH register map . . . . . 1164

36 Public key accelerator (PKA) applied to
STM32L4P5xx and STM32L4Q5xx only . . . . . 1166

36.1 Introduction . . . . . 1166

36.2 PKA main features . . . . . 1166

36.3PKA functional description . . . . .1166
36.3.1PKA block diagram . . . . .1166
36.3.2PKA internal signals . . . . .1167
36.3.3PKA reset and clocks . . . . .1167
36.3.4PKA public key acceleration . . . . .1167
36.3.5Typical applications for PKA . . . . .1169
36.3.6PKA procedure to perform an operation . . . . .1171
36.3.7PKA error management . . . . .1172
36.4PKA operating modes . . . . .1172
36.4.1Introduction . . . . .1172
36.4.2Montgomery parameter computation . . . . .1173
36.4.3Modular addition . . . . .1174
36.4.4Modular subtraction . . . . .1174
36.4.5Modular and Montgomery multiplication . . . . .1174
36.4.6Modular exponentiation . . . . .1175
36.4.7Modular inversion . . . . .1176
36.4.8Modular reduction . . . . .1177
36.4.9Arithmetic addition . . . . .1177
36.4.10Arithmetic subtraction . . . . .1177
36.4.11Arithmetic multiplication . . . . .1178
36.4.12Arithmetic comparison . . . . .1178
36.4.13RSA CRT exponentiation . . . . .1178
36.4.14Point on elliptic curve Fp check . . . . .1179
36.4.15ECC Fp scalar multiplication . . . . .1180
36.4.16ECDSA sign . . . . .1181
36.4.17ECDSA verification . . . . .1183
36.5Example of configurations and processing times . . . . .1184
36.5.1Supported elliptic curves . . . . .1184
36.5.2Computation times . . . . .1186
36.6PKA interrupts . . . . .1187
36.7PKA registers . . . . .1188
36.7.1PKA control register (PKA_CR) . . . . .1188
36.7.2PKA status register (PKA_SR) . . . . .1189
36.7.3PKA clear flag register (PKA_CLRFR) . . . . .1190
36.7.4PKA RAM . . . . .1190
36.7.5PKA register map . . . . .1191
37Advanced-control timers (TIM1/TIM8) . . . . .1192
37.1TIM1/TIM8 introduction . . . . .1192
37.2TIM1/TIM8 main features . . . . .1192
37.3TIM1/TIM8 functional description . . . . .1194
37.3.1Time-base unit . . . . .1194
37.3.2Counter modes . . . . .1196
37.3.3Repetition counter . . . . .1207
37.3.4External trigger input . . . . .1209
37.3.5Clock selection . . . . .1210
37.3.6Capture/compare channels . . . . .1214
37.3.7Input capture mode . . . . .1216
37.3.8PWM input mode . . . . .1217
37.3.9Forced output mode . . . . .1218
37.3.10Output compare mode . . . . .1219
37.3.11PWM mode . . . . .1220
37.3.12Asymmetric PWM mode . . . . .1223
37.3.13Combined PWM mode . . . . .1224
37.3.14Combined 3-phase PWM mode . . . . .1225
37.3.15Complementary outputs and dead-time insertion . . . . .1226
37.3.16Using the break function . . . . .1228
37.3.17Bidirectional break inputs . . . . .1234
37.3.18Clearing the OCxREF signal on an external event . . . . .1235
37.3.196-step PWM generation . . . . .1237
37.3.20One-pulse mode . . . . .1238
37.3.21Retriggerable one pulse mode . . . . .1239
37.3.22Encoder interface mode . . . . .1240
37.3.23UIF bit remapping . . . . .1242
37.3.24Timer input XOR function . . . . .1243
37.3.25Interfacing with Hall sensors . . . . .1243
37.3.26Timer synchronization . . . . .1246
37.3.27ADC synchronization . . . . .1250
37.3.28DMA burst mode . . . . .1250
37.3.29Debug mode . . . . .1251
37.4TIM1/TIM8 registers . . . . .1252
37.4.1TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . .1252
37.4.2TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . .1253
37.4.3TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) . . . . .1256
37.4.4TIMx DMA/interrupt enable register (TIMx_DIER)(x = 1, 8) . . . . .1258
37.4.5TIMx status register (TIMx_SR)(x = 1, 8) . . . . .1260
37.4.6TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . .1262
37.4.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . .		1263
37.4.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . .		1264
37.4.9TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . .		1267
37.4.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . .		1268
37.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 1, 8) . . . . .		1270
37.4.12TIMx counter (TIMx_CNT)(x = 1, 8) . . . . .1273
37.4.13TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . .1273
37.4.14TIMx auto-reload register (TIMx_ARR)(x = 1, 8) . . . . .1273
37.4.15TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . .1274
37.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 1, 8) . . . . .1274
37.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 1, 8) . . . . .1275
37.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 1, 8) . . . . .1275
37.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 1, 8) . . . . .1276
37.4.20TIMx break and dead-time register
(TIMx_BDTR)(x = 1, 8) . . . . .		1276
37.4.21TIMx DMA control register (TIMx_DCR)(x = 1, 8) . . . . .1280
37.4.22TIMx DMA address for full transfer
(TIMx_DMAR)(x = 1, 8) . . . . .		1281
37.4.23TIM1 option register 1 (TIM1_OR1) . . . . .1282
37.4.24TIM8 option register 1 (TIM8_OR1) . . . . .1282
37.4.25TIMx capture/compare mode register 3
(TIMx_CCMR3)(x = 1, 8) . . . . .		1283
37.4.26TIMx capture/compare register 5 (TIMx_CCR5)(x = 1, 8) . . . . .1284
37.4.27TIMx capture/compare register 6 (TIMx_CCR6)(x = 1, 8) . . . . .1285
37.4.28TIM1 option register 2 (TIM1_OR2) . . . . .1285
37.4.29TIM1 option register 3 (TIM1_OR3) . . . . .1287
37.4.30TIM8 option register 2 (TIM8_OR2) . . . . .1289
37.4.31TIM8 option register 3 (TIM8_OR3) . . . . .1290
37.4.32TIM1 register map . . . . .1293
37.4.33TIM8 register map . . . . .1295
38General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . .1298
38.1TIM2/TIM3/TIM4/TIM5 introduction . . . . .1298
38.2TIM2/TIM3/TIM4/TIM5 main features . . . . .1298
38.3TIM2/TIM3/TIM4/TIM5 functional description . . . . .1300
38.3.1Time-base unit . . . . .1300
38.3.2Counter modes . . . . .1302
38.3.3Clock selection . . . . .1312
38.3.4Capture/Compare channels . . . . .1316
38.3.5Input capture mode . . . . .1318
38.3.6PWM input mode . . . . .1319
38.3.7Forced output mode . . . . .1320
38.3.8Output compare mode . . . . .1321
38.3.9PWM mode . . . . .1322
38.3.10Asymmetric PWM mode . . . . .1325
38.3.11Combined PWM mode . . . . .1326
38.3.12Clearing the OCxREF signal on an external event . . . . .1327
38.3.13One-pulse mode . . . . .1329
38.3.14Retriggerable one pulse mode . . . . .1330
38.3.15Encoder interface mode . . . . .1331
38.3.16UIF bit remapping . . . . .1333
38.3.17Timer input XOR function . . . . .1333
38.3.18Timers and external trigger synchronization . . . . .1334
38.3.19Timer synchronization . . . . .1337
38.3.20DMA burst mode . . . . .1342
38.3.21Debug mode . . . . .1343
38.4TIM2/TIM3/TIM4/TIM5 registers . . . . .1344
38.4.1TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . .1344
38.4.2TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . .1345
38.4.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . .1347
38.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . .1350
38.4.5TIMx status register (TIMx_SR)(x = 2 to 5) . . . . .1351
38.4.6TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . .1352
38.4.7TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5) . . . . .		1353
38.4.8TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5) . . . . .		1355
38.4.9TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5) .....		1357
38.4.10TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5) .....		1358
38.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 5) .....		1359
38.4.12TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) .....1360
38.4.13TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) .....1361
38.4.14TIMx prescaler (TIMx_PSC)(x = 2 to 5) .....1361
38.4.15TIMx auto-reload register (TIMx_ARR)(x = 2 to 5) .....1362
38.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) .....1362
38.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) .....1363
38.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) .....1363
38.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) .....1364
38.4.20TIMx DMA control register (TIMx_DCR)(x = 2 to 5) .....1365
38.4.21TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) .....1365
38.4.22TIM2 option register 1 (TIM2_OR1) .....1365
38.4.23TIM3 option register 1 (TIM3_OR1) .....1366
38.4.24TIM2 option register 2 (TIM2_OR2) .....1366
38.4.25TIM3 option register 2 (TIM3_OR2) .....1367
38.4.26TIMx register map .....1368
39General-purpose timers (TIM15/TIM16/TIM17) .....1371
39.1TIM15/TIM16/TIM17 introduction .....1371
39.2TIM15 main features .....1371
39.3TIM16/TIM17 main features .....1372
39.4TIM15/TIM16/TIM17 functional description .....1375
39.4.1Time-base unit .....1375
39.4.2Counter modes .....1377
39.4.3Repetition counter .....1381
39.4.4Clock selection .....1382
39.4.5Capture/compare channels .....1384
39.4.6Input capture mode .....1386
39.4.7PWM input mode (only for TIM15) .....1387
39.4.8Forced output mode .....1388
39.4.9Output compare mode .....1389
39.4.10PWM mode .....1390
39.4.11Combined PWM mode (TIM15 only) .....1391
39.4.12Complementary outputs and dead-time insertion . . . . .1392
39.4.13Using the break function . . . . .1394
39.4.14Bidirectional break inputs . . . . .1399
39.4.15One-pulse mode . . . . .1401
39.4.16Retriggerable one pulse mode (TIM15 only) . . . . .1403
39.4.17UIF bit remapping . . . . .1403
39.4.18Timer input XOR function (TIM15 only) . . . . .1405
39.4.19External trigger synchronization (TIM15 only) . . . . .1406
39.4.20Slave mode – combined reset + trigger mode . . . . .1408
39.4.21DMA burst mode . . . . .1408
39.4.22Timer synchronization (TIM15) . . . . .1410
39.4.23Using timer output as trigger for other timers (TIM16/TIM17) . . . . .1410
39.4.24Debug mode . . . . .1410
39.5TIM15 registers . . . . .1411
39.5.1TIM15 control register 1 (TIM15_CR1) . . . . .1411
39.5.2TIM15 control register 2 (TIM15_CR2) . . . . .1412
39.5.3TIM15 slave mode control register (TIM15_SMCR) . . . . .1414
39.5.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .1415
39.5.5TIM15 status register (TIM15_SR) . . . . .1416
39.5.6TIM15 event generation register (TIM15_EGR) . . . . .1418
39.5.7TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		1419
39.5.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		1420
39.5.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .1423
39.5.10TIM15 counter (TIM15_CNT) . . . . .1426
39.5.11TIM15 prescaler (TIM15_PSC) . . . . .1426
39.5.12TIM15 auto-reload register (TIM15_ARR) . . . . .1426
39.5.13TIM15 repetition counter register (TIM15_RCR) . . . . .1427
39.5.14TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .1427
39.5.15TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .1428
39.5.16TIM15 break and dead-time register (TIM15_BDTR) . . . . .1428
39.5.17TIM15 DMA control register (TIM15_DCR) . . . . .1431
39.5.18TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .1431
39.5.19TIM15 option register 1 (TIM15_OR1) . . . . .1432
39.5.20TIM15 option register 2 (TIM15_OR2) . . . . .1432
39.5.21TIM15 register map . . . . .1434
39.6TIM16/TIM17 registers . . . . .1437
39.6.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .1437
39.6.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .1438
39.6.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .1439
39.6.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .1440
39.6.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .1441
39.6.6TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 16 to 17) . . . . .		1442
39.6.7TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 16 to 17) . . . . .		1443
39.6.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .1445
39.6.9TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .1447
39.6.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .1448
39.6.11TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . .1448
39.6.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .1449
39.6.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .1449
39.6.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .1450
39.6.15TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .1452
39.6.16TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . .1453
39.6.17TIM16 option register 1 (TIM16_OR1) . . . . .1453
39.6.18TIM16 option register 2 (TIM16_OR2) . . . . .1454
39.6.19TIM17 option register 1 (TIM17_OR1) . . . . .1455
39.6.20TIM17 option register 2 (TIM17_OR2) . . . . .1456
39.6.21TIM16/TIM17 register map . . . . .1458
40Basic timers (TIM6/TIM7) . . . . .1460
40.1TIM6/TIM7 introduction . . . . .1460
40.2TIM6/TIM7 main features . . . . .1460
40.3TIM6/TIM7 functional description . . . . .1461
40.3.1Time-base unit . . . . .1461
40.3.2Counting mode . . . . .1463
40.3.3UIF bit remapping . . . . .1466
40.3.4Clock source . . . . .1466
40.3.5Debug mode . . . . .1467
40.4TIM6/TIM7 registers . . . . .1467
40.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . .1467
40.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . .1469
40.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . .1469
40.4.4TIMx status register (TIMx_SR)(x = 6 to 7) . . . . .1470
40.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . .1470
40.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . .1470
40.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . .1471
40.4.8TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . .1471
40.4.9TIMx register map . . . . .1472
41Low-power timer (LPTIM) applied to
STM32L4Rxxx and STM32L4Sxxx only . . . . .		1473
41.1Introduction . . . . .1473
41.2LPTIM main features . . . . .1473
41.3LPTIM implementation . . . . .1474
41.4LPTIM functional description . . . . .1474
41.4.1LPTIM block diagram . . . . .1474
41.4.2LPTIM pins and internal signals . . . . .1475
41.4.3LPTIM trigger mapping . . . . .1475
41.4.4LPTIM reset and clocks . . . . .1476
41.4.5Glitch filter . . . . .1476
41.4.6Prescaler . . . . .1477
41.4.7Trigger multiplexer . . . . .1478
41.4.8Operating mode . . . . .1478
41.4.9Timeout function . . . . .1480
41.4.10Waveform generation . . . . .1480
41.4.11Register update . . . . .1481
41.4.12Counter mode . . . . .1482
41.4.13Timer enable . . . . .1482
41.4.14Timer counter reset . . . . .1483
41.4.15Encoder mode . . . . .1483
41.4.16Debug mode . . . . .1485
41.5LPTIM low-power modes . . . . .1485
41.6LPTIM interrupts . . . . .1486
41.7LPTIM registers . . . . .1486
41.7.1LPTIM interrupt and status register (LPTIM_ISR) . . . . .1487
41.7.2LPTIM interrupt clear register (LPTIM_ICR) . . . . .1488
41.7.3LPTIM interrupt enable register (LPTIM_IER) . . . . .1488
41.7.4LPTIM configuration register (LPTIM_CFGR) .....1489
41.7.5LPTIM control register (LPTIM_CR) .....1492
41.7.6LPTIM compare register (LPTIM_CMP) .....1494
41.7.7LPTIM autoreload register (LPTIM_ARR) .....1494
41.7.8LPTIM counter register (LPTIM_CNT) .....1495
41.7.9LPTIM1 option register (LPTIM1_OR) .....1495
41.7.10LPTIM2 option register (LPTIM2_OR) .....1496
41.7.11LPTIM register map .....1497
42Low-power timer (LPTIM) applied to
STM32L4P5xx and STM32L4Q5xx only .....		1499
42.1Introduction .....1499
42.2LPTIM main features .....1499
42.3LPTIM implementation .....1500
42.4LPTIM functional description .....1500
42.4.1LPTIM block diagram .....1500
42.4.2LPTIM pins and internal signals .....1501
42.4.3LPTIM trigger mapping .....1501
42.4.4LPTIM reset and clocks .....1502
42.4.5Glitch filter .....1502
42.4.6Prescaler .....1503
42.4.7Trigger multiplexer .....1504
42.4.8Operating mode .....1504
42.4.9Timeout function .....1506
42.4.10Waveform generation .....1506
42.4.11Register update .....1507
42.4.12Counter mode .....1508
42.4.13Timer enable .....1509
42.4.14Timer counter reset .....1509
42.4.15Encoder mode .....1510
42.4.16Repetition Counter .....1511
42.4.17Debug mode .....1512
42.5LPTIM low-power modes .....1513
42.6LPTIM interrupts .....1513
42.7LPTIM registers .....1514
42.7.1LPTIM interrupt and status register (LPTIM_ISR) .....1514
42.7.2LPTIM interrupt clear register (LPTIM_ICR) .....1515
42.7.3LPTIM interrupt enable register (LPTIM_IER) .....1516
42.7.4LPTIM configuration register (LPTIM_CFGR) .....1517
42.7.5LPTIM control register (LPTIM_CR) .....1520
42.7.6LPTIM compare register (LPTIM_CMP) .....1521
42.7.7LPTIM autoreload register (LPTIM_ARR) .....1521
42.7.8LPTIM counter register (LPTIM_CNT) .....1522
42.7.9LPTIM1 option register (LPTIM1_OR) .....1522
42.7.10LPTIM2 option register (LPTIM2_OR) .....1523
42.7.11LPTIM repetition register (LPTIM_RCR) .....1523
42.7.12LPTIM register map .....1524
43Infrared interface (IRTIM) .....1526
44Independent watchdog (IWDG) .....1527
44.1Introduction .....1527
44.2IWDG main features .....1527
44.3IWDG functional description .....1527
44.3.1IWDG block diagram .....1527
44.3.2Window option .....1528
44.3.3Hardware watchdog .....1529
44.3.4Low-power freeze .....1529
44.3.5Register access protection .....1529
44.3.6Debug mode .....1529
44.4IWDG registers .....1530
44.4.1IWDG key register (IWDG_KR) .....1530
44.4.2IWDG prescaler register (IWDG_PR) .....1531
44.4.3IWDG reload register (IWDG_RLR) .....1532
44.4.4IWDG status register (IWDG_SR) .....1533
44.4.5IWDG window register (IWDG_WINR) .....1534
44.4.6IWDG register map .....1535
45System window watchdog (WWDG) .....1536
45.1Introduction .....1536
45.2WWDG main features .....1536
45.3WWDG functional description .....1536
45.3.1WWDG block diagram .....1537
45.3.2Enabling the watchdog .....1537
45.3.3Controlling the down-counter .....1537
45.3.4How to program the watchdog timeout .....1537
45.3.5Debug mode .....1539
45.4WWDG interrupts .....1539
45.5WWDG registers .....1539
45.5.1WWDG control register (WWDG_CR) .....1539
45.5.2WWDG configuration register (WWDG_CFR) .....1540
45.5.3WWDG status register (WWDG_SR) .....1540
45.5.4WWDG register map .....1541
46Real-time clock (RTC) applied to
STM32L4Rxxx and STM32L4Sxxx only .....		1542
46.1Introduction .....1542
46.2RTC main features .....1543
46.3RTC functional description .....1544
46.3.1RTC block diagram .....1544
46.3.2GPIOs controlled by the RTC .....1545
46.3.3Clock and prescalers .....1547
46.3.4Real-time clock and calendar .....1548
46.3.5Programmable alarms .....1548
46.3.6Periodic auto-wakeup .....1548
46.3.7RTC initialization and configuration .....1549
46.3.8Reading the calendar .....1551
46.3.9Resetting the RTC .....1552
46.3.10RTC synchronization .....1552
46.3.11RTC reference clock detection .....1553
46.3.12RTC smooth digital calibration .....1553
46.3.13Time-stamp function .....1555
46.3.14Tamper detection .....1556
46.3.15Calibration clock output .....1558
46.3.16Alarm output .....1559
46.4RTC low-power modes .....1559
46.5RTC interrupts .....1560
46.6RTC registers .....1561
46.6.1RTC time register (RTC_TR) .....1561

47 Real-time clock (RTC) applied to STM32L4P5xx and STM32L4Q5xx only . . . . . 1587

47.3.12RTC synchronization . . . . .1599
47.3.13RTC reference clock detection . . . . .1599
47.3.14RTC smooth digital calibration . . . . .1600
47.3.15Timestamp function . . . . .1602
47.3.16Calibration clock output . . . . .1603
47.3.17Tamper and alarm output . . . . .1604
47.4RTC low-power modes . . . . .1604
47.5RTC interrupts . . . . .1605
47.6RTC registers . . . . .1606
47.6.1RTC time register (RTC_TR) . . . . .1606
47.6.2RTC date register (RTC_DR) . . . . .1607
47.6.3RTC sub second register (RTC_SSR) . . . . .1608
47.6.4RTC initialization control and status register (RTC_ICSR) . . . . .1608
47.6.5RTC prescaler register (RTC_PRER) . . . . .1610
47.6.6RTC wakeup timer register (RTC_WUTR) . . . . .1611
47.6.7RTC control register (RTC_CR) . . . . .1611
47.6.8RTC write protection register (RTC_WPR) . . . . .1615
47.6.9RTC calibration register (RTC_CALR) . . . . .1615
47.6.10RTC shift control register (RTC_SHIFTR) . . . . .1616
47.6.11RTC timestamp time register (RTC_TSTR) . . . . .1617
47.6.12RTC timestamp date register (RTC_TSDR) . . . . .1618
47.6.13RTC timestamp sub second register (RTC_TSSSR) . . . . .1618
47.6.14RTC alarm A register (RTC_ALRMAR) . . . . .1619
47.6.15RTC alarm A sub second register (RTC_ALRMASSR) . . . . .1620
47.6.16RTC alarm B register (RTC_ALRMBR) . . . . .1621
47.6.17RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .1622
47.6.18RTC status register (RTC_SR) . . . . .1623
47.6.19RTC masked interrupt status register (RTC_MISR) . . . . .1624
47.6.20RTC status clear register (RTC_SCR) . . . . .1625
47.6.21RTC alarm A binary mode register (RTC_ALRABINR) . . . . .1626
47.6.22RTC alarm B binary mode register (RTC_ALRBBINR) . . . . .1626
47.6.23RTC register map . . . . .1627
48Tamper and backup registers (TAMP) applied to
STM32L4P5xx and STM32L4Q5xx only . . . . .		1629
48.1Introduction . . . . .1629
48.2TAMP main features . . . . .1629
48.3TAMP functional description . . . . .1630
48.3.1TAMP block diagram . . . . .1630
48.3.2TAMP pins and internal signals . . . . .1630
48.3.3TAMP register write protection . . . . .1631
48.3.4Tamper detection . . . . .1631
48.4TAMP low-power modes . . . . .1634
48.5TAMP interrupts . . . . .1634
48.6TAMP registers . . . . .1634
48.6.1TAMP control register 1 (TAMP_CR1) . . . . .1635
48.6.2TAMP control register 2 (TAMP_CR2) . . . . .1636
48.6.3TAMP filter control register (TAMP_FLTCR) . . . . .1637
48.6.4TAMP interrupt enable register (TAMP_IER) . . . . .1638
48.6.5TAMP status register (TAMP_SR) . . . . .1639
48.6.6TAMP masked interrupt status register (TAMP_MISR) . . . . .1640
48.6.7TAMP status clear register (TAMP_SCR) . . . . .1641
48.6.8TAMP backup x register (TAMP_BKPxR) . . . . .1641
48.6.9TAMP register map . . . . .1643
49Inter-integrated circuit (I2C) interface . . . . .1644
49.1Introduction . . . . .1644
49.2I2C main features . . . . .1644
49.3I2C implementation . . . . .1645
49.4I2C functional description . . . . .1645
49.4.1I2C block diagram . . . . .1646
49.4.2I2C pins and internal signals . . . . .1647
49.4.3I2C clock requirements . . . . .1647
49.4.4Mode selection . . . . .1648
49.4.5I2C initialization . . . . .1648
49.4.6Software reset . . . . .1653
49.4.7Data transfer . . . . .1654
49.4.8I2C slave mode . . . . .1656
49.4.9I2C master mode . . . . .1665
49.4.10I2C_TIMINGR register configuration examples . . . . .1677
49.4.11SMBus specific features . . . . .1678
49.4.12SMBus initialization . . . . .1681
49.4.13SMBus: I2C_TIMEOUTR register configuration examples . . . . .1683
49.4.14SMBus slave mode . . . . .1684
49.4.15Wakeup from Stop mode on address match . . . . .1691
49.4.16Error conditions . . . . .1691
49.4.17DMA requests . . . . .1693
49.4.18Debug mode . . . . .1694
49.5I2C low-power modes . . . . .1694
49.6I2C interrupts . . . . .1695
49.7I2C registers . . . . .1696
49.7.1I2C control register 1 (I2C_CR1) . . . . .1696
49.7.2I2C control register 2 (I2C_CR2) . . . . .1699
49.7.3I2C own address 1 register (I2C_OAR1) . . . . .1701
49.7.4I2C own address 2 register (I2C_OAR2) . . . . .1702
49.7.5I2C timing register (I2C_TIMINGR) . . . . .1703
49.7.6I2C timeout register (I2C_TIMEOUTR) . . . . .1704
49.7.7I2C interrupt and status register (I2C_ISR) . . . . .1705
49.7.8I2C interrupt clear register (I2C_ICR) . . . . .1707
49.7.9I2C PEC register (I2C_PECR) . . . . .1708
49.7.10I2C receive data register (I2C_RXDR) . . . . .1709
49.7.11I2C transmit data register (I2C_TXDR) . . . . .1709
49.7.12I2C register map . . . . .1710
50Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .1712
50.1USART introduction . . . . .1712
50.2USART main features . . . . .1713
50.3USART extended features . . . . .1714
50.4USART implementation . . . . .1714
50.5USART functional description . . . . .1715
50.5.1USART block diagram . . . . .1715
50.5.2USART signals . . . . .1716
50.5.3USART character description . . . . .1717
50.5.4USART FIFOs and thresholds . . . . .1719
50.5.5USART transmitter . . . . .1719
50.5.6USART receiver . . . . .1723
50.5.7USART baud rate generation . . . . .1730
50.5.8Tolerance of the USART receiver to clock deviation . . . . .1731
51.4LPUART functional description . . . . .1802
51.4.1LPUART block diagram . . . . .1802
51.4.2LPUART signals . . . . .1803
51.4.3LPUART character description . . . . .1803
51.4.4LPUART FIFOs and thresholds . . . . .1804
51.4.5LPUART transmitter . . . . .1805
51.4.6LPUART receiver . . . . .1808
51.4.7LPUART baud rate generation . . . . .1812
51.4.8Tolerance of the LPUART receiver to clock deviation . . . . .1813
51.4.9LPUART multiprocessor communication . . . . .1814
51.4.10LPUART parity control . . . . .1816
51.4.11LPUART single-wire Half-duplex communication . . . . .1817
51.4.12Continuous communication using DMA and LPUART . . . . .1817
51.4.13RS232 Hardware flow control and RS485 Driver Enable . . . . .1820
51.4.14LPUART low-power management . . . . .1822
51.5LPUART in low-power modes . . . . .1825
51.6LPUART interrupts . . . . .1826
51.7LPUART registers . . . . .1827
51.7.1LPUART control register 1 [alternate] (LPUART_CR1) . . . . .1827
51.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .1830
51.7.3LPUART control register 2 (LPUART_CR2) . . . . .1833
51.7.4LPUART control register 3 (LPUART_CR3) . . . . .1835
51.7.5LPUART baud rate register (LPUART_BRR) . . . . .1838
51.7.6LPUART request register (LPUART_RQR) . . . . .1839
51.7.7LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .1839
51.7.8LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .1844
51.7.9LPUART interrupt flag clear register (LPUART_ICR) . . . . .1847
51.7.10LPUART receive data register (LPUART_RDR) . . . . .1848
51.7.11LPUART transmit data register (LPUART_TDR) . . . . .1848
51.7.12LPUART prescaler register (LPUART_PRESC) . . . . .1849
51.7.13LPUART register map . . . . .1850
52Serial peripheral interface (SPI) . . . . .1852
52.1Introduction . . . . .1852
52.2SPI main features . . . . .1852
52.3SPI implementation . . . . .1852
52.4SPI functional description . . . . .1853
52.4.1General description . . . . .1853
52.4.2Communications between one master and one slave . . . . .1854
52.4.3Standard multi-slave communication . . . . .1856
52.4.4Multi-master communication . . . . .1857
52.4.5Slave select (NSS) pin management . . . . .1858
52.4.6Communication formats . . . . .1859
52.4.7Configuration of SPI . . . . .1861
52.4.8Procedure for enabling SPI . . . . .1862
52.4.9Data transmission and reception procedures . . . . .1862
52.4.10SPI status flags . . . . .1872
52.4.11SPI error flags . . . . .1873
52.4.12NSS pulse mode . . . . .1874
52.4.13TI mode . . . . .1874
52.4.14CRC calculation . . . . .1875
52.5SPI interrupts . . . . .1877
52.6SPI registers . . . . .1878
52.6.1SPI control register 1 (SPIx_CR1) . . . . .1878
52.6.2SPI control register 2 (SPIx_CR2) . . . . .1880
52.6.3SPI status register (SPIx_SR) . . . . .1882
52.6.4SPI data register (SPIx_DR) . . . . .1883
52.6.5SPI CRC polynomial register (SPIx_CRCPR) . . . . .1884
52.6.6SPI Rx CRC register (SPIx_RXCRCR) . . . . .1884
52.6.7SPI Tx CRC register (SPIx_TXCRCR) . . . . .1884
52.6.8SPI register map . . . . .1886
53Serial audio interface (SAI) . . . . .1887
53.1Introduction . . . . .1887
53.2SAI main features . . . . .1887
53.3SAI implementation . . . . .1888
53.4SAI functional description . . . . .1888
53.4.1SAI block diagram . . . . .1888
53.4.2SAI pins and internal signals . . . . .1890
53.4.3Main SAI modes . . . . .1890
53.4.4SAI synchronization mode . . . . .1891
53.4.5Audio data size . . . . .1892
53.4.6Frame synchronization . . . . .1893
53.4.7Slot configuration . . . . .1896
53.4.8SAI clock generator . . . . .1898
53.4.9Internal FIFOs . . . . .1900
53.4.10PDM interface . . . . .1902
53.4.11AC'97 link controller . . . . .1910
53.4.12SPDIF output . . . . .1912
53.4.13Specific features . . . . .1915
53.4.14Error flags . . . . .1919
53.4.15Disabling the SAI . . . . .1922
53.4.16SAI DMA interface . . . . .1922
53.5SAI interrupts . . . . .1923
53.6SAI registers . . . . .1925
53.6.1SAI global configuration register (SAI_GCR) . . . . .1925
53.6.2SAI configuration register 1 (SAI_ACR1) . . . . .1925
53.6.3SAI configuration register 1 (SAI_BCR1) . . . . .1928
53.6.4SAI configuration register 2 (SAI_ACR2) . . . . .1931
53.6.5SAI configuration register 2 (SAI_BCR2) . . . . .1933
53.6.6SAI frame configuration register (SAI_AFR) . . . . .1935
53.6.7SAI frame configuration register (SAI_BFR) . . . . .1936
53.6.8SAI slot register (SAI_ASLOTR) . . . . .1937
53.6.9SAI slot register (SAI_BSLOTR) . . . . .1938
53.6.10SAI interrupt mask register (SAI_AIM) . . . . .1939
53.6.11SAI interrupt mask register (SAI_BIM) . . . . .1941
53.6.12SAI status register (SAI_ASR) . . . . .1942
53.6.13SAI status register (SAI_BSR) . . . . .1944
53.6.14SAI clear flag register (SAI_ACLRFR) . . . . .1946
53.6.15SAI clear flag register (SAI_BCLRFR) . . . . .1947
53.6.16SAI data register (SAI_ADR) . . . . .1948
53.6.17SAI data register (SAI_BDR) . . . . .1949
53.6.18SAI PDM control register (SAI_PDMCR) . . . . .1949
53.6.19SAI PDM delay register (SAI_PDMPLY) . . . . .1950
53.6.20SAI register map . . . . .1953
54Secure digital input/output MultiMediaCard interface (SDMMC) . . .1955
54.1SDMMC main features . . . . .1955
54.2SDMMC implementation . . . . .1955
54.3SDMMC bus topology . . . . .1956
54.4SDMMC operation modes . . . . .1958
54.5SDMMC functional description . . . . .1958
54.5.1SDMMC block diagram . . . . .1959
54.5.2SDMMC pins and internal signals . . . . .1959
54.5.3General description . . . . .1960
54.5.4SDMMC adapter . . . . .1961
54.5.5SDMMC AHB slave interface . . . . .1983
54.5.6SDMMC AHB master interface . . . . .1983
54.5.7AHB and SDMMC_CK clock relation . . . . .1985
54.6Card functional description . . . . .1986
54.6.1SD I/O mode . . . . .1986
54.6.2CMD12 send timing . . . . .1994
54.6.3Sleep (CMD5) . . . . .1997
54.6.4Interrupt mode (Wait-IRQ) . . . . .1998
54.6.5Boot operation . . . . .1999
54.6.6Response R1b handling . . . . .2002
54.6.7Reset and card cycle power . . . . .2003
54.7Hardware flow control . . . . .2004
54.8Ultra-high-speed phase I (UHS-I) voltage switch . . . . .2005
54.9SDMMC interrupts . . . . .2008
54.10SDMMC registers . . . . .2010
54.10.1SDMMC power control register (SDMMC_POWER) . . . . .2010
54.10.2SDMMC clock control register (SDMMC_CLKCR) . . . . .2011
54.10.3SDMMC argument register (SDMMC_ARGR) . . . . .2013
54.10.4SDMMC command register (SDMMC_CMDR) . . . . .2013
54.10.5SDMMC command response register (SDMMC_RESPCMDR) . . . . .2015
54.10.6SDMMC response x register (SDMMC_RESPxR) . . . . .2016
54.10.7SDMMC data timer register (SDMMC_DTIMER) . . . . .2016
54.10.8SDMMC data length register (SDMMC_DLENR) . . . . .2017
54.10.9SDMMC data control register (SDMMC_DCTRL) . . . . .2018
54.10.10SDMMC data counter register (SDMMC_DCNTR) . . . . .2019
54.10.11SDMMC status register (SDMMC_STAR) . . . . .2020
54.10.12SDMMC interrupt clear register (SDMMC_ICR) . . . . .2023
54.10.13SDMMC mask register (SDMMC_MASKR) . . . . .2025
54.10.14SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . . . .2028
54.10.15SDMMC data FIFO registers x (SDMMC_FIFORx) . . . . .2028
54.10.16SDMMC DMA control register (SDMMC_IDMACTLRLR) . . . . .2029
54.10.17SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) . . . . .2030
54.10.18SDMMC IDMA buffer 0 base address register
(SDMMC_IDMABASE0R) . . . . .		2030
54.10.19SDMMC IDMA buffer 1 base address register
(SDMMC_IDMABASE1R) . . . . .		2031
54.10.20SDMMC register map . . . . .2032
55Controller area network (bxCAN) . . . . .2035
55.1Introduction . . . . .2035
55.2bxCAN main features . . . . .2035
55.3bxCAN general description . . . . .2036
55.3.1CAN 2.0B active core . . . . .2036
55.3.2Control, status and configuration registers . . . . .2036
55.3.3Tx mailboxes . . . . .2036
55.3.4Acceptance filters . . . . .2037
55.4bxCAN operating modes . . . . .2038
55.4.1Initialization mode . . . . .2038
55.4.2Normal mode . . . . .2038
55.4.3Sleep mode (low-power) . . . . .2039
55.5Test mode . . . . .2040
55.5.1Silent mode . . . . .2040
55.5.2Loop back mode . . . . .2040
55.5.3Loop back combined with silent mode . . . . .2041
55.6Behavior in debug mode . . . . .2041
55.7bxCAN functional description . . . . .2041
55.7.1Transmission handling . . . . .2041
55.7.2Time triggered communication mode . . . . .2043
55.7.3Reception handling . . . . .2043
55.7.4Identifier filtering . . . . .2045
55.7.5Message storage . . . . .2049
55.7.6Error management . . . . .2050
55.7.7Bit timing . . . . .2050
55.8bxCAN interrupts . . . . .2054
55.9CAN registers . . . . .2055
55.9.1Register access protection . . . . .2055
56.11OTG_FS data FIFOs . . . . .2097
56.11.1Peripheral FIFO architecture . . . . .2098
56.11.2Host FIFO architecture . . . . .2099
56.11.3FIFO RAM allocation . . . . .2100
56.12OTG_FS system performance . . . . .2102
56.13OTG_FS interrupts . . . . .2102
56.14OTG_FS control and status registers . . . . .2104
56.14.1CSR memory map . . . . .2104
56.15OTG_FS registers . . . . .2109
56.15.1OTG control and status register (OTG_GOTGCTL) . . . . .2109
56.15.2OTG interrupt register (OTG_GOTGINT) . . . . .2112
56.15.3OTG AHB configuration register (OTG_GAHBCFG) . . . . .2113
56.15.4OTG USB configuration register (OTG_GUSBCFG) . . . . .2114
56.15.5OTG reset register (OTG_GRSTCTL) . . . . .2116
56.15.6OTG core interrupt register (OTG_GINTSTS) . . . . .2118
56.15.7OTG interrupt mask register (OTG_GINTMSK) . . . . .2122
56.15.8OTG receive status debug read register (OTG_GRXSTSR) . . . . .2125
56.15.9OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . .2126
56.15.10OTG status read and pop registers (OTG_GRXSTSP) . . . . .2127
56.15.11OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . . . .2128
56.15.12OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .2129
56.15.13OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . .		2129
56.15.14OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . .		2130
56.15.15OTG general core configuration register (OTG_GCCFG) . . . . .2131
56.15.16OTG core ID register (OTG_CID) . . . . .2133
56.15.17OTG core LPM configuration register (OTG_GLPMCFG) . . . . .2133
56.15.18OTG power down register (OTG_GPWRDN) . . . . .2137
56.15.19OTG ADP timer, control and status register
(OTG_GADPCTL) . . . . .		2137
56.15.20OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . .		2139
56.15.21OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . .		2140
56.15.22Host-mode registers . . . . .2140
56.15.23OTG host configuration register (OTG_HCFG) . . . . .2140
56.15.24OTG host frame interval register (OTG_HFIR) . . . . .2141
56.15.25OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . .		2142
56.15.26OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . .		2143
56.15.27OTG host all channels interrupt register (OTG_HAINT) . . . . .2144
56.15.28OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . .		2144
56.15.29OTG host port control and status register (OTG_HPRT) . . . . .2145
56.15.30OTG host channel x characteristics register (OTG_HCCHARx) . . . . .2147
56.15.31OTG host channel x interrupt register (OTG_HCINTx) . . . . .2148
56.15.32OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . . . .2149
56.15.33OTG host channel x transfer size register (OTG_HCTSIZx) . . . . .2150
56.15.34Device-mode registers . . . . .2151
56.15.35OTG device configuration register (OTG_DCFG) . . . . .2151
56.15.36OTG device control register (OTG_DCTL) . . . . .2153
56.15.37OTG device status register (OTG_DSTS) . . . . .2155
56.15.38OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . .		2156
56.15.39OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . .		2157
56.15.40OTG device all endpoints interrupt register (OTG_Daint) . . . . .2158
56.15.41OTG all endpoints interrupt mask register
(OTG_DaintMSK) . . . . .		2159
56.15.42OTG device V BUS discharge time register
(OTG_DVBUSDIS) . . . . .		2159
56.15.43OTG device V BUS pulsing time register
(OTG_DVBUSPULSE) . . . . .		2160
56.15.44OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPMPMSK) . . . . .		2160
56.15.45OTG device control IN endpoint 0 control register
(OTG_DIEPCTL0) . . . . .		2161
56.15.46OTG device IN endpoint x control register (OTG_DIEPCTLx) . . . . .2162
56.15.47OTG device IN endpoint x interrupt register (OTG_DIEPINTx) . . . . .2165
56.15.48OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) . . . . .		2166
56.15.49OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) . . . . .		2167
56.15.50OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) . . . . .2168
56.15.51OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0) . . . . .		2169
56.15.52OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . . .2170
56.15.53OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0) . . . . .		2172
56.15.54OTG device OUT endpoint x control register
(OTG_DOEPCTLx) . . . . .		2173
56.15.55OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx) . . . . .		2175
56.15.56OTG power and clock gating control register (OTG_PCGCCTL) . . .2176
56.15.57OTG_FS register map . . . . .2177
56.16OTG_FS programming model . . . . .2186
56.16.1Core initialization . . . . .2186
56.16.2Host initialization . . . . .2187
56.16.3Device initialization . . . . .2187
56.16.4Host programming model . . . . .2188
56.16.5Device programming model . . . . .2209
56.16.6Worst case response time . . . . .2230
56.16.7OTG programming model . . . . .2232
57Debug support (DBG) . . . . .2238
57.1Overview . . . . .2238
57.2Reference Arm® documentation . . . . .2239
57.3SWJ debug port (serial wire and JTAG) . . . . .2239
57.3.1Mechanism to select the JTAG-DP or the SW-DP . . . . .2240
57.4Pinout and debug port pins . . . . .2240
57.4.1SWJ debug port pins . . . . .2241
57.4.2Flexible SWJ-DP pin assignment . . . . .2241
57.4.3Internal pull-up and pull-down on JTAG pins . . . . .2242
57.4.4Using serial wire and releasing the unused debug pins as GPIOs . . .2243
57.5JTAG TAP connection . . . . .2243
57.6ID codes and locking mechanism . . . . .2244
57.6.1MCU device ID code . . . . .2245
57.6.2Boundary scan TAP . . . . .2245
57.6.3Cortex®-M4 TAP . . . . .2245
57.6.4Cortex®-M4 JEDEC-106 ID code . . . . .2246
57.7JTAG debug port . . . . .2246
57.8SW debug port . . . . .2248
57.8.1SW protocol introduction . . . . .2248
57.8.2SW protocol sequence . . . . .2248
57.8.3SW DP state machine (reset, idle states, ID code) . . . . .2249
57.8.4DP and AP read/write accesses . . . . .2249
57.8.5SW-DP registers . . . . .2250
57.8.6SW-AP registers . . . . .2251
57.9AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP . . . . .		2251
57.10Core debug . . . . .2252
57.11Capability of the debugger host to connect under system reset . . . . .2252
57.12FPB (Flash patch breakpoint) . . . . .2253
57.13DWT (data watchpoint trigger) . . . . .2253
57.14ITM (instrumentation trace macrocell) . . . . .2253
57.14.1General description . . . . .2253
57.14.2Time stamp packets, synchronization and overflow packets . . . . .2254
57.15ETM (Embedded trace macrocell) . . . . .2255
57.15.1General description . . . . .2255
57.15.2Signal protocol, packet types . . . . .2256
57.15.3Main ETM registers . . . . .2256
57.15.4Configuration example . . . . .2256
57.16MCU debug component (DBGMCU) . . . . .2257
57.16.1Debug support for low-power modes . . . . .2257
57.16.2Debug support for timers, RTC, watchdog, bxCAN and I 2 C . . . . .2257
57.16.3Debug MCU configuration register (DBGMCU_CR) . . . . .2257
57.16.4Debug MCU APB1 freeze register1 (DBGMCU_APB1FZR1) . . . . .2259
57.16.5Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2) . . . . .2261
57.16.6Debug MCU APB2 freeze register (DBGMCU_APB2FZR) . . . . .2261
57.17TPIU (trace port interface unit) . . . . .2263
57.17.1Introduction . . . . .2263
57.17.2TRACE pin assignment . . . . .2263
57.17.3TPIU formatter . . . . .2265
57.17.4TPIU frame synchronization packets . . . . .2266
57.17.5Transmission of the synchronization frame packet . . . . .2266
57.17.6Synchronous mode . . . . .2266
57.17.7Asynchronous mode . . . . .2267
57.17.8TRACECLKIN connection inside STM32L4+ Series . . . . .2267
57.17.9TPIU registers . . . . .2268

List of tables

Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary addresses . . . . . 96

Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary addresses . . . . . 101

Table 3. SRAM2 organization. . . . . 108

Table 4. Boot modes. . . . . 111

Table 5. Memory mapping versus boot mode/physical remap . . . . . 112

Table 6. Flash module - 2 Mbytes dual-bank organization, DBANK = 1 (64 bits read width) . . . . . 117

Table 7. Flash module - 2 Mbytes single-bank organization, DBANK = 0 (128 bits read width) . . . . . 117

Table 8. Flash module - 1 Mbyte dual-bank organization, DB1M = 1 (64 bits read width) . . . . . 118

Table 9. Flash module - 1 Mbyte single-bank organization, DB1M = 0 (128 bits read width) . . . . . 119

Table 10. Flash module - 512 Kbytes dual-bank organization, DB1M = 1 (64 bits read width) . . . . . 119

Table 11. Flash module - 512 Kbytes single-bank organization DB1M = 0 (128 bits read width) . . . . . 120

Table 12. Number of wait states according to CPU clock (HCLK) frequency. . . . . 122

Table 13. Option byte format . . . . . 134

Table 14. Option byte organization. . . . . 134

Table 15. Flash memory read protection status . . . . . 144

Table 16. Access status versus protection level and execution modes . . . . . 146

Table 17. PCROP protection . . . . . 148

Table 18. WRP protection. . . . . 150

Table 19. Flash interrupt request . . . . . 150

Table 20. Flash interface - register map and reset values . . . . . 168

Table 21. Segment accesses according to the Firewall state. . . . . 173

Table 22. Segment granularity and area ranges . . . . . 174

Table 23. Firewall register map and reset values. . . . . 182

Table 24. Range 1 boost mode configuration. . . . . 191

Table 25. PVM features . . . . . 195

Table 26. Low-power mode summary . . . . . 199

Table 27. Functionalities depending on the working mode. . . . . 201

Table 28. Low-power run . . . . . 205

Table 29. Sleep. . . . . 207

Table 30. Low-power sleep. . . . . 208

Table 31. Stop 0 mode . . . . . 210

Table 32. Stop 1 mode . . . . . 211

Table 33. Stop 2 mode . . . . . 213

Table 34. Standby mode. . . . . 215

Table 35. Shutdown mode . . . . . 217

Table 36. PWR register map and reset values. . . . . 237

Table 37. Clock source frequency . . . . . 252

Table 38. RCC register map and reset values . . . . . 317

Table 39. CRS features . . . . . 322

Table 40. Effect of low-power modes on CRS . . . . . 326

Table 41.Interrupt control bits . . . . .326
Table 42.CRS register map and reset values . . . . .332
Table 43.Port bit configuration table . . . . .335
Table 44.GPIO register map and reset values . . . . .349
Table 45.BOOSTEN and ANASWVDD set/reset (when at least one analog peripheral supplied by VDDA is enabled) . . . . .354
Table 46.SYSCFG register map and reset values . . . . .364
Table 47.STM32L4+ Series peripherals interconnect matrix . . . . .366
Table 48.DMA1 and DMA2 implementation . . . . .376
Table 49.DMA internal input/output signals . . . . .378
Table 50.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .383
Table 51.DMA interrupt requests . . . . .385
Table 52.DMA register map and reset values . . . . .393
Table 53.DMAMUX instantiation . . . . .397
Table 54.DMAMUX: assignment of multiplexer inputs to resources (STM32L4Rxxx and STM32L4Sxxx devices) . . . . .398
Table 55.DMAMUX: assignment of multiplexer inputs to resources (STM32L4P5xx and STM32L4Q5xx devices) . . . . .399
Table 56.DMAMUX: assignment of trigger inputs to resources (STM32L4Rxxx and STM32L4Sxxx devices) . . . . .400
Table 57.DMAMUX: assignment of trigger inputs to resources (STM32L4P5xx and STM32L4Q5xx devices) . . . . .401
Table 58.DMAMUX: assignment of synchronization inputs to resources (STM32L4Rxxx and STM32L4Sxxx devices) . . . . .401
Table 59.DMAMUX: assignment of synchronization inputs to resources (STM32L4P5xx and STM32L4Q5xx devices) . . . . .402
Table 60.DMAMUX signals . . . . .404
Table 61.DMAMUX interrupts . . . . .408
Table 62.DMAMUX register map and reset values . . . . .413
Table 63.Supported color mode in input . . . . .418
Table 64.Data order in memory . . . . .419
Table 65.Alpha mode configuration . . . . .420
Table 66.Supported CLUT color mode . . . . .421
Table 67.CLUT data order in system memory . . . . .421
Table 68.Supported color mode in output . . . . .422
Table 69.Data order in memory . . . . .422
Table 70.Standard data order in memory . . . . .423
Table 71.Output FIFO byte reordering steps . . . . .424
Table 72.DMA2D interrupt requests . . . . .430
Table 73.DMA2D register map and reset values . . . . .450
Table 74.GFXMMU interrupt requests . . . . .459
Table 75.GFXMMU register map and reset values . . . . .466
Table 76.STM32L4Rxxx and STM32L4Sxxx vector table . . . . .468
Table 77.STM32L4P5xx and STM32Q5xx vector table . . . . .471
Table 78.EXTI lines connections . . . . .479
Table 79.Extended interrupt/event controller register map and reset values . . . . .488
Table 80.CRC internal input/output signals . . . . .490
Table 81.CRC register map and reset values . . . . .495
Table 82.FMC implementation . . . . .497
Table 83.NOR/PSRAM bank selection . . . . .500
Table 84.NOR/PSRAM External memory address . . . . .500
Table 85.NAND memory mapping and timing registers . . . . .501
Table 86.NAND bank selection . . . . .501
Table 87.Programmable NOR/PSRAM access parameters . . . . .503
Table 88.Non-multiplexed I/O NOR Flash memory . . . . .503
Table 89.16-bit multiplexed I/O NOR Flash memory . . . . .504
Table 90.Non-multiplexed I/Os PSRAM/SRAM . . . . .504
Table 91.16-Bit multiplexed I/O PSRAM . . . . .504
Table 92.NOR Flash/PSRAM: example of supported memories
and transactions . . . . .		505
Table 93.FMC_BCRx bitfields (mode 1) . . . . .508
Table 94.FMC_BTRx bitfields (mode 1) . . . . .509
Table 95.FMC_BCRx bitfields (mode A) . . . . .511
Table 96.FMC_BTRx bitfields (mode A) . . . . .511
Table 97.FMC_BWTRx bitfields (mode A) . . . . .512
Table 98.FMC_BCRx bitfields (mode 2/B) . . . . .514
Table 99.FMC_BTRx bitfields (mode 2/B) . . . . .514
Table 100.FMC_BWTRx bitfields (mode 2/B) . . . . .515
Table 101.FMC_BCRx bitfields (mode C) . . . . .516
Table 102.FMC_BTRx bitfields (mode C) . . . . .517
Table 103.FMC_BWTRx bitfields (mode C) . . . . .517
Table 104.FMC_BCRx bitfields (mode D) . . . . .519
Table 105.FMC_BTRx bitfields (mode D) . . . . .520
Table 106.FMC_BWTRx bitfields (mode D) . . . . .520
Table 107.FMC_BCRx bitfields (Muxed mode) . . . . .522
Table 108.FMC_BTRx bitfields (Muxed mode) . . . . .523
Table 109.FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .528
Table 110.FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .529
Table 111.FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .530
Table 112.FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .531
Table 113.Programmable NAND Flash access parameters . . . . .540
Table 114.8-bit NAND Flash . . . . .541
Table 115.16-bit NAND Flash . . . . .542
Table 116.Supported memories and transactions . . . . .543
Table 117.ECC result relevant bits . . . . .552
Table 118.FMC register map and reset values . . . . .553
Table 119.OCTOSPI implementation . . . . .556
Table 120.Command/address phase description . . . . .566
Table 121.Address alignment cases . . . . .582
Table 122.OCTOSPI interrupt requests . . . . .583
Table 123.OCTOSPI register map and reset values . . . . .607
Table 124.OCTOSPIM implementation on STM32L4+ Series . . . . .610
Table 125.OCTOSPIM register map and reset values . . . . .616
Table 126.ADC features . . . . .619
Table 127.ADC internal input/output signals . . . . .621
Table 128.ADC input/output pins . . . . .621
Table 129.Configuring the trigger polarity for regular external triggers . . . . .638
Table 130.Configuring the trigger polarity for injected external triggers . . . . .638
Table 131.ADC1 - External triggers for regular channels . . . . .639
Table 132.ADC1 - External trigger for injected channels . . . . .640
Table 133.TSAR timings depending on resolution . . . . .652
Table 134.Offset computation versus data resolution . . . . .655
Table 135.Analog watchdog channel selection . . . . .666
Table 136.Analog watchdog 1 comparison . . . . .667
Table 137.Analog watchdog 2 and 3 comparison . . . . .667
Table 138.Maximum output results versus N and M (gray cells indicate truncation). . . . .671
Table 139.Oversampler operating modes summary . . . . .675
Table 140.ADC interrupts per each ADC. . . . .694
Table 141.DELAY bits versus ADC resolution. . . . .725
Table 142.ADC global register map. . . . .726
Table 143.ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC). . . . .727
Table 144.ADC register map and reset values (master and slave ADC common registers) offset = 0x300 . . . . .729
Table 145.DAC features . . . . .731
Table 146.DAC input/output pins. . . . .733
Table 147.DAC trigger selection . . . . .736
Table 148.Sample and refresh timings . . . . .741
Table 149.Channel output modes summary . . . . .742
Table 150.Effect of low-power modes on DAC . . . . .748
Table 151.DAC interrupts . . . . .749
Table 152.DAC register map and reset values . . . . .766
Table 153.VREF buffer modes . . . . .768
Table 154.VREFBUF register map and reset values. . . . .770
Table 155.DCMI input/output pins . . . . .772
Table 156.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .774
Table 157.Positioning of captured data bytes in 32-bit words (10-bit width) . . . . .774
Table 158.Positioning of captured data bytes in 32-bit words (12-bit width) . . . . .774
Table 159.Positioning of captured data bytes in 32-bit words (14-bit width) . . . . .775
Table 160.Data storage in monochrome progressive video format. . . . .780
Table 161.Data storage in RGB progressive video format . . . . .781
Table 162.Data storage in YCbCr progressive video format . . . . .781
Table 163.Data storage in YCbCr progressive video format - Y extraction mode . . . . .782
Table 164.DCMI interrupts. . . . .782
Table 165.DCMI register map and reset values . . . . .794
Table 166.PSSI input/output pins . . . . .797
Table 167.PSSI internal input/output signals. . . . .797
Table 168.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .798
Table 169.Positioning of captured data bytes in 32-bit words (16-bit width) . . . . .799
Table 170.PSSI interrupt requests. . . . .802
Table 171.PSSI register map and reset values . . . . .808
Table 172.COMP1 input plus assignment . . . . .811
Table 173.COMP1 input minus assignment . . . . .811
Table 174.COMP2 input plus assignment . . . . .812
Table 175.COMP2 input minus assignment . . . . .812
Table 176.Comparator behavior in the low power modes . . . . .815
Table 177.Interrupt control bits . . . . .816
Table 178.COMP register map and reset values. . . . .821
Table 179.Operational amplifier possible connections . . . . .823
Table 180.Operating modes and calibration . . . . .828
Table 181.Effect of low-power modes on the OPAMP . . . . .829
Table 182.OPAMP register map and reset values . . . . .834
Table 183.STM32L4Rxxx and STM32L4Sxxx DFSDM1 implementation . . . . .837
Table 184.STM32L4P5xx and STM32L4Q5xx DFSDM1 implementation . . . . .837
Table 185.DFSDM external pins . . . . .839
Table 186.DFSDM internal signals . . . . .839
Table 187.DFSDM triggers connection . . . . .839
Table 188.DFSDM break connection. . . . .840
Table 189.Filter maximum output resolution (peak data values from filter output) for some FOSR values . . . . .855
Table 190.Integrator maximum output resolution (peak data values from integrator output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . . .856
Table 191.DFSDM interrupt requests . . . . .864
Table 192.DFSDM register map and reset values. . . . .885
Table 193.LTDC implementation . . . . .895
Table 194.LTDC pins and signal interface. . . . .896
Table 195.Clock domain for each register . . . . .897
Table 196.Pixel data mapping versus color format . . . . .902
Table 197.LTDC interrupt requests . . . . .906
Table 198.LTDC register map and reset values . . . . .926
Table 199.DSI pins . . . . .932
Table 200.DSI internal input/output signals . . . . .933
Table 201.Location of color components in the LTDC interface . . . . .936
Table 202.Multiplicity of the payload size in pixels for each data type . . . . .937
Table 203.Contention detection timeout counters configuration . . . . .949
Table 204.List of events of different categories of the PRESP_TO counter . . . . .950
Table 205.PRESP_TO counter configuration . . . . .953
Table 206.Frame requirement configuration registers. . . . .965
Table 207.RGB components . . . . .967
Table 208.Slew-rate and delay tuning . . . . .969
Table 209.Custom lane configuration . . . . .970
Table 210.Custom timing parameters . . . . .970
Table 211.DSI Wrapper interrupt requests . . . . .973
Table 212.Error causes and recovery . . . . .975
Table 213.DSI register map and reset values . . . . .1041
Table 214.Acquisition sequence summary . . . . .1050
Table 215.Spread spectrum deviation versus AHB clock frequency. . . . .1052
Table 216.I/O state depending on its mode and IODEF bit value . . . . .1053
Table 217.Effect of low-power modes on TSC . . . . .1055
Table 218.Interrupt control bits . . . . .1055
Table 219.TSC register map and reset values . . . . .1064
Table 220.RNG internal input/output signals . . . . .1067
Table 221.RNG interrupt requests. . . . .1074
Table 222.RNG register map and reset map. . . . .1078
Table 223.RNG internal input/output signals . . . . .1080
Table 224.RNG interrupt requests. . . . .1088
Table 225.RNG configurations . . . . .1088
Table 226.RNG register map and reset map. . . . .1093
Table 227.AES internal input/output signals . . . . .1095
Table 228.CTR mode initialization vector definition. . . . .1112
Table 229.GCM last block definition . . . . .1114
Table 230.Initialization of SAES_IVRx registers in GCM mode. . . . .1115
Table 231.Initialization of AES_IVRx registers in CCM mode . . . . .1122
Table 232.Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .1127
Table 233.AES interrupt requests . . . . .1130
Table 234.Processing latency for ECB, CBC and CTR. . . . .1131
Table 235.Processing latency for GCM and CCM (in clock cycles). . . . .1131
Table 236.AES register map and reset values . . . . .1141
Table 237.HASH internal input/output signals . . . . .1145
Table 238.Hash processor outputs . . . . .1148
Table 239.HASH interrupt requests . . . . .1155
Table 240.Processing time (in clock cycle) . . . . .1155
Table 241.HASH register map and reset values . . . . .1164
Table 242.Internal input/output signals . . . . .1167
Table 243.PKA integer arithmetic functions list . . . . .1168
Table 244.PKA prime field (Fp) elliptic curve functions list . . . . .1168
Table 245.Montgomery parameter computation . . . . .1173
Table 246.Modular addition . . . . .1174
Table 247.Modular subtraction . . . . .1174
Table 248.Montgomery multiplication . . . . .1175
Table 249.Modular exponentiation (normal mode) . . . . .1176
Table 250.Modular exponentiation (fast mode) . . . . .1176
Table 251.Modular inversion . . . . .1176
Table 252.Modular reduction . . . . .1177
Table 253.Arithmetic addition . . . . .1177
Table 254.Arithmetic subtraction . . . . .1177
Table 255.Arithmetic multiplication . . . . .1178
Table 256.Arithmetic comparison . . . . .1178
Table 257.CRT exponentiation . . . . .1179
Table 258.Point on elliptic curve Fp check . . . . .1180
Table 259.ECC Fp scalar multiplication . . . . .1180
Table 260.ECC Fp scalar multiplication (Fast Mode) . . . . .1181
Table 261.ECDSA sign - Inputs . . . . .1182
Table 262.ECDSA sign - Outputs . . . . .1182
Table 263.Extended ECDSA sign (extra outputs) . . . . .1183
Table 264.ECDSA verification (inputs) . . . . .1183
Table 265.ECDSA verification (outputs) . . . . .1183
Table 266.Family of supported curves for ECC operations . . . . .1184
Table 267.Modular exponentiation computation times . . . . .1186
Table 268.ECC scalar multiplication computation times . . . . .1186
Table 269.ECDSA signature average computation times . . . . .1186
Table 270.ECDSA verification average computation times . . . . .1187
Table 271.Point on elliptic curve Fp check average computation times . . . . .1187
Table 272.Montgomery parameters average computation times . . . . .1187
Table 273.PKA interrupt requests . . . . .1187
Table 274.PKA register map and reset values . . . . .1191
Table 275.Behavior of timer outputs versus BRK/BRK2 inputs . . . . .1233
Table 276.Break protection disarming conditions . . . . .1235
Table 277.Counting direction versus encoder signals . . . . .1241
Table 278.TIMx internal trigger connection . . . . .1258
Table 279.Output control bits for complementary OCx and OCxN channels with break feature . . . . .1272
Table 280.TIM1 register map and reset values . . . . .1293
Table 281.TIM8 register map and reset values . . . . .1295
Table 282.Counting direction versus encoder signals . . . . .1332
Table 283.TIMx internal trigger connection . . . . .1349
Table 284.Output control bit for standard OCx channels . . . . .1360
Table 285.TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . .1368
Table 286.Break protection disarming conditions . . . . .1399
Table 287.TIMx Internal trigger connection . . . . .1415
Table 288.Output control bits for complementary OCx and OCxN channels with break feature
(TIM15) . . . . .1425
Table 289. TIM15 register map and reset values . . . . .1434
Table 290. Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . . . . .1447
Table 291. TIM16/TIM17 register map and reset values . . . . .1458
Table 292. TIMx register map and reset values . . . . .1472
Table 293. STM32L4Rxxx and STM32L4Sxxx LPTIM features . . . . .1474
Table 294. LPTIM input/output pins . . . . .1475
Table 295. LPTIM internal signals . . . . .1475
Table 296. LPTIM1 external trigger connection . . . . .1475
Table 297. LPTIM2 external trigger connection . . . . .1476
Table 298. Prescaler division ratios . . . . .1477
Table 299. Encoder counting scenarios . . . . .1484
Table 300. Effect of low-power modes on the LPTIM . . . . .1485
Table 301. Interrupt events . . . . .1486
Table 302. LPTIM register map and reset values . . . . .1497
Table 303. STM32L4Pxxx and STM32L4Qxxx LPTIM features . . . . .1500
Table 304. LPTIM input/output pins . . . . .1501
Table 305. LPTIM internal signals . . . . .1501
Table 306. LPTIM1 external trigger connection . . . . .1501
Table 307. LPTIM2 external trigger connection . . . . .1502
Table 308. Prescaler division ratios . . . . .1503
Table 309. Encoder counting scenarios . . . . .1510
Table 310. Effect of low-power modes on the LPTIM . . . . .1513
Table 311. Interrupt events . . . . .1513
Table 312. LPTIM register map and reset values . . . . .1524
Table 313. IWDG register map and reset values . . . . .1535
Table 314. WWDG register map and reset values . . . . .1541
Table 315. RTC pin PC13 configuration . . . . .1545
Table 316. RTC_OUT mapping . . . . .1546
Table 317. RTC functions over modes . . . . .1547
Table 318. Effect of low-power modes on RTC . . . . .1559
Table 319. Interrupt control bits . . . . .1560
Table 320. RTC register map and reset values . . . . .1585
Table 321. RTC input/output pins . . . . .1589
Table 322. RTC internal input/output signals . . . . .1589
Table 323. RTC interconnection . . . . .1589
Table 324. PC13 configuration . . . . .1590
Table 325. RTC_OUT mapping . . . . .1592
Table 326. Effect of low-power modes on RTC . . . . .1604
Table 327. RTC pins functionality over modes . . . . .1605
Table 328. Interrupt requests . . . . .1605
Table 329. RTC register map and reset values . . . . .1627
Table 330. TAMP input/output pins . . . . .1630
Table 331. TAMP internal input/output signals . . . . .1631
Table 332. TAMP interconnection . . . . .1631
Table 333. Effect of low-power modes on TAMP . . . . .1634
Table 334. Interrupt requests . . . . .1634
Table 335. TAMP register map and reset values . . . . .1643
Table 336. I2C implementation . . . . .1645
Table 337. I2C input/output pins . . . . .1647
Table 338. I2C internal input/output signals . . . . .1647
Table 339.Comparison of analog vs. digital filters . . . . .1649
Table 340.I2C-SMBus specification data setup and hold times . . . . .1652
Table 341.I2C configuration. . . . .1656
Table 342.I2C-SMBus specification clock timings . . . . .1667
Table 343.Examples of timing settings for fI2CCLK = 8 MHz . . . . .1677
Table 344.Examples of timings settings for fI2CCLK = 16 MHz . . . . .1677
Table 345.Examples of timings settings for fI2CCLK = 48 MHz . . . . .1678
Table 346.SMBus timeout specifications . . . . .1680
Table 347.SMBus with PEC configuration . . . . .1682
Table 348.Examples of TIMEOUTA settings for various I2CCLK frequencies
(max t TIMEOUT = 25 ms) . . . . .		1683
Table 349.Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . .1683
Table 350.Examples of TIMEOUTA settings for various I2CCLK frequencies
(max t IDLE = 50 µs) . . . . .		1683
Table 351.Effect of low-power modes on the I2C . . . . .1694
Table 352.I2C Interrupt requests . . . . .1695
Table 353.I2C register map and reset values . . . . .1710
Table 354.USART / LPUART features . . . . .1714
Table 355.Noise detection from sampled data . . . . .1729
Table 356.Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .1732
Table 357.Tolerance of the USART receiver when BRR[3:0] is different from 0000. . . . .1733
Table 358.USART frame formats . . . . .1738
Table 359.Effect of low-power modes on the USART . . . . .1761
Table 360.USART interrupt requests. . . . .1762
Table 361.USART register map and reset values . . . . .1797
Table 362.USART / LPUART features . . . . .1801
Table 363.Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz . . . . .1812
Table 364.Error calculation for programmed baud rates at fCK = 100 MHz . . . . .1813
Table 365.Tolerance of the LPUART receiver. . . . .1814
Table 367.Effect of low-power modes on the LPUART . . . . .1825
Table 368.LPUART interrupt requests. . . . .1826
Table 369.LPUART register map and reset values . . . . .1850
Table 370.STM32L4Rxxx/STM32L4Sxxx and STM32L4P5xx/STM32L4Q5xx SPI implementation1853
Table 371.SPI interrupt requests . . . . .1877
Table 372.SPI register map and reset values . . . . .1886
Table 373.STM32L4S/STM32L4R SAI features . . . . .1888
Table 374.SAI internal input/output signals . . . . .1890
Table 375.SAI input/output pins. . . . .1890
Table 376.External synchronization selection . . . . .1892
Table 377.Clock generator programming examples . . . . .1900
Table 378.TDM settings. . . . .1907
Table 379.TDM frame configuration examples . . . . .1909
Table 380.SOPD pattern . . . . .1913
Table 381.Parity bit calculation . . . . .1913
Table 382.Audio sampling frequency versus symbol rates . . . . .1914
Table 383.SAI interrupt sources . . . . .1923
Table 384.SAI register map and reset values . . . . .1953
Table 385.STM32L4Rxxx and STM32L4Sxxx SDMMC features . . . . .1955
Table 386.STM32L4P5xx and STM32L4Q5xx SDMMC features . . . . .1955
Table 387.SDMMC operation modes SD & SDIO . . . . .1958
Table 388.SDMMC operation modes e•MMC . . . . .1958
Table 389.SDMMC internal input/output signals . . . . .1959
Table 390.SDMMC pins . . . . .1959
Table 391.SDMMC Command and data phase selection . . . . .1961
Table 392.Command token format . . . . .1966
Table 393.Short response with CRC token format . . . . .1967
Table 394.Short response without CRC token format . . . . .1967
Table 395.Long response with CRC token format . . . . .1967
Table 396.Specific Commands overview . . . . .1968
Table 397.Command path status flags . . . . .1969
Table 398.Command path error handling . . . . .1969
Table 399.Data token format . . . . .1977
Table 400.Data path status flags and clear bits . . . . .1977
Table 401.Data path error handling . . . . .1979
Table 402.Data FIFO access . . . . .1980
Table 403.Transmit FIFO status flags . . . . .1981
Table 404.Receive FIFO status flags . . . . .1982
Table 405.AHB and SDMMC_CK clock frequency relation . . . . .1985
Table 406.SDIO special operation control . . . . .1986
Table 407.4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . .1990
Table 408.CMD12 use cases . . . . .1994
Table 409.SDMMC interrupts . . . . .2008
Table 410.Response type and SDMMC_RESPxR registers . . . . .2016
Table 411.SDMMC register map . . . . .2032
Table 412.Transmit mailbox mapping . . . . .2049
Table 413.Receive mailbox mapping . . . . .2049
Table 414.bxCAN register map and reset values . . . . .2075
Table 415.OTG_FS speeds supported . . . . .2079
Table 416.OTG_FS implementation . . . . .2082
Table 417.OTG_FS input/output pins . . . . .2083
Table 418.OTG_FS input/output signals . . . . .2084
Table 419.Compatibility of STM32 low power modes with the OTG . . . . .2096
Table 420.Core global control and status registers (CSRs) . . . . .2104
Table 421.Host-mode control and status registers (CSRs) . . . . .2105
Table 422.Device-mode control and status registers . . . . .2106
Table 423.Data FIFO (DFIFO) access register map . . . . .2108
Table 424.Power and clock gating control and status registers . . . . .2108
Table 425.TRDT values (FS) . . . . .2115
Table 426.Minimum duration for soft disconnect . . . . .2154
Table 427.OTG_FS register map and reset values . . . . .2177
Table 428.SWJ debug port pins . . . . .2241
Table 429.Flexible SWJ-DP pin assignment . . . . .2241
Table 430.JTAG debug port data registers . . . . .2246
Table 431.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .2247
Table 432.Packet request (8-bits) . . . . .2248
Table 433.ACK response (3 bits) . . . . .2249
Table 434.DATA transfer (33 bits) . . . . .2249
Table 435.SW-DP registers . . . . .2250
Table 436.Cortex®-M4 AHB-AP registers . . . . .2251
Table 437.Core debug registers . . . . .2252
Table 438.Main ITM registers . . . . .2254
Table 439.Main ETM registers . . . . .2256
Table 440.Asynchronous TRACE pin assignment . . . . .2263
Table 441.Synchronous TRACE pin assignment . . . . .2264
Table 442. Flexible TRACE pin assignment . . . . .2264
Table 443. Important TPIU registers. . . . .2268
Table 444. DBGMCU register map and reset values . . . . .2270
Table 445. Document revision history . . . . .2274

List of figures

Figure 1.System architecture for STM32L4Rxxx and STM32L4Sxxx . . . . .89
Figure 2.System architecture for STM32L4P5xx and STM32L4Q5xx . . . . .90
Figure 3.Memory map for STM32L4Rxxx and STM32L4Sxxx . . . . .94
Figure 4.Memory map for STM32L4P5xx and STM32L4Q5xx . . . . .95
Figure 5.Sequential 16-bit instructions execution (64-bit read data width) . . . . .125
Figure 6.Changing the Read protection (RDP) level. . . . .146
Figure 7.STM32L4+ Series firewall connection schematics . . . . .171
Figure 8.Firewall functional states . . . . .175
Figure 9.STM32L4P5xx/Q5xx, STM32L4S5xx/R5xx and STM32L4S7xx/L4R7xx
power supply overview . . . . .		184
Figure 10.STM32L4S9xx/L4R9xx power supply overview . . . . .185
Figure 11.Internal main regulator overview. . . . .189
Figure 12.Brown-out reset waveform . . . . .194
Figure 13.PVD thresholds . . . . .194
Figure 14.Low-power modes possible transitions. . . . .198
Figure 15.Simplified diagram of the reset circuit. . . . .240
Figure 16.Clock tree for STM32L4Rxxx and STM32L4Sxxx devices . . . . .244
Figure 17.DSI clock tree . . . . .245
Figure 18.Clock tree for STM32L4P5xx and STM32L4Q5xx devices. . . . .246
Figure 19.HSE/ LSE clock sources. . . . .247
Figure 20.Frequency measurement with TIM15 in capture mode. . . . .255
Figure 21.Frequency measurement with TIM16 in capture mode. . . . .256
Figure 22.Frequency measurement with TIM17 in capture mode. . . . .256
Figure 23.CRS block diagram. . . . .323
Figure 24.CRS counter behavior . . . . .324
Figure 25.Basic structure of an I/O port bit . . . . .334
Figure 26.Basic structure of a 5-Volt tolerant I/O port bit . . . . .334
Figure 27.Input floating/pull up/pull down configurations . . . . .339
Figure 28.Output configuration . . . . .340
Figure 29.Alternate function configuration . . . . .340
Figure 30.High impedance-analog configuration . . . . .341
Figure 31.DMA block diagram . . . . .377
Figure 32.DMAMUX block diagram . . . . .403
Figure 33.Synchronization mode of the DMAMUX request line multiplexer channel . . . . .406
Figure 34.Event generation of the DMA request line multiplexer channel . . . . .406
Figure 35.DMA2D block diagram . . . . .417
Figure 36.Intel 8080 16-bit mode (RGB565). . . . .423
Figure 37.Intel 8080 18/24-bit mode (RGB888) . . . . .424
Figure 38.GFXMMU block diagram . . . . .453
Figure 39.Virtual buffer . . . . .454
Figure 40.Virtual buffer and physical buffer memory map . . . . .455
Figure 41.MMU block diagram . . . . .456
Figure 42.Block validation/comparator implementation . . . . .457
Figure 43.Configurable interrupt/event block diagram . . . . .477
Figure 44.External interrupt/event GPIO mapping . . . . .479
Figure 45.CRC calculation unit block diagram . . . . .490
Figure 46.FMC block diagram. . . . .497
Figure 47.FMC memory banks . . . . .500
Figure 48.Mode 1 read access waveforms . . . . .507
Figure 49.Mode 1 write access waveforms . . . . .508
Figure 50.Mode A read access waveforms . . . . .510
Figure 51.Mode A write access waveforms . . . . .510
Figure 52.Mode 2 and mode B read access waveforms . . . . .512
Figure 53.Mode 2 write access waveforms . . . . .513
Figure 54.Mode B write access waveforms . . . . .513
Figure 55.Mode C read access waveforms . . . . .515
Figure 56.Mode C write access waveforms . . . . .516
Figure 57.Mode D read access waveforms . . . . .518
Figure 58.Mode D write access waveforms . . . . .519
Figure 59.Muxed read access waveforms . . . . .521
Figure 60.Muxed write access waveforms . . . . .522
Figure 61.Asynchronous wait during a read access waveforms . . . . .524
Figure 62.Asynchronous wait during a write access waveforms . . . . .525
Figure 63.Wait configuration waveforms . . . . .527
Figure 64.Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . .528
Figure 65.Synchronous multiplexed write mode waveforms - PSRAM (CRAM) . . . . .530
Figure 66.NAND Flash controller waveforms for common memory access . . . . .544
Figure 67.Access to non 'CE don't care' NAND-Flash . . . . .545
Figure 68.OCTOSPI block diagram in octal configuration . . . . .557
Figure 69.OCTOSPI block diagram in quad configuration . . . . .557
Figure 70.OCTOSPI block diagram in dual-quad configuration . . . . .558
Figure 71.SDR read command in octal configuration . . . . .559
Figure 72.DTR read in Octal-SPI mode with DQS (Macronix mode) example . . . . .562
Figure 73.SDR write command in Octo-SPI mode example . . . . .564
Figure 74.DTR write in Octal-SPI mode (Macronix mode) example . . . . .564
Figure 75.Example of HyperBus read operation . . . . .566
Figure 76.HyperBus write operation with initial latency . . . . .567
Figure 77.HyperBus read operation with additional latency . . . . .567
Figure 78.HyperBus write operation with additional latency . . . . .568
Figure 79.HyperBus write operation with no latency . . . . .568
Figure 80.HyperBus read operation page crossing with latency . . . . .569
Figure 81.NCS when CKMODE = 0 (T = CLK period) . . . . .580
Figure 82.NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .581
Figure 83.NCS when CKMODE = 1 in DTR mode (T = CLK period) . . . . .581
Figure 84.NCS when CKMODE = 1 with an abort (T = CLK period) . . . . .581
Figure 85.OCTOSPIM block diagram for SMT32L4P5xx and STM32L4Q5xx . . . . .611
Figure 86.OCTOSPIM block diagram for SMT32L4Rxxx and STM32L4Sxxx . . . . .611
Figure 87.ADC block diagram . . . . .620
Figure 88.ADC clock scheme . . . . .623
Figure 89.ADC1 connectivity . . . . .624
Figure 90.ADC2 connectivity . . . . .625
Figure 91.ADC calibration . . . . .628
Figure 92.Updating the ADC calibration factor . . . . .629
Figure 93.Mixing single-ended and differential channels . . . . .629
Figure 94.Enabling / disabling the ADC . . . . .631
Figure 95.Analog to digital conversion time . . . . .636
Figure 96.Stopping ongoing regular conversions . . . . .637
Figure 97.Stopping ongoing regular and injected conversions . . . . .637
Figure 98.Triggers sharing between ADC master and ADC slave . . . . .639
Figure 99.Injected conversion latency . . . . .642
Figure 100. Example of JSQR queue of context (sequence change) . . . . .645
Figure 101. Example of JSQR queue of context (trigger change) . . . . .645
Figure 102. Example of JSQR queue of context with overflow before conversion . . . . .646
Figure 103. Example of JSQR queue of context with overflow during conversion . . . . .646
Figure 104. Example of JSQR queue of context with empty queue (case JQM=0). . . . .647
Figure 105. Example of JSQR queue of context with empty queue (case JQM=1). . . . .648
Figure 106. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion. . . . .		648
Figure 107. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . .		649
Figure 108. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs outside an ongoing conversion . . . . .		649
Figure 109. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . .650
Figure 110. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . .650
Figure 111. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . .651
Figure 112. Single conversions of a sequence, software trigger . . . . .653
Figure 113. Continuous conversion of a sequence, software trigger. . . . .653
Figure 114. Single conversions of a sequence, hardware trigger . . . . .654
Figure 115. Continuous conversions of a sequence, hardware trigger . . . . .654
Figure 116. Right alignment (offset disabled, unsigned value) . . . . .656
Figure 117. Right alignment (offset enabled, signed value). . . . .657
Figure 118. Left alignment (offset disabled, unsigned value) . . . . .657
Figure 119. Left alignment (offset enabled, signed value). . . . .658
Figure 120. Example of overrun (OVR) . . . . .659
Figure 121. AUTODLY=1, regular conversion in continuous mode, software trigger . . . . .662
Figure 122. AUTODLY=1, regular HW conversions interrupted by injected conversions
(DISCEN=0; JDISCEN=0) . . . . .		663
Figure 123. AUTODLY=1, regular HW conversions interrupted by injected conversions
(DISCEN=1, JDISCEN=1) . . . . .		664
Figure 124. AUTODLY=1, regular continuous conversions interrupted by injected conversions . . . . .665
Figure 125. AUTODLY=1 in auto- injected mode (JAUTO=1). . . . .665
Figure 126. Analog watchdog guarded area . . . . .666
Figure 127. ADC y _AWD x _OUT signal generation (on all regular channels). . . . .668
Figure 128. ADC y _AWD x _OUT signal generation (AWD x flag not cleared by software) . . . . .669
Figure 129. ADC y _AWD x _OUT signal generation (on a single regular channel) . . . . .669
Figure 130. ADC y _AWD x _OUT signal generation (on all injected channels) . . . . .669
Figure 131. 20-bit to 16-bit result truncation . . . . .670
Figure 132. Numerical example with 5-bit shift and rounding . . . . .670
Figure 133. Triggered regular oversampling mode (TROVS bit = 1). . . . .672
Figure 134. Regular oversampling modes (4x ratio) . . . . .673
Figure 135. Regular and injected oversampling modes used simultaneously . . . . .674
Figure 136. Triggered regular oversampling with injection . . . . .674
Figure 137. Oversampling in auto-injected mode . . . . .675
Figure 138. Dual ADC block diagram (1) . . . . .677
Figure 139. Injected simultaneous mode on 4 channels: dual ADC mode . . . . .678
Figure 140. Regular simultaneous mode on 16 channels: dual ADC mode . . . . .680
Figure 141. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . .681
Figure 142. Interleaved mode on 1 channel in single conversion mode: dual ADC mode. . . . .682
Figure 143. Interleaved conversion with injection . . . . .682
Figure 144. Alternate trigger: injected group of each ADC . . . . .683
Figure 145. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode. . . . .684
Figure 146. Alternate + regular simultaneous . . . . .685
Figure 147. Case of trigger occurring during injected conversion . . . . .685
Figure 148. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . .686
Figure 149. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . .		686
Figure 150. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . .		686
Figure 151. DMA Requests in regular simultaneous mode when MDMA=0b00 . . . . .687
Figure 152. DMA requests in regular simultaneous mode when MDMA=0b10 . . . . .688
Figure 153. DMA requests in interleaved mode when MDMA=0b10 . . . . .688
Figure 154. Temperature sensor channel block diagram . . . . .690
Figure 155. VBAT channel block diagram . . . . .691
Figure 156. VREFINT channel block diagram . . . . .692
Figure 157. Dual-channel DAC block diagram . . . . .732
Figure 158. Data registers in single DAC channel mode . . . . .734
Figure 159. Data registers in dual DAC channel mode . . . . .734
Figure 160. Timing diagram for conversion with trigger disabled TEN = 0 . . . . .735
Figure 161. DAC LFSR register calculation algorithm . . . . .738
Figure 162. DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .738
Figure 163. DAC triangle wave generation . . . . .739
Figure 164. DAC conversion (SW trigger enabled) with triangle wave generation . . . . .739
Figure 165. DAC Sample and hold mode phase diagram . . . . .742
Figure 166. DCMI block diagram . . . . .772
Figure 167. Top-level block diagram . . . . .772
Figure 168. DCMI signal waveforms . . . . .773
Figure 169. Timing diagram . . . . .775
Figure 170. Frame capture waveforms in snapshot mode . . . . .777
Figure 171. Frame capture waveforms in continuous grab mode . . . . .778
Figure 172. Coordinates and size of the window after cropping . . . . .778
Figure 173. Data capture waveforms . . . . .779
Figure 174. Pixel raster scan order . . . . .780
Figure 175. PSSI block diagram . . . . .796
Figure 176. Top-level block diagram . . . . .796
Figure 177. Data enable in receive mode waveform diagram (CKPOL=0) . . . . .800
Figure 178. Data enable waveform diagram in transmit mode (CKPOL=0) . . . . .800
Figure 179. Ready in receive mode waveform diagram (CKPOL=0) . . . . .801
Figure 180. Bidirectional PSSI_DE/PSSI_RDY waveform . . . . .802
Figure 181. Bidirectional PSSI_DE/PSSI_RDY connection diagram . . . . .802
Figure 182. Comparator block diagram . . . . .811
Figure 183. Window mode . . . . .813
Figure 184. Comparator hysteresis . . . . .814
Figure 185. Comparator output blanking . . . . .814
Figure 186. Standalone mode: external gain setting mode . . . . .824
Figure 187. Follower configuration . . . . .825
Figure 188. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . .826
Figure 189. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for
filtering . . . . .		827
Figure 190. Single DFSDM block diagram . . . . .838
Figure 191. Input channel pins redirection . . . . .842
Figure 192. Channel transceiver timing diagrams . . . . .845
Figure 193. Clock absence timing diagram for SPI . . . . .846
Figure 194. Clock absence timing diagram for Manchester coding . . . . .847
Figure 195. First conversion for Manchester coding (Manchester synchronization) . . . . .849
Figure 196. DFSDM_CHyDATINR registers operation modes and assignment . . . . .853
Figure 197. Example: Sinc3 filter response . . . . .855
Figure 198. LTDC block diagram . . . . .896
Figure 199. LCD-TFT synchronous timings . . . . .899
Figure 200. Layer window programmable parameters . . . . .902
Figure 201. Blending two layers with background . . . . .905
Figure 202. Interrupt events . . . . .906
Figure 203. DSI block diagram . . . . .932
Figure 204. DSI Host architecture . . . . .934
Figure 205. Flow to update the LTDC interface configuration using shadow registers . . . . .939
Figure 206. Immediate update procedure . . . . .940
Figure 207. Configuration update during the transmission of a frame . . . . .940
Figure 208. Adapted command mode usage flow . . . . .942
Figure 209. 24 bpp APB pixel to byte organization . . . . .946
Figure 210. 18 bpp APB pixel to byte organization . . . . .947
Figure 211. 16 bpp APB pixel to byte organization . . . . .947
Figure 212. 12 bpp APB pixel to byte organization . . . . .948
Figure 213. 8 bpp APB pixel to byte organization . . . . .948
Figure 214. Timing of PRESP_TO after a bus-turn-around . . . . .951
Figure 215. Timing of PRESP_TO after a read request (HS or LP). . . . .952
Figure 216. Timing of PRESP_TO after a write request (HS or LP) . . . . .953
Figure 217. Effect of prep mode at 1 . . . . .954
Figure 218. Command transmission periods within the image area . . . . .955
Figure 219. Transmission of commands on the last line of a frame. . . . .956
Figure 220. LPSIZE for non-burst with sync pulses . . . . .957
Figure 221. LPSIZE for burst or non-burst with sync events . . . . .957
Figure 222. VLPSIZE for non-burst with sync pulses . . . . .959
Figure 223. VLPSIZE for non-burst with sync events . . . . .959
Figure 224. VLPSIZE for burst mode . . . . .959
Figure 225. Location of LPSIZE and VLPSIZE in the image area . . . . .961
Figure 226. Clock lane and data lane in HS . . . . .962
Figure 227. Clock lane in HS and data lanes in LP . . . . .963
Figure 228. Clock lane and data lane in LP . . . . .963
Figure 229. Command transmission by the generic interface . . . . .964
Figure 230. Vertical color bar mode . . . . .966
Figure 231. Horizontal color bar mode . . . . .966
Figure 232. RGB888 BER testing pattern . . . . .967
Figure 233. Vertical pattern (103x15) . . . . .968
Figure 234. Horizontal pattern (103x15) . . . . .968
Figure 235. PLL block diagram . . . . .972
Figure 236. Error sources . . . . .975
Figure 237. Video packet transmission configuration flow diagram. . . . .986
Figure 238. Programming sequence to send a test pattern. . . . .988
Figure 239. Frame configuration registers . . . . .989
Figure 240. TSC block diagram . . . . .1048
Figure 241. Surface charge transfer analog I/O group structure . . . . .1049
Figure 242. Sampling capacitor voltage variation . . . . .1050
Figure 243. Charge transfer acquisition sequence . . . . .1051
Figure 244. Spread spectrum variation principle . . . . .1052
Figure 245. RNG block diagram . . . . .1067
Figure 246. Entropy source model. . . . .1068
Figure 247. RNG initialization overview . . . . .1071
Figure 248. RNG block diagram . . . . .1080
Figure 249. NIST SP800-90B entropy source model. . . . .1081
Figure 250. RNG initialization overview . . . . .1084
Figure 251. AES block diagram . . . . .1095
Figure 252. ECB encryption and decryption principle . . . . .1097
Figure 253. CBC encryption and decryption principle . . . . .1098
Figure 254. CTR encryption and decryption principle . . . . .1099
Figure 255. GCM encryption and authentication principle . . . . .1100
Figure 256. GMAC authentication principle . . . . .1100
Figure 257. CCM encryption and authentication principle . . . . .1101
Figure 258. Encryption key derivation for ECB/CBC decryption (Mode 2). . . . .1104
Figure 259. Example of suspend mode management . . . . .1105
Figure 260. ECB encryption . . . . .1106
Figure 261. ECB decryption . . . . .1106
Figure 262. CBC encryption . . . . .1107
Figure 263. CBC decryption . . . . .1107
Figure 264. ECB/CBC encryption (Mode 1). . . . .1108
Figure 265. ECB/CBC decryption (Mode 3). . . . .1109
Figure 266. Message construction in CTR mode. . . . .1111
Figure 267. CTR encryption . . . . .1112
Figure 268. CTR decryption . . . . .1112
Figure 269. Message construction in GCM . . . . .1114
Figure 270. GCM authenticated encryption . . . . .1115
Figure 271. Message construction in GMAC mode . . . . .1119
Figure 272. GMAC authentication mode . . . . .1119
Figure 273. Message construction in CCM mode . . . . .1120
Figure 274. CCM mode authenticated encryption . . . . .1122
Figure 275. 128-bit block construction with respect to data swap . . . . .1126
Figure 276. DMA transfer of a 128-bit data block during input phase . . . . .1128
Figure 277. DMA transfer of a 128-bit data block during output phase . . . . .1129
Figure 278. HASH block diagram . . . . .1144
Figure 279. Message data swapping feature . . . . .1146
Figure 280. HASH suspend/resume mechanism . . . . .1152
Figure 281. PKA block diagram . . . . .1167
Figure 282. Advanced-control timer block diagram . . . . .1193
Figure 283. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1195
Figure 284. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1195
Figure 285. Counter timing diagram, internal clock divided by 1 . . . . .1197
Figure 286. Counter timing diagram, internal clock divided by 2 . . . . .1197
Figure 287. Counter timing diagram, internal clock divided by 4 . . . . .1198
Figure 288. Counter timing diagram, internal clock divided by N . . . . .1198
Figure 289. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1199
Figure 290. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .1199
Figure 291. Counter timing diagram, internal clock divided by 1 . . . . .1201
Figure 292. Counter timing diagram, internal clock divided by 2 . . . . .1201
Figure 293. Counter timing diagram, internal clock divided by 4 . . . . .1202
Figure 294. Counter timing diagram, internal clock divided by N . . . . .1202
Figure 295. Counter timing diagram, update event when repetition counter is not used. . . . .1203
Figure 296. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .1204
Figure 297. Counter timing diagram, internal clock divided by 2 . . . . .1205
Figure 298. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .1205
Figure 299. Counter timing diagram, internal clock divided by N . . . . .1206
Figure 300. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .1206
Figure 301. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .1207
Figure 302. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1208
Figure 303. External trigger input block . . . . .1209
Figure 304. TIM1 ETR input circuitry . . . . .1209
Figure 305. TIM8 ETR input circuitry . . . . .1209
Figure 306. Control circuit in normal mode, internal clock divided by 1 . . . . .1210
Figure 307. TI2 external clock connection example. . . . .1211
Figure 308. Control circuit in external clock mode 1 . . . . .1212
Figure 309. External trigger input block . . . . .1212
Figure 310. Control circuit in external clock mode 2 . . . . .1213
Figure 311. Capture/compare channel (example: channel 1 input stage) . . . . .1214
Figure 312. Capture/compare channel 1 main circuit . . . . .1215
Figure 313. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .1215
Figure 314. Output stage of capture/compare channel (channel 4). . . . .1216
Figure 315. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .1216
Figure 316. PWM input mode timing . . . . .1218
Figure 317. Output compare mode, toggle on OC1 . . . . .1220
Figure 318. Edge-aligned PWM waveforms (ARR=8) . . . . .1221
Figure 319. Center-aligned PWM waveforms (ARR=8) . . . . .1222
Figure 320. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1224
Figure 321. Combined PWM mode on channel 1 and 3 . . . . .1225
Figure 322. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .1226
Figure 323. Complementary output with dead-time insertion . . . . .1227
Figure 324. Dead-time waveforms with delay greater than the negative pulse . . . . .1227
Figure 325. Dead-time waveforms with delay greater than the positive pulse. . . . .1228
Figure 326. Break and Break2 circuitry overview . . . . .1230
Figure 327. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .1232
Figure 328. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .1233
Figure 329. PWM output state following BRK assertion (OSSI=0) . . . . .1234
Figure 330. Output redirection (BRK2 request not represented) . . . . .1235
Figure 331. Clearing TIMx OCxREF . . . . .1236
Figure 332. 6-step generation, COM example (OSSR=1) . . . . .1237
Figure 333. Example of one pulse mode. . . . .1238
Figure 334. Retriggerable one pulse mode . . . . .1240
Figure 335. Example of counter operation in encoder interface mode. . . . .1241
Figure 336. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .1242
Figure 337. Measuring time interval between edges on 3 signals . . . . .1243
Figure 338. Example of Hall sensor interface . . . . .1245
Figure 339. Control circuit in reset mode . . . . .1246
Figure 340. Control circuit in Gated mode . . . . .1247
Figure 341. Control circuit in trigger mode . . . . .1248
Figure 342. Control circuit in external clock mode 2 + trigger mode . . . . .1249
Figure 343. General-purpose timer block diagram . . . . .1299
Figure 344. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1301
Figure 345. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1301
Figure 346. Counter timing diagram, internal clock divided by 1 . . . . .1302
Figure 347. Counter timing diagram, internal clock divided by 2 . . . . .1303
Figure 348. Counter timing diagram, internal clock divided by 4 . . . . .1303
Figure 349. Counter timing diagram, internal clock divided by N. . . . .1304
Figure 350. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1304
Figure 351. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .1305
Figure 352. Counter timing diagram, internal clock divided by 1 . . . . .1306
Figure 353. Counter timing diagram, internal clock divided by 2 . . . . .1306
Figure 354. Counter timing diagram, internal clock divided by 4 . . . . .1307
Figure 355. Counter timing diagram, internal clock divided by N . . . . .1307
Figure 356. Counter timing diagram, Update event when repetition counter is not used . . . . .1308
Figure 357. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .1309
Figure 358. Counter timing diagram, internal clock divided by 2 . . . . .1310
Figure 359. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .1310
Figure 360. Counter timing diagram, internal clock divided by N . . . . .1311
Figure 361. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .1311
Figure 362. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .1312
Figure 363. Control circuit in normal mode, internal clock divided by 1 . . . . .1313
Figure 364. TI2 external clock connection example. . . . .1313
Figure 365. Control circuit in external clock mode 1 . . . . .1314
Figure 366. External trigger input block . . . . .1315
Figure 367. Control circuit in external clock mode 2 . . . . .1316
Figure 368. Capture/Compare channel (example: channel 1 input stage) . . . . .1317
Figure 369. Capture/Compare channel 1 main circuit . . . . .1317
Figure 370. Output stage of Capture/Compare channel (channel 1). . . . .1318
Figure 371. PWM input mode timing . . . . .1320
Figure 372. Output compare mode, toggle on OC1 . . . . .1322
Figure 373. Edge-aligned PWM waveforms (ARR=8). . . . .1323
Figure 374. Center-aligned PWM waveforms (ARR=8). . . . .1324
Figure 375. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1325
Figure 376. Combined PWM mode on channels 1 and 3 . . . . .1327
Figure 377. Clearing TIMx_OCxREF . . . . .1328
Figure 378. Example of one-pulse mode. . . . .1329
Figure 379. Retriggerable one-pulse mode. . . . .1331
Figure 380. Example of counter operation in encoder interface mode . . . . .1332
Figure 381. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .1333
Figure 382. Control circuit in reset mode . . . . .1334
Figure 383. Control circuit in gated mode . . . . .1335
Figure 384. Control circuit in trigger mode . . . . .1336
Figure 385. Control circuit in external clock mode 2 + trigger mode . . . . .1337
Figure 386. Master/Slave timer example . . . . .1337
Figure 387. Master/slave connection example with 1 channel only timers . . . . .1338
Figure 388. Gating TIM2 with OC1REF of TIM3 . . . . .1339
Figure 389. Gating TIM2 with Enable of TIM3 . . . . .1340
Figure 390. Triggering TIM2 with update of TIM3 . . . . .1340
Figure 391. Triggering TIM2 with Enable of TIM3 . . . . .1341
Figure 392. Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . .1342
Figure 393. TIM15 block diagram . . . . .1373
Figure 394. TIM16/TIM17 block diagram . . . . .1374
Figure 395. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1376
Figure 396. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1376
Figure 397. Counter timing diagram, internal clock divided by 1 . . . . .1378
Figure 398. Counter timing diagram, internal clock divided by 2 . . . . .1378
Figure 399. Counter timing diagram, internal clock divided by 4 . . . . .1379
Figure 400. Counter timing diagram, internal clock divided by N . . . . .1379
Figure 401. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . .1380
Figure 402. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . .		1380
Figure 403. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1382
Figure 404. Control circuit in normal mode, internal clock divided by 1 . . . . .1383
Figure 405. TI2 external clock connection example. . . . .1383
Figure 406. Control circuit in external clock mode 1 . . . . .1384
Figure 407. Capture/compare channel (example: channel 1 input stage). . . . .1385
Figure 408. Capture/compare channel 1 main circuit . . . . .1385
Figure 409. Output stage of capture/compare channel (channel 1). . . . .1386
Figure 410. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .1386
Figure 411. PWM input mode timing . . . . .1388
Figure 412. Output compare mode, toggle on OC1 . . . . .1390
Figure 413. Edge-aligned PWM waveforms (ARR=8) . . . . .1391
Figure 414. Combined PWM mode on channel 1 and 2 . . . . .1392
Figure 415. Complementary output with dead-time insertion. . . . .1393
Figure 416. Dead-time waveforms with delay greater than the negative pulse. . . . .1393
Figure 417. Dead-time waveforms with delay greater than the positive pulse. . . . .1394
Figure 418. Break circuitry overview . . . . .1396
Figure 419. Output behavior in response to a break . . . . .1398
Figure 420. Output redirection . . . . .1400
Figure 421. Example of one pulse mode . . . . .1402
Figure 422. Retriggerable one pulse mode . . . . .1403
Figure 423. Measuring time interval between edges on 2 signals . . . . .1405
Figure 424. Control circuit in reset mode . . . . .1406
Figure 425. Control circuit in gated mode . . . . .1407
Figure 426. Control circuit in trigger mode . . . . .1408
Figure 427. Basic timer block diagram. . . . .1460
Figure 428. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1462
Figure 429. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1462
Figure 430. Counter timing diagram, internal clock divided by 1 . . . . .1463
Figure 431. Counter timing diagram, internal clock divided by 2 . . . . .1464
Figure 432. Counter timing diagram, internal clock divided by 4 . . . . .1464
Figure 433. Counter timing diagram, internal clock divided by N . . . . .1465
Figure 434. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . .		1465
Figure 435. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . .		1466
Figure 436. Control circuit in normal mode, internal clock divided by 1 . . . . .1467
Figure 437. Low-power timer block diagram . . . . .1474
Figure 438. Glitch filter timing diagram . . . . .1477
Figure 439. LPTIM output waveform, single counting mode configuration . . . . .1479
Figure 440. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set). . . . .		1479
Figure 441. LPTIM output waveform, Continuous counting mode configuration . . . . .1480
Figure 442. Waveform generation . . . . .1481
Figure 443. Encoder mode counting sequence . . . . .1485
Figure 444. Low-power timer block diagram . . . . .1500
Figure 445. Glitch filter timing diagram . . . . .1503
Figure 446. LPTIM output waveform, single counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . .		1505
Figure 447. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . .1505
Figure 448. LPTIM output waveform, Continuous counting mode configuration . . . . .1506
Figure 449. Waveform generation . . . . .1507
Figure 450. Encoder mode counting sequence . . . . .1511
Figure 451. Continuous counting mode when repetition register LPTIM_RCR different from zero (with PRELOAD = 1). . . . .1512
Figure 452. IRTIM internal hardware connections with TIM16 and TIM17 . . . . .1526
Figure 453. Independent watchdog block diagram . . . . .1527
Figure 454. Watchdog block diagram . . . . .1537
Figure 455. Window watchdog timing diagram . . . . .1538
Figure 456. RTC block diagram . . . . .1544
Figure 457. RTC block diagram . . . . .1588
Figure 458. TAMP block diagram . . . . .1630
Figure 459. I2C block diagram . . . . .1646
Figure 460. I2C bus protocol . . . . .1648
Figure 461. Setup and hold timings . . . . .1650
Figure 462. I2C initialization flowchart . . . . .1653
Figure 463. Data reception . . . . .1654
Figure 464. Data transmission . . . . .1655
Figure 465. Slave initialization flowchart . . . . .1658
Figure 466. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH= 0 . . . . .1660
Figure 467. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH= 1 . . . . .1661
Figure 468. Transfer bus diagrams for I2C slave transmitter . . . . .1662
Figure 469. Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . .1663
Figure 470. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . .1664
Figure 471. Transfer bus diagrams for I2C slave receiver . . . . .1664
Figure 472. Master clock generation . . . . .1666
Figure 473. Master initialization flowchart . . . . .1668
Figure 474. 10-bit address read access with HEAD10R=0 . . . . .1668
Figure 475. 10-bit address read access with HEAD10R=1 . . . . .1669
Figure 476. Transfer sequence flowchart for I2C master transmitter for N≤255 bytes . . . . .1670
Figure 477. Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . .1671
Figure 478. Transfer bus diagrams for I2C master transmitter . . . . .1672
Figure 479. Transfer sequence flowchart for I2C master receiver for N≤255 bytes . . . . .1674
Figure 480. Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . .1675
Figure 481. Transfer bus diagrams for I2C master receiver . . . . .1676
Figure 482. Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .1680
Figure 483. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC . . . . .1684
Figure 484. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . .1685
Figure 485. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . .1686
Figure 486. Bus transfer diagrams for SMBus slave receiver (SBC=1). . . . .1687
Figure 487. Bus transfer diagrams for SMBus master transmitter . . . . .1688
Figure 488. Bus transfer diagrams for SMBus master receiver . . . . .1690
Figure 489. USART block diagram . . . . .1715
Figure 490. Word length programming . . . . .1718
Figure 491. Configurable stop bits . . . . .1720
Figure 492. TC/TXE behavior when transmitting . . . . .1723
Figure 493. Start bit detection when oversampling by 16 or 8. . . . .1724
Figure 494. usart_ker_ck clock divider block diagram . . . . .1727
Figure 495. Data sampling when oversampling by 16 . . . . .1728
Figure 496.Data sampling when oversampling by 8 . . . . .1729
Figure 497.Mute mode using Idle line detection . . . . .1736
Figure 498.Mute mode using address mark detection . . . . .1737
Figure 499.Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .1740
Figure 500.Break detection in LIN mode vs. Framing error detection. . . . .1741
Figure 501.USART example of synchronous master transmission. . . . .1742
Figure 502.USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		1742
Figure 503.USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		1743
Figure 504.USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		1744
Figure 505.ISO 7816-3 asynchronous protocol . . . . .1746
Figure 506.Parity error detection using the 1.5 stop bits . . . . .1748
Figure 507.IrDA SIR ENDEC block diagram. . . . .1752
Figure 508.IrDA data modulation (3/16) - Normal mode. . . . .1752
Figure 509.Transmission using DMA . . . . .1754
Figure 510.Reception using DMA . . . . .1755
Figure 511.Hardware flow control between 2 USARTs . . . . .1755
Figure 512.RS232 RTS flow control . . . . .1756
Figure 513.RS232 CTS flow control . . . . .1757
Figure 514.Wakeup event verified (wakeup event = address match, FIFO disabled) . . . . .1760
Figure 515.Wakeup event not verified (wakeup event = address match,
FIFO disabled) . . . . .		1760
Figure 516.LPUART block diagram . . . . .1802
Figure 517.LPUART word length programming . . . . .1804
Figure 518.Configurable stop bits . . . . .1806
Figure 519.TC/TXE behavior when transmitting . . . . .1808
Figure 520.lpuart_ker_ck clock divider block diagram . . . . .1811
Figure 521.Mute mode using Idle line detection . . . . .1815
Figure 522.Mute mode using address mark detection . . . . .1816
Figure 523.Transmission using DMA . . . . .1818
Figure 524.Reception using DMA . . . . .1819
Figure 525.Hardware flow control between 2 LPUARTs . . . . .1820
Figure 526.RS232 RTS flow control . . . . .1820
Figure 527.RS232 CTS flow control . . . . .1821
Figure 528.Wakeup event verified (wakeup event = address match,
FIFO disabled) . . . . .		1824
Figure 529.Wakeup event not verified (wakeup event = address match,
FIFO disabled) . . . . .		1824
Figure 530.SPI block diagram. . . . .1853
Figure 531.Full-duplex single master/ single slave application. . . . .1854
Figure 532.Half-duplex single master/ single slave application . . . . .1855
Figure 533.Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		1856
Figure 534.Master and three independent slaves. . . . .1857
Figure 535.Multi-master application . . . . .1858
Figure 536.Hardware/software slave select management . . . . .1859
Figure 537.Data clock timing diagram . . . . .1860
Figure 538.Data alignment when data length is not equal to 8-bit or 16-bit . . . . .1861
Figure 539.Packing data in FIFO for transmission and reception. . . . .1865
Figure 540.Master full-duplex communication . . . . .1868
Figure 541. Slave full-duplex communication . . . . .1869
Figure 542. Master full-duplex communication with CRC . . . . .1870
Figure 543. Master full-duplex communication in packed mode . . . . .1871
Figure 544. NSSP pulse generation in Motorola SPI master mode . . . . .1874
Figure 545. TI mode transfer . . . . .1875
Figure 546. SAI functional block diagram . . . . .1889
Figure 547. Audio frame . . . . .1893
Figure 548. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .1895
Figure 549. FS role is start of frame (FSDEF = 0) . . . . .1896
Figure 550. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .1897
Figure 551. First bit offset . . . . .1897
Figure 552. Audio block clock generator overview . . . . .1898
Figure 553. PDM typical connection and timing . . . . .1902
Figure 554. Detailed PDM interface block diagram . . . . .1903
Figure 555. Start-up sequence . . . . .1904
Figure 556. SAI_ADR format in TDM, 32-bit slot width . . . . .1905
Figure 557. SAI_ADR format in TDM, 16-bit slot width . . . . .1906
Figure 558. SAI_ADR format in TDM, 8-bit slot width . . . . .1907
Figure 559. AC'97 audio frame . . . . .1910
Figure 560. Example of typical AC'97 configuration on devices featuring at least
2 embedded SAIs (three external AC'97 decoders) . . . . .		1911
Figure 561. SPDIF format . . . . .1912
Figure 562. SAI_xDR register ordering . . . . .1913
Figure 563. Data companding hardware in an audio block in the SAI . . . . .1917
Figure 564. Tristate strategy on SD output line on an inactive slot . . . . .1918
Figure 565. Tristate on output data line in a protocol like I2S . . . . .1919
Figure 566. Overrun detection error . . . . .1920
Figure 567. FIFO underrun event . . . . .1920
Figure 568. SDMMC “no response” and “no data” operations . . . . .1956
Figure 569. SDMMC (multiple) block read operation . . . . .1956
Figure 570. SDMMC (multiple) block write operation . . . . .1957
Figure 571. SDMMC (sequential) stream read operation . . . . .1957
Figure 572. SDMMC (sequential) stream write operation . . . . .1957
Figure 573. SDMMC block diagram . . . . .1959
Figure 574. SDMMC Command and data phase relation . . . . .1960
Figure 575. Control unit . . . . .1962
Figure 576. Command/response path . . . . .1963
Figure 577. Command path state machine (CPSM) . . . . .1964
Figure 578. Data path . . . . .1970
Figure 579. DDR mode data packet clocking . . . . .1971
Figure 580. DDR mode CRC status / boot acknowledgment clocking . . . . .1971
Figure 581. Data path state machine (DPSM) . . . . .1972
Figure 582. CLKMUX unit . . . . .1983
Figure 583. Asynchronous interrupt generation . . . . .1987
Figure 584. Synchronous interrupt period data read . . . . .1987
Figure 585. Synchronous interrupt period data write . . . . .1988
Figure 586. Asynchronous interrupt period data read . . . . .1989
Figure 587. Asynchronous interrupt period data write . . . . .1989
Figure 588. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25 . . . . .1992
Figure 589. Clock stop with SDMMC_CK for DDR50, SDR50 . . . . .1992
Figure 590. Read Wait with SDMMC_CK < 50 MHz . . . . .1993
Figure 591. Read Wait with SDMMC_CK > 50 MHz . . . . .1994
Figure 592. CMD12 stream timing . . . . .1996
Figure 593. CMD5 Sleep Awake procedure . . . . .1998
Figure 594. Normal boot mode operation . . . . .2000
Figure 595. Alternative boot mode operation . . . . .2001
Figure 596. Command response R1b busy signaling . . . . .2002
Figure 597. SDMMC state control . . . . .2003
Figure 598. Card cycle power / power up diagram . . . . .2004
Figure 599. CMD11 signal voltage switch sequence . . . . .2005
Figure 600. Voltage switch transceiver typical application . . . . .2007
Figure 601. CAN network topology . . . . .2036
Figure 602. Dual-CAN block diagram . . . . .2037
Figure 603. bxCAN operating modes . . . . .2039
Figure 604. bxCAN in silent mode . . . . .2040
Figure 605. bxCAN in loop back mode . . . . .2040
Figure 606. bxCAN in combined mode . . . . .2041
Figure 607. Transmit mailbox states . . . . .2043
Figure 608. Receive FIFO states . . . . .2044
Figure 609. Filter bank scale configuration - Register organization . . . . .2046
Figure 610. Example of filter numbering . . . . .2047
Figure 611. Filtering mechanism example . . . . .2048
Figure 612. CAN error state diagram . . . . .2050
Figure 613. Bit timing . . . . .2052
Figure 614. CAN frames . . . . .2053
Figure 615. Event flags and interrupt generation . . . . .2054
Figure 616. CAN mailbox registers . . . . .2066
Figure 617. OTG_FS full-speed block diagram . . . . .2083
Figure 618. OTG_FS A-B device connection . . . . .2085
Figure 619. OTG_FS peripheral-only connection . . . . .2087
Figure 620. OTG_FS host-only connection . . . . .2091
Figure 621. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .2095
Figure 622. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .2097
Figure 623. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .2098
Figure 624. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . .2099
Figure 625. Interrupt hierarchy . . . . .2103
Figure 626. Transmit FIFO write task . . . . .2189
Figure 627. Receive FIFO read task . . . . .2190
Figure 628. Normal bulk/control OUT/SETUP . . . . .2191
Figure 629. Bulk/control IN transactions . . . . .2195
Figure 630. Normal interrupt OUT . . . . .2198
Figure 631. Normal interrupt IN . . . . .2203
Figure 632. Isochronous OUT transactions . . . . .2205
Figure 633. Isochronous IN transactions . . . . .2208
Figure 634. Receive FIFO packet read . . . . .2212
Figure 635. Processing a SETUP packet . . . . .2214
Figure 636. Bulk OUT transaction . . . . .2221
Figure 637. TRDT max timing case . . . . .2231
Figure 638. A-device SRP . . . . .2232
Figure 639. B-device SRP . . . . .2233
Figure 640. A-device HNP . . . . .2234
Figure 641. B-device HNP . . . . .2236
Figure 642. Block diagram of STM32 MCU and Cortex ® -M4-level debug support . . . . .2238
Figure 643. SWJ debug port . . . . .2240

Figure 644. JTAG TAP connections . . . . . 2244
Figure 645. TPIU block diagram . . . . . 2263

Chapters