37. Revision history

• – Updated Arm word and added logo.
• USB section:
  • – Complete re-mastering of the section
  • – Added Section 32.4.2: OTG_FS/OTG_HS pin and internal signals.
  • – Updated Section 32.15.16: OTG core ID register (OTG_CID).
  • – Updated Section 32.15.41: OTG all endpoints interrupt mask register (OTG_DAINTRMSK) replacing bit 18 by bit 19 in OEPN bit description.
• Memory organization section
  • – Added Figure 1: Memory map.
• System and memory overview section
  • – Updated Figure 2: System architecture for STM32F72xxx and STM32F73xxx devices.
• Flash memory section:
  • – Updated Section 3.7.7: Flash option control register (FLASH_OPTCR1) and Section 3.7.8: Flash interface register map reset value at '0x0040 0080'.
• DMA section
  • – Updated Section 8.2: DMA main features 'up to 16channels per stream'.
  • – Updated Section 8.5.5: DMA stream x configuration register (DMA_SxCR) and Section 8.5.11: DMA register map CHSEL mapped from 2 to 3 bits.
• RCC section
  • Updated Figure 14: Clock tree OTG_HS_SCL renamed by OTG_HS_ULPI_CK.
  • Update Section 5.3.21: RCC clock control & status register (RCC_CSR) bit RMVF put in read/write.
  • Updated Section 5.3.27: RCC register map PADRSTF in PINRSTF.
  • Updated Section 5.3.20: RCC backup domain control register (RCC_BDCR) adding LSEDRV[1:0] in the description.
  • Updated Section 5.3.14: RCC APB2 peripheral clock enable register (RCC_APB2ENR) ADC1EN, ADC2EN and ADC2EN are enabled when bit set to '1'.
• PWR section:
  • Updated Section 4.1.3: Battery backup domain note removing 'only one I/O at a time can be used as an output' sentence.
  • Updated Section 4.1.3: Battery backup domain step 3 of 'Access to the backup SRAM' paragraph.
  • Updated Section 4.4.2: PWR power control/status register (PWR_CSR1) bits[19:18] UDRDY[1:0] description.

FMC section:
Updated Section : SDRAM control register x (FMC_SDCRx) replacing 'KCK_FMC' by 'HCLK' in RPIPE[1:0] description.

RTC section
Updated Section 25.6.3: RTC control register (RTC_CR) WUTE bit description adding note.
Updated Figure 287: RTC block diagram WUCKSEL dividers for /2,4,8,16.

Serial audio section:
– Updated Section 29.5.18: SAI register map MCJDIV by MCKDIV bit name.

SDMMC section:
Updated Section 30.8.8: SDMMC data length register (SDMMC_DLEN) note.

General-purpose timer section:
– Updated Section 19.4.3: TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) Bits 6:4 TS: Trigger selection description removing 'reserved'.
– Added Section 20.3.12: Retriggerable one pulse mode (TIM12 only) .
– Added Section 20.3.13: UIF bit remapping .
– Added Section 20.3.13: UIF bit remapping .

USART section:
– Updated Section 27.5.4: USART baud rate generation note, replacing '0d16' by '16d'.

Updated documentation convention section:

• – Added Section 1.1: General information .

Updated system architecture section:

• – Updated Figure 2: System architecture for STM32F72xxx and STM32F73xxx devices .

Updated memory organization section:

• – Updated Figure 1: Memory map .

Updated embedded Flash memory section:

• – Updated Section 3.3.1: Flash memory organization and added Table 4: STM32F730xx Flash memory organization .

Updated PWR section:

• – Updated title of Figure 5: STM32F7x2xx and STM32F730xx power supply overview and Figure 6: STM32F7x3xx and STM32F730xx power supply overview .
• – Added note 3 below Figure 6: STM32F7x3xx and STM32F730xx power supply overview about packages supporting the integrated OTG_HS PHY.

Updated RCC section:

• – Updated note1 and note2 below Figure 14: Clock tree .
• – Updated note1 adding STM32F730xx devices in Section 5.3.9: RCC APB2 peripheral reset register (RCC_APB2RSTR) and Section 5.3.14: RCC APB2 peripheral clock enable register (RCC_APB2ENR) .

Updated ADC section:

• – Updated Section 14.10: Temperature sensor .

Updated SAI section:

• – Updated title of Section 29.5.14: SAI interrupt mask register (SAI_BIM) and Section 29.5.14: SAI interrupt mask register (SAI_BIM) .

Updated USB section:

• – Updated Table 225: OTG_FS/OTG_HS implementation and added note2.

Updated USB PHY section:

• – Updated title of Section 33: USB PHY controller (USBPHYC) available on the STM32F7x3xx and STM32F730xx devices only .

Updated electronic signature section:

• – Updated Section 35.3: Package data register : '0x1FF0 7BF0' instead of '0x1FFF 7BF0' and Bits 10:8 PKG[2:0] description.