1. Documentation conventions

1.1 General information

The STM32F72xxx and STM32F73xxx devices have an Arm ^®(a) Cortex ^® -M7 core.

1.2 List of abbreviations for registers

The following abbreviations ^(b) are used in register descriptions:

1.3 Register reset value

Bits (binary notation) or bits nibbles (hexadecimal notation) of which the reset value is undefined are marked as X.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of them may not be used in the current document.

Bits (binary notation) or bits nibbles (hexadecimal notation) of which the reset value is unmodified are marked as U.

1.4 Glossary

This section gives a brief definition of acronyms and abbreviations used in this document:

• • The CPU core integrates two debug ports:
  • – JTAG debug port ( JTAG-DP ) provides a 5-pin standard interface based on the Joint Test Action Group (JTAG) protocol.
  • – SWD debug port ( SWD-DP ) provides a 2-pin (clock and data) interface based on the Serial Wire Debug (SWD) protocol.

For both the JTAG and SWD protocols, refer to the Cortex®-M7 Technical Reference Manual.

• • Word : data of 32-bit length.
• • Half-word : data of 16-bit length.
• • Byte : data of 8-bit length.
• • Double word : data of 64-bit length.
• • IAP (in-application programming) : IAP is the ability to re-program the flash memory of a microcontroller while the user program is running.
• • ICP (in-circuit programming) : ICP is the ability to program the flash memory of a microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the device is mounted on the user application board.
• • Option bytes : device configuration bits stored in the flash memory.
• • AHB : advanced high-performance bus.
• • AHBS : AHB slave bus.
• • AXIM : AXI master bus.
• • ITCM : Instruction tightly coupled memory.
• • DTCM : Data tightly coupled memory.
• • CPU : refers to the Cortex®-M7 core.

1.5 Availability of peripherals

For availability of peripherals and their number across all devices, refer to the particular device datasheet.

1.6 Memory organization

1.6.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

The addressable memory space is divided into eight main blocks, of 512 Mbytes each.

1.6.2 Memory map and register boundary addresses

Figure 1. Memory map

MSv41006V2

All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to the following table.

The following table gives the boundary addresses of the peripherals available in the devices.

Table 1. STM32F72xxx and STM32F73xxx register boundary addresses

Table 1. STM32F72xxx and STM32F73xxx register boundary addresses (continued)

1.7 Embedded SRAM

The STM32F72xxx and STM32F73xxx feature:

• • System SRAM up to 256 Kbytes including Data TCM RAM 64 Kbytes
• • Instruction RAM (ITCM-RAM) 16 Kbytes.
• • 4 Kbytes of backup SRAM (see section 5.1.2: Battery backup domain)

The embedded SRAM is divided into up to four blocks:

• • System SRAM:
  • – SRAM1 mapped at address 0x2001 0000 and accessible by all AHB masters from AHB bus Matrix.
  • – SRAM2 mapped at address 0x2003 C000 and accessible by all AHB masters from AHB bus Matrix.
  • – DTCM-RAM on TCM interface (Tightly Coupled Memory interface) mapped at address 0x2000 0000 and accessible by all AHB masters from AHB bus Matrix but through a specific AHB slave bus of the CPU.
• • Instruction SRAM:
  • – Instruction RAM (ITCM-RAM) mapped at address 0x0000 0000 and accessible only by CPU.

The SRAM1 and SRAM2 can be accessed as bytes, half-words (16 bits) or full words (32 bits). While DTCM and ITCM RAMs can be accessed as bytes, half-words (16 bits), full words (32 bits) or double words (64 bits). These memories can be addressed at maximum system clock frequency without wait state.

The AHB masters support concurrent SRAM accesses (from the USB OTG HS): for instance, the USB OTG HS can read/write from/to SRAM2 while the CPU is reading/writing from/to SRAM1.

1.8 Flash memory overview

The Flash memory interface manages CPU AXI and TCM accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. It accelerates code execution with ART on TCM interface or L1-Cache on AXIM interface.

The Flash memory is organized as follows:

• • A main memory block divided into sectors.
• • An information block:
  • – System memory from which the device boots in System memory boot mode
  • – 528 OTP (one-time programmable) bytes for user data.
  • – Option bytes to configure read and write protection, BOR level, software/hardware watchdog, boot memory base address and reset when the device is in Standby or Stop mode.

Refer to Section 3: Embedded Flash memory (FLASH) for more details.

1.9 Boot configuration

In the STM32F72xxx and STM32F73xxx, two different boot areas can be selected through the BOOT pin and the boot base address programmed in the BOOT_ADD0 and BOOT_ADD1 option bytes as shown in the Table 2 .

Table 2. Boot modes

The values on the BOOT pin are latched on the 4th rising edge of SYSCLK after reset release. It is up to the user to set the BOOT pin after reset.

The BOOT pin is also resampled when the device exits the Standby mode. Consequently, they must be kept in the required Boot mode configuration when the device is in the Standby mode.

After startup delay, the selection of the boot area is done before releasing the processor reset.

The BOOT_ADD0 and BOOT_ADD1 address option bytes allows to program any boot memory address from 0x0000 0000 to 0x2003 FFFF which includes:

• • All Flash address space mapped on ITCM or AXIM interface
• • All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface
• • The System memory bootloader

The BOOT_ADD0 / BOOT_ADD1 option bytes can be modified after reset in order to boot from any other boot address after next reset.

If the programmed boot memory address is out of the memory mapped area or a reserved area, the default boot fetch address is programmed as follows:

• – Boot address 0: ITCM-FLASH at 0x0020 0000
• – Boot address 1: ITCM-RAM at 0x0000 0000

When flash level 2 protection is enabled, only boot from Flash (on ITCM or AXIM interface) or system bootloader will be available. If the already programmed boot address in the BOOT_ADD0 and/or BOOT_ADD1 option bytes is out of the memory range or RAM address (on ITCM or AXIM) the default fetch will be forced from Flash on ITCM interface at address 0x00200000.

Embedded bootloader

The embedded bootloader code is located in the system memory. It is programmed by ST during production. For full information, refer to the application note (AN2606) STM32 microcontroller system memory boot mode.

By default, when the boot from system bootloader is selected, the code is executed from TCM interface. It could be executed from AXIM interface by reprogramming the BOOT_ADDx address option bytes to 0x1FF0 0000.