RM0431-STM32F72-73

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32F72xxx and STM32F73xxx microcontroller memory and peripherals.

The STM32F72xxx and STM32F73xxx is a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics refer to the datasheets.

For information on the Arm ® Cortex ® -M7 with FPU core, refer to the Cortex ® -M7 with FPU technical reference manual.

STM32F72xxx and STM32F73xxx microcontrollers include ST state-of-the-art patented technology.

Available from STMicroelectronics web site www.st.com :

Contents

3.3.4Unlocking the Flash control register . . . . .72
3.3.5Maximum program/erase parallelism . . . . .72
3.3.6Flash erase sequences . . . . .73
3.3.7Flash programming sequences . . . . .73
3.3.8Flash Interrupts . . . . .75
3.4FLASH Option bytes . . . . .75
3.4.1Option bytes description . . . . .75
3.4.2Option bytes programming . . . . .79
3.5FLASH memory protection . . . . .80
3.5.1Read protection (RDP) . . . . .80
3.5.2Write protections . . . . .82
3.5.3Proprietary code readout protection (PCROP) . . . . .83
3.6One-time programmable bytes . . . . .84
3.7FLASH registers . . . . .85
3.7.1Flash access control register (FLASH_ACR) . . . . .85
3.7.2Flash key register (FLASH_KEYR) . . . . .86
3.7.3Flash option key register (FLASH_OPTKEYR) . . . . .86
3.7.4Flash status register (FLASH_SR) . . . . .87
3.7.5Flash control register (FLASH_CR) . . . . .88
3.7.6Flash option control register (FLASH_OPTCR) . . . . .89
3.7.7Flash option control register (FLASH_OPTCR1) . . . . .92
3.7.8Flash option control register (FLASH_OPTCR2) . . . . .93
3.7.9Flash interface register map . . . . .94
4Power controller (PWR) . . . . .95
4.1Power supplies . . . . .95
4.1.1Independent A/D converter supply and reference voltage . . . . .97
4.1.2Independent USB transceivers supply . . . . .97
4.1.3Battery backup domain . . . . .99
4.1.4Voltage regulator . . . . .101
4.2Power supply supervisor . . . . .104
4.2.1Power-on reset (POR)/power-down reset (PDR) . . . . .104
4.2.2Brownout reset (BOR) . . . . .105
4.2.3Programmable voltage detector (PVD) . . . . .105
4.3Low-power modes . . . . .106
4.3.1Debug mode . . . . .109
4.3.2Run mode .....110
4.3.3Low-power mode .....110
4.3.4Sleep mode .....111
4.3.5Stop mode .....112
4.3.6Standby mode .....115
4.3.7Programming the RTC alternate functions to wake up the device from the Stop and Standby modes .....117
4.4Power control registers .....120
4.4.1PWR power control register (PWR_CR1) .....120
4.4.2PWR power control/status register (PWR_CSR1) .....122
4.4.3PWR power control/status register 2 (PWR_CR2) .....124
4.4.4PWR power control register 2 (PWR_CSR2) .....126
4.5PWR register map .....128
5Reset and clock control (RCC) .....129
5.1Reset .....129
5.1.1System reset .....129
5.1.2Power reset .....129
5.1.3Backup domain reset .....130
5.2Clocks .....130
5.2.1HSE clock .....134
5.2.2HSI clock .....135
5.2.3PLL .....136
5.2.4LSE clock .....137
5.2.5LSI clock .....137
5.2.6System clock (SYSCLK) selection .....137
5.2.7Clock security system (CSS) .....137
5.2.8RTC/AWU clock .....138
5.2.9Watchdog clock .....139
5.2.10Clock-out capability .....139
5.2.11Internal/external clock measurement using TIM5/TIM11 .....139
5.2.12Peripheral clock enable register (RCC_AHBxENR, RCC_APBxENRy) .....141
5.3RCC registers .....141
5.3.1RCC clock control register (RCC_CR) .....141
5.3.2RCC PLL configuration register (RCC_PLLCFGR) .....144
5.3.3RCC clock configuration register (RCC_CFGR) .....146
5.3.4RCC clock interrupt register (RCC_CIR) . . . . .148
5.3.5RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .151
5.3.6RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .154
5.3.7RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . .155
5.3.8RCC APB1 peripheral reset register (RCC_APB1RSTR) . . . . .155
5.3.9RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .159
5.3.10RCC AHB1 peripheral clock register (RCC_AHB1ENR) . . . . .161
5.3.11RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .162
5.3.12RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . .163
5.3.13RCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . .163
5.3.14RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .167
5.3.15RCC AHB1 peripheral clock enable in low-power mode register
(RCC_AHB1LPENR) . . . . .		170
5.3.16RCC AHB2 peripheral clock enable in low-power mode register
(RCC_AHB2LPENR) . . . . .		172
5.3.17RCC AHB3 peripheral clock enable in low-power mode register
(RCC_AHB3LPENR) . . . . .		173
5.3.18RCC APB1 peripheral clock enable in low-power mode register
(RCC_APB1LPENR) . . . . .		173
5.3.19RCC APB2 peripheral clock enabled in low-power mode register
(RCC_APB2LPENR) . . . . .		177
5.3.20RCC backup domain control register (RCC_BDCR) . . . . .179
5.3.21RCC clock control & status register (RCC_CSR) . . . . .180
5.3.22RCC spread spectrum clock generation register (RCC_SSCGR) . . . . .182
5.3.23RCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . .183
5.3.24RCC PLLSAI configuration register (RCC_PLLSAICFGR) . . . . .186
5.3.25RCC dedicated clocks configuration register (RCC_DCKCFGR1) . . . . .187
5.3.26RCC dedicated clocks configuration register (RCC_DCKCFGR2) . . . . .189
5.3.27RCC register map . . . . .192
6General-purpose I/Os (GPIO) . . . . .195
6.1Introduction . . . . .195
6.2GPIO main features . . . . .195
6.3GPIO functional description . . . . .195
6.3.1General-purpose I/O (GPIO) . . . . .198
6.3.2I/O pin alternate function multiplexer and mapping . . . . .198
6.3.3I/O port control registers . . . . .199
6.3.4I/O port data registers . . . . .199
7.2.4SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) .....217
7.2.5SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) .....218
7.2.6SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) .....219
7.2.7Compensation cell control register (SYSCFG_CMPCR) .....219
7.2.8SYSCFG register maps .....220
8Direct memory access controller (DMA) .....221
8.1DMA introduction .....221
8.2DMA main features .....221
8.3DMA functional description .....223
8.3.1DMA block diagram .....223
8.3.2DMA overview .....223
8.3.3DMA transactions .....224
8.3.4Channel selection .....224
8.3.5Arbiter .....226
8.3.6DMA streams .....226
8.3.7Source, destination and transfer modes .....226
8.3.8Pointer incrementation .....230
8.3.9Circular mode .....231
8.3.10Double-buffer mode .....231
8.3.11Programmable data width, packing/unpacking, endianness .....232
8.3.12Single and burst transfers .....233
8.3.13FIFO .....234
8.3.14DMA transfer completion .....237
8.3.15DMA transfer suspension .....238
8.3.16Flow controller .....239
8.3.17Summary of the possible DMA configurations .....240
8.3.18Stream configuration procedure .....240
8.3.19Error management .....241
8.4DMA interrupts .....242
8.5DMA registers .....243
8.5.1DMA low interrupt status register (DMA_LISR) .....243
8.5.2DMA high interrupt status register (DMA_HISR) .....244
8.5.3DMA low interrupt flag clear register (DMA_LIFCR) .....245
11.3CRC functional description . . . . .270
11.3.1CRC block diagram . . . . .270
11.3.2CRC internal signals . . . . .270
11.3.3CRC operation . . . . .270
11.4CRC registers . . . . .272
11.4.1CRC data register (CRC_DR) . . . . .272
11.4.2CRC independent data register (CRC_IDR) . . . . .272
11.4.3CRC control register (CRC_CR) . . . . .273
11.4.4CRC initial value (CRC_INIT) . . . . .274
11.4.5CRC polynomial (CRC_POL) . . . . .274
11.4.6CRC register map . . . . .275
12Flexible memory controller (FMC) . . . . .276
12.1Introduction . . . . .276
12.2FMC main features . . . . .276
12.3FMC block diagram . . . . .277
12.4AHB interface . . . . .278
12.4.1Supported memories and transactions . . . . .278
12.5External device address mapping . . . . .279
12.5.1NOR/PSRAM address mapping . . . . .280
12.5.2NAND flash memory address mapping . . . . .281
12.5.3SDRAM address mapping . . . . .282
12.6NOR flash/PSRAM controller . . . . .285
12.6.1External memory interface signals . . . . .286
12.6.2Supported memories and transactions . . . . .288
12.6.3General timing rules . . . . .290
12.6.4NOR flash/PSRAM controller asynchronous transactions . . . . .290
12.6.5Synchronous transactions . . . . .307
12.6.6NOR/PSRAM controller registers . . . . .314
12.7NAND flash controller . . . . .321
12.7.1External memory interface signals . . . . .321
12.7.2NAND flash supported memories and transactions . . . . .322
12.7.3Timing diagrams for NAND flash memory . . . . .323
12.7.4NAND flash operations . . . . .324
12.7.5NAND flash prewait functionality . . . . .324
12.7.6Computation of the error correction code (ECC) in NAND flash memory . . . . .325
12.7.7NAND flash controller registers . . . . .326
12.8SDRAM controller . . . . .332
12.8.1SDRAM controller main features . . . . .332
12.8.2SDRAM External memory interface signals . . . . .332
12.8.3SDRAM controller functional description . . . . .333
12.8.4Low-power modes . . . . .339
12.8.5SDRAM controller registers . . . . .343
12.8.6FMC register map . . . . .349
13Quad-SPI interface (QUADSPI) . . . . .352
13.1Introduction . . . . .352
13.2QUADSPI main features . . . . .352
13.3QUADSPI functional description . . . . .352
13.3.1QUADSPI block diagram . . . . .352
13.3.2QUADSPI pins . . . . .353
13.3.3QUADSPI command sequence . . . . .353
13.3.4QUADSPI signal interface protocol modes . . . . .356
13.3.5QUADSPI indirect mode . . . . .358
13.3.6QUADSPI automatic status-polling mode . . . . .360
13.3.7QUADSPI memory-mapped mode . . . . .360
13.3.8QUADSPI flash memory configuration . . . . .361
13.3.9QUADSPI delayed data sampling . . . . .361
13.3.10QUADSPI configuration . . . . .361
13.3.11QUADSPI use . . . . .362
13.3.12Sending the instruction only once . . . . .364
13.3.13QUADSPI error management . . . . .364
13.3.14QUADSPI busy bit and abort functionality . . . . .364
13.3.15NCS behavior . . . . .365
13.4QUADSPI interrupts . . . . .367
13.5QUADSPI registers . . . . .367
13.5.1QUADSPI control register (QUADSPI_CR) . . . . .367
13.5.2QUADSPI device configuration register (QUADSPI_DCR) . . . . .370
13.5.3QUADSPI status register (QUADSPI_SR) . . . . .371
13.5.4QUADSPI flag clear register (QUADSPI_FCR) . . . . .372
13.5.5QUADSPI data length register (QUADSPI_DLR) . . . . .372
13.5.6QUADSPI communication configuration register (QUADSPI_CCR) . . .373
13.5.7QUADSPI address register (QUADSPI_AR) . . . . .375
13.5.8QUADSPI alternate-byte register (QUADSPI_ABR) . . . . .375
13.5.9QUADSPI data register (QUADSPI_DR) . . . . .376
13.5.10QUADSPI polling status mask register (QUADSPI_PSMKR) . . . . .376
13.5.11QUADSPI polling status match register (QUADSPI_PSMAR) . . . . .377
13.5.12QUADSPI polling interval register (QUADSPI_PIR) . . . . .377
13.5.13QUADSPI low-power timeout register (QUADSPI_LPTR) . . . . .378
13.5.14QUADSPI register map . . . . .378
14Analog-to-digital converter (ADC) . . . . .380
14.1ADC introduction . . . . .380
14.2ADC main features . . . . .380
14.3ADC functional description . . . . .381
14.3.1ADC on-off control . . . . .382
14.3.2ADC1/2 and ADC3 connectivity . . . . .383
14.3.3ADC clock . . . . .386
14.3.4Channel selection . . . . .386
14.3.5Single conversion mode . . . . .387
14.3.6Continuous conversion mode . . . . .387
14.3.7Timing diagram . . . . .387
14.3.8Analog watchdog . . . . .388
14.3.9Scan mode . . . . .389
14.3.10Injected channel management . . . . .389
14.3.11Discontinuous mode . . . . .390
14.4Data alignment . . . . .391
14.5Channel-wise programmable sampling time . . . . .392
14.6Conversion on external trigger and trigger polarity . . . . .393
14.7Fast conversion mode . . . . .394
14.8Data management . . . . .395
14.8.1Using the DMA . . . . .395
14.8.2Managing a sequence of conversions without using the DMA . . . . .395
14.8.3Conversions without DMA and without overrun detection . . . . .396
14.9Multi ADC mode . . . . .396
14.9.1Injected simultaneous mode . . . . .399
14.9.2Regular simultaneous mode . . . . .400
14.9.3Interleaved mode . . . . .401
14.9.4Alternate trigger mode . . . . .403
14.9.5Combined regular/injected simultaneous mode . . . . .405
14.9.6Combined regular simultaneous + alternate trigger mode . . . . .405
14.10Temperature sensor . . . . .406
14.11Battery charge monitoring . . . . .408
14.12ADC interrupts . . . . .408
14.13ADC registers . . . . .409
14.13.1ADC status register (ADC_SR) . . . . .409
14.13.2ADC control register 1 (ADC_CR1) . . . . .410
14.13.3ADC control register 2 (ADC_CR2) . . . . .412
14.13.4ADC sample time register 1 (ADC_SMPR1) . . . . .413
14.13.5ADC sample time register 2 (ADC_SMPR2) . . . . .414
14.13.6ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . . . .414
14.13.7ADC watchdog higher threshold register (ADC_HTR) . . . . .415
14.13.8ADC watchdog lower threshold register (ADC_LTR) . . . . .415
14.13.9ADC regular sequence register 1 (ADC_SQR1) . . . . .416
14.13.10ADC regular sequence register 2 (ADC_SQR2) . . . . .416
14.13.11ADC regular sequence register 3 (ADC_SQR3) . . . . .417
14.13.12ADC injected sequence register (ADC_JSQR) . . . . .418
14.13.13ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . .418
14.13.14ADC regular data register (ADC_DR) . . . . .419
14.13.15ADC Common status register (ADC_CSR) . . . . .419
14.13.16ADC common control register (ADC_CCR) . . . . .420
14.13.17ADC common regular data register for dual and triple modes
(ADC_CDR) . . . . .		423
14.13.18ADC register map . . . . .423
15Digital-to-analog converter (DAC) . . . . .426
15.1DAC introduction . . . . .426
15.2DAC main features . . . . .426
15.3DAC functional description . . . . .427
15.3.1DAC channel enable . . . . .427
15.3.2DAC output buffer enable . . . . .428
15.3.3DAC data format . . . . .428
15.3.4DAC conversion . . . . .429
15.3.5DAC output voltage . . . . .430
15.3.6DAC trigger selection . . . . .430
15.3.7DMA request . . . . .431
15.3.8Noise generation . . . . .431
15.3.9Triangle-wave generation . . . . .432
15.4Dual DAC channel conversion . . . . .433
15.4.1Independent trigger without wave generation . . . . .434
15.4.2Independent trigger with single LFSR generation . . . . .434
15.4.3Independent trigger with different LFSR generation . . . . .434
15.4.4Independent trigger with single triangle generation . . . . .435
15.4.5Independent trigger with different triangle generation . . . . .435
15.4.6Simultaneous software start . . . . .435
15.4.7Simultaneous trigger without wave generation . . . . .436
15.4.8Simultaneous trigger with single LFSR generation . . . . .436
15.4.9Simultaneous trigger with different LFSR generation . . . . .436
15.4.10Simultaneous trigger with single triangle generation . . . . .437
15.4.11Simultaneous trigger with different triangle generation . . . . .437
15.5DAC registers . . . . .438
15.5.1DAC control register (DAC_CR) . . . . .438
15.5.2DAC software trigger register (DAC_SWTRIGR) . . . . .441
15.5.3DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . .		441
15.5.4DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . .		442
15.5.5DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . .		442
15.5.6DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . .		443
15.5.7DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . .		443
15.5.8DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . .		443
15.5.9Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . .		444
15.5.10DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . .		444
15.5.11DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . .		445
15.5.12DAC channel1 data output register (DAC_DOR1) . . . . .445
15.5.13DAC channel2 data output register (DAC_DOR2) . . . . .445
17.4.5AES decryption key preparation .....470
17.4.6AES ciphertext stealing and data padding .....471
17.4.7AES task suspend and resume .....472
17.4.8AES basic chaining modes (ECB, CBC) .....473
17.4.9AES counter (CTR) mode .....478
17.4.10AES Galois/counter mode (GCM) .....480
17.4.11AES Galois message authentication code (GMAC) .....485
17.4.12AES counter with CBC-MAC (CCM) .....487
17.4.13AES data registers and data swapping .....492
17.4.14AES key registers .....494
17.4.15AES initialization vector registers .....494
17.4.16AES DMA interface .....494
17.4.17AES error management .....497
17.5AES interrupts .....497
17.6AES processing latency .....498
17.7AES registers .....499
17.7.1AES control register (AES_CR) .....499
17.7.2AES status register (AES_SR) .....502
17.7.3AES data input register (AES_DINR) .....503
17.7.4AES data output register (AES_DOUTR) .....504
17.7.5AES key register 0 (AES_KEYR0) .....504
17.7.6AES key register 1 (AES_KEYR1) .....505
17.7.7AES key register 2 (AES_KEYR2) .....505
17.7.8AES key register 3 (AES_KEYR3) .....506
17.7.9AES initialization vector register 0 (AES_IVR0) .....506
17.7.10AES initialization vector register 1 (AES_IVR1) .....506
17.7.11AES initialization vector register 2 (AES_IVR2) .....507
17.7.12AES initialization vector register 3 (AES_IVR3) .....507
17.7.13AES key register 4 (AES_KEYR4) .....508
17.7.14AES key register 5 (AES_KEYR5) .....508
17.7.15AES key register 6 (AES_KEYR6) .....508
17.7.16AES key register 7 (AES_KEYR7) .....509
17.7.17AES suspend registers (AES_SUSPxR) .....509
17.7.18AES register map .....510
18Advanced-control timers (TIM1/TIM8) .....512
18.1TIM1/TIM8 introduction .....512
18.2TIM1/TIM8 main features . . . . .512
18.3TIM1/TIM8 functional description . . . . .514
18.3.1Time-base unit . . . . .514
18.3.2Counter modes . . . . .516
18.3.3Repetition counter . . . . .527
18.3.4External trigger input . . . . .529
18.3.5Clock selection . . . . .530
18.3.6Capture/compare channels . . . . .534
18.3.7Input capture mode . . . . .536
18.3.8PWM input mode . . . . .537
18.3.9Forced output mode . . . . .538
18.3.10Output compare mode . . . . .539
18.3.11PWM mode . . . . .540
18.3.12Asymmetric PWM mode . . . . .543
18.3.13Combined PWM mode . . . . .544
18.3.14Combined 3-phase PWM mode . . . . .545
18.3.15Complementary outputs and dead-time insertion . . . . .546
18.3.16Using the break function . . . . .548
18.3.17Clearing the OCxREF signal on an external event . . . . .554
18.3.186-step PWM generation . . . . .556
18.3.19One-pulse mode . . . . .557
18.3.20Retriggerable one pulse mode . . . . .558
18.3.21Encoder interface mode . . . . .559
18.3.22UIF bit remapping . . . . .561
18.3.23Timer input XOR function . . . . .562
18.3.24Interfacing with Hall sensors . . . . .562
18.3.25Timer synchronization . . . . .565
18.3.26ADC synchronization . . . . .569
18.3.27DMA burst mode . . . . .569
18.3.28Debug mode . . . . .570
18.4TIM1/TIM8 registers . . . . .571
18.4.1TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . .571
18.4.2TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . .572
18.4.3TIMx slave mode control register
(TIMx_SMCR)(x = 1, 8) . . . . .		575
18.4.4TIMx DMA/interrupt enable register
(TIMx_DIER)(x = 1, 8) . . . . .		577
18.4.5TIMx status register (TIMx_SR)(x = 1, 8) . . . . .579
18.4.6TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . .581
18.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 1, 8) . . .582
18.4.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . .		583
18.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 1, 8) . . .586
18.4.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . .		587
18.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 1, 8) . . . . .		588
18.4.12TIMx counter (TIMx_CNT)(x = 1, 8) . . . . .592
18.4.13TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . .592
18.4.14TIMx auto-reload register (TIMx_ARR)(x = 1, 8) . . . . .592
18.4.15TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . .593
18.4.16TIMx capture/compare register 1
(TIMx_CCR1)(x = 1, 8) . . . . .		593
18.4.17TIMx capture/compare register 2
(TIMx_CCR2)(x = 1, 8) . . . . .		594
18.4.18TIMx capture/compare register 3
(TIMx_CCR3)(x = 1, 8) . . . . .		594
18.4.19TIMx capture/compare register 4
(TIMx_CCR4)(x = 1, 8) . . . . .		595
18.4.20TIMx break and dead-time register
(TIMx_BDTR)(x = 1, 8) . . . . .		595
18.4.21TIMx DMA control register
(TIMx_DCR)(x = 1, 8) . . . . .		598
18.4.22TIMx DMA address for full transfer
(TIMx_DMAR)(x = 1, 8) . . . . .		599
18.4.23TIMx capture/compare mode register 3
(TIMx_CCMR3)(x = 1, 8) . . . . .		600
18.4.24TIMx capture/compare register 5
(TIMx_CCR5)(x = 1, 8) . . . . .		601
18.4.25TIMx capture/compare register 6
(TIMx_CCR6)(x = 1, 8) . . . . .		602
18.4.26TIM1 register map . . . . .603
18.4.27TIM8 register map . . . . .605
19General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . .608
19.1TIM2/TIM3/TIM4/TIM5 introduction . . . . .608
19.2TIM2/TIM3/TIM4/TIM5 main features . . . . .608
19.3TIM2/TIM3/TIM4/TIM5 functional description . . . . .610
19.3.1Time-base unit . . . . .610
19.3.2Counter modes . . . . .612
19.3.3Clock selection . . . . .622
19.3.4Capture/Compare channels . . . . .626
19.3.5Input capture mode . . . . .628
19.3.6PWM input mode . . . . .629
19.3.7Forced output mode . . . . .630
19.3.8Output compare mode . . . . .631
19.3.9PWM mode . . . . .632
19.3.10Asymmetric PWM mode . . . . .635
19.3.11Combined PWM mode . . . . .636
19.3.12Clearing the OCxREF signal on an external event . . . . .637
19.3.13One-pulse mode . . . . .639
19.3.14Retriggerable one pulse mode . . . . .640
19.3.15Encoder interface mode . . . . .641
19.3.16UIF bit remapping . . . . .643
19.3.17Timer input XOR function . . . . .643
19.3.18Timers and external trigger synchronization . . . . .644
19.3.19Timer synchronization . . . . .647
19.3.20DMA burst mode . . . . .652
19.3.21Debug mode . . . . .653
19.4TIM2/TIM3/TIM4/TIM5 registers . . . . .654
19.4.1TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . .654
19.4.2TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . .655
19.4.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . .657
19.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . .660
19.4.5TIMx status register (TIMx_SR)(x = 2 to 5) . . . . .661
19.4.6TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . .662
19.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) . . . . .663
19.4.8TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 2 to 5) . . . . .665
19.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) . . . . .667
19.4.10TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)(x = 2 to 5) . . . . .668
19.4.11TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 5) . . . . .669
19.4.12TIMx counter (TIMx_CNT)(x = 2 to 5) . . . . .670
19.4.13TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) . . . . .671
19.4.14TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . .671
19.4.15TIMx auto-reload register (TIMx_ARR)(x = 2 to 5) . . . . .672
19.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) . . . . .672
19.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) . . . . .672
19.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) . . . . .673
19.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) . . . . .673
19.4.20TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . .674
19.4.21TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . .675
19.4.22TIM2 option register (TIM2_OR) . . . . .675
19.4.23TIM5 option register (TIM5_OR) . . . . .675
19.4.24TIMx register map . . . . .677
20General-purpose timers (TIM9/TIM10/TIM11/TIM12/TIM13/TIM14) . . .680
20.1TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 introduction . . . . .680
20.2TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 main features . . . . .680
20.2.1TIM9/TIM12 main features . . . . .680
20.2.2TIM10/TIM11/TIM13/TIM14 main features . . . . .681
20.3TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 functional description . . . . .683
20.3.1Time-base unit . . . . .683
20.3.2Counter modes . . . . .685
20.3.3Clock selection . . . . .688
20.3.4Capture/compare channels . . . . .690
20.3.5Input capture mode . . . . .692
20.3.6PWM input mode (only for TIM9/TIM12) . . . . .693
20.3.7Forced output mode . . . . .694
20.3.8Output compare mode . . . . .694
20.3.9PWM mode . . . . .695
20.3.10Combined PWM mode (TIM9/TIM12 only) . . . . .696
20.3.11One-pulse mode . . . . .698
20.3.12Retriggerable one pulse mode (TIM12 only) . . . . .699
20.3.13UIF bit remapping . . . . .700
20.3.14TIM9/TIM12 external trigger synchronization . . . . .700
20.3.15Slave mode – combined reset + trigger mode . . . . .703
20.3.16Timer synchronization (TIM9/TIM12) . . . . .704
20.3.17Using timer output as trigger for other timers (TIM10/TIM11/TIM13/TIM14)
704		704
20.3.18Debug mode . . . . .704
20.4TIM9/TIM12 registers . . . . .704
20.4.1TIMx control register 1 (TIMx_CR1)(x = 9, 12) . . . . .704
20.4.2TIMx slave mode control register (TIMx_SMCR)(x = 9, 12) . . . . .705
20.4.3TIMx Interrupt enable register (TIMx_DIER)(x = 9, 12) . . . . .707
20.4.4TIMx status register (TIMx_SR)(x = 9, 12) . . . . .707
20.4.5TIMx event generation register (TIMx_EGR)(x = 9, 12) . . . . .709
20.4.6TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 9, 12) . . . . .710
20.4.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 9, 12) . . . . .		711
20.4.8TIMx capture/compare enable register (TIMx_CCER)(x = 9, 12) . . . . .713
20.4.9TIMx counter (TIMx_CNT)(x = 9, 12) . . . . .714
20.4.10TIMx prescaler (TIMx_PSC)(x = 9, 12) . . . . .715
20.4.11TIMx auto-reload register (TIMx_ARR)(x = 9, 12) . . . . .715
20.4.12TIMx capture/compare register 1 (TIMx_CCR1)(x = 9, 12) . . . . .715
20.4.13TIMx capture/compare register 2 (TIMx_CCR2)(x = 9, 12) . . . . .716
20.4.14TIM9/TIM12 register map . . . . .717
20.5TIM10/TIM11/TIM13/TIM14 registers . . . . .719
20.5.1TIMx control register 1 (TIMx_CR1)(x = 10, 11, 13, 14) . . . . .719
20.5.2TIMx Interrupt enable register (TIMx_DIER)(x = 10, 11, 13, 14) . . . . .720
20.5.3TIMx status register (TIMx_SR)(x = 10, 11, 13, 14) . . . . .720
20.5.4TIMx event generation register (TIMx_EGR)(x = 10, 11, 13, 14) . . . . .721
20.5.5TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 10, 11, 13, 14) . . . . .		722
20.5.6TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 10, 11, 13, 14) . . . . .		723
20.5.7TIMx capture/compare enable register
(TIMx_CCER)(x = 10, 11, 13, 14) . . . . .		725
20.5.8TIMx counter (TIMx_CNT)(x = 10, 11, 13, 14) . . . . .726
20.5.9TIMx prescaler (TIMx_PSC)(x = 10, 11, 13, 14) . . . . .727
20.5.10TIMx auto-reload register (TIMx_ARR)(x = 10, 11, 13, 14) . . . . .727
20.5.11TIMx capture/compare register 1 (TIMx_CCR1)(x = 10, 11, 13, 14) . . . . .727
20.5.12TIM11 option register 1 (TIM11_OR) . . . . .728
20.5.13TIM10/TIM11/TIM13/TIM14 register map . . . . .728
21Basic timers (TIM6/TIM7) . . . . .730
21.1TIM6/TIM7 introduction . . . . .730
21.2TIM6/TIM7 main features . . . . .730
21.3TIM6/TIM7 functional description . . . . .731
21.3.1Time-base unit . . . . .731
21.3.2Counting mode . . . . .733
21.3.3UIF bit remapping . . . . .736
21.3.4Clock source . . . . .736
21.3.5Debug mode . . . . .737
21.4TIM6/TIM7 registers . . . . .737
21.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . .737
21.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . .739
21.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . .739
21.4.4TIMx status register (TIMx_SR)(x = 6 to 7) . . . . .740
21.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . .740
21.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . .740
21.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . .741
21.4.8TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . .741
21.4.9TIMx register map . . . . .742
22Low-power timer (LPTIM) . . . . .743
22.1Introduction . . . . .743
22.2LPTIM main features . . . . .743
22.3LPTIM implementation . . . . .744
22.4LPTIM functional description . . . . .744
22.4.1LPTIM block diagram . . . . .744
22.4.2LPTIM trigger mapping . . . . .745
22.4.3LPTIM reset and clocks . . . . .745
22.4.4Glitch filter . . . . .745
22.4.5Prescaler . . . . .746
22.4.6Trigger multiplexer . . . . .747
22.4.7Operating mode . . . . .747
22.4.8Timeout function . . . . .749
22.4.9Waveform generation . . . . .749
22.4.10Register update . . . . .750
22.4.11Counter mode . . . . .751
22.4.12Timer enable . . . . .751
22.4.13Encoder mode . . . . .752
22.4.14Debug mode . . . . .753
22.5LPTIM low-power modes . . . . .753
24.3.3Controlling the down-counter . . . . .774
24.3.4How to program the watchdog timeout . . . . .774
24.3.5Debug mode . . . . .776
24.4WWDG interrupts . . . . .776
24.5WWDG registers . . . . .776
24.5.1WWDG control register (WWDG_CR) . . . . .776
24.5.2WWDG configuration register (WWDG_CFR) . . . . .777
24.5.3WWDG status register (WWDG_SR) . . . . .777
24.5.4WWDG register map . . . . .778
25Real-time clock (RTC) . . . . .779
25.1Introduction . . . . .779
25.2RTC main features . . . . .780
25.3RTC functional description . . . . .781
25.3.1RTC block diagram . . . . .781
25.3.2GPIOs controlled by the RTC . . . . .782
25.3.3Clock and prescalers . . . . .784
25.3.4Real-time clock and calendar . . . . .785
25.3.5Programmable alarms . . . . .785
25.3.6Periodic auto-wake-up . . . . .786
25.3.7RTC initialization and configuration . . . . .787
25.3.8Reading the calendar . . . . .788
25.3.9Resetting the RTC . . . . .789
25.3.10RTC synchronization . . . . .790
25.3.11RTC reference clock detection . . . . .790
25.3.12RTC smooth digital calibration . . . . .791
25.3.13Time-stamp function . . . . .793
25.3.14Tamper detection . . . . .794
25.3.15Calibration clock output . . . . .796
25.3.16Alarm output . . . . .796
25.4RTC low-power modes . . . . .796
25.5RTC interrupts . . . . .797
25.6RTC registers . . . . .798
25.6.1RTC time register (RTC_TR) . . . . .798
25.6.2RTC date register (RTC_DR) . . . . .799
25.6.3RTC control register (RTC_CR) . . . . .800
25.6.4RTC initialization and status register (RTC_ISR) . . . . .803
25.6.5RTC prescaler register (RTC_PRER) . . . . .806
25.6.6RTC wake-up timer register (RTC_WUTR) . . . . .807
25.6.7RTC alarm A register (RTC_ALRMAR) . . . . .808
25.6.8RTC alarm B register (RTC_ALRMBR) . . . . .809
25.6.9RTC write protection register (RTC_WPR) . . . . .810
25.6.10RTC sub second register (RTC_SSR) . . . . .810
25.6.11RTC shift control register (RTC_SHIFTR) . . . . .811
25.6.12RTC timestamp time register (RTC_TSTR) . . . . .812
25.6.13RTC timestamp date register (RTC_TSDR) . . . . .813
25.6.14RTC time-stamp sub second register (RTC_TSSSR) . . . . .814
25.6.15RTC calibration register (RTC_CALR) . . . . .815
25.6.16RTC tamper configuration register (RTC_TAMPCR) . . . . .816
25.6.17RTC alarm A sub second register (RTC_ALRMASSR) . . . . .819
25.6.18RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .820
25.6.19RTC option register (RTC_OR) . . . . .821
25.6.20RTC backup registers (RTC_BKPxR) . . . . .821
25.6.21RTC register map . . . . .822
26Inter-integrated circuit interface (I2C) . . . . .824
26.1Introduction . . . . .824
26.2I2C main features . . . . .824
26.3I2C implementation . . . . .825
26.4I2C functional description . . . . .825
26.4.1I2C block diagram . . . . .826
26.4.2I2C pins and internal signals . . . . .826
26.4.3I2C clock requirements . . . . .827
26.4.4I2C mode selection . . . . .827
26.4.5I2C initialization . . . . .828
26.4.6I2C reset . . . . .832
26.4.7I2C data transfer . . . . .832
26.4.8I2C target mode . . . . .834
26.4.9I2C controller mode . . . . .843
26.4.10I2C_TIMINGR register configuration examples . . . . .854
26.4.11SMBus specific features . . . . .856
26.4.12SMBus initialization . . . . .859
26.4.13SMBus I2C_TIMEOUTR register configuration examples . . . . .861
26.4.14SMBus target mode . . . . .861
26.4.15SMBus controller mode . . . . .865
26.4.16Error conditions . . . . .868
26.5I2C in low-power modes . . . . .870
26.6I2C interrupts . . . . .870
26.7I2C DMA requests . . . . .871
26.7.1Transmission using DMA . . . . .871
26.7.2Reception using DMA . . . . .871
26.8I2C debug modes . . . . .872
26.9I2C registers . . . . .872
26.9.1I2C control register 1 (I2C_CR1) . . . . .872
26.9.2I2C control register 2 (I2C_CR2) . . . . .875
26.9.3I2C own address 1 register (I2C_OAR1) . . . . .877
26.9.4I2C own address 2 register (I2C_OAR2) . . . . .878
26.9.5I2C timing register (I2C_TIMINGR) . . . . .879
26.9.6I2C timeout register (I2C_TIMEOUTR) . . . . .880
26.9.7I2C interrupt and status register (I2C_ISR) . . . . .881
26.9.8I2C interrupt clear register (I2C_ICR) . . . . .883
26.9.9I2C PEC register (I2C_PECR) . . . . .884
26.9.10I2C receive data register (I2C_RXDR) . . . . .884
26.9.11I2C transmit data register (I2C_TXDR) . . . . .885
26.9.12I2C register map . . . . .886
27Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .887
27.1Introduction . . . . .887
27.2USART main features . . . . .887
27.3USART extended features . . . . .888
27.4USART implementation . . . . .889
27.5USART functional description . . . . .889
27.5.1USART character description . . . . .892
27.5.2USART transmitter . . . . .894
27.5.3USART receiver . . . . .896
27.5.4USART baud rate generation . . . . .902
27.5.5Tolerance of the USART receiver to clock deviation . . . . .905
27.5.6USART auto baud rate detection . . . . .906
27.5.7Multiprocessor communication using USART . . . . .907
27.5.8Modbus communication using USART . . . . .909
27.5.9USART parity control . . . . .910
27.5.10USART LIN (local interconnection network) mode . . . . .911
27.5.11USART synchronous mode . . . . .913
27.5.12USART single-wire half-duplex communication . . . . .916
27.5.13USART smartcard mode . . . . .916
27.5.14USART IrDA SIR ENDEC block . . . . .921
27.5.15USART continuous communication in DMA mode . . . . .923
27.5.16RS232 hardware flow control and RS485 driver enable
using USART . . . . .		925
27.6USART in low-power modes . . . . .927
27.7USART interrupts . . . . .928
27.8USART registers . . . . .930
27.8.1USART control register 1 (USART_CR1) . . . . .930
27.8.2USART control register 2 (USART_CR2) . . . . .933
27.8.3USART control register 3 (USART_CR3) . . . . .936
27.8.4USART baud rate register (USART_BRR) . . . . .939
27.8.5USART guard time and prescaler register (USART_GTPR) . . . . .940
27.8.6USART receiver timeout register (USART_RTOR) . . . . .941
27.8.7USART request register (USART_RQR) . . . . .942
27.8.8USART interrupt and status register (USART_ISR) . . . . .943
27.8.9USART interrupt flag clear register (USART_ICR) . . . . .948
27.8.10USART receive data register (USART_RDR) . . . . .949
27.8.11USART transmit data register (USART_TDR) . . . . .949
27.8.12USART register map . . . . .950
28Serial peripheral interface / integrated interchip sound (SPI/I2S) . . .952
28.1Introduction . . . . .952
28.2SPI main features . . . . .952
28.3I2S main features . . . . .953
28.4SPI/I2S implementation . . . . .953
28.5SPI functional description . . . . .954
28.5.1General description . . . . .954
28.5.2Communications between one master and one slave . . . . .955
28.5.3Standard multislave communication . . . . .957
28.5.4Multimaster communication . . . . .958
28.5.5Slave select (NSS) pin management . . . . .959
28.5.6Communication formats . . . . .960
28.5.7Configuration of SPI . . . . .962
28.5.8Procedure for enabling SPI . . . . .963
28.5.9Data transmission and reception procedures . . . . .963
28.5.10SPI status flags . . . . .973
28.5.11SPI error flags . . . . .974
28.5.12NSS pulse mode . . . . .975
28.5.13TI mode . . . . .975
28.5.14CRC calculation . . . . .976
28.6SPI interrupts . . . . .978
28.7I2S functional description . . . . .979
28.7.1I2S general description . . . . .979
28.7.2I2S full duplex . . . . .980
28.7.3Supported audio protocols . . . . .981
28.7.4Start-up description . . . . .988
28.7.5Clock generator . . . . .990
28.7.6I 2 S master mode . . . . .993
28.7.7I 2 S slave mode . . . . .994
28.7.8I2S status flags . . . . .996
28.7.9I2S error flags . . . . .997
28.7.10DMA features . . . . .998
28.8I2S interrupts . . . . .998
28.9SPI and I2S registers . . . . .999
28.9.1SPI control register 1 (SPIx_CR1) . . . . .999
28.9.2SPI control register 2 (SPIx_CR2) . . . . .1001
28.9.3SPI status register (SPIx_SR) . . . . .1003
28.9.4SPI data register (SPIx_DR) . . . . .1005
28.9.5SPI CRC polynomial register (SPIx_CRCPR) . . . . .1005
28.9.6SPI Rx CRC register (SPIx_RXCRCR) . . . . .1005
28.9.7SPI Tx CRC register (SPIx_TXCRCR) . . . . .1006
28.9.8SPIx_I2S configuration register (SPIx_I2SCFGR) . . . . .1006
28.9.9SPIx_I2S prescaler register (SPIx_I2SPR) . . . . .1008
28.9.10SPI/I2S register map . . . . .1010
29Serial audio interface (SAI) . . . . .1011
29.1Introduction . . . . .1011
29.2SAI main features . . . . .1011
29.3SAI functional description . . . . .1013
29.3.1SAI block diagram . . . . .1013
29.3.2SAI pins and internal signals . . . . .1014
29.3.3Main SAI modes . . . . .1014
29.3.4SAI synchronization mode . . . . .1015
29.3.5Audio data size . . . . .1016
29.3.6Frame synchronization . . . . .1017
29.3.7Slot configuration . . . . .1020
29.3.8SAI clock generator . . . . .1022
29.3.9Internal FIFOs . . . . .1024
29.3.10AC'97 link controller . . . . .1026
29.3.11SPDIF output . . . . .1028
29.3.12Specific features . . . . .1031
29.3.13Error flags . . . . .1035
29.3.14Disabling the SAI . . . . .1038
29.3.15SAI DMA interface . . . . .1038
29.4SAI interrupts . . . . .1039
29.5SAI registers . . . . .1041
29.5.1SAI global configuration register (SAI_GCR) . . . . .1041
29.5.2SAI configuration register 1 (SAI_ACR1) . . . . .1041
29.5.3SAI configuration register 2 (SAI_ACR2) . . . . .1044
29.5.4SAI frame configuration register (SAI_AFRCR) . . . . .1046
29.5.5SAI slot register (SAI_ASLOTR) . . . . .1047
29.5.6SAI interrupt mask register (SAI_AIM) . . . . .1048
29.5.7SAI status register (SAI_ASR) . . . . .1049
29.5.8SAI clear flag register (SAI_ACLRFR) . . . . .1051
29.5.9SAI data register (SAI_ADR) . . . . .1052
29.5.10SAI configuration register 1 (SAI_BCR1) . . . . .1053
29.5.11SAI configuration register 2 (SAI_BCR2) . . . . .1055
29.5.12SAI frame configuration register (SAI_BFRCR) . . . . .1057
29.5.13SAI slot register (SAI_BSLOTR) . . . . .1058
29.5.14SAI interrupt mask register (SAI_BIM) . . . . .1059
29.5.15SAI status register (SAI_BSR) . . . . .1060
29.5.16SAI clear flag register (SAI_BCLRFR) . . . . .1062
29.5.17SAI data register (SAI_BDR) .....1063
29.5.18SAI register map .....1064
30SD/SDIO/MMC card host interface (SDMMC) .....1066
30.1SDMMC main features .....1066
30.2SDMMC bus topology .....1066
30.3SDMMC functional description .....1068
30.3.1SDMMC adapter .....1070
30.3.2SDMMC APB2 interface .....1081
30.4Card functional description .....1082
30.4.1Card identification mode .....1082
30.4.2Card reset .....1083
30.4.3Operating voltage range validation .....1083
30.4.4Card identification process .....1083
30.4.5Block write .....1084
30.4.6Block read .....1085
30.4.7Stream access, stream write and stream read
(MultiMediaCard only) .....		1085
30.4.8Erase: group erase and sector erase .....1087
30.4.9Wide bus selection or deselection .....1087
30.4.10Protection management .....1087
30.4.11Card status register .....1091
30.4.12SD status register .....1094
30.4.13SD I/O mode .....1098
30.4.14Commands and responses .....1099
30.5Response formats .....1102
30.5.1R1 (normal response command) .....1103
30.5.2R1b .....1103
30.5.3R2 (CID, CSD register) .....1103
30.5.4R3 (OCR register) .....1104
30.5.5R4 (Fast I/O) .....1104
30.5.6R4b .....1104
30.5.7R5 (interrupt request) .....1105
30.5.8R6 .....1105
30.6SDIO I/O card-specific operations .....1106
30.6.1SDIO I/O read wait operation by SDMMC_D2 signalling .....1106
30.6.2SDIO read wait operation by stopping SDMMC_CK .....1107
30.6.3SDIO suspend/resume operation . . . . .1107
30.6.4SDIO interrupts . . . . .1107
30.7HW flow control . . . . .1107
30.8SDMMC registers . . . . .1108
30.8.1SDMMC power control register (SDMMC_POWER) . . . . .1108
30.8.2SDMMC clock control register (SDMMC_CLKCR) . . . . .1108
30.8.3SDMMC argument register (SDMMC_ARG) . . . . .1111
30.8.4SDMMC command register (SDMMC_CMD) . . . . .1111
30.8.5SDMMC command response register (SDMMC_RESPCMD) . . . . .1112
30.8.6SDMMC response 1..4 register (SDMMC_RESPx) . . . . .1112
30.8.7SDMMC data timer register (SDMMC_DTIMER) . . . . .1113
30.8.8SDMMC data length register (SDMMC_DLEN) . . . . .1114
30.8.9SDMMC data control register (SDMMC_DCTRL) . . . . .1114
30.8.10SDMMC data counter register (SDMMC_DCOUNT) . . . . .1117
30.8.11SDMMC status register (SDMMC_STA) . . . . .1117
30.8.12SDMMC interrupt clear register (SDMMC_ICR) . . . . .1118
30.8.13SDMMC mask register (SDMMC_MASK) . . . . .1120
30.8.14SDMMC FIFO counter register (SDMMC_FIFOCNT) . . . . .1122
30.8.15SDMMC data FIFO register (SDMMC_FIFO) . . . . .1123
30.8.16SDMMC register map . . . . .1124
31Controller area network (bxCAN) . . . . .1126
31.1Introduction . . . . .1126
31.2bxCAN main features . . . . .1126
31.3bxCAN general description . . . . .1126
31.3.1CAN 2.0B active core . . . . .1127
31.3.2Control, status, and configuration registers . . . . .1127
31.3.3Tx mailboxes . . . . .1127
31.3.4Acceptance filters . . . . .1127
31.4bxCAN operating modes . . . . .1128
31.4.1Initialization mode . . . . .1128
31.4.2Normal mode . . . . .1129
31.4.3Sleep mode (low-power) . . . . .1129
31.5Test mode . . . . .1130
31.5.1Silent mode . . . . .1130
31.5.2Loop back mode . . . . .1131
31.5.3Loop back combined with silent mode . . . . .1131
31.6Behavior in debug mode . . . . .1132
31.7bxCAN functional description . . . . .1132
31.7.1Transmission handling . . . . .1132
31.7.2Time triggered communication mode . . . . .1134
31.7.3Reception handling . . . . .1134
31.7.4Identifier filtering . . . . .1135
31.7.5Message storage . . . . .1139
31.7.6Error management . . . . .1140
31.7.7Bit timing . . . . .1141
31.8bxCAN interrupts . . . . .1144
31.9CAN registers . . . . .1145
31.9.1Register access protection . . . . .1145
31.9.2CAN control and status registers . . . . .1145
31.9.3CAN mailbox registers . . . . .1155
31.9.4CAN filter registers . . . . .1161
31.9.5bxCAN register map . . . . .1165
32USB on-the-go full-speed/high-speed
(OTG_FS/OTG_HS) . . . . .		1169
32.1Introduction . . . . .1169
32.2OTG_FS/OTG_HS main features . . . . .1171
32.2.1General features . . . . .1171
32.2.2Host-mode features . . . . .1172
32.2.3Peripheral-mode features . . . . .1172
32.3OTG_FS/OTG_HS implementation . . . . .1173
32.4OTG_FS/OTG_HS functional description . . . . .1174
32.4.1OTG_FS/OTG_HS block diagram . . . . .1174
32.4.2OTG_FS/OTG_HS pin and internal signals . . . . .1176
32.4.3OTG_FS/OTG_HS core . . . . .1177
32.4.4Embedded full-speed OTG PHY connected to OTG_FS . . . . .1178
32.4.5Embedded full-speed OTG PHY connected to OTG_HS . . . . .1178
32.4.6OTG detections . . . . .1179
32.4.7High-speed OTG PHY connected to OTG_HS . . . . .1179
32.5OTG_FS/OTG_HS dual role device (DRD) . . . . .1179
32.5.1ID line detection . . . . .1179
32.5.2HNP dual role device . . . . .1180
32.5.3SRP dual role device . . . . .1180
32.6OTG_FS/OTG_HS as a USB peripheral . . . . .1180
32.6.1SRP-capable peripheral . . . . .1181
32.6.2Peripheral states . . . . .1181
32.6.3Peripheral endpoints . . . . .1182
32.7OTG_FS/OTG_HS as a USB host . . . . .1184
32.7.1SRP-capable host . . . . .1185
32.7.2USB host states . . . . .1185
32.7.3Host channels . . . . .1187
32.7.4Host scheduler . . . . .1188
32.8OTG_FS/OTG_HS SOF trigger . . . . .1189
32.8.1Host SOFs . . . . .1189
32.8.2Peripheral SOFs . . . . .1190
32.9OTG_FS/OTG_HS low-power modes . . . . .1190
32.10OTG_FS/OTG_HS Dynamic update of the OTG_HFIR register . . . . .1191
32.11OTG_FS/OTG_HS data FIFOs . . . . .1192
32.11.1Peripheral FIFO architecture . . . . .1193
32.11.2Host FIFO architecture . . . . .1194
32.11.3FIFO RAM allocation . . . . .1195
32.12OTG_FS system performance . . . . .1197
32.13OTG_FS/OTG_HS interrupts . . . . .1197
32.14OTG_FS/OTG_HS control and status registers . . . . .1199
32.14.1CSR memory map . . . . .1199
32.15OTG_FS/OTG_HS registers . . . . .1205
32.15.1OTG control and status register (OTG_GOTGCTL) . . . . .1205
32.15.2OTG interrupt register (OTG_GOTGINT) . . . . .1208
32.15.3OTG AHB configuration register (OTG_GAHBCFG) . . . . .1210
32.15.4OTG USB configuration register (OTG_GUSBCFG) . . . . .1212
32.15.5OTG reset register (OTG_GRSTCTL) . . . . .1216
32.15.6OTG core interrupt register (OTG_GINTSTS) . . . . .1219
32.15.7OTG interrupt mask register (OTG_GINTMSK) . . . . .1224
32.15.8OTG receive status debug read register (OTG_GRXSTSR) . . . . .1227
32.15.9OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . .1228
32.15.10OTG status read and pop registers (OTG_GRXSTSP) . . . . .1229
32.15.11OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . . . .1230
32.15.12OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .1231
32.15.13OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . .		1232
32.15.14OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . .		1233
32.15.15OTG general core configuration register (OTG_GCCFG) . . . . .1234
32.15.16OTG core ID register (OTG_CID) . . . . .1235
32.15.17OTG core LPM configuration register (OTG_GLPMCFG) . . . . .1236
32.15.18OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . .		1240
32.15.19OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . .		1240
32.15.20Host-mode registers . . . . .1241
32.15.21OTG host configuration register (OTG_HCFG) . . . . .1241
32.15.22OTG host frame interval register (OTG_HFIR) . . . . .1242
32.15.23OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . .		1243
32.15.24OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . .		1243
32.15.25OTG host all channels interrupt register (OTG_HAINT) . . . . .1244
32.15.26OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . .		1245
32.15.27OTG host port control and status register (OTG_HPRT) . . . . .1246
32.15.28OTG host channel x characteristics register (OTG_HCCHARx) . . . . .1248
32.15.29OTG host channel x split control register (OTG_HCSPLTx) . . . . .1249
32.15.30OTG host channel x interrupt register (OTG_HCINTx) . . . . .1250
32.15.31OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . . . .1252
32.15.32OTG host channel x transfer size register (OTG_HCTSIZx) . . . . .1253
32.15.33OTG host channel x DMA address register (OTG_HCDMAx) . . . . .1254
32.15.34Device-mode registers . . . . .1255
32.15.35OTG device configuration register (OTG_DCFG) . . . . .1255
32.15.36OTG device control register (OTG_DCTL) . . . . .1257
32.15.37OTG device status register (OTG_DSTS) . . . . .1259
32.15.38OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . .		1260
32.15.39OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . .		1261
32.15.40OTG device all endpoints interrupt register (OTG_DAINT) . . . . .1263
32.15.41OTG all endpoints interrupt mask register (OTG_DAININTMSK) .....1263
32.15.42OTG device V BUS discharge time register (OTG_DVBUSDIS) .....1264
32.15.43OTG device V BUS pulsing time register (OTG_DVBUSPULSE) .....1264
32.15.44OTG device threshold control register (OTG_DTHRCTL) .....1265
32.15.45OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK) .....1266
32.15.46OTG device each endpoint interrupt register (OTG_DEACHINT) . . .1267
32.15.47OTG device each endpoint interrupt mask register (OTG_DEACHINTMSK) .....1267
32.15.48OTG device each IN endpoint-1 interrupt mask register (OTG_HS_DIEPEACHMSK1) .....1268
32.15.49OTG device each OUT endpoint-1 interrupt mask register (OTG_HS_DOEPEACHMSK1) .....1269
32.15.50OTG device control IN endpoint 0 control register (OTG_DIEPCTL0) .....1270
32.15.51OTG device IN endpoint x control register (OTG_DIEPCTLx) . . . .1272
32.15.52OTG device IN endpoint x interrupt register (OTG_DIEPINTx) . . . .1274
32.15.53OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0) .....1276
32.15.54OTG device IN endpoint x DMA address register (OTG_DIEPDMAx) .....1277
32.15.55OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) .....1277
32.15.56OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) .1278
32.15.57OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0) .....1279
32.15.58OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . .1280
32.15.59OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0) .....1282
32.15.60OTG device OUT endpoint x DMA address register (OTG_DOEPDMAx) .....1283
32.15.61OTG device OUT endpoint x control register (OTG_DOEPCTLx) .....1284
32.15.62OTG device OUT endpoint x transfer size register (OTG_DOEPTSIZx) .....1286
32.15.63OTG power and clock gating control register (OTG_PCGCCTL) . . .1287
32.15.64OTG_FS/OTG_HS register map .....1288
32.16OTG_FS/OTG_HS programming model .....1301
32.16.1Core initialization .....1301
32.16.2Host initialization .....1302
32.16.3Device initialization .....1303
32.16.4DMA mode .....1303
32.16.5Host programming model .....1303
32.16.6Device programming model .....1337
32.16.7Worst case response time .....1357
32.16.8OTG programming model .....1359
33USB PHY controller (USBPHYC) available on the STM32F7x3xx and STM32F730xx devices only .....1366
33.1USBPHYC introduction .....1366
33.2USBPHYC main features .....1366
33.3USBPHYC functional description .....1366
33.3.1USBPHYC block diagram .....1366
33.3.2USBPHYC reset and clocks .....1367
33.4USBPHYC register interface .....1367
33.4.1USBPHYC PLL1 control register (USBPHYC_PLL1) .....1367
33.4.2USBPHYC tuning control register (USBPHYC_TUNE) .....1368
33.4.3USBPHYC LDO control and status register (USBPHYC_LDO) .....1370
33.4.4USBPHYC register map .....1371
34Debug support (DBG) .....1372
34.1Overview .....1372
34.2Reference ARM® documentation .....1373
34.3SWJ debug port (serial wire and JTAG) .....1373
34.3.1Mechanism to select the JTAG-DP or the SW-DP .....1374
34.4Pinout and debug port pins .....1374
34.4.1SWJ debug port pins .....1375
34.4.2Flexible SWJ-DP pin assignment .....1375
34.4.3Internal pull-up and pull-down on JTAG pins .....1375
34.4.4Using serial wire and releasing the unused debug pins as GPIOs ..1377
34.5STM32F72xxx and STM32F73xxx JTAG Debug Port connection .....1377
34.6ID codes and locking mechanism .....1379
34.6.1MCU device ID code .....1379
34.6.2Boundary scan Debug Port .....1379
34.6.3Cortex®-M7 with FPU Debug Port .....1379
34.6.4Cortex ® -M7 with FPU JEDEC-106 ID code . . . . .1380
34.7JTAG debug port . . . . .1380
34.8SW debug port . . . . .1382
34.8.1SW protocol introduction . . . . .1382
34.8.2SW protocol sequence . . . . .1382
34.8.3SW-DP state machine (reset, idle states, ID code) . . . . .1383
34.8.4DP and AP read/write accesses . . . . .1384
34.8.5SW-DP registers . . . . .1384
34.8.6SW-AP registers . . . . .1385
34.9AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP . . . . .		1386
34.10Core debug . . . . .1387
34.11Capability of the debugger host to connect under system reset . . . . .1388
34.12FPB (Flash patch breakpoint) . . . . .1388
34.13DWT (data watchpoint trigger) . . . . .1389
34.14ITM (instrumentation trace macrocell) . . . . .1389
34.14.1General description . . . . .1389
34.14.2Time stamp packets, synchronization and overflow packets . . . . .1389
34.15ETM (Embedded trace macrocell) . . . . .1391
34.15.1General description . . . . .1391
34.15.2Signal protocol, packet types . . . . .1391
34.15.3Main ETM registers . . . . .1392
34.15.4Configuration example . . . . .1392
34.16MCU debug component (DBGMCU) . . . . .1392
34.16.1Debug support for low-power modes . . . . .1392
34.16.2Debug support for timers, watchdog, bxCAN and I 2 C . . . . .1393
34.16.3Debug MCU configuration register . . . . .1393
34.16.4DBGMCU_CR register . . . . .1393
34.16.5Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . .1394
34.16.6Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . .1396
34.17Pelican TPIU (trace port interface unit) . . . . .1397
34.17.1Introduction . . . . .1397
34.17.2TRACE pin assignment . . . . .1398
34.17.3TPIU formatter . . . . .1400
34.17.4TPIU frame synchronization packets . . . . .1400
34.17.5Transmission of the synchronization frame packet . . . . .1400

List of tables

Table 1.STM32F72xxx and STM32F73xxx register boundary addresses . . . . .58
Table 2.Boot modes . . . . .62
Table 3.STM32F72xxx and STM32F732xx/F733xx Flash memory organization . . . . .69
Table 4.STM32F730xx Flash memory organization . . . . .69
Table 5.Number of wait states according to CPU clock (HCLK) frequency . . . . .70
Table 6.Maximum program/erase parallelism . . . . .72
Table 7.Flash interrupt request . . . . .75
Table 8.Option byte organization . . . . .75
Table 9.Access versus read protection level . . . . .81
Table 10.Protections on sector i . . . . .84
Table 11.OTP area organization . . . . .84
Table 12.Flash register map and reset values . . . . .94
Table 13.Voltage regulator configuration mode versus device operating mode . . . . .102
Table 14.Low-power mode summary . . . . .107
Table 15.Features over all modes . . . . .108
Table 16.Sleep-now entry and exit . . . . .112
Table 17.Sleep-on-exit entry and exit . . . . .112
Table 18.Stop operating modes . . . . .113
Table 19.Stop mode entry and exit (STM32F72xxx and STM32F73xxx) . . . . .115
Table 20.Standby mode entry and exit . . . . .116
Table 21.PWR - register map and reset values . . . . .128
Table 22.RCC register map and reset values . . . . .192
Table 23.Port bit configuration table . . . . .197
Table 24.GPIO register map and reset values . . . . .212
Table 25.SYSCFG register map and reset values . . . . .220
Table 26.DMA1 request mapping . . . . .225
Table 27.DMA2 request mapping . . . . .225
Table 28.Source and destination address . . . . .227
Table 29.Source and destination address registers in double-buffer mode (DBM = 1) . . . . .232
Table 30.Packing/unpacking and endian behavior (bit PINC = MINC = 1) . . . . .233
Table 31.Restriction on NDT versus PSIZE and MSIZE . . . . .233
Table 32.FIFO threshold configurations . . . . .236
Table 33.Possible DMA configurations . . . . .240
Table 34.DMA interrupt requests . . . . .242
Table 35.DMA register map and reset values . . . . .252
Table 36.STM32F72xxx and STM32F73xxx vector table . . . . .257
Table 37.External interrupt/event controller register map and reset values . . . . .268
Table 38.CRC internal input/output signals . . . . .270
Table 39.CRC register map and reset values . . . . .275
Table 40.NOR/PSRAM bank selection . . . . .280
Table 41.NOR/PSRAM External memory address . . . . .281
Table 42.NAND memory mapping and timing registers . . . . .281
Table 43.NAND bank selection . . . . .281
Table 44.SDRAM bank selection . . . . .282
Table 45.SDRAM address mapping . . . . .282
Table 46.SDRAM address mapping with 8-bit data bus width . . . . .283
Table 47.SDRAM address mapping with 16-bit data bus width . . . . .283
Table 48.SDRAM address mapping with 32-bit data bus width . . . . .284
Table 49.Programmable NOR/PSRAM access parameters . . . . .286
Table 50.Non-multiplexed I/O NOR flash memory. . . . .287
Table 51.16-bit multiplexed I/O NOR flash memory . . . . .287
Table 52.Non-multiplexed I/Os PSRAM/SRAM . . . . .287
Table 53.16-Bit multiplexed I/O PSRAM . . . . .288
Table 54.NOR flash/PSRAM: example of supported memories
and transactions . . . . .		289
Table 55.FMC_BCRx bitfields (mode 1) . . . . .292
Table 56.FMC_BTRx bitfields (mode 1) . . . . .292
Table 57.FMC_BCRx bitfields (mode A) . . . . .294
Table 58.FMC_BTRx bitfields (mode A) . . . . .294
Table 59.FMC_BWTRx bitfields (mode A) . . . . .295
Table 60.FMC_BCRx bitfields (mode 2/B) . . . . .297
Table 61.FMC_BTRx bitfields (mode 2/B) . . . . .297
Table 62.FMC_BWTRx bitfields (mode 2/B) . . . . .298
Table 63.FMC_BCRx bitfields (mode C) . . . . .299
Table 64.FMC_BTRx bitfields (mode C) . . . . .300
Table 65.FMC_BWTRx bitfields (mode C) . . . . .300
Table 66.FMC_BCRx bitfields (mode D) . . . . .302
Table 67.FMC_BTRx bitfields (mode D) . . . . .302
Table 68.FMC_BWTRx bitfields (mode D) . . . . .303
Table 69.FMC_BCRx bitfields (Muxed mode) . . . . .304
Table 70.FMC_BTRx bitfields (Muxed mode) . . . . .305
Table 71.FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .310
Table 72.FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .311
Table 73.FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .312
Table 74.FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .313
Table 75.Programmable NAND flash access parameters . . . . .321
Table 76.8-bit NAND flash . . . . .321
Table 77.16-bit NAND flash . . . . .322
Table 78.Supported memories and transactions . . . . .322
Table 79.ECC result relevant bits . . . . .331
Table 80.SDRAM signals . . . . .332
Table 81.FMC register map and reset values . . . . .349
Table 82.QUADSPI pins . . . . .353
Table 83.QUADSPI interrupt requests. . . . .367
Table 84.QUADSPI register map and reset values . . . . .378
Table 85.ADC pins. . . . .382
Table 86.Analog watchdog channel selection . . . . .388
Table 87.Configuring the trigger polarity . . . . .393
Table 88.External trigger for regular channels. . . . .393
Table 89.External trigger for injected channels . . . . .394
Table 90.ADC interrupts . . . . .408
Table 91.ADC global register map. . . . .423
Table 92.ADC register map and reset values for each ADC . . . . .423
Table 93.ADC register map and reset values (common ADC registers) . . . . .425
Table 94.DAC pins. . . . .427
Table 95.External triggers . . . . .430
Table 96.DAC register map . . . . .447
Table 97.RNG internal input/output signals . . . . .449
Table 98.RNG interrupt requests. . . . .454
Table 99.RNG configurations . . . . .455
Table 100.RNG register map and reset map . . . . .458
Table 101.AES internal input/output signals . . . . .460
Table 102.CTR mode initialization vector definition . . . . .479
Table 103.GCM last block definition . . . . .481
Table 104.GCM mode IVI bitfield initialization . . . . .482
Table 105.Initialization of AES_IVRx registers in CCM mode . . . . .489
Table 106.Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .494
Table 107.DMA channel configuration for memory-to-AES data transfer . . . . .495
Table 108.DMA channel configuration for AES-to-memory data transfer . . . . .496
Table 109.AES interrupt requests . . . . .498
Table 110.Processing latency (in clock cycle) for ECB, CBC and CTR. . . . .498
Table 111.Processing latency for GCM and CCM (in clock cycle) . . . . .498
Table 112.AES register map and reset values . . . . .510
Table 113.Behavior of timer outputs versus BRK/BRK2 inputs . . . . .553
Table 114.Counting direction versus encoder signals . . . . .560
Table 115.TIMx internal trigger connection . . . . .577
Table 116.Output control bits for complementary OCx and OCxN channels with break feature . . . . .591
Table 117.TIM1 register map and reset values . . . . .603
Table 118.TIM8 register map and reset values . . . . .605
Table 119.Counting direction versus encoder signals . . . . .642
Table 120.TIMx internal trigger connection . . . . .660
Table 121.Output control bit for standard OCx channels. . . . .670
Table 122.TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . .677
Table 123.TIMx internal trigger connection . . . . .707
Table 124.Output control bit for standard OCx channels. . . . .714
Table 125.TIM9/TIM12 register map and reset values . . . . .717
Table 126.Output control bit for standard OCx channels. . . . .726
Table 127.TIM10/TIM11/TIM13/TIM14 register map and reset values . . . . .728
Table 128.TIMx register map and reset values . . . . .742
Table 129.STM32F72xxx and STM32F73xxx LPTIM features . . . . .744
Table 130.LPTIM1 external trigger connection . . . . .745
Table 131.Prescaler division ratios . . . . .746
Table 132.Encoder counting scenarios . . . . .752
Table 133.Effect of low-power modes on the LPTIM. . . . .753
Table 134.Interrupt events . . . . .754
Table 135.LPTIM register map and reset values. . . . .763
Table 136.IWDG register map and reset values . . . . .772
Table 137.WWDG register map and reset values . . . . .778
Table 138.RTC pin PC13 configuration . . . . .782
Table 139.RTC pin PI8 configuration. . . . .783
Table 140.RTC pin PC2 configuration. . . . .784
Table 141.RTC functions over modes . . . . .784
Table 142.Effect of low-power modes on RTC . . . . .796
Table 143.Interrupt control bits . . . . .797
Table 144.RTC register map and reset values . . . . .822
Table 145.I2C implementation. . . . .825
Table 146.I2C input/output pins . . . . .826
Table 147.I2C internal input/output signals . . . . .826
Table 148.Comparison of analog and digital filters . . . . .828
Table 149.I 2 C-bus and SMBus specification data setup and hold times . . . . .831
Table 150.I2C configuration. . . . .834
Table 151.I 2 C-bus and SMBus specification clock timings . . . . .845
Table 152.Timing settings for \( f_{I2CCLK} \) of 8 MHz. . . . .855
Table 153.Timing settings for \( f_{I2CCLK} \) of 16 MHz. . . . .855
Table 154.Timing settings for \( f_{I2CCLK} \) of 48 MHz. . . . .856
Table 155.SMBus timeout specifications. . . . .858
Table 156.SMBus with PEC configuration. . . . .860
Table 157.TIMEOUTA[11:0] for maximum \( t_{TIMEOUT} \) of 25 ms. . . . .861
Table 158.TIMEOUTB[11:0] for maximum \( t_{LOW:SEXT} \) and \( t_{LOW:MEXT} \) of 8 ms . . . . .861
Table 159.TIMEOUTA[11:0] for maximum \( t_{IDLE} \) of 50 \( \mu \) s . . . . .861
Table 160.Effect of low-power modes to I2C. . . . .870
Table 161.I2C interrupt requests. . . . .870
Table 162.I2C register map and reset values . . . . .886
Table 163.STM32F72xxx and STM32F73xxx USART features . . . . .889
Table 164.Noise detection from sampled data . . . . .901
Table 165.Error calculation for programmed baud rates at \( f_{CK} = 216 \) MHz
in both cases of oversampling by 8 (OVER8 = 1). . . . .		904
Table 166.Error calculation for programmed baud rates at \( f_{CK} = 216 \) MHz
in both cases of oversampling by 16 (OVER8 = 0). . . . .		904
Table 167.Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .905
Table 168.Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . .905
Table 169.Frame formats . . . . .910
Table 170.Effect of low-power modes on the USART . . . . .927
Table 171.USART interrupt requests. . . . .928
Table 172.USART register map and reset values . . . . .950
Table 173.STM32F72xxx and STM32F73xxx SPI and SPI/I2S implementation. . . . .953
Table 174.SPI interrupt requests. . . . .978
Table 175.Audio-frequency precision using 48 MHz clock derived from HSE. . . . .992
Table 176.I2S interrupt requests. . . . .998
Table 177.SPI/I2S register map and reset values . . . . .1010
Table 178.SAI internal input/output signals . . . . .1014
Table 179.SAI input/output pins. . . . .1014
Table 180.External synchronization selection . . . . .1016
Table 181.Example of possible audio frequency sampling range . . . . .1023
Table 182.SOPD pattern . . . . .1029
Table 183.Parity bit calculation . . . . .1029
Table 184.Audio sampling frequency versus symbol rates . . . . .1030
Table 185.SAI interrupt sources . . . . .1039
Table 186.SAI register map and reset values . . . . .1064
Table 187.SDMMC I/O definitions. . . . .1069
Table 188.Command format . . . . .1074
Table 189.Short response format . . . . .1075
Table 190.Long response format. . . . .1075
Table 191.Command path status flags . . . . .1075
Table 192.Data token format. . . . .1078
Table 193.DPSM flags. . . . .1079
Table 194.Transmit FIFO status flags . . . . .1080
Table 195.Receive FIFO status flags . . . . .1080
Table 196.Card status . . . . .1091
Table 197.SD status . . . . .1094
Table 198.Speed class code field . . . . .1095
Table 199.Performance move field . . . . .1096
Table 200.AU_SIZE field . . . . .1096
Table 201.Maximum AU size. . . . .1096
Table 202.Erase size field . . . . .1097
Table 203.Erase timeout field . . . . .1097
Table 204.Erase offset field . . . . .1097
Table 205.Block-oriented write commands . . . . .1100
Table 206.Block-oriented write protection commands . . . . .1101
Table 207.Erase commands . . . . .1101
Table 208.I/O mode commands . . . . .1101
Table 209.Lock card . . . . .1102
Table 210.Application-specific commands . . . . .1102
Table 211.R1 response . . . . .1103
Table 212.R2 response . . . . .1103
Table 213.R3 response . . . . .1104
Table 214.R4 response . . . . .1104
Table 215.R4b response . . . . .1104
Table 216.R5 response . . . . .1105
Table 217.R6 response . . . . .1106
Table 218.Response type and SDMMC_RESPx registers . . . . .1113
Table 219.SDMMC register map . . . . .1124
Table 220.Transmit mailbox mapping . . . . .1140
Table 221.Receive mailbox mapping . . . . .1140
Table 222.bxCAN register map and reset values . . . . .1165
Table 223.OTG_HS speeds supported . . . . .1170
Table 224.OTG_FS speeds supported . . . . .1170
Table 225.OTG_FS/OTG_HS implementation . . . . .1173
Table 226.OTG_FS input/output pins . . . . .1176
Table 227.OTG_HS input/output pins . . . . .1177
Table 228.OTG_FS/OTG_HS input/output signals . . . . .1177
Table 229.Compatibility of STM32 low power modes with the OTG . . . . .1190
Table 230.Core global control and status registers (CSRs) . . . . .1199
Table 231.Host-mode control and status registers (CSRs) . . . . .1200
Table 232.Device-mode control and status registers . . . . .1202
Table 233.Data FIFO (DFIFO) access register map . . . . .1205
Table 234.Power and clock gating control and status registers . . . . .1205
Table 235.TRDT values (FS) . . . . .1215
Table 236.TRDT values (HS) . . . . .1215
Table 237.Minimum duration for soft disconnect . . . . .1258
Table 238.OTG_FS/OTG_HS register map and reset values . . . . .1288
Table 239.USBPHYC register map and reset values . . . . .1371
Table 240.SWJ debug port pins . . . . .1375
Table 241.Flexible SWJ-DP pin assignment . . . . .1375
Table 242.JTAG debug port data registers . . . . .1380
Table 243.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .1382
Table 244.Packet request (8-bits) . . . . .1383
Table 245.ACK response (3 bits) . . . . .1383
Table 246.DATA transfer (33 bits) . . . . .1383
Table 247.SW-DP registers . . . . .1384
Table 248.Cortex ® -M7 with FPU AHB-AP registers . . . . .1386
Table 249.Core debug registers . . . . .1387
Table 250.Main ITM registers . . . . .1390
Table 251.Asynchronous TRACE pin assignment . . . . .1398
Table 252.Synchronous TRACE pin assignment . . . . .1398
Table 253.Flexible TRACE pin assignment . . . . .1399
Table 254. Important TPIU registers. . . . .1402
Table 255. DBG register map and reset values . . . . .1403
Table 256. Document revision history . . . . .1412

List of figures

Figure 1.Memory map . . . . .57
Figure 2.System architecture for STM32F72xxx and STM32F73xxx devices . . . . .63
Figure 3.Flash memory interface connection inside system architecture
(STM32F72xxx and STM32F73xxx) . . . . .		67
Figure 4.RDP levels . . . . .82
Figure 5.STM32F7x2xx and STM32F730xx power supply overview . . . . .95
Figure 6.STM32F7x3xx and STM32F730xx power supply overview . . . . .96
Figure 7.VDDUSB connected to VDD power supply . . . . .98
Figure 8.VDDUSB connected to external independent power supply . . . . .98
Figure 9.Backup domain . . . . .101
Figure 10.Power-on reset/power-down reset waveform . . . . .104
Figure 11.BOR thresholds . . . . .105
Figure 12.PVD thresholds . . . . .106
Figure 13.Simplified diagram of the reset circuit . . . . .130
Figure 14.Clock tree . . . . .131
Figure 15.HSE/ LSE clock sources . . . . .135
Figure 16.Frequency measurement with TIM5 in Input capture mode . . . . .140
Figure 17.Frequency measurement with TIM11 in Input capture mode . . . . .141
Figure 18.Basic structure of an I/O port bit . . . . .196
Figure 19.Basic structure of a 5-Volt tolerant I/O port bit . . . . .196
Figure 20.Input floating / pull up / pull down configurations . . . . .201
Figure 21.Output configuration . . . . .202
Figure 22.Alternate function configuration . . . . .203
Figure 23.High impedance-analog configuration . . . . .203
Figure 24.DMA block diagram . . . . .223
Figure 25.Channel selection . . . . .225
Figure 26.Peripheral-to-memory mode . . . . .228
Figure 27.Memory-to-peripheral mode . . . . .229
Figure 28.Memory-to-memory mode . . . . .230
Figure 29.FIFO structure . . . . .235
Figure 30.External interrupt/event controller block diagram . . . . .262
Figure 31.External interrupt/event GPIO mapping . . . . .264
Figure 32.CRC calculation unit block diagram . . . . .270
Figure 33.FMC block diagram . . . . .277
Figure 34.FMC memory banks . . . . .280
Figure 35.Mode 1 read access waveforms . . . . .291
Figure 36.Mode 1 write access waveforms . . . . .291
Figure 37.Mode A read access waveforms . . . . .293
Figure 38.Mode A write access waveforms . . . . .293
Figure 39.Mode 2 and mode B read access waveforms . . . . .295
Figure 40.Mode 2 write access waveforms . . . . .296
Figure 41.Mode B write access waveforms . . . . .296
Figure 42.Mode C read access waveforms . . . . .298
Figure 43.Mode C write access waveforms . . . . .299
Figure 44.Mode D read access waveforms . . . . .301
Figure 45.Mode D write access waveforms . . . . .301
Figure 46.Muxed read access waveforms . . . . .303
Figure 47.Muxed write access waveforms . . . . .304
Figure 48.Asynchronous wait during a read access waveforms . . . . .306
Figure 49.Asynchronous wait during a write access waveforms . . . . .307
Figure 50.Wait configuration waveforms . . . . .309
Figure 51.Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . .310
Figure 52.Synchronous multiplexed write mode waveforms - PSRAM (CRAM) . . . . .312
Figure 53.NAND flash controller waveforms for common memory access . . . . .323
Figure 54.Access to non 'CE don't care' NAND-flash . . . . .325
Figure 55.Burst write SDRAM access waveforms . . . . .334
Figure 56.Burst read SDRAM access . . . . .335
Figure 57.Logic diagram of Read access with RBURST bit set (CAS=1, RPIPE=0) . . . . .336
Figure 58.Read access crossing row boundary . . . . .338
Figure 59.Write access crossing row boundary . . . . .338
Figure 60.Self-refresh mode . . . . .341
Figure 61.Power-down mode . . . . .342
Figure 62.QUADSPI block diagram when dual-flash mode is disabled . . . . .352
Figure 63.QUADSPI block diagram when dual-flash mode is enabled . . . . .353
Figure 64.Example of read command in quad-SPI mode . . . . .354
Figure 65.Example of a DDR command in quad-SPI mode . . . . .357
Figure 66.NCS when CKMODE = 0 (T = CLK period) . . . . .365
Figure 67.NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .365
Figure 68.NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . .366
Figure 69.NCS when CKMODE = 1 with an abort (T = CLK period) . . . . .366
Figure 70.Single ADC block diagram . . . . .381
Figure 71.ADC1 connectivity . . . . .383
Figure 72.ADC2 connectivity . . . . .384
Figure 73.ADC3 connectivity . . . . .385
Figure 74.Timing diagram . . . . .388
Figure 75.Analog watchdog's guarded area . . . . .388
Figure 76.Injected conversion latency . . . . .390
Figure 77.Right alignment of 12-bit data . . . . .392
Figure 78.Left alignment of 12-bit data . . . . .392
Figure 79.Left alignment of 6-bit data . . . . .392
Figure 80.Multi ADC block diagram (1) . . . . .397
Figure 81.Injected simultaneous mode on 4 channels: dual ADC mode . . . . .400
Figure 82.Injected simultaneous mode on 4 channels: triple ADC mode . . . . .400
Figure 83.Regular simultaneous mode on 16 channels: dual ADC mode . . . . .401
Figure 84.Regular simultaneous mode on 16 channels: triple ADC mode . . . . .401
Figure 85.Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode . . . . .402
Figure 86.Interleaved mode on 1 channel in continuous conversion mode: triple ADC mode . . . . .403
Figure 87.Alternate trigger: injected group of each ADC . . . . .404
Figure 88.Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . .404
Figure 89.Alternate trigger: injected group of each ADC . . . . .405
Figure 90.Alternate + regular simultaneous . . . . .406
Figure 91.Case of trigger occurring during injected conversion . . . . .406
Figure 92.Temperature sensor and VREFINT channel block diagram . . . . .407
Figure 93.DAC channel block diagram . . . . .427
Figure 94.DAC output buffer connection . . . . .428
Figure 95.Data registers in single DAC channel mode . . . . .429
Figure 96.Data registers in dual DAC channel mode . . . . .429
Figure 97.Timing diagram for conversion with trigger disabled TEN = 0 . . . . .430
Figure 98.DAC LFSR register calculation algorithm . . . . .432
Figure 99.DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .432
Figure 100. DAC triangle wave generation . . . . .433
Figure 101. DAC conversion (SW trigger enabled) with triangle wave generation . . . . .433
Figure 102. RNG block diagram . . . . .449
Figure 103. Entropy source model . . . . .450
Figure 104. AES block diagram . . . . .460
Figure 105. ECB encryption and decryption principle . . . . .462
Figure 106. CBC encryption and decryption principle . . . . .463
Figure 107. CTR encryption and decryption principle . . . . .464
Figure 108. GCM encryption and authentication principle . . . . .465
Figure 109. GMAC authentication principle . . . . .465
Figure 110. CCM encryption and authentication principle . . . . .466
Figure 111. STM32 cryptolib AES flowchart examples . . . . .467
Figure 112. STM32 cryptolib AES flowchart examples (continued) . . . . .468
Figure 113. Encryption key derivation for ECB/CBC decryption (Mode 2) . . . . .471
Figure 114. Example of suspend mode management . . . . .472
Figure 115. ECB encryption . . . . .473
Figure 116. ECB decryption . . . . .473
Figure 117. CBC encryption . . . . .474
Figure 118. CBC decryption . . . . .474
Figure 119. ECB/CBC encryption (Mode 1) . . . . .475
Figure 120. ECB/CBC decryption (Mode 3) . . . . .476
Figure 121. Message construction in CTR mode . . . . .478
Figure 122. CTR encryption . . . . .479
Figure 123. CTR decryption . . . . .479
Figure 124. Message construction in GCM . . . . .481
Figure 125. GCM authenticated encryption . . . . .482
Figure 126. Message construction in GMAC mode . . . . .486
Figure 127. GMAC authentication mode . . . . .486
Figure 128. Message construction in CCM mode . . . . .487
Figure 129. CCM mode authenticated decryption . . . . .489
Figure 130. 128-bit block construction with respect to data swap . . . . .493
Figure 131. DMA transfer of a 128-bit data block during input phase . . . . .495
Figure 132. DMA transfer of a 128-bit data block during output phase . . . . .496
Figure 133. AES interrupt signal generation . . . . .497
Figure 134. Advanced-control timer block diagram . . . . .513
Figure 135. Counter timing diagram with prescaler division change from 1 to 2 . . . . .515
Figure 136. Counter timing diagram with prescaler division change from 1 to 4 . . . . .515
Figure 137. Counter timing diagram, internal clock divided by 1 . . . . .517
Figure 138. Counter timing diagram, internal clock divided by 2 . . . . .517
Figure 139. Counter timing diagram, internal clock divided by 4 . . . . .518
Figure 140. Counter timing diagram, internal clock divided by N . . . . .518
Figure 141. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .519
Figure 142. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .519
Figure 143. Counter timing diagram, internal clock divided by 1 . . . . .521
Figure 144. Counter timing diagram, internal clock divided by 2 . . . . .521
Figure 145. Counter timing diagram, internal clock divided by 4 . . . . .522
Figure 146. Counter timing diagram, internal clock divided by N . . . . .522
Figure 147. Counter timing diagram, update event when repetition counter is not used . . . . .523
Figure 148. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .524
Figure 149. Counter timing diagram, internal clock divided by 2 . . . . .525
Figure 150. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .525
Figure 151. Counter timing diagram, internal clock divided by N . . . . .526
Figure 152. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .526
Figure 153. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .527
Figure 154. Update rate examples depending on mode and TIMx_RCR register settings . . . . .528
Figure 155. External trigger input block . . . . .529
Figure 156. Control circuit in normal mode, internal clock divided by 1 . . . . .530
Figure 157. TI2 external clock connection example. . . . .531
Figure 158. Control circuit in external clock mode 1 . . . . .532
Figure 159. External trigger input block . . . . .532
Figure 160. Control circuit in external clock mode 2 . . . . .533
Figure 161. Capture/compare channel (example: channel 1 input stage) . . . . .534
Figure 162. Capture/compare channel 1 main circuit . . . . .535
Figure 163. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .535
Figure 164. Output stage of capture/compare channel (channel 4). . . . .536
Figure 165. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .536
Figure 166. PWM input mode timing . . . . .538
Figure 167. Output compare mode, toggle on OC1 . . . . .540
Figure 168. Edge-aligned PWM waveforms (ARR=8) . . . . .541
Figure 169. Center-aligned PWM waveforms (ARR=8). . . . .542
Figure 170. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .544
Figure 171. Combined PWM mode on channel 1 and 3 . . . . .545
Figure 172. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .546
Figure 173. Complementary output with dead-time insertion . . . . .547
Figure 174. Dead-time waveforms with delay greater than the negative pulse . . . . .547
Figure 175. Dead-time waveforms with delay greater than the positive pulse. . . . .548
Figure 176. Break and Break2 circuitry overview . . . . .550
Figure 177. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .552
Figure 178. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .553
Figure 179. PWM output state following BRK assertion (OSSI=0) . . . . .554
Figure 180. Clearing TIMx_OCxREF . . . . .555
Figure 181. 6-step generation, COM example (OSSR=1) . . . . .556
Figure 182. Example of one pulse mode. . . . .557
Figure 183. Retriggerable one pulse mode . . . . .559
Figure 184. Example of counter operation in encoder interface mode. . . . .560
Figure 185. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .561
Figure 186. Measuring time interval between edges on 3 signals . . . . .562
Figure 187. Example of Hall sensor interface . . . . .564
Figure 188. Control circuit in reset mode . . . . .565
Figure 189. Control circuit in Gated mode . . . . .566
Figure 190. Control circuit in trigger mode . . . . .567
Figure 191. Control circuit in external clock mode 2 + trigger mode . . . . .568
Figure 192. General-purpose timer block diagram . . . . .609
Figure 193. Counter timing diagram with prescaler division change from 1 to 2 . . . . .611
Figure 194. Counter timing diagram with prescaler division change from 1 to 4 . . . . .611
Figure 195. Counter timing diagram, internal clock divided by 1 . . . . .612
Figure 196. Counter timing diagram, internal clock divided by 2 . . . . .613
Figure 197. Counter timing diagram, internal clock divided by 4 . . . . .613
Figure 198. Counter timing diagram, internal clock divided by N. . . . .614
Figure 199. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .614
Figure 200. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .615
Figure 201. Counter timing diagram, internal clock divided by 1 . . . . .616
Figure 202. Counter timing diagram, internal clock divided by 2 . . . . .616
Figure 203. Counter timing diagram, internal clock divided by 4 . . . . .617
Figure 204. Counter timing diagram, internal clock divided by N . . . . .617
Figure 205. Counter timing diagram, Update event . . . . .618
Figure 206. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .619
Figure 207. Counter timing diagram, internal clock divided by 2 . . . . .620
Figure 208. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .620
Figure 209. Counter timing diagram, internal clock divided by N . . . . .621
Figure 210. Counter timing diagram, Update event with ARPE=1 (counter underflow) . . . . .621
Figure 211. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .622
Figure 212. Control circuit in normal mode, internal clock divided by 1 . . . . .623
Figure 213. TI2 external clock connection example . . . . .623
Figure 214. Control circuit in external clock mode 1 . . . . .624
Figure 215. External trigger input block . . . . .625
Figure 216. Control circuit in external clock mode 2 . . . . .626
Figure 217. Capture/Compare channel (example: channel 1 input stage) . . . . .627
Figure 218. Capture/Compare channel 1 main circuit . . . . .627
Figure 219. Output stage of Capture/Compare channel (channel 1) . . . . .628
Figure 220. PWM input mode timing . . . . .630
Figure 221. Output compare mode, toggle on OC1 . . . . .632
Figure 222. Edge-aligned PWM waveforms (ARR=8) . . . . .633
Figure 223. Center-aligned PWM waveforms (ARR=8) . . . . .634
Figure 224. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .635
Figure 225. Combined PWM mode on channels 1 and 3 . . . . .637
Figure 226. Clearing TIMx_OCxREF . . . . .638
Figure 227. Example of one-pulse mode . . . . .639
Figure 228. Retriggerable one-pulse mode . . . . .641
Figure 229. Example of counter operation in encoder interface mode . . . . .642
Figure 230. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .643
Figure 231. Control circuit in reset mode . . . . .644
Figure 232. Control circuit in gated mode . . . . .645
Figure 233. Control circuit in trigger mode . . . . .646
Figure 234. Control circuit in external clock mode 2 + trigger mode . . . . .647
Figure 235. Master/Slave timer example . . . . .648
Figure 236. Master/slave connection example with 1 channel only timers . . . . .648
Figure 237. Gating TIM with OC1REF of TIM3 . . . . .649
Figure 238. Gating TIM with Enable of TIM3 . . . . .650
Figure 239. Triggering TIM with update of TIM3 . . . . .651
Figure 240. Triggering TIM with Enable of TIM3 . . . . .651
Figure 241. Triggering TIM3 and TIM2 with TIM3 TI1 input . . . . .652
Figure 242. General-purpose timer block diagram (TIM9/TIM12) . . . . .681
Figure 243. General-purpose timer block diagram (TIM10/TIM11/TIM13/TIM14) . . . . .682
Figure 244. Counter timing diagram with prescaler division change from 1 to 2 . . . . .684
Figure 245. Counter timing diagram with prescaler division change from 1 to 4 . . . . .684
Figure 246. Counter timing diagram, internal clock divided by 1 . . . . .685
Figure 247. Counter timing diagram, internal clock divided by 2 . . . . .686
Figure 248. Counter timing diagram, internal clock divided by 4 . . . . .686
Figure 249. Counter timing diagram, internal clock divided by N . . . . .687
Figure 250. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded) . . . . .		687
Figure 251. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded) . . . . .		688
Figure 252. Control circuit in normal mode, internal clock divided by 1 . . . . .689
Figure 253. TI2 external clock connection example . . . . .689
Figure 254.Control circuit in external clock mode 1 . . . . .690
Figure 255.Capture/compare channel (example: channel 1 input stage) . . . . .691
Figure 256.Capture/compare channel 1 main circuit . . . . .691
Figure 257.Output stage of capture/compare channel (channel 1). . . . .692
Figure 258.PWM input mode timing . . . . .694
Figure 259.Output compare mode, toggle on OC1. . . . .695
Figure 260.Edge-aligned PWM waveforms (ARR=8) . . . . .696
Figure 261.Combined PWM mode on channel 1 and 2 . . . . .697
Figure 262.Example of one pulse mode. . . . .698
Figure 263.Retriggerable one pulse mode . . . . .700
Figure 264.Control circuit in reset mode . . . . .701
Figure 265.Control circuit in gated mode . . . . .702
Figure 266.Control circuit in trigger mode . . . . .702
Figure 267.Basic timer block diagram. . . . .730
Figure 268.Counter timing diagram with prescaler division change from 1 to 2 . . . . .732
Figure 269.Counter timing diagram with prescaler division change from 1 to 4 . . . . .732
Figure 270.Counter timing diagram, internal clock divided by 1 . . . . .733
Figure 271.Counter timing diagram, internal clock divided by 2 . . . . .734
Figure 272.Counter timing diagram, internal clock divided by 4 . . . . .734
Figure 273.Counter timing diagram, internal clock divided by N . . . . .735
Figure 274.Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . .		735
Figure 275.Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . .		736
Figure 276.Control circuit in normal mode, internal clock divided by 1 . . . . .737
Figure 277.Low-power timer block diagram . . . . .744
Figure 278.Glitch filter timing diagram . . . . .746
Figure 279.LPTIM output waveform, single counting mode configuration . . . . .748
Figure 280.LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set). . . . .		748
Figure 281.LPTIM output waveform, Continuous counting mode configuration . . . . .749
Figure 282.Waveform generation . . . . .750
Figure 283.Encoder mode counting sequence . . . . .753
Figure 284.Independent watchdog block diagram . . . . .764
Figure 285.Watchdog block diagram . . . . .774
Figure 286.Window watchdog timing diagram . . . . .775
Figure 287.RTC block diagram . . . . .781
Figure 288.Block diagram . . . . .826
Figure 289.I 2 C-bus protocol . . . . .828
Figure 290.Setup and hold timings . . . . .829
Figure 291.I2C initialization flow . . . . .832
Figure 292.Data reception . . . . .833
Figure 293.Data transmission . . . . .833
Figure 294.Target initialization flow . . . . .837
Figure 295.Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .838
Figure 296.Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .839
Figure 297.Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .840
Figure 298.Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .841
Figure 299.Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .842
Figure 300.Transfer bus diagrams for I2C target receiver
(mandatory events only). . . . .		842
Figure 301.Controller clock generation . . . . .844
Figure 302. Controller initialization flow . . . . .846
Figure 303. 10-bit address read access with HEAD10R = 0 . . . . .846
Figure 304. 10-bit address read access with HEAD10R = 1 . . . . .847
Figure 305. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .848
Figure 306. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .849
Figure 307. Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . .		850
Figure 308. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .852
Figure 309. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .853
Figure 310. Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . .		854
Figure 311. Timeout intervals for t LOW:SEXT , t LOW:MEXT . . . . .858
Figure 312. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .862
Figure 313. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .862
Figure 314. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .864
Figure 315. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .865
Figure 316. Bus transfer diagrams for SMBus controller transmitter . . . . .866
Figure 317. Bus transfer diagrams for SMBus controller receiver . . . . .868
Figure 318. USART block diagram . . . . .891
Figure 319. Word length programming . . . . .893
Figure 320. Configurable stop bits . . . . .895
Figure 321. TC/TXE behavior when transmitting . . . . .896
Figure 322. Start bit detection when oversampling by 16 or 8. . . . .897
Figure 323. Data sampling when oversampling by 16. . . . .900
Figure 324. Data sampling when oversampling by 8. . . . .901
Figure 325. Mute mode using Idle line detection . . . . .908
Figure 326. Mute mode using address mark detection . . . . .909
Figure 327. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .912
Figure 328. Break detection in LIN mode vs. Framing error detection. . . . .913
Figure 329. USART example of synchronous transmission. . . . .914
Figure 330. USART data clock timing diagram (M bits = 00). . . . .914
Figure 331. USART data clock timing diagram (M bits = 01) . . . . .915
Figure 332. RX data setup/hold time . . . . .915
Figure 333. ISO 7816-3 asynchronous protocol . . . . .917
Figure 334. Parity error detection using the 1.5 stop bits . . . . .918
Figure 335. IrDA SIR ENDEC- block diagram . . . . .922
Figure 336. IrDA data modulation (3/16) - normal mode . . . . .922
Figure 337. Transmission using DMA . . . . .924
Figure 338. Reception using DMA . . . . .925
Figure 339. Hardware flow control between 2 USARTs . . . . .925
Figure 340. RS232 RTS flow control . . . . .926
Figure 341. RS232 CTS flow control . . . . .927
Figure 342. USART interrupt mapping diagram . . . . .929
Figure 343. SPI block diagram. . . . .954
Figure 344. Full-duplex single master/ single slave application. . . . .955
Figure 345. Half-duplex single master/ single slave application . . . . .956
Figure 346. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		957
Figure 347. Master and three independent slaves. . . . .958
Figure 348. Multimaster application . . . . .959
Figure 349. Hardware/software slave select management . . . . .960
Figure 350. Data clock timing diagram . . . . .961
Figure 351. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .962
Figure 352. Packing data in FIFO for transmission and reception . . . . .966
Figure 353. Master full-duplex communication . . . . .969
Figure 354. Slave full-duplex communication . . . . .970
Figure 355. Master full-duplex communication with CRC . . . . .971
Figure 356. Master full-duplex communication in packed mode . . . . .972
Figure 357. NSSP pulse generation in Motorola SPI master mode . . . . .975
Figure 358. TI mode transfer . . . . .976
Figure 359. I2S block diagram . . . . .979
Figure 360. Full-duplex communication . . . . .981
Figure 361. I 2 S Philips protocol waveforms (16/32-bit full accuracy). . . . .982
Figure 362. I 2 S Philips standard waveforms (24-bit frame) . . . . .982
Figure 363. Transmitting 0x8EAA33 . . . . .983
Figure 364. Receiving 0x8EAA33 . . . . .983
Figure 365. I 2 S Philips standard (16-bit extended to 32-bit packet frame) . . . . .983
Figure 366. Example of 16-bit data frame extended to 32-bit channel frame . . . . .983
Figure 367. MSB Justified 16-bit or 32-bit full-accuracy length . . . . .984
Figure 368. MSB justified 24-bit frame length . . . . .984
Figure 369. MSB justified 16-bit extended to 32-bit packet frame . . . . .985
Figure 370. LSB justified 16-bit or 32-bit full-accuracy . . . . .985
Figure 371. LSB justified 24-bit frame length . . . . .985
Figure 372. Operations required to transmit 0x3478AE. . . . .986
Figure 373. Operations required to receive 0x3478AE . . . . .986
Figure 374. LSB justified 16-bit extended to 32-bit packet frame . . . . .986
Figure 375. Example of 16-bit data frame extended to 32-bit channel frame . . . . .987
Figure 376. PCM standard waveforms (16-bit) . . . . .987
Figure 377. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .988
Figure 378. Start sequence in master mode . . . . .989
Figure 379. Audio sampling frequency definition . . . . .990
Figure 380. I 2 S clock generator architecture . . . . .990
Figure 381. SAI functional block diagram . . . . .1013
Figure 382. Audio frame . . . . .1017
Figure 383. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .1019
Figure 384. FS role is start of frame (FSDEF = 0). . . . .1020
Figure 385. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .1021
Figure 386. First bit offset . . . . .1021
Figure 387. Audio block clock generator overview . . . . .1022
Figure 388. AC'97 audio frame . . . . .1026
Figure 389. Example of typical AC'97 configuration on devices featuring at least
two embedded SAIs (three external AC'97 decoders) . . . . .		1027
Figure 390. SPDIF format . . . . .1028
Figure 391. SAI_xDR register ordering . . . . .1029
Figure 392. Data companding hardware in an audio block in the SAI . . . . .1032
Figure 393. Tristate strategy on SD output line on an inactive slot . . . . .1034
Figure 394. Tristate on output data line in a protocol like I2S . . . . .1035
Figure 395. Overrun detection error. . . . .1036
Figure 396. FIFO underrun event . . . . .1036
Figure 397. “No response” and “no data” operations. . . . .1067
Figure 398. (Multiple) block read operation . . . . .1067
Figure 399. (Multiple) block write operation . . . . .1067
Figure 400. Sequential read operation. . . . .1068
Figure 401. Sequential write operation . . . . .1068
Figure 402. SDMMC block diagram . . . . .1068
Figure 403. SDMMC adapter . . . . .1070
Figure 404. Control unit . . . . .1071
Figure 405. SDMMC_CK clock dephasing (BYPASS = 0). . . . .1072
Figure 406. SDMMC adapter command path . . . . .1072
Figure 407. Command path state machine (SDMMC). . . . .1073
Figure 408. SDMMC command transfer . . . . .1074
Figure 409. Data path . . . . .1076
Figure 410. Data path state machine (DPSM). . . . .1077
Figure 411. CAN network topology . . . . .1127
Figure 412. Single-CAN block diagram . . . . .1128
Figure 413. bxCAN operating modes. . . . .1130
Figure 414. bxCAN in silent mode . . . . .1131
Figure 415. bxCAN in Loop back mode . . . . .1131
Figure 416. bxCAN in combined mode . . . . .1132
Figure 417. Transmit mailbox states . . . . .1133
Figure 418. Receive FIFO states . . . . .1134
Figure 419. Filter bank scale configuration - Register organization. . . . .1137
Figure 420. Example of filter numbering . . . . .1138
Figure 421. Filtering mechanism example . . . . .1139
Figure 422. CAN error state diagram. . . . .1140
Figure 423. Bit timing . . . . .1142
Figure 424. CAN frames . . . . .1143
Figure 425. Event flags and interrupt generation. . . . .1144
Figure 426. CAN mailbox registers . . . . .1156
Figure 427. OTG_FS full-speed block diagram . . . . .1174
Figure 428. OTG_HS high-speed block diagram for STM32F7x2xx . . . . .1175
Figure 429. OTG_HS high-speed block diagram for STM32F7x3xx . . . . .1176
Figure 430. OTG_FS/OTG_HS A-B device connection. . . . .1179
Figure 431. OTG_FS/OTG_HS peripheral-only connection . . . . .1181
Figure 432. OTG_FS/OTG_HS host-only connection . . . . .1185
Figure 433. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .1189
Figure 434. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .1192
Figure 435. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .1193
Figure 436. Host-mode FIFO address mapping and AHB FIFO access mapping. . . . .1194
Figure 437. Interrupt hierarchy. . . . .1198
Figure 438. Transmit FIFO write task . . . . .1306
Figure 439. Receive FIFO read task . . . . .1307
Figure 440. Normal bulk/control OUT/SETUP . . . . .1309
Figure 441. Bulk/control IN transactions . . . . .1313
Figure 442. Normal interrupt OUT . . . . .1316
Figure 443. Normal interrupt IN . . . . .1321
Figure 444. Isochronous OUT transactions . . . . .1323
Figure 445. Isochronous IN transactions . . . . .1326
Figure 446. Normal bulk/control OUT/SETUP transactions - DMA . . . . .1328
Figure 447. Normal bulk/control IN transaction - DMA. . . . .1330
Figure 448. Normal interrupt OUT transactions - DMA mode . . . . .1331
Figure 449. Normal interrupt IN transactions - DMA mode . . . . .1332
Figure 450. Normal isochronous OUT transaction - DMA mode . . . . .1333
Figure 451. Normal isochronous IN transactions - DMA mode . . . . .1334
Figure 452. Receive FIFO packet read . . . . .1340
Figure 453. Processing a SETUP packet . . . . .1342
Figure 454. Bulk OUT transaction . . . . .1349
Figure 455. TRDT max timing case . . . . .1359
Figure 456. A-device SRP . . . . .1360
Figure 457. B-device SRP . . . . .1361
Figure 458. A-device HNP . . . . .1362
Figure 459. B-device HNP . . . . .1364
Figure 460. USBPHYC block diagram . . . . .1367
Figure 461. Block diagram of STM32 MCU and Cortex®-M7 with FPU -level
debug support . . . . .		1372
Figure 462. SWJ debug port . . . . .1374
Figure 463. JTAG Debug Port connections . . . . .1378
Figure 464. TPIU block diagram . . . . .1397

Chapters