37. Revision history

Table 253. Document revision history

DateRevisionChanges
03-Nov-20161Initial release.
15-Dec-20162Updated:
– Section 18: General-purpose timers (TIM2 to TIM5)
– Section 19: General-purpose timers (TIM9 to TIM14)
– Section 20: Basic timers (TIM6/7)
09-Mar-20173Updated:
– Section 11.2: FSMC main features
– Section 11.5: External device address mapping
– Section 11.5.1: NOR/PSRAM address mapping
Added:
– Section 12.3.2: QUADSPI pins
– Table 71: QUADSPI pins
03-May-20174Updated:
– Section 13: Analog-to-digital converter (ADC)
– Section 25: Real-time clock (RTC)
– Section 29: Serial peripheral interface/ inter-IC sound (SPI/I2S)
12-Jun-20175Updated:
– Table 5: Flash module organization
– Section 3.4.1: Relation between CPU clock frequency and Flash memory read time
– Section 3.5.3: Erase
– Section 3.6.4: Write protections
– Section 3.8.5: Flash control register (FLASH_CR)
– Table 40: Vector table for STM32F413/423
– Section 10.2.5: External interrupt/event line mapping
– Section 10.3: EXTI registers
– Table 41: External interrupt/event controller register map and reset values
22-Sep-20176Updated:
– Table 13: Flash register map and reset values
– Section 32: Controller area network (bxCAN)
18-Feb-20187Updated:
– Section 24: AES hardware accelerator (AES)
– Section 33: USB on-the-go full-speed (OTG_FS)

Table 253. Document revision history (continued)

DateRevisionChanges
22-May-20188Updated:
– Figure 13: Clock tree
– Section 6.3.27: RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)
– Section 26.6: FMPI2C interrupts
– Figure 32: FSMC memory banks
Removed:
– Figure 387: I2C interrupt mapping diagram .
21-Oct-20249Added Section 36: Important security notice .
Flash:
Updated Table 7: Maximum program/erase parallelism .
Added Note before Table 11: Access versus read protection level .
PWR:
Updated Section 5.1.2: Battery backup domain .
Updated Section 5.2.3: Programmable voltage detector (PVD) .
Updated Section 5.4.1: PWR power control register (PWR_CR) .
Updated Section 5.4.2: PWR power control/status register (PWR_CSR) .
RCC:
Updated Section 6.1.1: System reset .
Updated Section 6.1.3: Backup domain reset .
Updated Section 6.3: RCC registers
GPIO:
Updated Section 7.3.2: I/O pin multiplexer and mapping .
DMA:
Updated Section 9.1: DMA introduction .
Updated Section 9.3.4: Channel selection .
Updated Section Table 30.: DMA1 request mapping .
ADC:
Updating Section 13.2: ADC main features .
Updating Table 74: ADC pins .
Updated Section : Temperature sensor, V REFINT and V BAT internal channels .
Updating Table 77: External trigger for regular channels .
Updating Table 78: External trigger for injected channels .
Updating Section 13.9: Temperature sensor .
Updating Section 13.12.1: ADC status register (ADC_SR) .
DAC:
Updated Figure 69: Data registers in dual DAC channel mode .

Table 253. Document revision history (continued)

DateRevisionChanges
21-Oct-20249
(Continued)

DFSDM:
Updated Section 15.2: DFSDM main features .
Updated introduction in Section 15.7: DFSDM channel y registers (y=0..7) .
Updated Section 15.7.5: DFSDM channel y data input register (DFSDM_CHyDATINR) .
Updated introduction in Section 15.8: DFSDM filter x module registers (x=0..3) .
RNG:
The whole section is re-edited.
TIM1/TIM8:
Updated Section 17.3.16: Encoder interface mode .
Updated SMS bitfield in Section 17.4.3: TIM1&TIM8 slave mode control register (TIMx_SMCR) .
Updated OC1P bitfield in Section 17.4.7: TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) .
TIM2/TIM5:
Updated Section 18.3.12: Encoder interface mode .
Updated SMS bitfield in Section 18.4.3: TIMx slave mode control register (TIMx_SMCR) .
updated OC1PE bitfield in Section 18.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1) .
TIM9 to TIM14:
Updated OC1PE bitfield in Section 19.5.5: TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) .
Updated OC1M bitfield in Section 19.5.5: TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) .
LPTIM:
Updated Section 21.2: LPTIM main features .
Updated Section 21.4.4: LPTIM reset and clocks .
Updated Section 21.4.7: Trigger multiplexer .
Updated Section 21.4.10: Waveform generation .
Added Section 21.5: LPTIM low-power modes .
Updated Section 21.7: LPTIM registers .
IWDG:
Updated note below Table 122: Min/max IWDG timeout periods (ms) at 32 kHz (LSI) .
WWDG:
Updated Section 23.5: Debug mode .
AES:
Updated Section : Suspend/resume operations in GCM mode .
RTC:
Updated Section 25.3.6: Reading the calendar .
Updated WUTE bitfield in Section 25.6.3: RTC control register (RTC_CR) .

Table 253. Document revision history (continued)

DateRevisionChanges
21-Oct-20249
(Continued)

Updated Section 25.6.4: RTC initialization and status register (RTC_ISR) .

I2C:
The whole section is re-edited.

SAI:
Updated Section 30.4: Main SAI modes .
Updated FRL bitfield in Section 30.17.3: SAI xFrame configuration register (SAI_XFRCR) where x is A or B .

SDIO:
Updated CLKDIV bitfield in Section 31.8.2: SDIO clock control register (SDIO_CLKCR) .

OTG:
Updated Section 33.4.3: OTG_FS core .
Updated Section 33.4.4: Embedded full-speed OTG PHY connected to OTG_FS .
Updated Section 33.4.5: OTG detections .
Updated introduction in Section 33.7: OTG_FS as a USB host .
Updated Table 228: Core global control and status registers (CSRs) .
Updated introduction in Section 33.15.2: OTG interrupt register (OTG_GOTGINT) .
Updated Section 33.15.8: OTG receive status debug read register (OTG_GRXSTSR) .
Added Section 33.15.9: OTG receive status debug read [alternate] (OTG_GRXSTSR) .
Added Section 33.15.10: OTG status read and pop registers (OTG_GRXSTSP) .
Added Section 33.15.11: OTG status read and pop registers [alternate] (OTG_GRXSTSP) .
Updated Section 33.15.19: OTG device IN endpoint transmit FIFO x size register (OTG_DIEPTXFx) .
Updated RLDCTRL bitfield in Section 33.15.22: OTG host frame interval register (OTG_HFIR) .
Updated Section 33.15.29: OTG host channel x interrupt register (OTG_HCINTx) .
Updated Section 33.15.31: OTG host channel x transfer size register (OTG_HCTSIZx) .
Updated Section 33.15.36: OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) .
Updated Section 33.15.37: OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) .
Updated Section 33.15.44: OTG device IN endpoint x control register (OTG_DIEPCTLx) .
Updated Section 33.15.45: OTG device IN endpoint x interrupt register (OTG_DIEPINTx) .
Updated Section 33.15.47: OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) .
Updated Section 33.16.3: Device initialization .

Table 253. Document revision history (continued)

DateRevisionChanges
21-Oct-20249
(Continued)		Updated Section : Endpoint deactivation .
DEBUG:
Updated Section 34.4.2: Flexible SWJ-DP pin assignment .
Updated Section : DBGMCU_IDCODE .
Updated Section 34.16.4: Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) .

Index

A

ADC_CCR363
ADC_CR1352
ADC_CR2354
ADC_CSR362
ADC_DR362
ADC_HTR357
ADC_JDRx361
ADC_JOFRx357
ADC_JSQR361
ADC_LTR358
ADC_SMPR1356
ADC_SMPR2357
ADC_SQR1358
ADC_SQR2359
ADC_SQR3360
ADC_SR351
AES_CR728
AES_DINR732
AES_DOUTR733
AES_IVR735
AES_KEYRx733
AES_SR731

C

CAN_BTR1106
CAN_ESR1105
CAN_FA1R1115
CAN_FFA1R1114
CAN_FIRx1115
CAN_FM1R1113
CAN_FMR1113
CAN_FS1R1114
CAN_IER1104
CAN_MCR1097
CAN_MSR1099
CAN_RDHxR1112
CAN_RDLxR1112
CAN_RDTxR1111
CAN_RF0R1103
CAN_RF1R1103
CAN_RIxR1110
CAN_TDHxR1110
CAN_TDLxR1109
CAN_TDTxR1109
CAN_TIxR1108
CAN_TSR1100
CKGATENR180
CRC_DR91
CRC_IDR92

D

DAC_CR378
DAC_DHR12L1382
DAC_DHR12L2383
DAC_DHR12LD384
DAC_DHR12R1381
DAC_DHR12R2383
DAC_DHR12RD384
DAC_DHR8R1382
DAC_DHR8R2383
DAC_DHR8RD385
DAC_DOR1385
DAC_DOR2385
DAC_SR386
DAC_SWTRIGR381
DBGMCU_APB1_FZ1298
DBGMCU_APB2_FZ1300
DBGMCU_CR1297
DBGMCU_IDCODE1284
DFSDM_CHyAWSCDR423
DFSDM_CHyCFG1420
DFSDM_CHyCFG2423
DFSDM_CHyDATINR425
DFSDM_CHyWDATR424
DFSDM_FLTxAWCFR438
DFSDM_FLTxAWHTR436
DFSDM_FLTxAWLTR436
DFSDM_FLTxAWSR437
DFSDM_FLTxCNVTIMR439
DFSDM_FLTxC1426
DFSDM_FLTxC2429
DFSDM_FLTxEXMAX438
DFSDM_FLTxEXMIN439
DFSDM_FLTxFR433
DFSDM_FLTxiCR432
DFSDM_FLTxiSR430
DFSDM_FLTxJCHGR433
DFSDM_FLTxJDATAR434
DFSDM_FLTxRDATAR435
DMA_HIFCR239
DMA_HISR238
DMA_LIFCR239
DMA_LISR237
DMA_SxCR240
DMA_SxFR245
DMA_SxM0AR244
DMA_SxM1AR245
DMA_SxNDTR243
DMA_SxPAR244

E

EXTI_EM260
EXTI_FTSR262
EXTI_IMR260
EXTI_PR264
EXTI_RTSR261
EXTI_SWIER263

F

FLASH_ACR82
FLASH_CR85
FLASH_KEYR83
FLASH_OPTCR86
FLASH_OPTKEYR83
FLASH_SR84
FMPI2C_CR1827
FMPI2C_CR2830
FMPI2C_ICR838
FMPI2C_ISR835
FMPI2C_OAR1832
FMPI2C_OAR2832
FMPI2C_PECR839
FMPI2C_RXDR839
FMPI2C_TIMEOUTR834
FMPI2C_TIMINGR833
FMPI2C_TXDR840
FSMC_BCRx299
FSMC_BTRx301
FSMC_BWTRx304

G

GPIOx_AFRH202
GPIOx_AFRL201
GPIOx_BSRR199
GPIOx_IDR199
GPIOx_LCKR200
GPIOx_MODER197
GPIOx_ODR199
GPIOx_OSPEEDR198
GPIOx_OTYPER197
GPIOx_PUPDR198

I

I2C_CCR870
I2C_CR1862
I2C_CR2864
I2C_DR866
I2C_OAR1865
I2C_OAR2866
I2C_SR1866
I2C_SR2869
I2C_TRISE871
IWDG_KR677
IWDG_PR678
IWDG_RLR679
IWDG_SR679

L

LPTIM_ARR672
LPTIM_CFGR668
LPTIM_CMP671
LPTIM_CNT672
LPTIM_CR670
LPTIM_ICR666
LPTIM_IER667
LPTIM_ISR665
LPTIM1_OR673

O

OTG_CID1175
OTG_DAIN1198
OTG_DAINMSK1199
OTG_DCFG1191
OTG_DCTL1192
OTG_DIEPCTL01201
OTG_DIEPCTLx1202
OTG_DIEPEMPMSK1200
OTG_DIEPINTx1205
OTG_DIEPMSK1196
OTG_DIEPTSIZ01206
OTG_DIEPTSIZx1208
OTG_DIEPTXF01171
OTG_DIEPTXFx1179
OTG_DOEPCTL01209
OTG_DOEPCTLx1213
OTG_DOEPINTx1210
OTG_DOEPMSK1197
OTG_DOEPTSIZ01212
OTG_DOEPTSIZx1215
OTG_DSTS1195
OTG_DTXFSTSx1207
OTG_DVBUSDIS1199
OTG_DVBUSPULSE1200
OTG_GAHBCFG1155
OTG_GCCFG1173
OTG_GINTMSK1164
OTG_GINTSTS1160
OTG_GLPMCFG1175
OTG_GOTGCTL1151
OTG_GOTGINT1154
OTG_GRSTCTL1158
OTG_GRXFSIZ1171
OTG_GRXSTSP1169-1170
OTG_GRXSTSR1167-1168
OTG_GUSBCFG1156
OTG_HAINT1183
OTG_HAINTMSK1184
OTG_HCCHARx1187
OTG_HCFG1180
OTG_HCINTMSKx1189
OTG_HCINTx1188
OTG_HCTSIZx1190
OTG_HFIR1181
OTG_HFNUM1182
OTG_HNPTXFSIZ1171
OTG_HNPTXSTS1172
OTG_HPRT1185
OTG_HPTXFSIZ1179
OTG_HPTXSTS1182
OTG_PCGCCTL1216

P

PWR_CR112
PWR_CSR114

Q

QUADSPI_ABR331
QUADSPI_AR331
QUADSPI_CCR329
QUADSPI_CR323
QUADSPI_DCR326
QUADSPI_DLR328
QUADSPI_DR332
QUADSPI_FCR328
QUADSPI_LPTR334
QUADSPI_PIR333
QUADSPI_PSMAR333
QUADSPI_PSMKR332
QUADSPI_SR327

R

RCC_AHB1ENR149
RCC_AHB1LPENR160
RCC_AHB1RSTR138
RCC_AHB2ENR151-152
RCC_AHB2LPENR162-163
RCC_AHB2RSTR140-141
RCC_AHB3ENR153
RCC_AHB3LPENR163
RCC_AHB3RSTR142
RCC_APB1ENR153
RCC_APB1LPENR165
RCC_APB2ENR157
RCC_APB2LPENR168
RCC_APB2RSTR146
RCC_BDCR171
RCC_CFGR133
RCC_CIR136
RCC_CR129
RCC_CSR172
RCC_DCKCFGR178
RCC_DCKCFGR2181
RCC_PLLCFGR131
RCC_PLLI2SCFGR176
RCC_SSCGR175
RNG_CR457
RNG_DR459
RNG_SR458
RTC_ALRMAR766
RTC_ALRMASSR774
RTC_ALRMBR767
RTC_ALRMBSSR775
RTC_BKPxR776
RTC_CALIBR765
RTC_CALR771
RTC_CR759
RTC_DR758
RTC_ISR761
RTC_PRER763
RTC_SHIFTTR769
RTC_SSR768
RTC_TAFCR772
RTC_TR757
RTC_TSDR770
RTC_TSSSR771
RTC_TSTR770
RTC_WPR768
RTC_WUTR764

S

SDIO_ARG1061
SDIO_CLKCR1059
SDIO_DCOUNT1067

SDIO_DCTRL ..... 1064
SDIO_DLEN ..... 1064
SDIO_DTIMER ..... 1063
SDIO_FIFO ..... 1073
SDIO_FIFOCNT ..... 1072
SDIO_ICR ..... 1068
SDIO_MASK ..... 1070
SDIO_POWER ..... 1059
SDIO_RESPCMD ..... 1062
SDIO_RESPx ..... 1062
SDIO_STA ..... 1067
SPI_CR1 ..... 967
SPI_CR2 ..... 969
SPI_CRCPR ..... 972
SPI_DR ..... 972
SPI_I2SCFGR ..... 974
SPI_I2SPR ..... 975
SPI_RXCRCR ..... 973
SPI_SR ..... 970
SPI_TXCRCR ..... 973
SYSCFG_CFGR ..... 211
SYSCFG_CFGR2 ..... 209
SYSCFG_CMPCR ..... 210
SYSCFG_EXTICR1 ..... 207
SYSCFG_EXTICR2 ..... 207
SYSCFG_EXTICR3 ..... 208
SYSCFG_EXTICR4 ..... 209
SYSCFG_MCHDLYCR ..... 211
SYSCFG_MEMRMP ..... 205

T

TIM2_OR ..... 589
TIM5_OR ..... 590
TIMx_ARR ..... 585, 625, 636, 651
TIMx_BDTR ..... 526
TIMx_CCER ..... 520, 583, 624, 635
TIMx_CCMR1 ..... 515, 579, 620, 632
TIMx_CCMR2 ..... 518, 582
TIMx_CCR1 ..... 525, 586, 626, 637
TIMx_CCR2 ..... 525, 586, 626
TIMx_CCR3 ..... 526, 587
TIMx_CCR4 ..... 526, 587
TIMx_CNT ..... 524, 585, 625, 636, 650
TIMx_CR1 ..... 506, 570, 614, 629, 648
TIMx_CR2 ..... 507, 572, 649
TIMx_DCR ..... 528, 588
TIMx_DIER ..... 511, 575, 617, 630, 649
TIMx_DMAR ..... 529, 588
TIMx_EGR ..... 514, 578, 620, 631, 650
TIMx_PSC ..... 524, 585, 625, 636, 651
TIMx_RCR ..... 524

TIMx_SMCR ..... 509, 573, 616
TIMx_SR ..... 513, 576, 618, 630, 650

U

USART_BRR ..... 918
USART_CR1 ..... 919
USART_CR2 ..... 921
USART_CR3 ..... 922
USART_DR ..... 918
USART_GTPR ..... 924
USART_SR ..... 915

W

WWDG_CFR ..... 686
WWDG_CR ..... 685
WWDG_SR ..... 686

IMPORTANT NOTICE – READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers' products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2024 STMicroelectronics – All rights reserved