20. Basic timers (TIM6/7)

20.1 Introduction

The basic timers TIM6, TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler.

20.2 TIM6/7 main features

Basic timer (TIM6/TIM7) features include:

• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536
• Interrupt/DMA generation on the update event: counter overflow

Figure 204. Basic timer block diagram

Block diagram of a basic timer (TIM6/7) showing internal components: Trigger Controller, Auto-reload register, PSC prescaler, and CNT counter. It includes input signals like TIMxCLK, CK_PSC, and CK_INT, and output signals like TRGO, UI, and Interrupt & DMA output.

The diagram illustrates the internal architecture of a basic timer. The main components are:

Trigger Controller: Receives Internal clock (CK_INT) from TIMxCLK from RCC . It has a Control block that receives Reset, enable, Count signals. It outputs TRGO .
Auto-reload register: Receives U (Event) signals. It outputs Stop, clear or up signals to the counter. It also has a U (Event) output.
PSC prescaler: Receives CK_PSC and outputs CK_CNT to the counter.
CNT counter: Receives CK_CNT and Stop, clear or up signals. It outputs UI (Interrupt & DMA output).

Notes:

Reg : Preload registers transferred to active registers on U event according to control bit
Event : Indicated by a dashed arrow
Interrupt & DMA output : Indicated by a jagged arrow

MSv34754V1

Block diagram of a basic timer (TIM6/7) showing internal components: Trigger Controller, Auto-reload register, PSC prescaler, and CNT counter. It includes input signals like TIMxCLK, CK_PSC, and CK_INT, and output signals like TRGO, UI, and Interrupt & DMA output.

20.3 TIM6/7 functional description

20.3.1 Time-base unit

The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter Register (TIMx_CNT)
• Prescaler Register (TIMx_PSC)
• Auto-Reload Register (TIMx_ARR)

The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set.

Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 205 and Figure 206 give some examples of the counter behavior when the prescaler ratio is changed on the fly.

Figure 205. Counter timing diagram with prescaler division change from 1 to 2

Timing diagram for Figure 205 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. It illustrates a change in prescaler division from 1 to 2.

This timing diagram illustrates the behavior of a timer when the prescaler division is changed from 1 to 2. The signals shown are:

CK_PSC : Prescaler clock signal, a continuous square wave.
CEN : Counter enable signal, which goes high to enable counting.
Timerclock = CK_CNT : The clock signal for the counter, derived from CK_PSC. Its frequency changes when the prescaler division changes.
Counter register : Shows hexadecimal values F7, F8, F9, FA, FB, FC, followed by a rollover to 00, 01, 02, 03.
Update event (UEV) : A pulse generated when the counter reaches its maximum value (FC) and rolls over.
Prescaler control register : Initially set to 0 (division 1). It is updated to 1 (division 2) via a write to TIMx_PSC. This change takes effect on the next update event.
Prescaler buffer : A buffer that latches the new prescaler value (1) from the control register.
Prescaler counter : A counter that divides the CK_PSC frequency. It counts from 0 to 1 (division 1) initially, then after the update, it counts from 0 to 1, 0 to 1, 0 to 1 (division 2).

Vertical dashed lines indicate key timing points: the initial update event, the write to the prescaler control register, and the subsequent update event where the new division takes effect. The diagram is labeled MS31076V2.

Timing diagram for Figure 205 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. It illustrates a change in prescaler division from 1 to 2.

Figure 206. Counter timing diagram with prescaler division change from 1 to 4

Timing diagram for Figure 206 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. It illustrates a change in prescaler division from 1 to 4.

This timing diagram illustrates the behavior of a timer when the prescaler division is changed from 1 to 4. The signals shown are:

CK_PSC : Prescaler clock signal, a continuous square wave.
CEN : Counter enable signal, which goes high to enable counting.
Timerclock = CK_CNT : The clock signal for the counter. Its frequency decreases when the prescaler division changes from 1 to 4.
Counter register : Shows hexadecimal values F7, F8, F9, FA, FB, FC, followed by a rollover to 00, 01.
Update event (UEV) : A pulse generated when the counter reaches its maximum value (FC) and rolls over.
Prescaler control register : Initially set to 0 (division 1). It is updated to 3 (division 4) via a write to TIMx_PSC. This change takes effect on the next update event.
Prescaler buffer : A buffer that latches the new prescaler value (3) from the control register.
Prescaler counter : A counter that divides the CK_PSC frequency. It counts from 0 to 1 (division 1) initially, then after the update, it counts from 0 to 3 (division 4).

Timing diagram for Figure 206 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. It illustrates a change in prescaler division from 1 to 4.

20.3.2 Counting mode

The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent).

When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register)
• The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36.

Figure 207. Counter timing diagram, internal clock divided by 1

The timing diagram illustrates the counter's behavior over time. The top signal, CK_PSC, is a periodic square wave. Below it, CNT_EN is a horizontal line that goes high at a certain point. When CNT_EN is high, the Timerclock = CK_CNT signal becomes a periodic square wave. The Counter register is shown as a sequence of values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. The Counter overflow signal is a pulse that goes high when the counter reaches 36 and returns low when it rolls over to 00. The Update event (UEV) signal is a pulse that goes high at the same time as the counter overflows. The Update interrupt flag (UIF) signal is a pulse that goes high at the same time as the counter overflows and returns low shortly after. Vertical dashed lines indicate the timing relationships between the signals.

Timing diagram for a counter in counting mode. The diagram shows the relationship between the prescaler clock (CK_PSC), counter enable (CNT_EN), timer clock (CK_CNT), counter register values, counter overflow, update event (UEV), and update interrupt flag (UIF).

MS31078V2

Figure 208. Counter timing diagram, internal clock divided by 2

This diagram shows the timer signals when the internal clock is divided by 2. The timer clock (CK_CNT) pulses every two cycles of the prescaler clock (CK_PSC) once CNT_EN is high. The counter register increments on each CK_CNT pulse. When the counter reaches its limit (after 0036), it overflows to 0000, triggering a Counter overflow pulse, an Update event (UEV) pulse, and setting the Update interrupt flag (UIF) high.

Signal	State 1	State 2	State 3	State 4 (Overflow)	State 5
CK_PSC	Clocking	Clocking	Clocking	Clocking	Clocking
CNT_EN	High	High	High	High	High
Timerclock = CK_CNT	Pulse	Pulse	Pulse	Pulse	Pulse
Counter register	0034	0035	0036	0000	0001
Counter overflow	Low	Low	Low	High (Pulse)	Low
Update event (UEV)	Low	Low	Low	High (Pulse)	Low
Update interrupt flag (UIF)	Low	Low	Low	High (Latched)	High

MS31079V2

Counter timing diagram, internal clock divided by 2

Figure 209. Counter timing diagram, internal clock divided by 4

This diagram shows the timer signals when the internal clock is divided by 4. The timer clock (CK_CNT) pulses every four cycles of the prescaler clock (CK_PSC) once CNT_EN is high. The counter register increments on each CK_CNT pulse. When the counter overflows from 0036 to 0000, it triggers the overflow, UEV, and UIF signals.

Signal	State 1	State 2	State 3 (Overflow)	State 4
CK_PSC	Clocking	Clocking	Clocking	Clocking
CNT_EN	High	High	High	High
Timerclock = CK_CNT	Low	Pulse	Pulse	Low
Counter register	0035	0036	0000	0001
Counter overflow	Low	Low	High (Pulse)	Low
Update event (UEV)	Low	Low	High (Pulse)	Low
Update interrupt flag (UIF)	Low	Low	High (Latched)	High

MS31080V2

Counter timing diagram, internal clock divided by 4

Figure 210. Counter timing diagram, internal clock divided by N

MS31081V2

Figure 210: Counter timing diagram, internal clock divided by N. The diagram shows several signal traces over time: CK_PSC (prescaler clock), Timerclock = CK_CNT (counter clock), Counter register, Counter overflow, Update event (UEV), and Update interrupt flag (UIF). The Counter register increments from 1F to 20, then resets to 00. The reset to 00 coincides with a pulse on Counter overflow and Update event (UEV), and a rising edge on Update interrupt flag (UIF).

Figure 211. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded)

MS31082V2

Figure 211: Counter timing diagram, update event when ARPE = 0. Traces include CK_PSC, CEN (counter enable), Timerclock = CK_CNT, Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), and Auto-reload preload register. The Counter register counts from 31 up to 36, then resets to 00 and continues counting. The reset occurs because the Auto-reload preload register was updated from FF to 36. A note 'Write a new value in TIMx_ARR' points to the moment the preload register changes. The overflow and update events trigger when the counter reaches the new ARR value of 36.

Figure 212. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)

Figure 212: Counter timing diagram showing the relationship between CK_PSC, CEN, Timerclock (CK_CNT), Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), Auto-reload preload register, and Auto-reload shadow register. The diagram illustrates the sequence of events leading to an update event when ARPE=1 and the counter reaches the preloaded auto-reload value (36).

The timing diagram shows the following signals and their states over time:

CK_PSC : A periodic square wave representing the prescaler clock.
CEN : Counter Enable signal, which is initially low and then goes high to enable the counter.
Timerclock = CK_CNT : The clock signal for the counter, which is derived from CK_PSC.
Counter register : Shows the counter values incrementing from F0 to F7. When the counter reaches F5, it triggers an overflow and an update event.
Counter overflow : A pulse that occurs when the counter reaches the maximum value (F5) and rolls over to 00.
Update event (UEV) : A pulse that occurs when the counter reaches the auto-reload value (36).
Update interrupt flag (UIF) : A flag that is set when an update event occurs.
Auto-reload preload register : Shows the value F5 being written to the register, which is then preloaded with the value 36.
Auto-reload shadow register : Shows the value F5 being written to the register, which is then preloaded with the value 36.

An annotation indicates that a new value should be written in the TIMx_ARR register. The diagram is labeled MS31083V2.

Figure 212: Counter timing diagram showing the relationship between CK_PSC, CEN, Timerclock (CK_CNT), Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), Auto-reload preload register, and Auto-reload shadow register. The diagram illustrates the sequence of events leading to an update event when ARPE=1 and the counter reaches the preloaded auto-reload value (36).

20.3.3 Clock source

The counter clock is provided by the Internal clock (CK_INT) source.

The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 213 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Figure 213. Control circuit in normal mode, internal clock divided by 1

Timing diagram for Figure 213 showing control circuit in normal mode. The diagram illustrates the relationship between the internal clock, counter enable (CEN=CNT_EN), update generation (UG), counter initialization (CNT_INIT), counter clock (CK_CNT = CK_PSC), and the counter register values over time.

The timing diagram shows the following signals and their relationship:

Internal clock: A continuous square wave.
CEN=CNT_EN: Counter Enable. It is initially low, then goes high to enable counting, and later goes low to stop counting.
UG: Update Generation. It is initially low. When CEN goes high, UG goes high briefly to generate an update event, then returns to low.
CNT_INIT: Counter Initialization. It is initially low. When CEN goes high, CNT_INIT goes high briefly to initialize the counter, then returns to low.
Counter clock = CK_CNT = CK_PSC: The clock for the counter. It is initially low. When CEN goes high, it becomes a square wave derived from the internal clock.
Counter register: Shows the count values. It starts at 31, increments to 32, 33, 34, 35, 36, then overflows to 00, 01, 02, 03, 04, 05, 06, 07. The counter stops counting when CEN goes low.

MS31085V2

Timing diagram for Figure 213 showing control circuit in normal mode. The diagram illustrates the relationship between the internal clock, counter enable (CEN=CNT_EN), update generation (UG), counter initialization (CNT_INIT), counter clock (CK_CNT = CK_PSC), and the counter register values over time.

20.3.4 Debug mode

When the microcontroller enters the debug mode (Cortex ^®-M4 with FPU core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to Section 34.16.2: Debug support for timers, watchdog, bxCAN and I ²C .

20.4 TIM6/7 registers

Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions.

The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

20.4.1 TIM6/7 control register 1 (TIMx_CR1)

Address offset: 0x00

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ARPE	Res.	Res.	Res.	OPM	URS	UDIS	CEN
								rw				rw	rw	rw	rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered.

1: TIMx_ARR register is buffered.

Bits 6:4 Reserved, must be kept at reset value.

Bit 3 OPM : One-pulse mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the CEN bit).

Bit 2 URS : Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generates an update interrupt or DMA request if enabled.

These events can be:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS : Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN : Counter enable

0: Counter disabled

1: Counter enabled

Note: Gated mode can work only if the CEN bit has been previously set by software.

However trigger mode can set the CEN bit automatically by hardware.

CEN is cleared automatically in one-pulse mode, when an update event occurs.

20.4.2 TIM6/7 control register 2 (TIMx_CR2)

Address offset: 0x04

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MMS[2:0]			Res.	Res.	Res.	Res.
									rW	rW	rW

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 MMS : Master mode selection

These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:

000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.

001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.

When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register).

010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

Bits 3:0 Reserved, must be kept at reset value.

20.4.3 TIM6/7 DMA/Interrupt enable register (TIMx_DIER)

Address offset: 0x0C

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	UDE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIE
							rW								rW

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 UDE : Update DMA request enable

0: Update DMA request disabled.

1: Update DMA request enabled.

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 UIE : Update interrupt enable

0: Update interrupt disabled.

1: Update interrupt enabled.

20.4.4 TIM6/7 status register (TIMx_SR)

Address offset: 0x10

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIF
															rc_w0

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UIF : Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register.

20.4.5 TIM6/7 event generation register (TIMx_EGR)

Address offset: 0x14

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UG
															w

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UG : Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action.

1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).

20.4.6 TIM6/7 counter (TIMx_CNT)

Address offset: 0x24

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 CNT[15:0] : Counter value

20.4.7 TIM6/7 prescaler (TIMx_PSC)

Address offset: 0x28

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency (CK_CNT) is equal to $f_{CK\_PSC} / (PSC[15:0] + 1)$ .

PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).

20.4.8 TIM6/7 auto-reload register (TIMx_ARR)

Address offset: 0x2C

Reset value: 0xFFFF

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 ARR[15:0] : Auto-reload value

ARR is the value to be loaded into the actual auto-reload register.

Refer to Section 20.3.1: Time-base unit on page 641 for more details about ARR update and behavior.

The counter is blocked while the auto-reload value is null.

20.4.9 TIM6/7 register map

TIMx registers are mapped as 16-bit addressable registers as described in the table below:

Table 114. TIM6 register map and reset values

Offset	Register	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	TIMx_CR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ARPE	Res.	Res.	Res.	OPM	URS	UDIS	CEN
0x00	Reset value									0				0	0	0	0
0x04	TIMx_CR2	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MMS[2:0]			Res.	Res.	Res.	Res.
0x04	Reset value										0	0	0
0x08	Res.
0x0C	TIMx_DIER	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UDE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIE
0x0C	Reset value								0								0
0x10	TIMx_SR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIF
0x10	Reset value																0
0x14	TIMx_EGR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UG
0x14	Reset value																0
0x18	Res.
0x1C	Res.
0x20	Res.
0x24	TIMx_CNT	CNT[15:0]
0x24	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x28	TIMx_PSC	PSC[15:0]
0x28	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x2C	TIMx_ARR	ARR[15:0]
0x2C	Reset value	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

Refer to Section 2.2 on page 57 for the register boundary addresses.