14. Digital-to-analog converter (DAC)

14.1 DAC introduction

The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each with its own converter. In dual DAC channel mode, conversions could be done independently or simultaneously when both channels are grouped together for synchronous update operations. An input reference pin, $V_{REF+}$ (shared with ADC) is available for better resolution.

14.2 DAC main features

• Two DAC converters: one output channel each
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channel for independent or simultaneous conversions
• DMA capability for each channel
• DMA underrun error detection
• External triggers for conversion
• Input voltage reference, $V_{REF+}$

Figure 67 shows the block diagram of a DAC channel and Table 83 gives the pin description.

Figure 67. DAC channel block diagram

The block diagram illustrates the internal architecture of a DAC channel. At the top, a 'DAC control register' is connected to 'Control logicx'. The 'Control logicx' block contains 'LFSRx' and 'trianglex' sub-blocks. A 'DHRx' register provides a 12-bit input to the 'Control logicx'. The 'Control logicx' outputs a 12-bit signal to a 'DORx' register, which in turn outputs a 12-bit signal to the 'Digital-to-analog converterx'. The 'Digital-to-analog converterx' produces the 'DAC_OUTx' signal. External inputs include 'EXT1_9', 'V_DDA', 'V_SSA', and 'V_REF+'. A 'trigger selectorx' block receives inputs from 'SWTRIGx', 'TIM2_TRGO', 'TIM4_TRGO', 'TIM5_TRGO', 'TIM6_TRGO', 'TIM7_TRGO', and 'TIM8_TRGO', and its output is connected to the 'Control logicx'. The 'DAC control register' also receives 'TSELx[2:0] bits' and 'DMAENx' signals, and it outputs 'DMA requestx', 'TENx', 'MAMPx[3:0] bits', and 'WAVENx[1:0] bits' to the 'Control logicx'. The diagram is labeled 'ai14708b' in the bottom right corner.

Figure 67. DAC channel block diagram. The diagram shows a DAC channel block containing a DAC control register, a trigger selector, a DHRx register, a control logic block (with LFSRx and trianglex), a DORx register, and a Digital-to-analog converterx. External signals include EXT1_9, V_DDA, V_SSA, V_REF+, and DAC_OUTx. Internal signals include TSELx[2:0] bits, SWTRIGx, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO, TIM6_TRGO, TIM7_TRGO, TIM8_TRGO, DMAENx, DMA requestx, TENx, MAMPx[3:0] bits, WAVENx[1:0] bits, and 12-bit data buses.

Table 83. DAC pins

Name	Signal type	Remarks
V _REF+	Input, analog reference positive	The higher/positive reference voltage for the DAC, $V \leq V_{REF+} \leq V_{DDA}$
V _DDA	Input, analog supply	Analog power supply
V _SSA	Input, analog supply ground	Ground for analog power supply
DAC_OUTx	Analog output signal	DAC channelx analog output

Note: Once the DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is automatically connected to the analog converter output (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN).

14.3 DAC functional description

14.3.1 DAC channel enable

Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time $t_{\text{WAKEUP}}$ .

Note: The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital interface is enabled even if the ENx bit is reset.

14.3.2 DAC output buffer enable

The DAC integrates two output buffers that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. Each DAC channel output buffer can be enabled and disabled using the corresponding BOFFx bit in the DAC_CR register.

14.3.3 DAC data format

Depending on the selected configuration mode, the data have to be written into the specified register as described below:

• Single DAC channelx, there are three possibilities:
- – 8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0] bits (stored into the DHRx[11:4] bits)
- – 12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4] bits (stored into the DHRx[11:0] bits)
- – 12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0] bits (stored into the DHRx[11:0] bits)

Depending on the loaded DAC_DHRyyxx register, the data written by the user is shifted and stored into the corresponding DHRx (data holding registerx, which are internal non-memory-mapped registers). The DHRx register is then loaded into the DORx register either automatically, by software trigger or by an external event trigger.

Figure 68. Data registers in single DAC channel mode

Figure 68: Data registers in single DAC channel mode. A diagram showing three rows of a 32-bit register (bits 31 to 0). The first row shows 8-bit right alignment, where the 8 least significant bits (0-7) are shaded. The second row shows 12-bit left alignment, where the 12 most significant bits (31-20) are shaded. The third row shows 12-bit right alignment, where the 12 least significant bits (11-0) are shaded. The label 'ai14710b' is in the bottom right corner.

• Dual DAC channels, there are three possibilities:
- – 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD [7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits)
- – 12-bit left alignment: data for DAC channel1 to be loaded into the DAC_DHR12LD [15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DAC_DHR12LD [31:20] bits (stored into the DHR2[11:0] bits)
- – 12-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR12RD [11:0] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DAC_DHR12LD [27:16] bits (stored into the DHR2[11:0] bits)

Depending on the loaded DAC_DHRyyxD register, the data written by the user is shifted and stored into DHR1 and DHR2 (data holding registers, which are internal non-memory-mapped registers). The DHR1 and DHR2 registers are then loaded into the DOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an external event trigger.

Figure 69. Data registers in dual DAC channel mode

Figure 69: Data registers in dual DAC channel mode. A diagram showing three rows of a 32-bit register (bits 31 to 0). The first row shows 8-bit right alignment, where the 8 least significant bits (0-7) are shaded. The second row shows 12-bit left alignment, where the 12 most significant bits (31-20) are shaded. The third row shows 12-bit right alignment, where the 12 least significant bits (11-0) are shaded. The label 'ai14709' is in the bottom right corner.

14.3.4 DAC conversion

The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12LD).

Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later.

When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time $t_{\text{SETTLING}}$ that depends on the power supply voltage and the analog output load.

Figure 70. Timing diagram for conversion with trigger disabled TEN = 0

Timing diagram for conversion with trigger disabled (TEN = 0). The diagram shows three signals: APB1_CLK (a square wave), DHR (Digital-to-Analog Register, holding value 0x1AC), and DOR (Output Register, holding value 0x1AC). The DOR signal is shown as a step function that updates its value to 0x1AC after a settling time t_SETTLING. The output voltage available on the DAC_OUT pin is shown as a curve that rises from its initial value to the new value corresponding to 0x1AC. The settling time t_SETTLING is indicated by a horizontal double-headed arrow between the DOR update and the output voltage curve reaching its final value. The diagram is labeled ai14711c.

14.3.5 DAC output voltage

Digital inputs are converted to output voltages on a linear conversion between 0 and $V_{\text{REF+}}$ . The analog output voltages on each DAC channel pin are determined by the following equation:

\text{DACoutput} = V_{\text{REF}} \times \frac{\text{DOR}}{4096}

14.3.6 DAC trigger selection

If the TENx control bit is set, conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8 possible events will trigger conversion as shown in Table 84 .

Table 84. External triggers

Source	Type	TSEL[2:0]
Timer 6 TRGO event	Internal signal from on-chip timers	000
Timer 8 TRGO event		001
Timer 7 TRGO event		010
Timer 5 TRGO event		011
Timer 2 TRGO event		100
Timer 4 TRGO event		101
EXTI line9	External pin	110
SWTRIG	Software control bit	111

Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on the selected external interrupt line 9, the last data stored into the DAC_DHRx register are transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1 cycles after the trigger occurs.

If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents.

Note: TSELx[2:0] bit cannot be changed when the ENx bit is set.

When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one APB1 clock cycle.

14.3.7 DMA request

Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests.

A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred into the DAC_DORx register.

In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one DMA request is needed, the user should set only the corresponding DMAENx bit. In this way, the application can manage both DAC channels in dual mode by using one DMA request and a unique DMA channel.

DMA underrun

The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgement for the first external trigger is received (first request), then no new request is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set, reporting the error condition. DMA data transfers are then disabled and no further DMA request is treated. The DAC channelx continues to convert old data.

The software should clear the DMAUDRx flag by writing “1”, clear the DMAEN bit of the used DMA stream and re-initialize both DMA and DAC channelx to restart the transfer correctly. The software should modify the DAC trigger conversion frequency or lighten the DMA workload to avoid a new DMA underrun. Finally, the DAC conversion could be resumed by enabling both DMA data transfer and conversion trigger.

For each DAC channelx, an interrupt is also generated if its corresponding DMAUDRIEx bit in the DAC_CR register is enabled.

14.3.8 Noise generation

In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift register) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The preloaded value in LFSR is 0xAAA. This register is updated three APB1 clock cycles after each trigger event, following a specific calculation algorithm.

Figure 71. DAC LFSR register calculation algorithm

Diagram of the DAC LFSR register calculation algorithm. It shows a 12-bit shift register with cells numbered 11 down to 0. The output of cell 0 is fed back through a NOR gate. The output of the NOR gate is also fed back through an XOR gate. The XOR gate has four inputs: the output of cell 0, the output of cell 6 (labeled X^6), the output of cell 4 (labeled X^4), and the output of cell 1 (labeled X). The output of the XOR gate is fed back into cell 11 (labeled X^12). The 12-bit output of the register is also shown at the bottom.

The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register.

If LFSR is 0x0000, a '1' is injected into it (antilock-up mechanism).

It is possible to reset LFSR wave generation by resetting the WAVE[1:0] bits.

Figure 72. DAC conversion (SW trigger enabled) with LFSR wave generation

Timing diagram showing the relationship between APB1_CLK, DHR, DOR, and SWTRIG signals. APB1_CLK is a periodic square wave. DHR is a constant value of 0x00. DOR starts at 0xAAA, then changes to 0xD55. SWTRIG is a pulse that triggers the change in DOR. The diagram shows that the change in DOR occurs after a SWTRIG pulse and is synchronized with the APB1_CLK signal.

Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register.

14.3.9 Triangle-wave generation

It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVE[1:0] to "10". The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three APB1 clock cycles after each trigger event. The value of this counter is then added to the DAC_DHRx register without overflow and the sum is stored into the DAC_DORx register. The triangle counter is incremented as long as it is less than the maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is reached, the counter is decremented down to 0, then incremented again and so on.

It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits.

Figure 73. DAC triangle wave generation

Figure 73: DAC triangle wave generation graph. The y-axis shows 'MAMPx[3:0] max amplitude + DAC_DHRx base value' at the top and 'DAC_DHRx base value' at the bottom. The x-axis represents time. The graph shows a triangle wave starting at the base value, rising linearly (labeled 'Incrementation'), reaching the maximum amplitude, falling linearly (labeled 'Decrementation'), and returning to the base value. The wave then repeats. The label 'ai14715c' is in the bottom right corner.

Figure 74. DAC conversion (SW trigger enabled) with triangle wave generation

Figure 74: Timing diagram for DAC conversion with SW trigger enabled. The top signal is APB1_CLK, a periodic square wave. Below it is the DHR register, which is set to 0x00. The DOR register shows two values: 0xAA and 0xD5, which correspond to the peaks of the triangle wave. The SWTRIG signal is a pulse that triggers the conversion. The label 'ai14714b' is in the bottom right corner.

Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register.

The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed.

14.4 Dual DAC channel conversion

To efficiently use the bus bandwidth in applications that require the two DAC channels at the same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A unique register access is then required to drive both DAC channels at the same time.

Eleven possible conversion modes are possible using the two DAC channels and these dual registers. All the conversion modes can nevertheless be obtained using separate DHRx registers if needed.

All modes are described in the paragraphs below.