8. System configuration controller (SYSCFG)

The system configuration controller is mainly used to remap the memory accessible in the code area and manage the external interrupt line connection to the GPIOs.

8.1 I/O compensation cell

By default the I/O compensation cell is not used. However when the I/O output buffer speed is configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell for slew rate control on I/O \( t_{f(IO)out}/t_{r(IO)out} \) commutation to reduce the I/O noise on power supply.

When the compensation cell is enabled, a READY flag is set to indicate that the compensation cell is ready and can be used. The I/O compensation cell can be used only when the supply voltage ranges from 2.4 to 3.6 V.

8.2 SYSCFG registers

8.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)

This register is used for specific configurations on memory remap:

• • Two bits are used to configure the type of memory accessible at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the BOOT pins.
• • After reset these bits take the value selected by the BOOT pins. When booting from main Flash memory with BOOT0 pin set to 0, this register takes the value 0x00.

In remap mode, the CPU can access the external memory via ICode bus instead of System bus which boosts up the performance.

Address offset: 0x00

Reset value: 0x0000 000X (X is the memory mode selected by the BOOT pins)

Bits 31:2 Reserved, must be kept at reset value.

Bits 1:0 MEM_MODE : Memory mapping selection

Set and cleared by software. This bit controls the memory internal mapping at address 0x0000 0000. After reset these bits take the value selected by the Boot pins.

00: Main Flash memory mapped at 0x0000 0000

01: System Flash memory mapped at 0x0000 0000

10: reserved

11: Embedded SRAM mapped at 0x0000 0000

Note: Refer to Figure 2: Memory map for details about the memory mapping at address 0x0000 0000.

8.2.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 ADC1DC2 :

0: No effect.

1: Refer to AN4073 on how to use this bit

Note: These bits can be set only if the following conditions are met:

• - ADC clock higher or equal to 30 MHz.
• - Only one ADC1DC2 bit must be selected if ADC conversions do not start at the same time and the sampling times differ.
• - These bits must not be set when the ADCDC1 bit is set in PWR_CR register.

Bits 15:0 Reserved, must be kept at reset value.

8.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)

Address offset: 0x08

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 0 to 3)

These bits are written by software to select the source input for the EXTIx external interrupt.

• 0000: PA[x] pin
• 0001: PB[x] pin
• 0010: PC[x] pin
• 0011: PD[x] pin
• 0100: PE[x] pin
• 0101: PF[x] pin
• 0110: PG[x] pin
• 0111: PH[x] pin (Reserved for EXTI3 and EXTI2 configurations)
• Other configurations: reserved

8.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 4 to 7)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PF[x] pin

0110: PG[x] pin

Other configurations: reserved

8.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)

Address offset: 0x10

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 8 to 11)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PF[x] pin

0110: PG[x] pin

Other configurations: reserved

8.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)

Address offset: 0x14

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 12 to 15)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PF[x] pin

0110: PG[x] pin

8.2.7 SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x1C

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

This bit is set by software. It can be cleared only by a system reset. It enables and locks the PVD connection to TIM1/8 Break input. It also locks (write protection) the PVDE and PVDS[2:0] bits of PWR_CR register.

0: PVD interrupt not connected to TIM1/8 Break input. PVDE and PVDS[2:0] can be read and modified

1: PVD interrupt connected to TIM1/8 Break input. PVDE and PVDS[2:0] are read-only

Bit 1 Reserved, must be kept at reset value.

This bit is set and cleared by software. It enables and locks the LOCKUP (Hardfault) output of the Cortex®-M4 with FPU core with TIM1/8 Break input.

0: Cortex®-M4 with FPU LOCKUP output not connected to TIM1/8 Break input

1: Cortex®-M4 with FPU LOCKUP output connected to TIM1/8 Break input

8.2.8 Compensation cell control register (SYSCFG_CMPCR)

Address offset: 0x20

Reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value.

0: I/O compensation cell not ready

1: O compensation cell ready

Bits 7:2 Reserved, must be kept at reset value.

0: I/O compensation cell power-down mode

1: I/O compensation cell enabled

8.2.9 SYSCFG configuration register (SYSCFG_CFGR)

Address offset: 0x2C

Reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 I2CFMP1_SDA

Set and cleared by software. When this bit is set, it forces FM+ drive capability on I2CFMP1_SDA pin selected through GPIO port mode register and GPIO alternate function selection bits.

Bit 0 I2CFMP1_SCL

Set and cleared by software. When this bit is set, it forces FM+ drive capability on I2CFMP1_SCL pin selected through GPIO port mode register and GPIO alternate function selection bits.

8.2.10 DFSDM Multi-channel delay control register (SYSCFG_MCHDLYCR)

Address offset: 0x30

Reset value: 0x0000 0000

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 DFSDM2_CKOSEL : Source selection for DFSDM2_CKOUT (M2 multiplexer on Figure 81: Multi-channel delay block for pulse skipping )

0: The source for DFSDM2_CKOUT is the CkOut generated by the DFSDM2

1: The source for DFSDM2_CKOUT is the output of M27

Bit 17 DFSDM2_CFG : CkIn source selection for DFSDM2 (M9, M10, M11, M12, M13, M14, M15, M16 and M2 multiplexers on Figure 81: Multi-channel delay block for pulse skipping )

0: The source for CkIn[7:0] signals are the pins DFSDM2_CKINy (M[16:9] = 0)

1: The source for CkIn[7:0] signals are provided by the outputs of DM[6:3] (M16:9] = 1)

1. Bit 16 DFSDM2_CK37SEL : Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1 (DM3 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping )
   0: The gated clock is distributed to Ckin3 (DM3 = 0)
   1: The gated clock is distributed to Ckin7 (DM3 = 1)
2. Bit 15 DFSDM2_CK26SEL : Distribution of the DFSDM2 bitstream clock gated by TIM3 OC2 (DM4 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping )
   0: The gated clock is distributed to Ckin2 (DM4 = 0)
   1: The gated clock is distributed to Ckin6 (DM4 = 1)
3. Bit 14 DFSDM2_CK15SEL : Distribution of the DFSDM2 bitstream clock gated by TIM3 OC3 (DM5 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping )
   0: The gated clock is distributed to Ckin1 (DM5 = 0)
   1: The gated clock is distributed to Ckin5 (DM5 = 1)
4. Bit 13 DFSDM2_CK04SEL : Distribution of the DFSDM2 bitstream clock gated by TIM3 OC4 (DM6 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping )
   0: The gated clock is distributed to Ckin0 (DM6 = 0)
   1: The gated clock is distributed to Ckin4 (DM6 = 1)
5. Bit 12 DFSDM2_D6SEL : Source selection for DatIn6 of DFSDM2 (M20 multiplexer on Figure 81: Multi-channel delay block for pulse skipping )
   0: The source for DatIn6 is from the DFSDM2_DATIN6 pin (M20 = 0)
   1: DatIn6 is sharing the same data than DatIn7 (M20 = 1)
6. Bit 11 DFSDM2_D4SEL : Source selection for DatIn4 of DFSDM2 (M19 multiplexer on Figure 81: Multi-channel delay block for pulse skipping )
   0: The source for DatIn4 is from the DFSDM2_DATIN4 pin (M19 = 0)
   1: DatIn4 is sharing the same data than DatIn5 (M19 = 1)
7. Bit 10 DFSDM2_D2SEL : Source selection for DatIn2 of DFSDM2 (M18 multiplexer on Figure 81: Multi-channel delay block for pulse skipping )
   0: The source for DatIn2 is from the DFSDM2_DATIN2 pin (M18 = 0)
   1: DatIn2 is sharing the same data than DatIn3 (M18 = 1)
8. Bit 9 DFSDM2_D0SEL : Source selection for DatIn0 of DFSDM2 (M17 multiplexer on Figure 81: Multi-channel delay block for pulse skipping )
   0: The source for DatIn0 is from the DFSDM2_DATIN0 pin (M17 = 0)
   1: DatIn0 is sharing the same data than DatIn1 (M17 = 1)
9. Bit 8 MCHDLYEN2 : MCHDLY clock enable for DFSDM2 (G3,G4,G5,G6 gating signal on Figure 81: Multi-channel delay block for pulse skipping )
   0: Delay clock for DFSDM2 is disabled (G[6:3] = 0)
   1: Delay clock for DFSDM2 is enabled (G[6:3] = 1)
10. Bit 7 DFSDM1_CK0SEL : Source selection for DFSDM1_CKOUT (M1 multiplexer on Figure 81: Multi-channel delay block for pulse skipping )
    0: The source for DFSDM1_CKOUT is the CkOut generated by the DFSDM1 (M1=0)
    1: The source for DFSDM1_CKOUT is the output of M27 (M1=1)
11. Bit 6 DFSDM1_CFG : Ckin source selection for DFSDM1 (M3,M4,M5,M6 multiplexer on Figure 1)
    0: The source for Ckin[3:0] signals are the pins DFSDM1_CKINy (M[6:3] = 0)
    1: The source for Ckin[3:0] signals are provided by the outputs of DM[2:1] (M[6:3] = 1)
12. Bit 5 DFSDM1_CK13SEL : Distribution of the DFSDM1 bitstream clock gated by TIM4 OC1 (DM1 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping )
    0: The gated clock is distributed to Ckin1 (DM1 = 0)
    1: The gated clock is distributed to Ckin3 (DM1 = 1)

1. Bit 4 DFSDM1_CK02SEL : Distribution of the DFSDM1 bitstream clock gated by TIM4 OC2 (DM2 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping )
   0: The gated clock is distributed to Ckin0 (DM2 = 0)
   1: The gated clock is distributed to Ckin2 (DM2 = 1)
2. Bit 3 DFSDM1_D2SEL : Source selection for DatIn2 of DFSDM1 (M8 multiplexer on Figure 81: Multi-channel delay block for pulse skipping )
   0: The source for DatIn2 is from the DFSDM1_DATIN2 pin (M8 = 0)
   1: DatIn2 is sharing the same data than DatIn3 (M8 = 1)
3. Bit 2 DFSDM1_D0SEL : Source selection for DatIn0 of DFSDM1 (M7 multiplexer on Figure 81: Multi-channel delay block for pulse skipping )
   0: The source for DatIn0 is from the DFSDM1_DATIN0 pin (M7 = 0)
   1: DatIn0 is sharing the same data than DatIn1 (M7 = 1)
4. Bit 1 MCHDLYEN1 : MCHDLY clock enable for DFSDM1 (G1,G2 gating signal on Figure 81: Multi-channel delay block for pulse skipping )
   0: Delay clock for DFSDM1 is disabled (G[2:1] = 0)
   1: Delay clock for DFSDM1 is enabled (G[2:1] = 1)
5. Bit 0 BSCKSEL : Bitstream clock source selection (M27, M28, M29 multiplexers on Figure 81: Multi-channel delay block for pulse skipping )
   0: The clock source is stopped for the bitstream clock (M[29:27] = 0)
   1: The DFSDM2 is selected as clock source for the bitstream clock (M[29:27] = 1)

8.2.11 SYSCFG register map

The following table gives the SYSCFG register map and the reset values.

Table 29. SYSCFG register map and reset values

Refer to Section 2.2 on page 57 for the register boundary addresses.