RM0430-STM32F413-423

This reference manual targets application developers. It provides complete information on how to use the memory and the peripherals of the STM32F413/423 microcontrollers.

The STM32F413/423 is a line of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics refer to the datasheet.

For information on the Arm ® Cortex ® -M4 with FPU core, refer to the Cortex ® -M4 Technical Reference Manual .

The STM32F413/423 microcontrollers include ST state-of-the-art patented technology.

Available from STMicroelectronics web site www.st.com :

Contents

1Documentation conventions . . . . .52
1.1General information . . . . .52
1.2List of abbreviations for registers . . . . .52
1.3Glossary . . . . .53
1.4Availability of peripherals . . . . .53
2System and memory overview . . . . .54
2.1System architecture . . . . .54
2.1.1I-bus . . . . .55
2.1.2D-bus . . . . .55
2.1.3S-bus . . . . .55
2.1.4DMA memory bus . . . . .55
2.1.5DMA peripheral bus . . . . .56
2.1.6BusMatrix . . . . .56
2.1.7AHB/APB bridges (APB) . . . . .56
2.2Memory organization . . . . .57
2.2.1Introduction . . . . .57
2.2.2Memory map and register boundary addresses . . . . .58
2.3Embedded SRAM . . . . .62
2.4Flash memory overview . . . . .62
2.5Bit banding . . . . .62
2.6Boot configuration . . . . .63
3Embedded Flash memory interface . . . . .66
3.1Introduction . . . . .66
3.2Main features . . . . .66
3.3Embedded Flash memory . . . . .67
3.4Read interface . . . . .68
3.4.1Relation between CPU clock frequency and Flash memory read time . . . . .68
3.4.2Adaptive real-time memory accelerator (ART Accelerator™) . . . . .69
3.5Erase and program operations . . . . .71
3.5.1Unlocking the Flash control register . . . . .71
3.5.2Program/erase parallelism . . . . .72
3.5.3Erase .....72
3.5.4Programming .....73
3.5.5Interrupts .....74
3.6Option bytes .....74
3.6.1Description of user option bytes .....74
3.6.2Programming user option bytes .....76
3.6.3Read protection (RDP) .....76
3.6.4Write protections .....78
3.6.5Proprietary code readout protection (PCROP) .....79
3.7One-time programmable bytes .....81
3.8Flash interface registers .....82
3.8.1Flash access control register (FLASH_ACR) .....82
3.8.2Flash key register (FLASH_KEYR) .....83
3.8.3Flash option key register (FLASH_OPTKEYR) .....83
3.8.4Flash status register (FLASH_SR) .....84
3.8.5Flash control register (FLASH_CR) .....85
3.8.6Flash option control register (FLASH_OPTCR) .....86
3.8.7Flash interface register map .....89
4CRC calculation unit .....90
4.1CRC introduction .....90
4.2CRC main features .....90
4.3CRC functional description .....90
4.4CRC registers .....91
4.4.1Data register (CRC_DR) .....91
4.4.2Independent data register (CRC_IDR) .....92
4.4.3Control register (CRC_CR) .....92
4.4.4CRC register map .....93
5Power controller (PWR) .....94
5.1Power supplies .....94
5.1.1Independent A/D converter supply and reference voltage .....95
5.1.2Battery backup domain .....95
5.1.3Voltage regulator .....97
5.2Power supply supervisor .....98
5.2.1Power-on reset (POR)/power-down reset (PDR) .....98
5.2.2Brownout reset (BOR) .....98
5.2.3Programmable voltage detector (PVD) .....99
5.3Low-power modes .....100
5.3.1Slowing down system clocks .....102
5.3.2Peripheral clock gating .....102
5.3.3Sleep mode .....103
5.3.4Batch acquisition mode .....104
5.3.5Stop mode .....105
5.3.6Standby mode .....108
5.3.7Programming the RTC alternate functions to wake up the device from
the Stop and Standby modes .....		109
5.4Power control registers .....112
5.4.1PWR power control register (PWR_CR) .....112
5.4.2PWR power control/status register (PWR_CSR) .....114
5.5PWR register map .....116
6Reset and clock control (RCC) for STM32F413/423 .....117
6.1Reset .....117
6.1.1System reset .....117
6.1.2Power reset .....118
6.1.3Backup domain reset .....118
6.2Clocks .....119
6.2.1HSE clock .....121
6.2.2HSI clock .....122
6.2.3PLL configuration .....123
6.2.4LSE clock .....123
6.2.5LSI clock .....124
6.2.6System clock (SYSCLK) selection .....124
6.2.7Clock security system (CSS) .....124
6.2.8RTC/AWU clock .....125
6.2.9Watchdog clock .....125
6.2.10Clock-out capability .....126
6.2.11Internal/external clock measurement using TIM5/TIM11 .....126
6.3RCC registers .....129
6.3.1RCC clock control register (RCC_CR) .....129
6.3.2RCC PLL configuration register (RCC_PLLCFGR) .....131
6.3.3RCC clock configuration register (RCC_CFGR) .....133
6.3.4RCC clock interrupt register (RCC_CIR) . . . . .136
6.3.5RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .138
6.3.6RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
for STM32F413xx . . . . .		140
6.3.7RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
for STM32F423xx . . . . .		141
6.3.8RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . .142
6.3.9RCC APB1 peripheral reset register for (RCC_APB1RSTR) . . . . .142
6.3.10RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .146
6.3.11RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .149
6.3.12RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
for STM32F413xx . . . . .		151
6.3.13RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
for STM32F423xx . . . . .		152
6.3.14RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . .153
6.3.15RCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . .153
6.3.16RCC APB2 peripheral clock enable register
(RCC_APB2ENR) . . . . .		157
6.3.17RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR) . . . . .		160
6.3.18RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR) for STM32F413xx . . . . .		162
6.3.19RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR) for STM32F423xx . . . . .		163
6.3.20RCC AHB3 peripheral clock enable in low power mode register
(RCC_AHB3LPENR) . . . . .		163
6.3.21RCC APB1 peripheral clock enable in low power mode register
(RCC_APB1LPENR) . . . . .		165
6.3.22RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR) . . . . .		168
6.3.23RCC Backup domain control register (RCC_BDCR) . . . . .171
6.3.24RCC clock control & status register (RCC_CSR) . . . . .172
6.3.25RCC spread spectrum clock generation register (RCC_SSCGR) . . . . .175
6.3.26RCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . .176
6.3.27RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR) . . . . .178
6.3.28RCC clocks gated enable register (CKGATENR) . . . . .180
6.3.29RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR2) . . . . .181
6.3.30RCC register map . . . . .182
7General-purpose I/Os (GPIO) . . . . .185

8 System configuration controller (SYSCFG) . . . . . 205

8.1I/O compensation cell . . . . .205
8.2SYSCFG registers . . . . .205
8.2.1SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .205
8.2.2SYSCFG peripheral mode configuration register (SYSCFG_PMC) . . . . .206
8.2.3SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . .		207
8.2.4SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . .		207
8.2.5SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . .		208
8.2.6SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . .		209
8.2.7SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .209
8.2.8Compensation cell control register (SYSCFG_CMPCR) . . . . .210
8.2.9SYSCFG configuration register (SYSCFG_CFGR) . . . . .211
8.2.10DFSDM Multi-channel delay control register (SYSCFG_MCHDLYCR) . . . . .211
8.2.11SYSCFG register map . . . . .214
9Direct memory access controller (DMA) . . . . .215
9.1DMA introduction . . . . .215
9.2DMA main features . . . . .215
9.3DMA functional description . . . . .217
9.3.1DMA block diagram . . . . .217
9.3.2DMA overview . . . . .217
9.3.3DMA transactions . . . . .218
9.3.4Channel selection . . . . .218
9.3.5Arbiter . . . . .220
9.3.6DMA streams . . . . .220
9.3.7Source, destination and transfer modes . . . . .220
9.3.8Pointer incrementation . . . . .224
9.3.9Circular mode . . . . .225
9.3.10Double-buffer mode . . . . .225
9.3.11Programmable data width, packing/unpacking, endianness . . . . .226
9.3.12Single and burst transfers . . . . .227
9.3.13FIFO . . . . .228
9.3.14DMA transfer completion . . . . .231
9.3.15DMA transfer suspension . . . . .232
9.3.16Flow controller . . . . .233
9.3.17Summary of the possible DMA configurations . . . . .234
9.3.18Stream configuration procedure . . . . .234
9.3.19Error management . . . . .235
9.4DMA interrupts . . . . .236
9.5DMA registers . . . . .237
9.5.1DMA low interrupt status register (DMA_LISR) . . . . .237
9.5.2DMA high interrupt status register (DMA_HISR) . . . . .238
9.5.3DMA low interrupt flag clear register (DMA_LIFCR) . . . . .239
9.5.4DMA high interrupt flag clear register (DMA_HIFCR) . . . . .239
9.5.5DMA stream x configuration register (DMA_SxCR) . . . . .240
9.5.6DMA stream x number of data register (DMA_SxNDTR) . . . . .243
9.5.7DMA stream x peripheral address register (DMA_SxPAR) . . . . .244
9.5.8DMA stream x memory 0 address register
(DMA_SxM0AR) . . . . .		244
9.5.9DMA stream x memory 1 address register
(DMA_SxM1AR) . . . . .		245
9.5.10DMA stream x FIFO control register (DMA_SxFCR) . . . . .245
9.5.11DMA register map . . . . .246
10Interrupts and events . . . . .251
10.1Nested vectored interrupt controller (NVIC) . . . . .251
10.1.1NVIC features . . . . .251
10.1.2SysTick calibration value register . . . . .251
10.1.3Interrupt and exception vectors . . . . .251
10.2External interrupt/event controller (EXTI) . . . . .251
10.2.1EXTI main features . . . . .256
10.2.2EXTI block diagram . . . . .256
10.2.3Wakeup event management . . . . .256
10.2.4Functional description . . . . .258
10.2.5External interrupt/event line mapping . . . . .259
10.3EXTI registers . . . . .260
10.3.1Interrupt mask register (EXTI_IMR) . . . . .260
10.3.2Event mask register (EXTI_EMR) . . . . .260
10.3.3Rising trigger selection register (EXTI_RTSR) . . . . .261
10.3.4Falling trigger selection register (EXTI_FTSR) . . . . .262
10.3.5Software interrupt event register (EXTI_SWIER) . . . . .263
10.3.6Pending register (EXTI_PR) . . . . .264
10.3.7EXTI register map .....265
11Flexible memory controller (FMC) .....266
11.1Introduction .....266
11.2FSMC main features .....266
11.3FMC block diagram .....267
11.4AHB interface .....267
11.4.1Supported memories and transactions .....268
11.5External device address mapping .....269
11.5.1NOR/PSRAM address mapping .....269
11.6NOR flash/PSRAM controller .....270
11.6.1External memory interface signals .....271
11.6.2Supported memories and transactions .....273
11.6.3General timing rules .....274
11.6.4NOR flash/PSRAM controller asynchronous transactions .....274
11.6.5Synchronous transactions .....292
11.6.6NOR/PSRAM controller registers .....299
11.6.7FSMC register map .....306
12Quad-SPI interface (QUADSPI) .....308
12.1Introduction .....308
12.2QUADSPI main features .....308
12.3QUADSPI functional description .....308
12.3.1QUADSPI block diagram .....308
12.3.2QUADSPI pins .....309
12.3.3QUADSPI command sequence .....309
12.3.4QUADSPI signal interface protocol modes .....312
12.3.5QUADSPI indirect mode .....314
12.3.6QUADSPI automatic status-polling mode .....316
12.3.7QUADSPI memory-mapped mode .....316
12.3.8QUADSPI flash memory configuration .....317
12.3.9QUADSPI delayed data sampling .....317
12.3.10QUADSPI configuration .....317
12.3.11QUADSPI use .....318
12.3.12Sending the instruction only once .....320
12.3.13QUADSPI error management .....320
12.3.14QUADSPI busy bit and abort functionality . . . . .320
12.3.15NCS behavior . . . . .321
12.4QUADSPI interrupts . . . . .323
12.5QUADSPI registers . . . . .323
12.5.1QUADSPI control register (QUADSPI_CR) . . . . .323
12.5.2QUADSPI device configuration register (QUADSPI_DCR) . . . . .326
12.5.3QUADSPI status register (QUADSPI_SR) . . . . .327
12.5.4QUADSPI flag clear register (QUADSPI_FCR) . . . . .328
12.5.5QUADSPI data length register (QUADSPI_DLR) . . . . .328
12.5.6QUADSPI communication configuration register (QUADSPI_CCR) . . . . .329
12.5.7QUADSPI address register (QUADSPI_AR) . . . . .331
12.5.8QUADSPI alternate-byte register (QUADSPI_ABR) . . . . .331
12.5.9QUADSPI data register (QUADSPI_DR) . . . . .332
12.5.10QUADSPI polling status mask register (QUADSPI_PSMKR) . . . . .332
12.5.11QUADSPI polling status match register (QUADSPI_PSMAR) . . . . .333
12.5.12QUADSPI polling interval register (QUADSPI_PIR) . . . . .333
12.5.13QUADSPI low-power timeout register (QUADSPI_LPTR) . . . . .334
12.5.14QUADSPI register map . . . . .334
13Analog-to-digital converter (ADC) . . . . .336
13.1ADC introduction . . . . .336
13.2ADC main features . . . . .336
13.3ADC functional description . . . . .337
13.3.1ADC on-off control . . . . .338
13.3.2ADC clock . . . . .338
13.3.3Channel selection . . . . .338
13.3.4Single conversion mode . . . . .339
13.3.5Continuous conversion mode . . . . .339
13.3.6Timing diagram . . . . .340
13.3.7Analog watchdog . . . . .340
13.3.8Scan mode . . . . .341
13.3.9Injected channel management . . . . .341
13.3.10Discontinuous mode . . . . .342
13.4Data alignment . . . . .343
13.5Channel-wise programmable sampling time . . . . .344
13.6Conversion on external trigger and trigger polarity . . . . .345
13.7Fast conversion mode . . . . .346
13.8Data management . . . . .347
13.8.1Using the DMA . . . . .347
13.8.2Managing a sequence of conversions without using the DMA . . . . .347
13.8.3Conversions without DMA and without overrun detection . . . . .348
13.9Temperature sensor . . . . .348
13.10Battery charge monitoring . . . . .349
13.11ADC interrupts . . . . .350
13.12ADC registers . . . . .351
13.12.1ADC status register (ADC_SR) . . . . .351
13.12.2ADC control register 1 (ADC_CR1) . . . . .352
13.12.3ADC control register 2 (ADC_CR2) . . . . .354
13.12.4ADC sample time register 1 (ADC_SMPR1) . . . . .356
13.12.5ADC sample time register 2 (ADC_SMPR2) . . . . .357
13.12.6ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . . . .357
13.12.7ADC watchdog higher threshold register (ADC_HTR) . . . . .357
13.12.8ADC watchdog lower threshold register (ADC_LTR) . . . . .358
13.12.9ADC regular sequence register 1 (ADC_SQR1) . . . . .358
13.12.10ADC regular sequence register 2 (ADC_SQR2) . . . . .359
13.12.11ADC regular sequence register 3 (ADC_SQR3) . . . . .360
13.12.12ADC injected sequence register (ADC_JSQR) . . . . .361
13.12.13ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . .361
13.12.14ADC regular data register (ADC_DR) . . . . .362
13.12.15ADC Common status register (ADC_CSR) . . . . .362
13.12.16ADC common control register (ADC_CCR) . . . . .363
13.12.17ADC register map . . . . .364
14Digital-to-analog converter (DAC) . . . . .366
14.1DAC introduction . . . . .366
14.2DAC main features . . . . .366
14.3DAC functional description . . . . .368
14.3.1DAC channel enable . . . . .368
14.3.2DAC output buffer enable . . . . .368
14.3.3DAC data format . . . . .368
14.3.4DAC conversion . . . . .369
14.3.5DAC output voltage . . . . .370
14.3.6DAC trigger selection . . . . .370
14.3.7DMA request . . . . .371
14.3.8Noise generation . . . . .371
14.3.9Triangle-wave generation . . . . .372
14.4Dual DAC channel conversion . . . . .373
14.4.1Independent trigger without wave generation . . . . .374
14.4.2Independent trigger with single LFSR generation . . . . .374
14.4.3Independent trigger with different LFSR generation . . . . .374
14.4.4Independent trigger with single triangle generation . . . . .375
14.4.5Independent trigger with different triangle generation . . . . .375
14.4.6Simultaneous software start . . . . .375
14.4.7Simultaneous trigger without wave generation . . . . .376
14.4.8Simultaneous trigger with single LFSR generation . . . . .376
14.4.9Simultaneous trigger with different LFSR generation . . . . .376
14.4.10Simultaneous trigger with single triangle generation . . . . .377
14.4.11Simultaneous trigger with different triangle generation . . . . .377
14.5DAC registers . . . . .378
14.5.1DAC control register (DAC_CR) . . . . .378
14.5.2DAC software trigger register (DAC_SWTRIGR) . . . . .381
14.5.3DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . .		381
14.5.4DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . .		382
14.5.5DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . .		382
14.5.6DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . .		383
14.5.7DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . .		383
14.5.8DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . .		383
14.5.9Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . .		384
14.5.10DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . .		384
14.5.11DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . .		385
14.5.12DAC channel1 data output register (DAC_DOR1) . . . . .385
14.5.13DAC channel2 data output register (DAC_DOR2) . . . . .385
14.5.14DAC status register (DAC_SR) . . . . .386
14.5.15DAC register map . . . . .386
15Digital filter for sigma delta modulators (DFSDM) . . . . .388
15.1Introduction . . . . .388
15.2DFSDM main features . . . . .389
15.3DFSDM implementation . . . . .390
15.4DFSDM functional description . . . . .391
15.4.1DFSDM block diagram . . . . .391
15.4.2DFSDM pins and internal signals . . . . .392
15.4.3DFSDM reset and clocks . . . . .393
15.4.4Serial channel transceivers . . . . .394
15.4.5Configuring the input serial interface . . . . .407
15.4.6Parallel data inputs . . . . .407
15.4.7Channel selection . . . . .409
15.4.8Digital filter configuration . . . . .410
15.4.9Integrator unit . . . . .411
15.4.10Analog watchdog . . . . .411
15.4.11Short-circuit detector . . . . .414
15.4.12Extreme detector . . . . .414
15.4.13Data unit block . . . . .415
15.4.14Signed data format . . . . .416
15.4.15Launching conversions . . . . .416
15.4.16Continuous and fast continuous modes . . . . .417
15.4.17Request precedence . . . . .417
15.4.18Power optimization in run mode . . . . .418
15.5DFSDM interrupts . . . . .418
15.6DFSDM DMA transfer . . . . .420
15.7DFSDM channel y registers (y=0..7) . . . . .420
15.7.1DFSDM channel y configuration register (DFSDM_CHyCFGR1) . . . . .420
15.7.2DFSDM channel y configuration register (DFSDM_CHyCFGR2) . . . . .423
15.7.3DFSDM channel y analog watchdog and short-circuit detector register (DFSDM_CHyAWSCDR) . . . . .423
15.7.4DFSDM channel y watchdog filter data register (DFSDM_CHyWDATR) . . . . .424
15.7.5DFSDM channel y data input register (DFSDM_CHyDATINR) . . . . .425
15.8DFSDM filter x module registers (x=0..3) . . . . .426

15.8.1 DFSDM filter x control register 1 (DFSDM_FLTxCR1) . . . . . 426

15.8.2 DFSDM filter x control register 2 (DFSDM_FLTxCR2) . . . . . 429

15.8.3 DFSDM filter x interrupt and status register (DFSDM_FLTxISR) . . . . . 430

15.8.4 DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) . . . . . 432

15.8.5 DFSDM filter x injected channel group selection register
(DFSDM_FLTxJCHGR) . . . . . 433

15.8.6 DFSDM filter x control register (DFSDM_FLTxFCR) . . . . . 433

15.8.7 DFSDM filter x data register for injected group
(DFSDM_FLTxJDATAR) . . . . . 434

15.8.8 DFSDM filter x data register for the regular channel
(DFSDM_FLTxRDATAR) . . . . . 435

15.8.9 DFSDM filter x analog watchdog high threshold register
(DFSDM_FLTxAWHTR) . . . . . 436

15.8.10 DFSDM filter x analog watchdog low threshold register
(DFSDM_FLTxAWLTR) . . . . . 436

15.8.11 DFSDM filter x analog watchdog status register
(DFSDM_FLTxAWSR) . . . . . 437

15.8.12 DFSDM filter x analog watchdog clear flag register
(DFSDM_FLTxAWCFR) . . . . . 438

15.8.13 DFSDM filter x extremes detector maximum register
(DFSDM_FLTxEXMAX) . . . . . 438

15.8.14 DFSDM filter x extremes detector minimum register
(DFSDM_FLTxEXMIN) . . . . . 439

15.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . . . . . 439

15.8.16 DFSDM register map . . . . . 440

16 True random number generator (RNG) . . . . . 450

16.1 Introduction . . . . . 450

16.2 RNG main features . . . . . 450

16.3 RNG functional description . . . . . 451

16.3.1 RNG block diagram . . . . . 451

16.3.2 RNG internal signals . . . . . 451

16.3.3 Random number generation . . . . . 452

16.3.4 RNG initialization . . . . . 454

16.3.5 RNG operation . . . . . 454

16.3.6 RNG clocking . . . . . 455

16.3.7 Error management . . . . . 455

16.3.8 RNG low-power use . . . . . 456

16.4 RNG interrupts . . . . . 456

16.5RNG processing time . . . . .456
16.6RNG entropy source validation . . . . .456
16.6.1Introduction . . . . .456
16.6.2Validation conditions . . . . .457
16.6.3Data collection . . . . .457
16.7RNG registers . . . . .457
16.7.1RNG control register (RNG_CR) . . . . .457
16.7.2RNG status register (RNG_SR) . . . . .458
16.7.3RNG data register (RNG_DR) . . . . .459
16.7.4RNG register map . . . . .460
17Advanced-control timers (TIM1&TIM8) . . . . .461
17.1TIM1&TIM8 introduction . . . . .461
17.2TIM1&TIM8 main features . . . . .461
17.3TIM1&TIM8 functional description . . . . .463
17.3.1Time-base unit . . . . .463
17.3.2Counter modes . . . . .465
17.3.3Repetition counter . . . . .474
17.3.4Clock selection . . . . .477
17.3.5Capture/compare channels . . . . .480
17.3.6Input capture mode . . . . .483
17.3.7PWM input mode . . . . .484
17.3.8Forced output mode . . . . .484
17.3.9Output compare mode . . . . .485
17.3.10PWM mode . . . . .486
17.3.11Complementary outputs and dead-time insertion . . . . .489
17.3.12Using the break function . . . . .491
17.3.13Clearing the OCxREF signal on an external event . . . . .494
17.3.146-step PWM generation . . . . .495
17.3.15One-pulse mode . . . . .496
17.3.16Encoder interface mode . . . . .497
17.3.17Timer input XOR function . . . . .500
17.3.18Interfacing with Hall sensors . . . . .500
17.3.19TIMx and external trigger synchronization . . . . .502
17.3.20Timer synchronization . . . . .505
17.3.21Debug mode . . . . .505
17.4TIM1&TIM8 registers . . . . .506
17.4.1TIM1&TIM8 control register 1 (TIMx_CR1) . . . . .506
17.4.2TIM1&TIM8 control register 2 (TIMx_CR2) . . . . .507
17.4.3TIM1&TIM8 slave mode control register (TIMx_SMCR) . . . . .509
17.4.4TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . .511
17.4.5TIM1&TIM8 status register (TIMx_SR) . . . . .513
17.4.6TIM1&TIM8 event generation register (TIMx_EGR) . . . . .514
17.4.7TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . .515
17.4.8TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . .518
17.4.9TIM1&TIM8 capture/compare enable register (TIMx_CCER) . . . . .520
17.4.10TIM1&TIM8 counter (TIMx_CNT) . . . . .524
17.4.11TIM1&TIM8 prescaler (TIMx_PSC) . . . . .524
17.4.12TIM1 auto-reload register (TIMx_ARR) . . . . .524
17.4.13TIM1&TIM8 repetition counter register (TIMx_RCR) . . . . .524
17.4.14TIM1&TIM8 capture/compare register 1 (TIMx_CCR1) . . . . .525
17.4.15TIM1 capture/compare register 2 (TIMx_CCR2) . . . . .525
17.4.16TIM1&TIM8 capture/compare register 3 (TIMx_CCR3) . . . . .526
17.4.17TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) . . . . .526
17.4.18TIM1&TIM8 break and dead-time register (TIMx_BDTR) . . . . .526
17.4.19TIM1&TIM8 DMA control register (TIMx_DCR) . . . . .528
17.4.20TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) . . . . .529
17.4.21TIM1&TIM8 register map . . . . .530
18General-purpose timers (TIM2 to TIM5) . . . . .532
18.1TIM2 to TIM5 introduction . . . . .532
18.2TIM2 to TIM5 main features . . . . .532
18.3TIM2 to TIM5 functional description . . . . .533
18.3.1Time-base unit . . . . .533
18.3.2Counter modes . . . . .535
18.3.3Clock selection . . . . .544
18.3.4Capture/compare channels . . . . .547
18.3.5Input capture mode . . . . .549
18.3.6PWM input mode . . . . .550
18.3.7Forced output mode . . . . .551
18.3.8Output compare mode . . . . .551
18.3.9PWM mode . . . . .553
18.3.10One-pulse mode . . . . .556
18.3.11Clearing the OCxREF signal on an external event . . . . .557
18.3.12Encoder interface mode . . . . .558
18.3.13Timer input XOR function . . . . .560
18.3.14Timers and external trigger synchronization . . . . .560
18.3.15Timer synchronization . . . . .564
18.3.16Debug mode . . . . .569
18.4TIM2 to TIM5 registers . . . . .570
18.4.1TIMx control register 1 (TIMx_CR1) . . . . .570
18.4.2TIMx control register 2 (TIMx_CR2) . . . . .572
18.4.3TIMx slave mode control register (TIMx_SMCR) . . . . .573
18.4.4TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . .575
18.4.5TIMx status register (TIMx_SR) . . . . .576
18.4.6TIMx event generation register (TIMx_EGR) . . . . .578
18.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . .579
18.4.8TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . .582
18.4.9TIMx capture/compare enable register (TIMx_CCER) . . . . .583
18.4.10TIMx counter (TIMx_CNT) . . . . .585
18.4.11TIMx prescaler (TIMx_PSC) . . . . .585
18.4.12TIMx auto-reload register (TIMx_ARR) . . . . .585
18.4.13TIMx capture/compare register 1 (TIMx_CCR1) . . . . .586
18.4.14TIMx capture/compare register 2 (TIMx_CCR2) . . . . .586
18.4.15TIMx capture/compare register 3 (TIMx_CCR3) . . . . .587
18.4.16TIMx capture/compare register 4 (TIMx_CCR4) . . . . .587
18.4.17TIMx DMA control register (TIMx_DCR) . . . . .588
18.4.18TIMx DMA address for full transfer (TIMx_DMAR) . . . . .588
18.4.19TIM2 option register (TIM2_OR) . . . . .589
18.4.20TIM5 option register (TIM5_OR) . . . . .590
18.4.21TIMx register map . . . . .591
19General-purpose timers (TIM9 to TIM14) . . . . .593
19.1TIM9 to TIM14 introduction . . . . .593
19.2TIM9 to TIM14 main features . . . . .593
19.2.1TIM9/TIM12 main features . . . . .593
19.2.2TIM10/TIM11 and TIM13/TIM14 main features . . . . .594
19.3TIM9 to TIM14 functional description . . . . .596
19.3.1Time-base unit . . . . .596
19.3.2Counter modes . . . . .598
19.3.3Clock selection . . . . .601
19.3.4Capture/compare channels . . . . .603
19.3.5Input capture mode . . . . .604
19.3.6PWM input mode (only for TIM9/12) . . . . .605
19.3.7Forced output mode . . . . .606
19.3.8Output compare mode . . . . .607
19.3.9PWM mode . . . . .608
19.3.10One-pulse mode . . . . .609
19.3.11TIM9/12 external trigger synchronization . . . . .611
19.3.12Timer synchronization (TIM9/12) . . . . .614
19.3.13Debug mode . . . . .614
19.4TIM9 and TIM12 registers . . . . .614
19.4.1TIM9/12 control register 1 (TIMx_CR1) . . . . .614
19.4.2TIM9/12 slave mode control register (TIMx_SMCR) . . . . .616
19.4.3TIM9/12 Interrupt enable register (TIMx_DIER) . . . . .617
19.4.4TIM9/12 status register (TIMx_SR) . . . . .618
19.4.5TIM9/12 event generation register (TIMx_EGR) . . . . .620
19.4.6TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) . . . . .620
19.4.7TIM9/12 capture/compare enable register (TIMx_CCER) . . . . .624
19.4.8TIM9/12 counter (TIMx_CNT) . . . . .625
19.4.9TIM9/12 prescaler (TIMx_PSC) . . . . .625
19.4.10TIM9/12 auto-reload register (TIMx_ARR) . . . . .625
19.4.11TIM9/12 capture/compare register 1 (TIMx_CCR1) . . . . .626
19.4.12TIM9/12 capture/compare register 2 (TIMx_CCR2) . . . . .626
19.4.13TIM9/12 register map . . . . .627
19.5TIM10/11/13/14 registers . . . . .629
19.5.1TIM10/11/13/14 control register 1 (TIMx_CR1) . . . . .629
19.5.2TIM10/11/13/14 Interrupt enable register (TIMx_DIER) . . . . .630
19.5.3TIM10/11/13/14 status register (TIMx_SR) . . . . .630
19.5.4TIM10/11/13/14 event generation register (TIMx_EGR) . . . . .631
19.5.5TIM10/11/13/14 capture/compare mode register 1
(TIMx_CCMR1) . . . . .		632
19.5.6TIM10/11/13/14 capture/compare enable register
(TIMx_CCER) . . . . .		635
19.5.7TIM10/11/13/14 counter (TIMx_CNT) . . . . .636
19.5.8TIM10/11/13/14 prescaler (TIMx_PSC) . . . . .636
19.5.9TIM10/11/13/14 auto-reload register (TIMx_ARR) . . . . .636
19.5.10TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) . . . . .637
19.5.11TIM11 option register 1 (TIM11_OR) . . . . .637
19.5.12TIM10/11/13/14 register map . . . . .638
20Basic timers (TIM6/7) . . . . .640
20.1Introduction . . . . .640
20.2TIM6/7 main features . . . . .640
20.3TIM6/7 functional description . . . . .641
20.3.1Time-base unit . . . . .641
20.3.2Counting mode . . . . .643
20.3.3Clock source . . . . .646
20.3.4Debug mode . . . . .647
20.4TIM6/7 registers . . . . .648
20.4.1TIM6/7 control register 1 (TIMx_CR1) . . . . .648
20.4.2TIM6/7 control register 2 (TIMx_CR2) . . . . .649
20.4.3TIM6/7 DMA/Interrupt enable register (TIMx_DIER) . . . . .649
20.4.4TIM6/7 status register (TIMx_SR) . . . . .650
20.4.5TIM6/7 event generation register (TIMx_EGR) . . . . .650
20.4.6TIM6/7 counter (TIMx_CNT) . . . . .650
20.4.7TIM6/7 prescaler (TIMx_PSC) . . . . .651
20.4.8TIM6/7 auto-reload register (TIMx_ARR) . . . . .651
20.4.9TIM6/7 register map . . . . .652
21Low-power timer (LPTIM) . . . . .653
21.1Introduction . . . . .653
21.2LPTIM main features . . . . .653
21.3LPTIM implementation . . . . .654
21.4LPTIM functional description . . . . .654
21.4.1LPTIM block diagram . . . . .654
21.4.2LPTIM trigger mapping . . . . .655
21.4.3LPTIM input1 multiplexing . . . . .655
21.4.4LPTIM reset and clocks . . . . .655
21.4.5Glitch filter . . . . .656
21.4.6Prescaler . . . . .657
21.4.7Trigger multiplexer . . . . .657
21.4.8Operating mode . . . . .658
21.4.9Timeout function . . . . .659
21.4.10Waveform generation . . . . .659
21.4.11Register update . . . . .661
21.4.12Counter mode . . . . .661
21.4.13Timer enable . . . . .662
21.4.14Encoder mode . . . . .662
21.4.15Debug mode . . . . .663
21.5LPTIM low-power modes . . . . .664
21.6LPTIM interrupts . . . . .664
21.7LPTIM registers . . . . .665
21.7.1LPTIM interrupt and status register (LPTIM_ISR) . . . . .665
21.7.2LPTIM interrupt clear register (LPTIM_ICR) . . . . .666
21.7.3LPTIM interrupt enable register (LPTIM_IER) . . . . .667
21.7.4LPTIM configuration register (LPTIM_CFGR) . . . . .668
21.7.5LPTIM control register (LPTIM_CR) . . . . .670
21.7.6LPTIM compare register (LPTIM_CMP) . . . . .671
21.7.7LPTIM autoreload register (LPTIM_ARR) . . . . .672
21.7.8LPTIM counter register (LPTIM_CNT) . . . . .672
21.7.9LPTIM1 option register (LPTIM1_OPTR) . . . . .673
21.7.10LPTIM register map . . . . .674
22Independent watchdog (IWDG) . . . . .675
22.1IWDG introduction . . . . .675
22.2IWDG main features . . . . .675
22.3IWDG functional description . . . . .675
22.3.1Hardware watchdog . . . . .675
22.3.2Register access protection . . . . .675
22.3.3Debug mode . . . . .676
22.4IWDG registers . . . . .677
22.4.1Key register (IWDG_KR) . . . . .677
22.4.2Prescaler register (IWDG_PR) . . . . .678
22.4.3Reload register (IWDG_RLR) . . . . .679
22.4.4Status register (IWDG_SR) . . . . .679
22.4.5IWDG register map . . . . .680
23Window watchdog (WWDG) . . . . .681
23.1WWDG introduction . . . . .681
23.2WWDG main features . . . . .681
23.3WWDG functional description . . . . .681
23.4How to program the watchdog timeout . . . . .683
23.5Debug mode . . . . .684
23.6WWDG registers . . . . .685
23.6.1Control register (WWDG_CR) . . . . .685
23.6.2Configuration register (WWDG_CFR) . . . . .686
23.6.3Status register (WWDG_SR) . . . . .686
23.6.4WWDG register map . . . . .687
24AES hardware accelerator (AES) . . . . .688
24.1Introduction . . . . .688
24.2AES main features . . . . .688
24.3AES implementation . . . . .689
24.4AES functional description . . . . .689
24.4.1AES block diagram . . . . .689
24.4.2AES internal signals . . . . .689
24.4.3AES cryptographic core . . . . .690
24.4.4AES procedure to perform a cipher operation . . . . .695
24.4.5AES decryption key preparation . . . . .699
24.4.6AES ciphertext stealing and data padding . . . . .700
24.4.7AES task suspend and resume . . . . .701
24.4.8AES basic chaining modes (ECB, CBC) . . . . .702
24.4.9AES counter (CTR) mode . . . . .707
24.4.10AES Galois/counter mode (GCM) . . . . .709
24.4.11AES Galois message authentication code (GMAC) . . . . .714
24.4.12AES counter with CBC-MAC (CCM) . . . . .716
24.4.13AES data registers and data swapping . . . . .721
24.4.14AES key registers . . . . .723
24.4.15AES initialization vector registers . . . . .723
24.4.16AES DMA interface . . . . .723
24.4.17AES error management . . . . .726
24.5AES interrupts . . . . .726
24.6AES processing latency . . . . .727
24.7AES registers . . . . .728
24.7.1AES control register (AES_CR) . . . . .728
24.7.2AES status register (AES_SR) . . . . .731
24.7.3AES data input register (AES_DINR) . . . . .732
24.7.4AES data output register (AES_DOUTR) . . . . .733
24.7.5AES key register 0 (AES_KEYR0) . . . . .733
24.7.6AES key register 1 (AES_KEYR1) . . . . .734
24.7.7AES key register 2 (AES_KEYR2) . . . . .734
24.7.8AES key register 3 (AES_KEYR3) . . . . .735
24.7.9AES initialization vector register 0 (AES_IVR0) . . . . .735
24.7.10AES initialization vector register 1 (AES_IVR1) . . . . .735
24.7.11AES initialization vector register 2 (AES_IVR2) . . . . .736
24.7.12AES initialization vector register 3 (AES_IVR3) . . . . .736
24.7.13AES key register 4 (AES_KEYR4) . . . . .737
24.7.14AES key register 5 (AES_KEYR5) . . . . .737
24.7.15AES key register 6 (AES_KEYR6) . . . . .737
24.7.16AES key register 7 (AES_KEYR7) . . . . .738
24.7.17AES suspend registers (AES_SUSPxR) . . . . .738
24.7.18AES register map . . . . .739
25Real-time clock (RTC) . . . . .741
25.1Introduction . . . . .741
25.2RTC main features . . . . .741
25.3RTC functional description . . . . .743
25.3.1Clock and prescalers . . . . .743
25.3.2Real-time clock and calendar . . . . .743
25.3.3Programmable alarms . . . . .744
25.3.4Periodic auto-wakeup . . . . .744
25.3.5RTC initialization and configuration . . . . .745
25.3.6Reading the calendar . . . . .747
25.3.7Resetting the RTC . . . . .748
25.3.8RTC synchronization . . . . .748
25.3.9RTC reference clock detection . . . . .749
25.3.10RTC coarse digital calibration . . . . .749
25.3.11RTC smooth digital calibration . . . . .750
25.3.12Timestamp function . . . . .752
25.3.13Tamper detection . . . . .753
25.3.14Calibration clock output . . . . .754
25.3.15Alarm output . . . . .755
25.4RTC and low power modes . . . . .755
25.5RTC interrupts . . . . .756
25.6RTC registers . . . . .757
25.6.1RTC time register (RTC_TR) . . . . .757
25.6.2RTC date register (RTC_DR) . . . . .758
25.6.3RTC control register (RTC_CR) . . . . .759
25.6.4RTC initialization and status register (RTC_ISR) . . . . .761
25.6.5RTC prescaler register (RTC_PRER) . . . . .763
25.6.6RTC wakeup timer register (RTC_WUTR) . . . . .764
25.6.7RTC calibration register (RTC_CALIBR) . . . . .765
25.6.8RTC alarm A register (RTC_ALRMAR) . . . . .766
25.6.9RTC alarm B register (RTC_ALRMBR) . . . . .767
25.6.10RTC write protection register (RTC_WPR) . . . . .768
25.6.11RTC sub second register (RTC_SSR) . . . . .768
25.6.12RTC shift control register (RTC_SHIFT) . . . . .769
25.6.13RTC time stamp time register (RTC_TSTR) . . . . .770
25.6.14RTC time stamp date register (RTC_TSDR) . . . . .770
25.6.15RTC timestamp sub second register (RTC_TSSSR) . . . . .771
25.6.16RTC calibration register (RTC_CALR) . . . . .771
25.6.17RTC tamper and alternate function configuration register
(RTC_TAFCR) . . . . .		772
25.6.18RTC alarm A sub second register (RTC_ALRMASSR) . . . . .774
25.6.19RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .775
25.6.20RTC backup registers (RTC_BKPxR) . . . . .776
25.6.21RTC register map . . . . .776
26Fast-mode Plus Inter-integrated circuit interface (FMPI2C) . . . . .779
26.1Introduction . . . . .779
26.2FMPI2C main features . . . . .779
26.3FMPI2C implementation . . . . .780
26.4FMPI2C functional description . . . . .780
26.4.1FMPI2C block diagram . . . . .781
26.4.2FMPI2C pins and internal signals . . . . .781
26.4.3FMPI2C clock requirements . . . . .782
26.4.4FMPI2C mode selection . . . . .782
26.4.5FMPI2C initialization . . . . .783
26.4.6FMPI2C reset . . . . .787
26.4.7FMPI2C data transfer . . . . .788
26.4.8FMPI2C slave mode . . . . .790
26.4.9FMPI2C master mode . . . . .799
26.4.10FMPI2C_TIMINGR register configuration examples . . . . .810
26.4.11SMBus specific features . . . . .812
26.4.12SMBus initialization . . . . .814
26.4.13SMBus FMPI2C_TIMEOUTR register configuration examples . . . . .816
26.4.14SMBus slave mode . . . . .817
26.4.15SMBus master mode . . . . .820
26.4.16Error conditions . . . . .823
26.5FMPI2C in low-power modes . . . . .825
26.6FMPI2C interrupts . . . . .825
26.7FMPI2C DMA requests . . . . .826
26.7.1Transmission using DMA . . . . .826
26.7.2Reception using DMA . . . . .826
26.8FMPI2C debug modes . . . . .827
26.9FMPI2C registers . . . . .827
26.9.1FMPI2C control register 1 (FMPI2C_CR1) . . . . .827
26.9.2FMPI2C control register 2 (FMPI2C_CR2) . . . . .830
26.9.3FMPI2C own address 1 register (FMPI2C_OAR1) . . . . .832
26.9.4FMPI2C own address 2 register (FMPI2C_OAR2) . . . . .832
26.9.5FMPI2C timing register (FMPI2C_TIMINGR) . . . . .833
26.9.6FMPI2C timeout register (FMPI2C_TIMEOUTR) . . . . .834
26.9.7FMPI2C interrupt and status register (FMPI2C_ISR) . . . . .835
26.9.8FMPI2C interrupt clear register (FMPI2C_ICR) . . . . .838
26.9.9FMPI2C PEC register (FMPI2C_PECR) . . . . .839
26.9.10FMPI2C receive data register (FMPI2C_RXDR) . . . . .839
26.9.11FMPI2C transmit data register (FMPI2C_TXDR) . . . . .840
26.9.12FMPI2C register map . . . . .841
27Inter-integrated circuit (I 2 C) interface . . . . .842
27.1I 2 C introduction . . . . .842
27.2I 2 C main features . . . . .843
27.3I 2 C functional description . . . . .844
27.3.1Mode selection . . . . .844
27.3.2I2C slave mode .....845
27.3.3I2C master mode .....848
27.3.4Error conditions .....853
27.3.5Programmable noise filter .....854
27.3.6SDA/SCL line control .....855
27.3.7SMBus .....855
27.3.8DMA requests .....857
27.3.9Packet error checking .....859
27.4I 2 C interrupts .....860
27.5I 2 C debug mode .....861
27.6I 2 C registers .....862
27.6.1I 2 C control register 1 (I2C_CR1) .....862
27.6.2I 2 C control register 2 (I2C_CR2) .....864
27.6.3I 2 C own address register 1 (I2C_OAR1) .....865
27.6.4I 2 C own address register 2 (I2C_OAR2) .....866
27.6.5I 2 C data register (I2C_DR) .....866
27.6.6I 2 C status register 1 (I2C_SR1) .....866
27.6.7I 2 C status register 2 (I2C_SR2) .....869
27.6.8I 2 C clock control register (I2C_CCR) .....870
27.6.9I 2 C TRISE register (I2C_TRISE) .....871
27.6.10I 2 C FLTR register (I2C_FLTR) .....872
27.6.11I2C register map .....873
28Universal synchronous receiver transmitter (USART)
/universal asynchronous receiver transmitter (UART) .....		874
28.1USART introduction .....874
28.2USART main features .....875
28.3USART implementation .....876
28.4USART functional description .....876
28.4.1USART character description .....879
28.4.2Transmitter .....880
28.4.3Receiver .....883
28.4.4Fractional baud rate generation .....888
28.4.5USART receiver tolerance to clock deviation .....897
28.4.6Multiprocessor communication .....898
28.4.7Parity control .....900
28.4.8LIN (local interconnection network) mode . . . . .901
28.4.9USART synchronous mode . . . . .903
28.4.10Single-wire half-duplex communication . . . . .905
28.4.11Smartcard . . . . .906
28.4.12IrDA SIR ENDEC block . . . . .908
28.4.13Continuous communication using DMA . . . . .910
28.4.14Hardware flow control . . . . .912
28.5USART interrupts . . . . .914
28.6USART registers . . . . .915
28.6.1Status register (USART_SR) . . . . .915
28.6.2Data register (USART_DR) . . . . .918
28.6.3Baud rate register (USART_BRR) . . . . .918
28.6.4Control register 1 (USART_CR1) . . . . .919
28.6.5Control register 2 (USART_CR2) . . . . .921
28.6.6Control register 3 (USART_CR3) . . . . .922
28.6.7Guard time and prescaler register (USART_GTPR) . . . . .924
28.6.8USART register map . . . . .925
29Serial peripheral interface/ inter-IC sound (SPI/I2S) . . . . .926
29.1Introduction . . . . .926
29.1.1SPI main features . . . . .927
29.1.2SPI extended features . . . . .928
29.1.3I2S features . . . . .928
29.2SPI/I2S implementation . . . . .928
29.3SPI functional description . . . . .929
29.3.1General description . . . . .929
29.3.2Communications between one master and one slave . . . . .930
29.3.3Standard multislave communication . . . . .933
29.3.4Multimaster communication . . . . .934
29.3.5Slave select (NSS) pin management . . . . .934
29.3.6Communication formats . . . . .936
29.3.7SPI configuration . . . . .938
29.3.8Procedure for enabling SPI . . . . .938
29.3.9Data transmission and reception procedures . . . . .939
29.3.10Procedure for disabling the SPI . . . . .941
29.3.11Communication using DMA (direct memory addressing) . . . . .942
29.3.12SPI status flags . . . . .944
29.3.13SPI error flags . . . . .945
29.4SPI special features . . . . .946
29.4.1TI mode . . . . .946
29.4.2CRC calculation . . . . .947
29.5SPI interrupts . . . . .949
29.6I 2 S functional description . . . . .950
29.6.1I 2 S general description . . . . .950
29.6.2I 2 S full-duplex . . . . .951
29.6.3Supported audio protocols . . . . .952
29.6.4Clock generator . . . . .958
29.6.5I 2 S master mode . . . . .961
29.6.6I 2 S slave mode . . . . .963
29.6.7I 2 S status flags . . . . .964
29.6.8I 2 S error flags . . . . .965
29.6.9I 2 S interrupts . . . . .966
29.6.10DMA features . . . . .966
29.7SPI and I 2 S registers . . . . .967
29.7.1SPI control register 1 (SPI_CR1) (not used in I 2 S mode) . . . . .967
29.7.2SPI control register 2 (SPI_CR2) . . . . .969
29.7.3SPI status register (SPI_SR) . . . . .970
29.7.4SPI data register (SPI_DR) . . . . .972
29.7.5SPI CRC polynomial register (SPI_CRCPR) (not used in I 2 S mode) . . . . .972
29.7.6SPI RX CRC register (SPI_RXCRCR) (not used in I 2 S mode) . . . . .973
29.7.7SPI TX CRC register (SPI_TXCRCR) (not used in I 2 S mode) . . . . .973
29.7.8SPI_I 2 S configuration register (SPI_I2SCFGR) . . . . .974
29.7.9SPI_I 2 S prescaler register (SPI_I2SPR) . . . . .975
29.7.10SPI register map . . . . .977
30Serial audio interface (SAI) . . . . .978
30.1Introduction . . . . .978
30.2Main features . . . . .979
30.3Functional block diagram . . . . .979
30.4Main SAI modes . . . . .981
30.5SAI synchronization mode . . . . .982
30.6Audio data size . . . . .982
30.7Frame synchronization . . . . .982
30.7.1Frame length . . . . .983
30.7.2Frame synchronization polarity . . . . .983
30.7.3Frame synchronization active level length . . . . .984
30.7.4Frame synchronization offset . . . . .984
30.7.5FS signal role . . . . .984
30.8Slot configuration . . . . .985
30.9SAI clock generator . . . . .987
30.10Internal FIFOs . . . . .988
30.11AC'97 link controller . . . . .991
30.12Specific features . . . . .991
30.12.1Mute mode . . . . .992
30.12.2MONO/STEREO function . . . . .992
30.12.3Companding mode . . . . .993
30.12.4Output data line management on an inactive slot . . . . .994
30.13Error flags . . . . .996
30.13.1FIFO overrun/underrun (OVRUDR) . . . . .996
30.13.2Anticipated frame synchronisation detection (AFSDET) . . . . .998
30.13.3Late frame synchronization detection . . . . .998
30.13.4Codec not ready (CNRDY AC'97) . . . . .999
30.13.5Wrong clock configuration in master mode (with NODIV = 0) . . . . .999
30.14Interrupt sources . . . . .999
30.15Disabling the SAI . . . . .1000
30.16SAI DMA interface . . . . .1001
30.17SAI registers . . . . .1002
30.17.1SAI xConfiguration register 1 (SAI_xCR1) where x is A or B . . . . .1002
30.17.2SAI xConfiguration register 2 (SAI_xCR2) where x is A or B . . . . .1005
30.17.3SAI xFrame configuration register (SAI_xFRCR) where x is A or B . . . . .1007
30.17.4SAI xSlot register (SAI_xSLOTR) where x is A or B . . . . .1009
30.17.5SAI xInterrupt mask register2(SAI_xIM) where x is A or B . . . . .1010
30.17.6SAI xStatus register (SAI_xSR) where x is A or B . . . . .1012
30.17.7SAI xClear flag register (SAI_xCLRFR) where X is A or B . . . . .1014
30.17.8SAI xData register (SAI_xDR) where x is A or B . . . . .1015
30.17.9SAI register map . . . . .1015
31Secure digital input/output interface (SDIO) . . . . .1017
31.1SDIO main features . . . . .1017
31.2SDIO bus topology . . . . .1017
31.3SDIO functional description . . . . .1019
31.3.1SDIO adapter . . . . .1021
31.3.2SDIO APB2 interface . . . . .1032
31.4Card functional description . . . . .1033
31.4.1Card identification mode . . . . .1033
31.4.2Card reset . . . . .1034
31.4.3Operating voltage range validation . . . . .1034
31.4.4Card identification process . . . . .1034
31.4.5Block write . . . . .1035
31.4.6Block read . . . . .1036
31.4.7Stream access, stream write and stream read
(MultiMediaCard only) . . . . .		1036
31.4.8Erase: group erase and sector erase . . . . .1038
31.4.9Wide bus selection or deselection . . . . .1038
31.4.10Protection management . . . . .1038
31.4.11Card status register . . . . .1042
31.4.12SD status register . . . . .1045
31.4.13SD I/O mode . . . . .1049
31.4.14Commands and responses . . . . .1050
31.5Response formats . . . . .1053
31.5.1R1 (normal response command) . . . . .1054
31.5.2R1b . . . . .1054
31.5.3R2 (CID, CSD register) . . . . .1054
31.5.4R3 (OCR register) . . . . .1055
31.5.5R4 (Fast I/O) . . . . .1055
31.5.6R4b . . . . .1055
31.5.7R5 (interrupt request) . . . . .1056
31.5.8R6 . . . . .1056
31.6SDIO I/O card-specific operations . . . . .1057
31.6.1SDIO I/O read wait operation by SDIO_D2 signalling . . . . .1057
31.6.2SDIO read wait operation by stopping SDIO_CK . . . . .1058
31.6.3SDIO suspend/resume operation . . . . .1058
31.6.4SDIO interrupts . . . . .1058
31.7HW flow control . . . . .1058
32.7.1Transmission handling . . . . .1084
32.7.2Time triggered communication mode . . . . .1086
32.7.3Reception handling . . . . .1086
32.7.4Identifier filtering . . . . .1087
32.7.5Message storage . . . . .1091
32.7.6Error management . . . . .1092
32.7.7Bit timing . . . . .1093
32.8bxCAN interrupts . . . . .1096
32.9CAN registers . . . . .1097
32.9.1Register access protection . . . . .1097
32.9.2CAN control and status registers . . . . .1097
32.9.3CAN mailbox registers . . . . .1107
32.9.4CAN filter registers . . . . .1113
32.9.5bxCAN register map . . . . .1117
33USB on-the-go full-speed (OTG_FS) . . . . .1121
33.1Introduction . . . . .1121
33.2OTG_FS main features . . . . .1122
33.2.1General features . . . . .1122
33.2.2Host-mode features . . . . .1123
33.2.3Peripheral-mode features . . . . .1123
33.2.4Split rail for USB . . . . .1123
33.3OTG_FS implementation . . . . .1124
33.4OTG_FS functional description . . . . .1125
33.4.1OTG_FS block diagram . . . . .1125
33.4.2OTG_FS pin and internal signals . . . . .1125
33.4.3OTG_FS core . . . . .1126
33.4.4Embedded full-speed OTG PHY connected to OTG_FS . . . . .1126
33.4.5OTG detections . . . . .1127
33.5OTG_FS dual role device (DRD) . . . . .1127
33.5.1ID line detection . . . . .1127
33.5.2HNP dual role device . . . . .1128
33.5.3SRP dual role device . . . . .1128
33.6OTG_FS as a USB peripheral . . . . .1128
33.6.1SRP-capable peripheral . . . . .1129
33.6.2Peripheral states . . . . .1129
33.6.3Peripheral endpoints . . . . .1130
33.7OTG_FS as a USB host . . . . .1132
33.7.1SRP-capable host . . . . .1133
33.7.2USB host states . . . . .1133
33.7.3Host channels . . . . .1135
33.7.4Host scheduler . . . . .1136
33.8OTG_FS SOF trigger . . . . .1137
33.8.1Host SOFs . . . . .1137
33.8.2Peripheral SOFs . . . . .1137
33.9OTG_FS low-power modes . . . . .1138
33.10OTG_FS Dynamic update of the OTG_HFIR register . . . . .1139
33.11OTG_FS data FIFOs . . . . .1139
33.11.1Peripheral FIFO architecture . . . . .1140
33.11.2Host FIFO architecture . . . . .1141
33.11.3FIFO RAM allocation . . . . .1142
33.12OTG_FS system performance . . . . .1144
33.13OTG_FS interrupts . . . . .1144
33.14OTG_FS control and status registers . . . . .1146
33.14.1CSR memory map . . . . .1146
33.15OTG_FS registers . . . . .1150
33.15.1OTG control and status register (OTG_GOTGCTL) . . . . .1151
33.15.2OTG interrupt register (OTG_GOTGINT) . . . . .1154
33.15.3OTG AHB configuration register (OTG_GAHBCFG) . . . . .1155
33.15.4OTG USB configuration register (OTG_GUSBCFG) . . . . .1156
33.15.5OTG reset register (OTG_GRSTCTL) . . . . .1158
33.15.6OTG core interrupt register (OTG_GINTSTS) . . . . .1160
33.15.7OTG interrupt mask register (OTG_GINTMSK) . . . . .1164
33.15.8OTG receive status debug read register (OTG_GRXSTSR) . . . . .1167
33.15.9OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . .1168
33.15.10OTG status read and pop registers (OTG_GRXSTSP) . . . . .1169
33.15.11OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . . . .1170
33.15.12OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .1171
33.15.13OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . .		1171
33.15.14OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . .		1172
33.15.15OTG general core configuration register (OTG_GCCFG) . . . . .1173
33.15.16OTG core ID register (OTG_CID) . . . . .1175
33.15.17OTG core LPM configuration register (OTG_GLPMCFG) . . . . .1175
33.15.18OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . .		1179
33.15.19OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . .		1179
33.15.20Host-mode registers . . . . .1180
33.15.21OTG host configuration register (OTG_HCFG) . . . . .1180
33.15.22OTG host frame interval register (OTG_HFIR) . . . . .1181
33.15.23OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . .		1182
33.15.24OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . .		1182
33.15.25OTG host all channels interrupt register (OTG_HAINT) . . . . .1183
33.15.26OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . .		1184
33.15.27OTG host port control and status register (OTG_HPRT) . . . . .1185
33.15.28OTG host channel x characteristics register (OTG_HCCHARx) . . . . .1187
33.15.29OTG host channel x interrupt register (OTG_HCINTx) . . . . .1188
33.15.30OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . . . .1189
33.15.31OTG host channel x transfer size register (OTG_HCTSIZx) . . . . .1190
33.15.32Device-mode registers . . . . .1191
33.15.33OTG device configuration register (OTG_DCFG) . . . . .1191
33.15.34OTG device control register (OTG_DCTL) . . . . .1192
33.15.35OTG device status register (OTG_DSTS) . . . . .1195
33.15.36OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . .		1196
33.15.37OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . .		1197
33.15.38OTG device all endpoints interrupt register (OTG_DAINT) . . . . .1198
33.15.39OTG all endpoints interrupt mask register
(OTG_DaintMSK) . . . . .		1199
33.15.40OTG device V BUS discharge time register
(OTG_DVBUSDIS) . . . . .		1199
33.15.41OTG device V BUS pulsing time register
(OTG_DVBUSPULSE) . . . . .		1200
33.15.42OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) . . . . .		1200
33.15.43OTG device control IN endpoint 0 control register
(OTG_DIEPCTL0) . . . . .		1201
33.15.44OTG device IN endpoint x control register (OTG_DIEPCTLx) . . . . .1202
33.15.45OTG device IN endpoint x interrupt register (OTG_DIEPINTx) . . . . .1205
33.15.46OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) . . . . .		1206
33.15.47OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) . . . . .		1207
33.15.48OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) . . . . .1208
33.15.49OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0) . . . . .		1209
33.15.50OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . . . . .1210
33.15.51OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0) . . . . .		1212
33.15.52OTG device OUT endpoint x control register
(OTG_DOEPCTLx) . . . . .		1213
33.15.53OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx) . . . . .		1215
33.15.54OTG power and clock gating control register (OTG_PCGCCTL) . . . . .1216
33.15.55OTG_FS register map . . . . .1217
33.16OTG_FS programming model . . . . .1225
33.16.1Core initialization . . . . .1225
33.16.2Host initialization . . . . .1226
33.16.3Device initialization . . . . .1226
33.16.4Host programming model . . . . .1227
33.16.5Device programming model . . . . .1248
33.16.6Worst case response time . . . . .1269
33.16.7OTG programming model . . . . .1271
34Debug support (DBG) . . . . .1277
34.1Overview . . . . .1277
34.2Reference Arm® documentation . . . . .1278
34.3SWJ debug port (serial wire and JTAG) . . . . .1278
34.3.1Mechanism to select the JTAG-DP or the SW-DP . . . . .1279
34.4Pinout and debug port pins . . . . .1279
34.4.1SWJ debug port pins . . . . .1280
34.4.2Flexible SWJ-DP pin assignment . . . . .1280
34.4.3Internal pull-up and pull-down on JTAG pins . . . . .1280
34.4.4Using serial wire and releasing the unused debug pins as GPIOs . . . . .1282
34.5JTAG TAP connection . . . . .1282
34.6ID codes and locking mechanism . . . . .1284
34.6.1MCU device ID code . . . . .1284
34.6.2Boundary scan TAP . . . . .1284
34.6.3Cortex ® -M4 with FPU TAP . . . . .1284
34.6.4Cortex ® -M4 with FPU JEDEC-106 ID code . . . . .1285
34.7JTAG debug port . . . . .1285
34.8SW debug port . . . . .1287
34.8.1SW protocol introduction . . . . .1287
34.8.2SW protocol sequence . . . . .1287
34.8.3SW-DP state machine (reset, idle states, ID code) . . . . .1288
34.8.4DP and AP read/write accesses . . . . .1288
34.8.5SW-DP registers . . . . .1289
34.8.6SW-AP registers . . . . .1290
34.9AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP . . . . .		1290
34.10Core debug . . . . .1291
34.11Capability of the debugger host to connect under system reset . . . . .1292
34.12FPB (Flash patch breakpoint) . . . . .1292
34.13DWT (data watchpoint trigger) . . . . .1293
34.14ITM (instrumentation trace macrocell) . . . . .1293
34.14.1General description . . . . .1293
34.14.2Time stamp packets, synchronization and overflow packets . . . . .1293
34.15ETM (Embedded trace macrocell) . . . . .1295
34.15.1General description . . . . .1295
34.15.2Signal protocol, packet types . . . . .1295
34.15.3Main ETM registers . . . . .1295
34.15.4Configuration example . . . . .1296
34.16MCU debug component (DBGMCU) . . . . .1296
34.16.1Debug support for low-power modes . . . . .1296
34.16.2Debug support for timers, watchdog, bxCAN and I 2 C . . . . .1297
34.16.3Debug MCU configuration register . . . . .1297
34.16.4Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . .1298
34.16.5Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . .1300
34.17TPIU (trace port interface unit) . . . . .1301
34.17.1Introduction . . . . .1301
34.17.2TRACE pin assignment . . . . .1302

List of tables

Table 1.Register boundary addresses . . . . .59
Table 2.Boot modes . . . . .63
Table 3.Embedded bootloader interfaces . . . . .64
Table 4.Memory mapping vs. Boot mode/physical remap in STM32F413/423 . . . . .65
Table 5.Flash module organization . . . . .67
Table 6.Number of wait states according to CPU clock (HCLK) frequency . . . . .68
Table 7.Maximum program/erase parallelism . . . . .72
Table 8.Flash interrupt request . . . . .74
Table 9.Option byte organization . . . . .74
Table 10.Description of the option bytes . . . . .75
Table 11.Access versus read protection level . . . . .78
Table 12.OTP area organization . . . . .81
Table 13.Flash register map and reset values . . . . .89
Table 14.CRC calculation unit register map and reset values . . . . .93
Table 15.Low-power mode summary . . . . .102
Table 16.Sleep-now entry and exit . . . . .103
Table 17.Sleep-on-exit entry and exit . . . . .103
Table 18.BAM-now entry and exit . . . . .104
Table 19.BAM-on-exit entry and exit . . . . .105
Table 20.Stop operating modes . . . . .106
Table 21.Stop mode entry and exit . . . . .107
Table 22.Standby mode entry and exit . . . . .109
Table 23.PWR - register map and reset values . . . . .116
Table 24.RCC register map and reset values for STM32F413/423 . . . . .182
Table 25.Port bit configuration table . . . . .186
Table 26.Flexible SWJ-DP pin assignment . . . . .189
Table 27.RTC additional functions . . . . .196
Table 28.GPIO register map and reset values . . . . .202
Table 29.SYSCFG register map and reset values . . . . .214
Table 30.DMA1 request mapping . . . . .219
Table 31.DMA2 request mapping . . . . .219
Table 32.Source and destination address . . . . .220
Table 33.Source and destination address registers in double-buffer mode (DBM = 1) . . . . .226
Table 34.Packing/unpacking and endian behavior (bit PINC = MINC = 1) . . . . .227
Table 35.Restriction on NDT versus PSIZE and MSIZE . . . . .227
Table 36.FIFO threshold configurations . . . . .230
Table 37.Possible DMA configurations . . . . .234
Table 38.DMA interrupt requests . . . . .236
Table 39.DMA register map and reset values . . . . .246
Table 40.Vector table for STM32F413/423 . . . . .252
Table 41.External interrupt/event controller register map and reset values . . . . .265
Table 42.NOR/PSRAM bank selection . . . . .269
Table 43.NOR/PSRAM External memory address . . . . .269
Table 44.Programmable NOR/PSRAM access parameters . . . . .271
Table 45.Non-multiplexed I/O NOR flash memory . . . . .271
Table 46.16-bit multiplexed I/O NOR flash memory . . . . .272
Table 47.Non-multiplexed I/Os PSRAM/SRAM . . . . .272
Table 48.16-Bit multiplexed I/O PSRAM . . . . .272
Table 49.NOR flash/PSRAM: example of supported memories and transactions . . . . .273
Table 50.FSMC_BCRx bitfields (mode 1) . . . . .276
Table 51.FSMC_BTRx bitfields (mode 1) . . . . .277
Table 52.FSMC_BCRx bitfields (mode A) . . . . .279
Table 53.FSMC_BTRx bitfields (mode A) . . . . .279
Table 54.FSMC_BWTRx bitfields (mode A) . . . . .280
Table 55.FSMC_BCRx bitfields (mode 2/B) . . . . .282
Table 56.FSMC_BTRx bitfields (mode 2/B) . . . . .282
Table 57.FSMC_BWTRx bitfields (mode 2/B) . . . . .283
Table 58.FSMC_BCRx bitfields (mode C) . . . . .284
Table 59.FSMC_BTRx bitfields (mode C) . . . . .285
Table 60.FSMC_BWTRx bitfields (mode C) . . . . .285
Table 61.FSMC_BCRx bitfields (mode D) . . . . .287
Table 62.FSMC_BTRx bitfields (mode D) . . . . .287
Table 63.FSMC_BWTRx bitfields (mode D) . . . . .288
Table 64.FSMC_BCRx bitfields (Muxed mode) . . . . .289
Table 65.FSMC_BTRx bitfields (Muxed mode) . . . . .290
Table 66.FSMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .295
Table 67.FSMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .296
Table 68.FSMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .297
Table 69.FSMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .298
Table 70.FSMC register map and reset values . . . . .306
Table 71.QUADSPI pins . . . . .309
Table 72.QUADSPI interrupt requests . . . . .323
Table 73.QUADSPI register map and reset values . . . . .334
Table 74.ADC pins . . . . .338
Table 75.Analog watchdog channel selection . . . . .341
Table 76.Configuring the trigger polarity . . . . .345
Table 77.External trigger for regular channels . . . . .345
Table 78.External trigger for injected channels . . . . .346
Table 79.ADC interrupts . . . . .350
Table 80.ADC global register map . . . . .364
Table 81.ADC register map and reset values . . . . .364
Table 82.ADC register map and reset values (common ADC registers) . . . . .365
Table 83.DAC pins . . . . .367
Table 84.External triggers . . . . .370
Table 85.DAC register map . . . . .386
Table 86.DFSDMx implementation . . . . .390
Table 87.DFSDM external pins . . . . .392
Table 88.DFSDM internal signals . . . . .392
Table 89.DFSDM triggers connection . . . . .392
Table 90.DFSDM break connection . . . . .393
Table 91.Demultiplexers (DM[6:1]) operation . . . . .406
Table 92.Use-cases examples for beamforming applications . . . . .406
Table 93.Filter maximum output resolution (peak data values from filter output) for some FOSR values . . . . .411
Table 94.Integrator maximum output resolution (peak data values from integrator output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . . .411
Table 95.DFSDM interrupt requests . . . . .419
Table 96.DFSDM register map and reset values . . . . .440
Table 97.RNG internal input/output signals . . . . .451
Table 98.RNG interrupt requests . . . . .456
Table 99.RNG configurations . . . . .457
Table 100.RNG register map and reset map . . . . .460
Table 101.Counting direction versus encoder signals . . . . .498
Table 102.TIMx Internal trigger connection . . . . .511
Table 103.Output control bits for complementary OCx and OCxN channels
with break feature . . . . .		523
Table 104.TIM1&TIM8 register map and reset values . . . . .530
Table 105.Counting direction versus encoder signals . . . . .559
Table 106.TIMx internal trigger connections . . . . .574
Table 107.Output control bit for standard OCx channels . . . . .584
Table 108.TIM2 to TIM5 register map and reset values . . . . .591
Table 109.TIMx internal trigger connections . . . . .617
Table 110.Output control bit for standard OCx channels . . . . .625
Table 111.TIM9/12 register map and reset values . . . . .627
Table 112.Output control bit for standard OCx channels . . . . .635
Table 113.TIM10/11/13/14 register map and reset values . . . . .638
Table 114.TIM6 register map and reset values . . . . .652
Table 115.STM32F413/423 LPTIM features . . . . .654
Table 116.LPTIM1 external trigger connection . . . . .655
Table 117.Prescaler division ratios . . . . .657
Table 118.Encoder counting scenarios . . . . .663
Table 119.Effect of low-power modes on the LPTIM . . . . .664
Table 120.Interrupt events . . . . .664
Table 121.LPTIM register map and reset values . . . . .674
Table 122.Min/max IWDG timeout periods (ms) at 32 kHz (LSI) . . . . .676
Table 123.IWDG register map and reset values . . . . .680
Table 124.WWDG register map and reset values . . . . .687
Table 125.AES internal input/output signals . . . . .689
Table 126.CTR mode initialization vector definition . . . . .708
Table 127.GCM last block definition . . . . .710
Table 128.GCM mode IVI bitfield initialization . . . . .711
Table 129.Initialization of AES_IVRx registers in CCM mode . . . . .718
Table 130.Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .723
Table 131.DMA channel configuration for memory-to-AES data transfer . . . . .724
Table 132.DMA channel configuration for AES-to-memory data transfer . . . . .725
Table 133.AES interrupt requests . . . . .727
Table 134.Processing latency (in clock cycle) for ECB, CBC and CTR . . . . .727
Table 135.Processing latency for GCM and CCM (in clock cycle) . . . . .727
Table 136.AES register map and reset values . . . . .739
Table 137.Effect of low power modes on RTC . . . . .755
Table 138.Interrupt control bits . . . . .756
Table 139.RTC register map and reset values . . . . .776
Table 140.FMPI2C implementation . . . . .780
Table 141.FMPI2C input/output pins . . . . .781
Table 142.FMPI2C internal input/output signals . . . . .781
Table 143.Comparison of analog and digital filters . . . . .784
Table 144.I 2 C-bus and SMBus specification data setup and hold times . . . . .786
Table 145.FMPI2C configuration . . . . .790
Table 146.I 2 C-bus and SMBus specification clock timings . . . . .801
Table 147.Timing settings for f I2CCLK of 8 MHz . . . . .811
Table 148.Timing settings for f I2CCLK of 16 MHz . . . . .811
Table 149.SMBus timeout specifications . . . . .813
Table 150.SMBus with PEC configuration . . . . .815
Table 151.TIMEOUTA[11:0] for maximum \( t_{TIMEOUT} \) of 25 ms . . . . .816
Table 152.TIMEOUTB[11:0] for maximum \( t_{LOW:SEXT} \) and \( t_{LOW:MEXT} \) of 8 ms . . . . .816
Table 153.TIMEOUTA[11:0] for maximum \( t_{IDLE} \) of 50 \( \mu \) s . . . . .816
Table 154.Effect of low-power modes to FMPI2C . . . . .825
Table 155.FMPI2C interrupt requests . . . . .825
Table 156.FMPI2C register map and reset values . . . . .841
Table 157.Maximum DNF[3:0] value to be compliant with Thd:dat(max) . . . . .854
Table 158.SMBus vs. I2C . . . . .855
Table 159.I2C Interrupt requests . . . . .860
Table 160.I2C register map and reset values . . . . .873
Table 161.USART features . . . . .876
Table 162.Noise detection from sampled data . . . . .887
Table 163.Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 12 \) MHz, oversampling by 16. . . . .890
Table 164.Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 12 \) MHz, oversampling by 8. . . . .890
Table 165.Error calculation for programmed baud rates at \( f_{PCLK} = 16 \) MHz or \( f_{PCLK} = 24 \) MHz, oversampling by 16. . . . .891
Table 166.Error calculation for programmed baud rates at \( f_{PCLK} = 16 \) MHz or \( f_{PCLK} = 24 \) MHz, oversampling by 8. . . . .892
Table 167.Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 16 \) MHz, oversampling by 16. . . . .892
Table 168.Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 16 \) MHz, oversampling by 8. . . . .893
Table 169.Error calculation for programmed baud rates at \( f_{PCLK} = 30 \) MHz or \( f_{PCLK} = 60 \) MHz, oversampling by 16. . . . .894
Table 170.Error calculation for programmed baud rates at \( f_{PCLK} = 30 \) MHz or \( f_{PCLK} = 60 \) MHz, oversampling by 8 . . . . .894
Table 171.Error calculation for programmed baud rates at \( f_{PCLK} = 42 \) MHz or \( f_{PCLK} = 84 \) MHz, oversampling by 16. . . . .895
Table 172.Error calculation for programmed baud rates at \( f_{PCLK} = 42 \) MHz or \( f_{PCLK} = 84 \) MHz, oversampling by 8. . . . .896
Table 173.USART receiver tolerance when DIV fraction is 0 . . . . .897
Table 174.USART receiver tolerance when DIV_Fraction is different from 0 . . . . .898
Table 175.Frame formats . . . . .900
Table 176.USART interrupt requests. . . . .914
Table 177.USART register map and reset values . . . . .925
Table 178.STM32F413/423 SPI implementation . . . . .928
Table 179.SPI interrupt requests . . . . .949
Table 180.Audio-frequency precision using standard 8 MHz HSE . . . . .960
Table 181.I 2 S interrupt requests . . . . .966
Table 182.SPI register map and reset values . . . . .977
Table 183.Example of possible audio frequency sampling range . . . . .988
Table 184.Interrupt sources. . . . .1000
Table 185.SAI register map and reset values . . . . .1015
Table 186.SDIO I/O definitions . . . . .1020
Table 187.Command format . . . . .1025
Table 188.Short response format . . . . .1026
Table 189.Long response format. . . . .1026
Table 190.Command path status flags . . . . .1026
Table 191.Data token format . . . . .1029
Table 192.DPSM flags . . . . .1030
Table 193.Transmit FIFO status flags . . . . .1031
Table 194.Receive FIFO status flags . . . . .1031
Table 195.Card status . . . . .1042
Table 196.SD status . . . . .1045
Table 197.Speed class code field . . . . .1046
Table 198.Performance move field . . . . .1047
Table 199.AU_SIZE field . . . . .1047
Table 200.Maximum AU size . . . . .1047
Table 201.Erase size field . . . . .1048
Table 202.Erase timeout field . . . . .1048
Table 203.Erase offset field . . . . .1048
Table 204.Block-oriented write commands . . . . .1051
Table 205.Block-oriented write protection commands . . . . .1052
Table 206.Erase commands . . . . .1052
Table 207.I/O mode commands . . . . .1052
Table 208.Lock card . . . . .1053
Table 209.Application-specific commands . . . . .1053
Table 210.R1 response . . . . .1054
Table 211.R2 response . . . . .1054
Table 212.R3 response . . . . .1055
Table 213.R4 response . . . . .1055
Table 214.R4b response . . . . .1055
Table 215.R5 response . . . . .1056
Table 216.R6 response . . . . .1057
Table 217.Response type and SDIO_RESPx registers . . . . .1063
Table 218.SDIO register map . . . . .1074
Table 219.CAN implementation . . . . .1077
Table 220.Transmit mailbox mapping . . . . .1092
Table 221.Receive mailbox mapping . . . . .1092
Table 222.bxCAN register map and reset values . . . . .1117
Table 223.OTG_FS speeds supported . . . . .1121
Table 224.OTG_FS implementation . . . . .1124
Table 225.OTG_FS input/output pins . . . . .1125
Table 226.OTG_FS input/output signals . . . . .1126
Table 227.Compatibility of STM32 low power modes with the OTG . . . . .1138
Table 228.Core global control and status registers (CSRs) . . . . .1146
Table 229.Host-mode control and status registers (CSRs) . . . . .1147
Table 230.Device-mode control and status registers . . . . .1148
Table 231.Data FIFO (DFIFO) access register map . . . . .1150
Table 232.Power and clock gating control and status registers . . . . .1150
Table 233.TRDT values . . . . .1157
Table 234.Minimum duration for soft disconnect . . . . .1194
Table 235.OTG_FS register map and reset values . . . . .1217
Table 236.SWJ debug port pins . . . . .1280
Table 237.Flexible SWJ-DP pin assignment . . . . .1280
Table 238.JTAG debug port data registers . . . . .1285
Table 239.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .1286
Table 240.Packet request (8-bits) . . . . .1287
Table 241.ACK response (3 bits) . . . . .1288
Table 242.DATA transfer (33 bits) . . . . .1288
Table 243.SW-DP registers . . . . .1289
Table 244.Cortex ® -M4 with FPU AHB-AP registers . . . . .1290
Table 245.Core debug registers . . . . .1291
Table 246.Main ITM registers . . . . .1294
Table 247.Main ETM registers . . . . .1296
Table 248.Asynchronous TRACE pin assignment . . . . .1302
Table 249.Synchronous TRACE pin assignment . . . . .1302
Table 250.Flexible TRACE pin assignment . . . . .1303
Table 251.Important TPIU registers . . . . .1305
Table 252.DBG register map and reset values . . . . .1307
Table 253.Document revision history . . . . .1312

List of figures

Figure 1.System architecture . . . . .55
Figure 2.Memory map . . . . .58
Figure 3.Flash memory interface connection inside system architecture . . . . .66
Figure 4.Sequential 32-bit instruction execution . . . . .70
Figure 5.RDP levels . . . . .78
Figure 6.PCROP levels . . . . .80
Figure 7.CRC calculation unit block diagram . . . . .90
Figure 8.Power supply overview . . . . .95
Figure 9.Power-on reset/power-down reset waveform . . . . .98
Figure 10.BOR thresholds . . . . .99
Figure 11.PVD thresholds . . . . .100
Figure 12.Simplified diagram of the reset circuit . . . . .118
Figure 13.Clock tree . . . . .120
Figure 14.HSE/ LSE clock sources . . . . .122
Figure 15.Frequency measurement with TIM5 in Input capture mode . . . . .127
Figure 16.Frequency measurement with TIM11 in Input capture mode . . . . .128
Figure 17.Basic structure of a five-volt tolerant I/O port bit . . . . .186
Figure 18.Selecting an alternate function on STM32F413/423 . . . . .190
Figure 19.Input floating/pull up/pull down configurations . . . . .193
Figure 20.Output configuration . . . . .194
Figure 21.Alternate function configuration . . . . .194
Figure 22.High impedance-analog configuration . . . . .195
Figure 23.DMA block diagram . . . . .217
Figure 24.Channel selection . . . . .218
Figure 25.Peripheral-to-memory mode . . . . .222
Figure 26.Memory-to-peripheral mode . . . . .223
Figure 27.Memory-to-memory mode . . . . .224
Figure 28.FIFO structure . . . . .229
Figure 29.External interrupt/event controller block diagram . . . . .256
Figure 30.External interrupt/event GPIO mapping . . . . .259
Figure 31.FSMC block diagram . . . . .267
Figure 32.FSMC memory banks . . . . .269
Figure 33.Mode 1 read access waveforms . . . . .275
Figure 34.Mode 1 write access waveforms . . . . .276
Figure 35.Mode A read access waveforms . . . . .278
Figure 36.Mode A write access waveforms . . . . .278
Figure 37.Mode 2 and mode B read access waveforms . . . . .280
Figure 38.Mode 2 write access waveforms . . . . .281
Figure 39.Mode B write access waveforms . . . . .281
Figure 40.Mode C read access waveforms . . . . .283
Figure 41.Mode C write access waveforms . . . . .284
Figure 42.Mode D read access waveforms . . . . .286
Figure 43.Mode D write access waveforms . . . . .286
Figure 44.Muxed read access waveforms . . . . .288
Figure 45.Muxed write access waveforms . . . . .289
Figure 46.Asynchronous wait during a read access waveforms . . . . .291
Figure 47.Asynchronous wait during a write access waveforms . . . . .292
Figure 48.Wait configuration waveforms . . . . .294
Figure 49.Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . .295
Figure 50.Synchronous multiplexed write mode waveforms - PSRAM (CRAM) . . . . .297
Figure 51.QUADSPI block diagram when dual-flash mode is disabled . . . . .308
Figure 52.QUADSPI block diagram when dual-flash mode is enabled . . . . .309
Figure 53.Example of read command in quad-SPI mode . . . . .310
Figure 54.Example of a DDR command in quad-SPI mode . . . . .313
Figure 55.NCS when CKMODE = 0 (T = CLK period) . . . . .321
Figure 56.NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .321
Figure 57.NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . .322
Figure 58.NCS when CKMODE = 1 with an abort (T = CLK period) . . . . .322
Figure 59.Single ADC block diagram . . . . .337
Figure 60.Timing diagram . . . . .340
Figure 61.Analog watchdog's guarded area . . . . .340
Figure 62.Injected conversion latency . . . . .342
Figure 63.Right alignment of 12-bit data . . . . .344
Figure 64.Left alignment of 12-bit data . . . . .344
Figure 65.Left alignment of 6-bit data . . . . .344
Figure 66.Temperature sensor and VREFINT channel block diagram . . . . .348
Figure 67.DAC channel block diagram . . . . .367
Figure 68.Data registers in single DAC channel mode . . . . .369
Figure 69.Data registers in dual DAC channel mode . . . . .369
Figure 70.Timing diagram for conversion with trigger disabled TEN = 0 . . . . .370
Figure 71.DAC LFSR register calculation algorithm . . . . .372
Figure 72.DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .372
Figure 73.DAC triangle wave generation . . . . .373
Figure 74.DAC conversion (SW trigger enabled) with triangle wave generation . . . . .373
Figure 75.Single DFSDM block diagram . . . . .391
Figure 76.Input channel pins redirection . . . . .395
Figure 77.Channel transceiver timing diagrams . . . . .397
Figure 78.Clock absence timing diagram for SPI . . . . .398
Figure 79.Clock absence timing diagram for Manchester coding . . . . .399
Figure 80.First conversion for Manchester coding (Manchester synchronization) . . . . .401
Figure 81.Multi-channel delay block for pulse skipping . . . . .404
Figure 82.Pulses skipper operation . . . . .405
Figure 83.DFSDM_CHyDATINR registers operation modes and assignment . . . . .409
Figure 84.Example: Sinc3 filter response . . . . .410
Figure 85.RNG block diagram . . . . .451
Figure 86.Entropy source model . . . . .452
Figure 87.Advanced-control timer block diagram . . . . .462
Figure 88.Counter timing diagram with prescaler division change from 1 to 2 . . . . .464
Figure 89.Counter timing diagram with prescaler division change from 1 to 4 . . . . .464
Figure 90.Counter timing diagram, internal clock divided by 1 . . . . .465
Figure 91.Counter timing diagram, internal clock divided by 2 . . . . .466
Figure 92.Counter timing diagram, internal clock divided by 4 . . . . .466
Figure 93.Counter timing diagram, internal clock divided by N . . . . .466
Figure 94.Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded) . . . . .		467
Figure 95.Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded) . . . . .		467
Figure 96.Counter timing diagram, internal clock divided by 1 . . . . .469
Figure 97.Counter timing diagram, internal clock divided by 2 . . . . .469
Figure 98.Counter timing diagram, internal clock divided by 4 . . . . .470
Figure 99.Counter timing diagram, internal clock divided by N . . . . .470
Figure 100.Counter timing diagram, update event when repetition counter is not used . . . . .471
Figure 101.Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .472
Figure 102.Counter timing diagram, internal clock divided by 2 . . . . .472
Figure 103.Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .473
Figure 104.Counter timing diagram, internal clock divided by N . . . . .473
Figure 105.Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .474
Figure 106.Counter timing diagram, update event with ARPE=1 (counter overflow) . . . . .474
Figure 107.Update rate examples depending on mode and TIMx_RCR register settings . . . . .476
Figure 108.Control circuit in normal mode, internal clock divided by 1 . . . . .477
Figure 109.TI2 external clock connection example . . . . .478
Figure 110.Control circuit in external clock mode 1 . . . . .479
Figure 111.External trigger input block . . . . .479
Figure 112.Control circuit in external clock mode 2 . . . . .480
Figure 113.Capture/compare channel (example: channel 1 input stage) . . . . .481
Figure 114.Capture/compare channel 1 main circuit . . . . .481
Figure 115.Output stage of capture/compare channel (channels 1 to 3) . . . . .482
Figure 116.Output stage of capture/compare channel (channel 4) . . . . .482
Figure 117.PWM input mode timing . . . . .484
Figure 118.Output compare mode, toggle on OC1 . . . . .486
Figure 119.Edge-aligned PWM waveforms (ARR=8) . . . . .487
Figure 120.Center-aligned PWM waveforms (ARR=8) . . . . .488
Figure 121.Complementary output with dead-time insertion . . . . .490
Figure 122.Dead-time waveforms with delay greater than the negative pulse . . . . .490
Figure 123.Dead-time waveforms with delay greater than the positive pulse . . . . .490
Figure 124.Output behavior in response to a break . . . . .493
Figure 125.Clearing TIMx_OCxREF . . . . .494
Figure 126.6-step generation, COM example (OSSR=1) . . . . .495
Figure 127.Example of one pulse mode . . . . .496
Figure 128.Example of counter operation in encoder interface mode . . . . .499
Figure 129.Example of encoder interface mode with TI1FP1 polarity inverted . . . . .499
Figure 130.Example of Hall sensor interface . . . . .501
Figure 131.Control circuit in reset mode . . . . .502
Figure 132.Control circuit in gated mode . . . . .503
Figure 133.Control circuit in trigger mode . . . . .504
Figure 134.Control circuit in external clock mode 2 + trigger mode . . . . .505
Figure 135.General-purpose timer block diagram . . . . .533
Figure 136.Counter timing diagram with prescaler division change from 1 to 2 . . . . .534
Figure 137.Counter timing diagram with prescaler division change from 1 to 4 . . . . .535
Figure 138.Counter timing diagram, internal clock divided by 1 . . . . .536
Figure 139.Counter timing diagram, internal clock divided by 2 . . . . .536
Figure 140.Counter timing diagram, internal clock divided by 4 . . . . .536
Figure 141.Counter timing diagram, internal clock divided by N . . . . .537
Figure 142.Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .537
Figure 143.Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) . . . . .538
Figure 144.Counter timing diagram, internal clock divided by 1 . . . . .539
Figure 145.Counter timing diagram, internal clock divided by 2 . . . . .539
Figure 146.Counter timing diagram, internal clock divided by 4 . . . . .539
Figure 147.Counter timing diagram, internal clock divided by N . . . . .540
Figure 148.Counter timing diagram, Update event . . . . .540
Figure 149.Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .541
Figure 150.Counter timing diagram, internal clock divided by 2 . . . . .542
Figure 151. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .542
Figure 152. Counter timing diagram, internal clock divided by N . . . . .542
Figure 153. Counter timing diagram, Update event with ARPE=1 (counter underflow) . . . . .543
Figure 154. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .543
Figure 155. Control circuit in normal mode, internal clock divided by 1 . . . . .544
Figure 156. TI2 external clock connection example . . . . .545
Figure 157. Control circuit in external clock mode 1 . . . . .546
Figure 158. External trigger input block . . . . .546
Figure 159. Control circuit in external clock mode 2 . . . . .547
Figure 160. Capture/compare channel (example: channel 1 input stage) . . . . .548
Figure 161. Capture/compare channel 1 main circuit . . . . .548
Figure 162. Output stage of capture/compare channel (channel 1) . . . . .549
Figure 163. PWM input mode timing . . . . .551
Figure 164. Output compare mode, toggle on OC1 . . . . .552
Figure 165. Edge-aligned PWM waveforms (ARR=8) . . . . .554
Figure 166. Center-aligned PWM waveforms (ARR=8) . . . . .555
Figure 167. Example of one-pulse mode . . . . .556
Figure 168. Clearing TIMx_OCxREF . . . . .558
Figure 169. Example of counter operation in encoder interface mode . . . . .559
Figure 170. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .560
Figure 171. Control circuit in reset mode . . . . .561
Figure 172. Control circuit in gated mode . . . . .562
Figure 173. Control circuit in trigger mode . . . . .562
Figure 174. Control circuit in external clock mode 2 + trigger mode . . . . .563
Figure 175. Master/Slave timer example . . . . .564
Figure 176. Gating timer 2 with OC1REF of timer 1 . . . . .565
Figure 177. Gating timer 2 with Enable of timer 1 . . . . .566
Figure 178. Triggering timer 2 with update of timer 1 . . . . .567
Figure 179. Triggering timer 2 with Enable of timer 1 . . . . .567
Figure 180. Triggering timer 1 and 2 with timer 1 TI1 input . . . . .569
Figure 181. General-purpose timer block diagram (TIM9 and TIM12) . . . . .594
Figure 182. General-purpose timer block diagram (TIM10/11/13/14) . . . . .595
Figure 183. Counter timing diagram with prescaler division change from 1 to 2 . . . . .597
Figure 184. Counter timing diagram with prescaler division change from 1 to 4 . . . . .597
Figure 185. Counter timing diagram, internal clock divided by 1 . . . . .598
Figure 186. Counter timing diagram, internal clock divided by 2 . . . . .599
Figure 187. Counter timing diagram, internal clock divided by 4 . . . . .599
Figure 188. Counter timing diagram, internal clock divided by N . . . . .599
Figure 189. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded) . . . . .		600
Figure 190. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded) . . . . .		600
Figure 191. Control circuit in normal mode, internal clock divided by 1 . . . . .601
Figure 192. TI2 external clock connection example . . . . .602
Figure 193. Control circuit in external clock mode 1 . . . . .602
Figure 194. Capture/compare channel (example: channel 1 input stage) . . . . .603
Figure 195. Capture/compare channel 1 main circuit . . . . .604
Figure 196. Output stage of capture/compare channel (channel 1) . . . . .604
Figure 197. PWM input mode timing . . . . .606
Figure 198. Output compare mode, toggle on OC1 . . . . .608
Figure 199. Edge-aligned PWM waveforms (ARR=8) . . . . .609
Figure 200. Example of One-pulse mode . . . . .610
Figure 201.Control circuit in reset mode . . . . .612
Figure 202.Control circuit in gated mode . . . . .613
Figure 203.Control circuit in trigger mode . . . . .613
Figure 204.Basic timer block diagram . . . . .640
Figure 205.Counter timing diagram with prescaler division change from 1 to 2 . . . . .642
Figure 206.Counter timing diagram with prescaler division change from 1 to 4 . . . . .642
Figure 207.Counter timing diagram, internal clock divided by 1 . . . . .643
Figure 208.Counter timing diagram, internal clock divided by 2 . . . . .644
Figure 209.Counter timing diagram, internal clock divided by 4 . . . . .644
Figure 210.Counter timing diagram, internal clock divided by N . . . . .645
Figure 211.Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .645
Figure 212.Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .646
Figure 213.Control circuit in normal mode, internal clock divided by 1 . . . . .647
Figure 214.Low-power timer block diagram . . . . .654
Figure 215.Glitch filter timing diagram . . . . .656
Figure 216.LPTIM output waveform, single counting mode configuration . . . . .658
Figure 217.LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set). . . . .658
Figure 218.LPTIM output waveform, Continuous counting mode configuration . . . . .659
Figure 219.Waveform generation . . . . .660
Figure 220.Encoder mode counting sequence . . . . .663
Figure 221.Independent watchdog block diagram . . . . .676
Figure 222.Watchdog block diagram . . . . .682
Figure 223.Window watchdog timing diagram . . . . .683
Figure 224.AES block diagram . . . . .689
Figure 225.ECB encryption and decryption principle . . . . .691
Figure 226.CBC encryption and decryption principle . . . . .692
Figure 227.CTR encryption and decryption principle . . . . .693
Figure 228.GCM encryption and authentication principle . . . . .694
Figure 229.GMAC authentication principle . . . . .694
Figure 230.CCM encryption and authentication principle . . . . .695
Figure 231.STM32 cryptolib AES flowchart examples . . . . .696
Figure 232.STM32 cryptolib AES flowchart examples (continued). . . . .697
Figure 233.Encryption key derivation for ECB/CBC decryption (Mode 2). . . . .700
Figure 234.Example of suspend mode management . . . . .701
Figure 235.ECB encryption . . . . .702
Figure 236.ECB decryption . . . . .702
Figure 237.CBC encryption . . . . .703
Figure 238.CBC decryption . . . . .703
Figure 239.ECB/CBC encryption (Mode 1). . . . .704
Figure 240.ECB/CBC decryption (Mode 3). . . . .705
Figure 241.Message construction in CTR mode. . . . .707
Figure 242.CTR encryption . . . . .708
Figure 243.CTR decryption . . . . .708
Figure 244.Message construction in GCM . . . . .710
Figure 245.GCM authenticated encryption . . . . .711
Figure 246.Message construction in GMAC mode . . . . .715
Figure 247.GMAC authentication mode . . . . .715
Figure 248.Message construction in CCM mode . . . . .716
Figure 249.CCM mode authenticated decryption . . . . .718
Figure 250.128-bit block construction with respect to data swap . . . . .722
Figure 251.DMA transfer of a 128-bit data block during input phase . . . . .724
Figure 252.DMA transfer of a 128-bit data block during output phase . . . . .725
Figure 253.AES interrupt signal generation . . . . .726
Figure 254.RTC block diagram . . . . .742
Figure 255.Block diagram . . . . .781
Figure 256.I 2 C-bus protocol . . . . .783
Figure 257.Setup and hold timings . . . . .784
Figure 258.FMPI2C initialization flow . . . . .787
Figure 259.Data reception . . . . .788
Figure 260.Data transmission . . . . .789
Figure 261.Slave initialization flow . . . . .792
Figure 262.Transfer sequence flow for FMPI2C slave transmitter, NOSTRETCH = 0 . . . . .794
Figure 263.Transfer sequence flow for FMPI2C slave transmitter, NOSTRETCH = 1 . . . . .795
Figure 264.Transfer bus diagrams for FMPI2C slave transmitter (mandatory events only) . . . . .796
Figure 265.Transfer sequence flow for FMPI2C slave receiver, NOSTRETCH = 0 . . . . .797
Figure 266.Transfer sequence flow for FMPI2C slave receiver, NOSTRETCH = 1 . . . . .798
Figure 267.Transfer bus diagrams for FMPI2C slave receiver
(mandatory events only) . . . . .		798
Figure 268.Master clock generation . . . . .800
Figure 269.Master initialization flow . . . . .802
Figure 270.10-bit address read access with HEAD10R = 0 . . . . .802
Figure 271.10-bit address read access with HEAD10R = 1 . . . . .803
Figure 272.Transfer sequence flow for FMPI2C master transmitter, N ≤ 255 bytes . . . . .804
Figure 273.Transfer sequence flow for FMPI2C master transmitter, N > 255 bytes . . . . .805
Figure 274.Transfer bus diagrams for FMPI2C master transmitter
(mandatory events only) . . . . .		806
Figure 275.Transfer sequence flow for FMPI2C master receiver, N ≤ 255 bytes . . . . .808
Figure 276.Transfer sequence flow for FMPI2C master receiver, N > 255 bytes . . . . .809
Figure 277.Transfer bus diagrams for FMPI2C master receiver
(mandatory events only) . . . . .		810
Figure 278.Timeout intervals for t LOW:SEXT , t LOW:MEXT . . . . .814
Figure 279.Transfer sequence flow for SMBus slave transmitter N bytes + PEC . . . . .817
Figure 280.Transfer bus diagram for SMBus slave transmitter (SBC = 1) . . . . .818
Figure 281.Transfer sequence flow for SMBus slave receiver N bytes + PEC . . . . .819
Figure 282.Bus transfer diagrams for SMBus slave receiver (SBC = 1) . . . . .820
Figure 283.Bus transfer diagrams for SMBus master transmitter . . . . .821
Figure 284.Bus transfer diagrams for SMBus master receiver . . . . .823
Figure 285.I2C bus protocol . . . . .844
Figure 286.I2C block diagram . . . . .845
Figure 287.Transfer sequence diagram for slave transmitter . . . . .847
Figure 288.Transfer sequence diagram for slave receiver . . . . .848
Figure 289.Transfer sequence diagram for master transmitter . . . . .851
Figure 290.Transfer sequence diagram for master receiver . . . . .852
Figure 291.I2C interrupt mapping diagram . . . . .861
Figure 292.USART block diagram . . . . .878
Figure 293.Word length programming . . . . .879
Figure 294.Configurable stop bits . . . . .881
Figure 295.TC/TXE behavior when transmitting . . . . .882
Figure 296.Start bit detection when oversampling by 16 or 8 . . . . .883
Figure 297.Data sampling when oversampling by 16 . . . . .886
Figure 298.Data sampling when oversampling by 8 . . . . .887
Figure 299. Mute mode using Idle line detection . . . . .899
Figure 300. Mute mode using address mark detection . . . . .899
Figure 301. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .902
Figure 302. Break detection in LIN mode vs. Framing error detection. . . . .903
Figure 303. USART example of synchronous transmission. . . . .904
Figure 304. USART data clock timing diagram (M=0) . . . . .904
Figure 305. USART data clock timing diagram (M=1) . . . . .905
Figure 306. RX data setup/hold time . . . . .905
Figure 307. ISO 7816-3 asynchronous protocol . . . . .906
Figure 308. Parity error detection using the 1.5 stop bits . . . . .907
Figure 309. IrDA SIR ENDEC- block diagram . . . . .909
Figure 310. IrDA data modulation (3/16) -Normal mode . . . . .909
Figure 311. Transmission using DMA . . . . .911
Figure 312. Reception using DMA . . . . .912
Figure 313. Hardware flow control between 2 USARTs . . . . .912
Figure 314. RTS flow control . . . . .913
Figure 315. CTS flow control . . . . .913
Figure 316. USART interrupt mapping diagram . . . . .915
Figure 317. SPI block diagram. . . . .929
Figure 318. Full-duplex single master/ single slave application. . . . .930
Figure 319. Half-duplex single master/ single slave application . . . . .931
Figure 320. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		932
Figure 321. Master and three independent slaves. . . . .933
Figure 322. Multimaster application. . . . .934
Figure 323. Hardware/software slave select management . . . . .935
Figure 324. Data clock timing diagram . . . . .937
Figure 325. TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0,
RXONLY=0) in the case of continuous transfers . . . . .		940
Figure 326. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0,
RXONLY=0) in the case of continuous transfers . . . . .		941
Figure 327. Transmission using DMA . . . . .943
Figure 328. Reception using DMA . . . . .944
Figure 329. TI mode transfer . . . . .947
Figure 330. I 2 S block diagram . . . . .950
Figure 331. I2S full-duplex block diagram . . . . .951
Figure 332. I 2 S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . .953
Figure 333. I 2 S Philips standard waveforms (24-bit frame with CPOL = 0). . . . .953
Figure 334. Transmitting 0x8EAA33 . . . . .953
Figure 335. Receiving 0x8EAA33 . . . . .954
Figure 336. I 2 S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . .954
Figure 337. Example of 16-bit data frame extended to 32-bit channel frame . . . . .954
Figure 338. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . .955
Figure 339. MSB justified 24-bit frame length with CPOL = 0 . . . . .955
Figure 340. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .955
Figure 341. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . .956
Figure 342. LSB justified 24-bit frame length with CPOL = 0 . . . . .956
Figure 343. Operations required to transmit 0x3478AE. . . . .956
Figure 344. Operations required to receive 0x3478AE . . . . .957
Figure 345. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .957
Figure 346. Example of 16-bit data frame extended to 32-bit channel frame . . . . .957
Figure 347. PCM standard waveforms (16-bit) . . . . .958
Figure 348. PCM standard waveforms (16-bit extended to 32-bit packet frame) . . . . .958
Figure 349. Audio sampling frequency definition . . . . .959
Figure 350. I 2 S clock generator architecture . . . . .959
Figure 351. Functional block diagram . . . . .980
Figure 352. Audio frame . . . . .982
Figure 353. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .985
Figure 354. FS role is start of frame (FSDEF = 0) . . . . .985
Figure 355. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .986
Figure 356. First bit offset . . . . .986
Figure 357. Audio block clock generator overview . . . . .987
Figure 358. AC'97 audio frame . . . . .991
Figure 359. Data companding hardware in an audio block in the SAI . . . . .993
Figure 360. Tristate strategy on SD output line on an inactive slot . . . . .995
Figure 361. Tristate on output data line in a protocol like I2S . . . . .996
Figure 362. Overrun detection error . . . . .997
Figure 363. FIFO underrun event . . . . .998
Figure 364. “No response” and “no data” operations . . . . .1018
Figure 365. (Multiple) block read operation . . . . .1018
Figure 366. (Multiple) block write operation . . . . .1018
Figure 367. Sequential read operation . . . . .1019
Figure 368. Sequential write operation . . . . .1019
Figure 369. SDIO block diagram . . . . .1019
Figure 370. SDIO adapter . . . . .1021
Figure 371. Control unit . . . . .1022
Figure 372. SDIO_CK clock dephasing (BYPASS = 0) . . . . .1022
Figure 373. SDIO adapter command path . . . . .1023
Figure 374. Command path state machine (SDIO) . . . . .1024
Figure 375. SDIO command transfer . . . . .1025
Figure 376. Data path . . . . .1027
Figure 377. Data path state machine (DPSM) . . . . .1028
Figure 378. CAN network topology . . . . .1077
Figure 379. Dual-CAN block diagram . . . . .1079
Figure 380. Single-CAN block diagram . . . . .1080
Figure 381. bxCAN operating modes . . . . .1082
Figure 382. bxCAN in silent mode . . . . .1083
Figure 383. bxCAN in Loop back mode . . . . .1083
Figure 384. bxCAN in combined mode . . . . .1084
Figure 385. Transmit mailbox states . . . . .1085
Figure 386. Receive FIFO states . . . . .1086
Figure 387. Filter bank scale configuration - Register organization . . . . .1089
Figure 388. Example of filter numbering . . . . .1090
Figure 389. Filtering mechanism example . . . . .1091
Figure 390. CAN error state diagram . . . . .1092
Figure 391. Bit timing . . . . .1094
Figure 392. CAN frames . . . . .1095
Figure 393. Event flags and interrupt generation . . . . .1096
Figure 394. CAN mailbox registers . . . . .1108
Figure 395. OTG_FS full-speed block diagram . . . . .1125
Figure 396. OTG_FS A-B device connection . . . . .1127
Figure 397. OTG_FS peripheral-only connection . . . . .1129
Figure 398. OTG_FS host-only connection . . . . .1133
Figure 399. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .1137
Figure 400. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .1139
Figure 401. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .1140
Figure 402. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . .1141
Figure 403. Interrupt hierarchy. . . . .1145
Figure 404. Transmit FIFO write task . . . . .1228
Figure 405. Receive FIFO read task . . . . .1229
Figure 406. Normal bulk/control OUT/SETUP . . . . .1230
Figure 407. Bulk/control IN transactions . . . . .1234
Figure 408. Normal interrupt OUT . . . . .1237
Figure 409. Normal interrupt IN . . . . .1242
Figure 410. Isochronous OUT transactions . . . . .1244
Figure 411. Isochronous IN transactions . . . . .1247
Figure 412. Receive FIFO packet read . . . . .1251
Figure 413. Processing a SETUP packet . . . . .1253
Figure 414. Bulk OUT transaction . . . . .1260
Figure 415. TRDT max timing case . . . . .1270
Figure 416. A-device SRP . . . . .1271
Figure 417. B-device SRP . . . . .1272
Figure 418. A-device HNP . . . . .1273
Figure 419. B-device HNP . . . . .1275
Figure 420. Block diagram of STM32 MCU and Cortex ® -M4 with FPU-level
debug support. . . . .		1277
Figure 421. SWJ debug port . . . . .1279
Figure 422. JTAG TAP connections . . . . .1283
Figure 423. TPIU block diagram . . . . .1301

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