47. Revision history

Updated RTC section:

• – Added case of RTC clocked by LSE in Section 32.3.9: Resetting the RTC .

Updated LDC-TFT section:

• – Updated Section 40: LCD-TFT display controller (LTDC) .
• – Updated Section 40.7.15: LTDC layer x window horizontal position configuration register (LTDC_LxWHPCR) removing “all values within this range are allowed” and updating the WHSPPPOS[11:0] and WHSTPOS[11:0] bit description.
• – Updated Section 40.7.15: LTDC layer x window horizontal position configuration register (LTDC_LxWHPCR) removing “all values within this range are allowed” and updating the WVSPPOS[10:0] and WVSTPOS[10:0] bit description.
• – Updated Table 127: LTDC pins and signal interface modifying ‘Data Enable’ by ‘Not Data Enable’.

Updated HASH section:

• – Updated Figure 189: Message data swapping feature .

Updated FMC section:

• – Updated Section : SRAM/NOR-flash chip-select timing register for bank x (FMC_BTRx) busturn bit description.
• – Updated Figure 47: Muxed write access waveforms NWE signal negative edge.
• – Updated Figure 53: NAND flash controller waveforms for common memory access replacing ‘MEMxHIZ’ by ‘MEMxHIZ+1’.
• – Updated Section : Common memory space timing register (FMC_PMEM) MEMHOLD[7:0] and Section : Attribute memory space timing register (FMC_PATT) ATTHOLD[7:0] replacing 257 HCLK by 256 HCLK.
• – Updated Section : SDRAM control register x (FMC_SDCRx) adding RPIPE[1:0] description.

Updated DMA section:

• – Updated Section 8.5.5: DMA stream x configuration register (DMA_SxCR) bit 18 “DBM or reserved” by “DBM” and “rw or r” by “rw”.

Updated RCC section:

• – Updated Section 5.2.8: RTC/AWU clock adding “the RTC remains clocked and functional under system reset” when the RTC clock is LSE.

Updated TIMER section:

• – Updated Section 28.4.7: TIMx prescaler (TIMx_PSC)(x = 6 to 7) PSC[15:0] bits description.
• – Updated Section 27.4.10: TIMx prescaler (TIMx_PSC)(x = 9, 12) PSC[15:0] bits description.
• – Updated Section 25.4.28: TIM1 register map and Section 25.4.29: TIM8 register map CC5IF and CC6IF bit names.
• – Updated Section 27.5.1: TIMx control register 1 (TIMx_CR1)(x = 10, 11, 13, 14) adding OPM bit-field.
• – Updated Section 27.5.13: TIM10/TIM11/TIM13/TIM14 register map adding OPM bit.
• – Updated Section 29: Low-power timer (LPTIM) changing register name LPTIMx_regrname in LPTIM_regrname.

Updated I2C2 section:

• – Updated Section 48.4.5: I2C initialization, Section 33.4.9: I2C master mode and Section 33.7.5: Timing register (I2C_TIMINGR).

Updated system configuration:

• – Updated Section 2.1.12: LCD-TFT controller DMA bus description.

Updated DFSDM section:

• – Updated DFSDM whole section.
• – Updated channel register name adding “z” index and filter register names adding “zFLT”.

Changed DFSDM into DFSDM1:

• – Updated Table 1: STM32F76xxx and STM32F77xxx register boundary addresses.
• – Updated Table 16: Features over all modes in Section 4: Power controller (PWR).
• – Updated Section 5.2: Clocks in Section 5: Reset and clock control (RCC).
• – Updated RCC registers in Section 5: Reset and clock control (RCC).
• – Updated Section 8: Direct memory access controller (DMA) Table 28: DMA2 request mapping
• – Updated Table 46: STM32F76xxx and STM32F77xxx vector table in Section 10: Nested vectored interrupt controller (NVIC).
• – Updated Section 17.8: DFSDM filter x module registers (x=0..3) address offset for all DFSDM_FLTx. registers replacing 0x100 * (x+1) by 0x100 + 0x80 * x.
• – Updated Section 17.8.16: DFSDM register map with correct offset calculation.

• – Updated Section 34: Universal synchronous/asynchronous receiver transmitter (USART/UART) changing register name USARTx_regname in USART_regname.

• – Updated Section 4.1.6: Voltage regulator removing low voltage mode.
• – Updated Section : Exiting low-power mode removing low voltage.

• – Updated Section 3.3.7: Flash erase sequences adding note about the FLASH_CR register.
• – Updated Section : Read from bank 1 while erasing bank 2 adding the same note.
• – Updated Section 3.3.8: Flash programming sequences adding a note in Section : Standard programming .
• – Updated Section : Read from bank 1 while programming bank 2 adding the same note.
• – Updated Section : Modifying user option bytes adding a note about the FLASH_OPTCR register.

• – Updated Section 7.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP) SWP_FB bit 8 adding a note.

Updated RCC section:

Updated Section 5.3.25: RCC dedicated clocks configuration register (RCC_DCKCFGR1) DFSDM in DFSDM1.

Update Section 5.3.21: RCC clock control & status register (RCC_CSR) bit RMVF put in read/write.

Updated Figure 13: Clock tree OTG_HS_SCL renamed by OTG_HS_ULPI_CK and the SYSCLK, Cortex core and HCLK clocks advertised as 216 MHz max.

Updated Section 5.3.2: RCC PLL configuration register (RCC_PLLCFGR) PLLP[1:0] bit description replacing by 'exceed 216 MHz on this domain'.

Updated Section 5.3.27: RCC register map PADRSTF in PINRSTF.

Updated Section 5.3.20: RCC backup domain control register (RCC_BDCR) adding LSEDRV[1:0] in the description.

Updated Section 5.3.14: RCC APB2 peripheral clock enable register (RCC_APB2ENR) : ADC1EN, ADC2EN and ADC2EN are enabled when bit set to '1'.

Updated Section 5.3.3: RCC clock configuration register (RCC_CFGR) caution in the PPRE1 and PPRE2 description.

Updated PWR section:

Updated Section 4.1.5: Battery backup domain note removing 'only one I/O at a time can be used as an output' sentence.

Updated Section 4.4.2: PWR power control/status register (PWR_CSR1) bits[19:18] UDRDY[1:0] description.

Updated LTDC section:

Updated Section 40: LCD-TFT display controller (LTDC) which must apply to the whole STM32F756xx and STM32F77xxx devices.

Updated SYSCFG section:

Updated Section 7.2.6: SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) adding '1000: PI[x] pin' line.

Updated Flash memory section:

Updated Section 3.4.1: Option bytes description:

• – Boot address option bytes when Boot pin =0: BOOT_ADDR0 = 0x8004 boot from SRAM1 is 0x2002000.
• – Boot address option bytes when Boot pin =1: BOOT_ADDR1 = 0x8004 boot from SRAM1 is 0x2002000.

Updated Section 3.7.7: Flash option control register (FLASH_OPTCR1) :

• – BOOT_ADDR0 = 0x8004 boot from SRAM1 is 0x2002000.
• – BOOT_ADDR1 = 0x8004 boot from SRAM1 is 0x2002000.

Updated Section 3.7.6: Flash option control register (FLASH_OPTCR) reset value at '0xFFFFFAFD'.

Updated Section 3.7.7: Flash option control register (FLASH_OPTCR1) and Section 3.7.8: Flash interface register map reset value at '0x0040 0080'.

Updated CRYPT section:
Updated Section 23: Cryptographic processor (CRYP) which must apply to the whole STM32F77xxx devices.

Updated HASH section:
Updated Section 24: Hash processor (HASH) which must apply to the whole STM32F77xxx devices.

Updated QUAD-SPI section:
Updated Section 14.3.5: QUADSPI indirect mode 'FIFO and data management' last paragraph for a 32-byte FIFO.

Updated I2C2 section:
Updated Section 48.4.10: I2C_TIMINGR register configuration examples .

Updated general-purpose timer section:
Updated Section : SDRAM control register x (FMC_SDCRx)
Bits [1:0] '01' description for SPDIFRX_FRAME_SYNC'.

Updated DFSDM section:
Updated JEXTSEL bit description in Section 17.8.1: DFSDM filter x control register 1 (DFSDM_FLTxCR1) .

Updated FMC section:
Updated Section : SDRAM control register x (FMC_SDCRx) replacing 'KCK_FMC' by 'HCLK' in RPIPE[1:0] description.

Updated USB section:
Updated Section 41.15.41: OTG all endpoints interrupt mask register (OTG_DAINTEMSK) replacing bit 18 by bit 19 in OEPM bit description.

Updated RTC section:
Updated Figure 344: RTC block diagram WUCKSEL dividers for /2,4,8,16.

Updated ETHERNET section:
Updated Section : Ethernet MAC MII address register (ETH_MACMIIAR) bits[4:2] clock range of setting 100 is valid for 150-216 MHz.

Updated USART section:
Updated USART configuration version 1.3.

Documentation conventions section:
Added Section 1.1: General information with Arm logo

USB section:

• – Complete re-mastering of the section
• – Added Section 41.4.2: OTG_FS/OTG_HS pin and internal signals .
• – Updated Section 41.15.16: OTG core ID register (OTG_CID) .
• – Updated Section 41.15.41: OTG all endpoints interrupt mask register (OTG_DAINTRMSK) replacing bit 18 by bit 19 in OEPM bit description.

Memory organization section
Added Figure 2: Memory map .

PWR section:
Updated Section 4.1.5: Battery backup domain note removing 'only one I/O at a time can be used as an output' sentence.
Updated Section 4.1.5: Battery backup domain step 3 of 'Access to the backup SRAM' paragraph.
Updated Section 4.4.2: PWR power control/status register (PWR_CSR1) bits[19:18] UDRDY[1:0] description.

SDMMC section:
Updated Section 39.8.8: SDMMC data length register (SDMMC_DLEN) note.

RTC section:
Updated Section 32.6.3: RTC control register (RTC_CR) WUTE bit description adding note.

I2C2 section:
Updated Figure 347: Setup and hold timings .

DSI Host (DSI) section:
Updated Section 20: DSI Host (DSI) .

DEBUG section:
Updated Section 44.6.1: MCU device ID code REV_ID[15:0] bit description adding revZ.

RCC section:
Updated Figure 13: Clock tree note 2 replacing by 'RCC_DCKCFGR1' register.
Updated Section 5.3.25: RCC dedicated clocks configuration register (RCC_DCKCFGR1) replacing in the section title by 'RCC_DCKCFGR1' register.
Updated Section 5.3.26: RCC dedicated clocks configuration register (RCC_DCKCFGR2) replacing register name by RCC_DCKCFGR2.

Small text updates in the document.
Updated:

• – Section 3.3.5: Maximum program/erase parallelism
• – Memory address for flash sector 10 in Table 4: 2 Mbytes of flash memory dual bank organization (128 bits read width)
• – Sector Erase
• – PTP clock source in Figure 13: Clock tree
• – External source (LSE bypass)
• – Section 3.5.1: Read protection (RDP)
• – BRE bit description in Section 3.7.5: Flash control register (FLASH_CR)
• – BOOT_ADDx range address in Section 3.7.7: Flash option control register (FLASH_OPTCR1)
• – Bit WWDGEN description in Section 5.3.13: RCC APB1 peripheral clock enable register (RCC_APB1ENR)
• – Section 5.3.25: RCC dedicated clocks configuration register (RCC_DCKCFGR1)
• – Section 32: Real-time clock (RTC)
• – Section 34: Universal synchronous/asynchronous receiver transmitter (USART/UART)
• – Added new revision 1 for REV_ID[15:0]
• – Base address for package data register in Section 45: Device electronic signature
• – Base address in Section 45.3: Package data register