7. System configuration controller (SYSCFG)

The system configuration controller is mainly used to:

• • Remap the memory areas
• • Select the Ethernet PHY interface
• • Manage the external interrupt line connection to the GPIOs.

7.1 I/O compensation cell

By default the I/O compensation cell is not used. However when the I/O output buffer speed is configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell for slew rate control on I/O \( t_{f(IO)out}/t_{r(IO)out} \) commutation to reduce the I/O noise on power supply.

When the compensation cell is enabled, a READY flag is set to indicate that the compensation cell is ready and can be used. The I/O compensation cell can be used only when the supply voltage ranges from 2.4 to 3.6 V.

7.2 SYSCFG registers

7.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)

This register is used for specific configurations on memory mapping:

• • 1bit is used to indicate which option bytes BOOT_ADD0 or BOOT_ADD1 defines the boot memory base address.
• • Other bits are used to swap FMC SDRAM Banks with FMC NOR/PSRAM bank

Address offset: 0x00

Reset value: 0x0000 0000

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:10 SWP_FMC[1:0] : FMC memory mapping swap

Set and cleared by software. These bits are used to swap the FMC SDRAM banks and FMC NOR/PSRAM in order to enable the code execution from SDRAM Banks without modifying the default MPU attribute

00: No FMC memory mapping swapping

SDRAM bank1 and Bank2 are mapped at 0xC000 0000 and 0xD000 0000 respectively (default mapping)

NOR/RAM is accessible @ 0x60000000 (default mapping)

01: NOR/RAM and SDRAM memory mapping swapped,

SDRAM bank1 and bank2 are mapped at 0x6000 0000 and 0x7000 0000, respectively

NOR/PSRAM bank is mapped at 0xC000 0000

10: Reserved

11: Reserved

Bit 9 Reserved, must be kept at reset value.

Bit 8 SWP_FB : Flash Bank swap

Set and Clear by software. This bit controls the Flash Bank 1 & Flash Bank 2 mapping.

0: Default Flash Bank mapping

- Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)

- Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)

1: Flash Bank swapped

- Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)

- Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)

Note: It is not recommended to write the SWP_FB bit while executing from Flash as it will result in a Flash content addresses swapping. It can be written from routines executing from ITCM RAM for example.

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 MEM_BOOT : Memory boot mapping

This bit indicates which option bytes BOOT_ADD0 or BOOT_ADD1 defines the boot memory base address.

0: Boot memory base address is defined by BOOT_ADD0 option byte (Factory Reset value: TCM-FLASH mapped at 0x00200000).

1: Boot memory base address is defined by BOOT_ADD1 option byte (Factory Reset value: System memory mapped at 0x001 0000).

Note: Refer to section 2.3: Memory map for details about the boot memory base address selection.

7.2.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 MII_RMII_SEL : Ethernet PHY interface selection

Set and Cleared by software. These bits control the PHY interface for the Ethernet MAC.

0: MII interface is selected

1: RMII PHY interface is selected

Note: This configuration must be done while the MAC is under reset and before enabling the MAC clocks.

Bits 22:19 Reserved, must be kept at reset value.

Bits 18:16 ADCxDC2 :

0: No effect.

1: Refer to AN4073 on how to use this bit.

Note: These bits can be set only if the following conditions are met:

- ADC clock higher or equal to 30 MHz.

- Only one ADCxDC2 bit must be selected if ADC conversions do not start at the same time and the sampling times differ.

- These bits must not be set when the ADCDC1 bit is set in PWR_CR register.

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 PB9_FMP : Fast Mode + Enable

Set and cleared by software.

0: Default value.

1: It forces FM+ drive capability on PB9 pin

Bit 6 PB8_FMP : PB8_FMP Fast Mode + Enable

Set and cleared by software.

0: Default value.

1: It forces FM+ drive capability on PB8 pin

Bit 5 PB7_FMP : PB7_FMP Fast Mode + Enable

Set and cleared by software.

0: Default value.

1: It forces FM+ drive capability on PB7 pin

Bit 4 PB6_FMP : PB6_FMP Fast Mode + Enable

Set and cleared by software.

0: Default value.

1: It forces PB6 IO pads in Fast Mode +.

Bit 3 I2C4_FMP : I2C4_FMP I2C4 Fast Mode + Enable

Set and cleared by software.

0: Default value.

1: It forces FM+ drive capability on I2C4 SCL & SDA pin selected through GPIO port mode register and GPIO alternate function selection bits

Bit 2 I2C3_FMP : I2C3_FMP I2C3 Fast Mode + Enable

Set and cleared by software.

0: Default value.

1: It forces FM+ drive capability on I2C3 SCL & SDA pin selected through GPIO port mode register and GPIO alternate function selection bits

Bit 1 I2C2_FMP : I2C2_FMP I2C2 Fast Mode + Enable

Set and cleared by software.

0: Default value.

1: It forces FM+ drive capability on I2C2 SCL & SDA pin selected through GPIO port mode register and GPIO alternate function selection bits

Bit 0 I2C1_FMP : I2C1_FMP I2C1 Fast Mode + Enable

Set and cleared by software.

0: Default value.

1: It forces FM+ drive capability on I2C1 SCL & SDA pin selected through GPIO port mode register and GPIO alternate function selection bits

7.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)

Address offset: 0x08

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 0 to 3)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PF[x] pin

0110: PG[x] pin

0111: PH[x] pin

1000: PI[x] pin

1001: PJ[x] pin

1010: PK[x] pin

7.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 4 to 7)

These bits are written by software to select the source input for the EXTIx external interrupt.

• 0000: PA[x] pin
• 0001: PB[x] pin
• 0010: PC[x] pin
• 0011: PD[x] pin
• 0100: PE[x] pin
• 0101: PF[x] pin
• 0110: PG[x] pin
• 0111: PH[x] pin
• 1000: PI[x] pin
• 1001: PJ[x] pin
• 1010: PK[x] pin

7.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)

Address offset: 0x10

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 8 to 11)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
1000: PI[x] pin
1001: PJ[x] pin
1010: PK[x] pin

Note: PK[11:8] are not used

7.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)

Address offset: 0x14

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 12 to 15)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
1000: PI[x] pin
1001: PJ[x] pin
1010: PK[x] pin

Note: PK[15:12] are not used

7.2.7 Class B register (SYSCFG_CBR)

Address offset: 0x1C

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 PVDL: PVD Lock

Set by software, cleared by system reset only.

This bit enables and locks the PVD connection with TIMER1, TIMER8 Break input. It also locks (write protect) the PVD_EN and PVDSEL[2:0] bits of the power controller.

0: PVD interrupt is not connected to Break input of TIMER1/8; PVDE and PLS[2:0] bits in PWR_CR1 register are RW.

1: PVD interrupt is connected to Break input of TIMER1/8; PVDE and PLS[2:0] bits in PWR_CR1 register are read only.

Bit 1 Reserved, must be kept at reset value.

Bit 0 CLL: Core Lockup Lock

Set by software, cleared by system reset only.

Where a fault or supervisor call occurs at a priority of -1 or above the Cortex-M7 enters lockup state. This bit enables and locks the Lockup output (raised during core lockup state) of Cortex-M7 with Break Input of TIMER1, TIMER8.

0: Lockup output of Cortex-M7 is not connected with Break input of TIMER1/8

1: Lockup output of Cortex-M7 is connected with Break input of TIMER1/8

7.2.8 Compensation cell control register (SYSCFG_CMPCR)

Address offset: 0x20

Reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 READY : Compensation cell ready flag

0: I/O compensation cell not ready

1: I/O compensation cell ready

Bits 7:2 Reserved, must be kept at reset value.

Bit 0 CMP_PD : Compensation cell power-down

0: I/O compensation cell power-down mode

1: I/O compensation cell enabled

7.2.9 SYSCFG register map

The following table gives the SYSCFG register map and the reset values.

Table 26. SYSCFG register map and reset values

Refer to Section 2.2 on page 76 for the register boundary addresses.