3. Embedded flash memory (FLASH)

3.1 Introduction

The flash memory interface manages Cortex ^® -M7 AXI and TCM accesses to the flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms.

The flash memory interface accelerates code execution with a system of instruction prefetch and cache lines on ITCM interface (ART Accelerator ^™ ).

3.2 Flash main features

• • Flash memory read operations with two data width modes supported:
  • – Single bank mode nDBANK=1: read access of 256 bits
  • – Dual bank mode nDBANK=0: read access of 128 bits
• • Flash memory program/erase operations
• • Read / write protections
• • Read While Write (RWW) (only possible in dual bank mode nDBANK=0)
• • Dual Boot mode (only possible in dual bank mode nDBANK=0)
• • ART Accelerator ^™ : 64 cache lines of 128/256 bits on ITCM interface (depending on read access width)
• • Prefetch on TCM instruction code

Figure 3 shows the flash memory interface connection inside the system architecture.

Figure 3. Flash memory interface connection inside system architecture (STM32F76xxx and STM32F77xxx)

3.3 Flash functional description

3.3.1 Flash memory organization

The flash memory has the following main features:

• • Capacity up to 2 Mbytes, in single bank mode (read width 256 bits) or in dual bank mode (read width 128 bits)
• • Supports dual boot mode thanks to nDBOOT option bit (only in dual bank mode nDBANK=0)
• • 256 bits wide data read in single bank mode or 128 bits wide data read in dual bank configuration
• • Byte, half-word, word and double word write
• • Sector, mass erase and bank mass erase (only in dual bank mode)

The flash memory is organized as follows:

• • Main memory organization depends on dual bank configuration bit:
  • – When the dual bank mode is disabled (nDBANK bit is set), the main memory block is divided into 4 sectors of 32 Kbytes, 1 Sector of 128 Kbytes, and 7 sectors of 256 Kbytes
  • – In dual bank mode (nDBANK bit is reset), the main memory is divided into two banks of 1 Mbyte. Each 1 Mbyte bank is composed of 4 sectors of 16 Kbytes, 1 Sector of 64 Kbytes and 7 sectors of 128 Kbytes
    • - If nDBANK=1, Size of main memory block: 4 sectors of 32 KBytes, 1 sector of 128 KBytes, 7 sectors of 256 KBytes (reference to memory organization)
    • - If nDBANK=0, Each 1MB banks is composed of: 4 sectors of 16 KBytes, 1 sector of 64 KBytes, 7 sectors of 128 KBytes (reference to memory organization)
• • Dual bank organization on 1 Mbyte devices

The dual bank feature on 1 Mbyte devices is available. it is enabled by setting the nDBANK option bit to 0.

To obtain a dual bank flash memory, the last 512 Kbytes of the single bank (sectors [8:11]) are re-structured in the same way as the first 512 Kbytes.

The sector numbering of dual bank memory organization is different from the single bank: the single bank memory contains 12 sectors whereas the dual bank memory contains 16 sectors (see Table 6 ).

For erase operation, the right sector numbering must be considered according to nDBANK option bit.

• – When the nDBANK bit is set (single bank mode), the erase operation must be performed on the default sector number.
• – When the nDBANK bit is reset, to perform an erase operation on bank 2, the sector number must be programmed (sector number from 12 to 19). Refer to FLASH_CR register for SNB (Sector number) configuration.

Refer to Table 5: 1 Mbyte flash memory single bank organization (256 bits read width) and Table 6: 1 Mbyte flash memory dual bank organization (128 bits read width)

width ) for details on 1 Mbyte single bank and 1 Mbyte dual bank organizations.

• • Information blocks containing:
  • – System memory from which the device boots in System memory boot mode
  • – 1024 OTP (one-time programmable) for user data
  • – The OTP area contains 16 additional bytes used to lock the corresponding OTP data block.
  • – Option bytes to configure read and write protection, BOR level, watchdog, boot memory base address, software/hardware and reset when the device is in Standby or Stop mode.

On 1 Mbyte devices the main memory block is divided into 4 sectors of 32 Kbytes, 1 sector of 128 Kbytes, and 3 sectors of 256 Kbytes. The dual bank feature is also available.

To obtain a dual bank flash memory, the main memory block is re-structured in the a way that the first and last 512 Kbytes of each bank has the same structure.

The sector numbering of dual bank memory organization is different from the single bank: the single bank memory contains 8 continuous sector numbers whereas the dual bank memory contains 16 sectors with discontinuity on sector numbering for each 512 Kbytes (see Table 5: 1 Mbyte flash memory single bank organization (256 bits read width) ).

For erase operation, the right sector numbering must be considered according to the dual bank nDBANK option bit.

• • When the nDBANK bit is set (single bank configuration), the erase operation must be performed on the default sector number.
• • When the nDBANK bit is reset (dual bank configuration), to perform an erase operation on bank 2, the sector number must be programmed (sector number from 12 to 19). Refer to FLASH_CR register for SNB (Sector number) configuration.

The embedded Flash has three main interfaces:

• • 64-bits ITCM interface:
  • – It is connected to the ITCM bus of Cortex-M7 and used for instruction execution and data read access.
  • – Write accesses are not supported on ITCM interface
  • – Supports a unified 64 cache lines (ART accelerator). The cache line size depends on nDBANK option bit, 256 bits width when in single bank configuration and 128 bits width in dual bank configuration
• • 64-bits AHB interface:
  • – It is connected to the AXI bus of Cortex-M7 through the AHB bus matrix and used for code execution, read and write accesses.
  • – DMAs and peripherals DMAs data transfer on Flash are done through the AHB interface whatever the addressed flash interface TCM or AHB.
• • 32-bits AHB register interface:
  • – It is used for control and status register accesses.

The main memory and information block organization is shown in the following tables:

Table 3. 2 Mbytes of flash memory single bank organization (256 bits read width)

Table 4. 2 Mbytes of flash memory dual bank organization (128 bits read width)

Table 4. 2 Mbytes of flash memory dual bank organization (128 bits read width) (continued)

Table 5. 1 Mbyte flash memory single bank organization (256 bits read width)

Table 6. 1 Mbyte flash memory dual bank organization (128 bits read width)

3.3.2 Read access latency

To correctly read data from flash memory, the number of wait states (LATENCY) must be correctly programmed in the Flash access control register (FLASH_ACR) according to the frequency of the CPU clock (HCLK) and the supply voltage of the device.

The correspondence between wait states and CPU clock frequency is given in Table 51 and Table 7 .

1. Note:
2. • - When VOS[1:0] = '0x01', the maximum value of \( f_{HCLK} \) is 144 MHz.
   • - When VOS[1:0] = '0x10', the maximum value of \( f_{HCLK} \) is 168 MHz. It can be extended to 180 MHz by activating the over-drive mode.
   • - When VOS[1:0] = '0x11', the maximum value of \( f_{HCLK} \) is 180 MHz. It can be extended to 216 MHz by activating the over-drive mode.
   • - The over-drive mode is not available when \( V_{DD} \) ranges from 1.8 to 2.1 V.
3. Refer to Section 10.1.4: Voltage regulator for details on how to activate the over-drive mode.

After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the FLASH_ACR register.

It is highly recommended to use the following software sequences to tune the number of wait states to access the flash memory with the CPU frequency.

Increasing the CPU frequency

1. 1. Program the new number of wait states to the LATENCY bits in the FLASH_ACR register
2. 2. Check that the new number of wait states is taken into account to access the flash memory by reading the FLASH_ACR register
3. 3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
4. 4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
5. 5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register.

Decreasing the CPU frequency

1. 1. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
2. 2. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
3. 3. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register
4. 4. Program the new number of wait states to the LATENCY bits in FLASH_ACR
5. 5. Check that the new number of wait states is used to access the flash memory by reading the FLASH_ACR register

Note: A change in CPU clock configuration or wait state (WS) configuration may not be effective straight away. To make sure that the current CPU clock frequency is the one you have

configured, you can check the AHB prescaler factor and clock source status values. To make sure that the number of WS you have programmed is effective, you can read the FLASH_ACR register.

Instruction prefetch

Depending on Flash dual bank mode configuration, each flash read operation provides:

In case of single bank mode (nDBANK option bit is set) 256 bits representing 8 instructions of 32 bits to 16 instructions of 16 bits according to the program launched. So, in case of sequential code, at least 8 CPU cycles are needed to execute the previous instruction line read.

When in dual bank mode (nDBANK option bit is reset) 128 bits representing 4 instructions of 32 bits to 8 instructions of 16 bits according to the program launched. So, in case of sequential code, at least 4 CPU cycles are needed to execute the previous instruction line read. The prefetch on ITCM bus allows to read the sequential next line of instructions in the flash while the current instruction line is requested by the CPU. The prefetch can be enabled by setting the PRFTEN bit of the FLASH_ACR register. This feature is useful if at least one Wait State is needed to access the flash. When the code is not sequential (branch), the instruction may not be present neither in the current instruction line used nor in the prefetched instruction line. In this case (miss), the penalty in term of number of cycles is at least equal to the number of Wait States.

Adaptive real-time memory accelerator (ART Accelerator™)

The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32 industry-standard Arm® Cortex®-M7 with FPU processors. It balances the inherent performance advantage of the Arm® Cortex®-M7 with FPU over flash memory technologies, which normally requires the processor to wait for the flash memory at higher operating frequencies.

To release the processor full performance, the accelerator implements a unified cache of an instruction and branch cache which increases program execution speed from the flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from flash memory at a CPU frequency up to 216 MHz.

The ART accelerator is available only for flash access on ITCM interface.

To limit the time lost due to jumps, it is possible to retain 64 lines of 256 bits (when in single bank mode configuration nDBANK=1 or 128 bits in dual bank configuration with nDBANK=0) in the ART accelerator. This feature can be enabled by setting the ARTEN bit of the FLASH_CR register. The ART Accelerator is unified, it contains instruction as well as data literal pools. Each time a miss occurs (requested data not present in the current data line used or in the instruction cache memory), the read line is copied in the instruction cache memory of ART. If a data contained in the instruction cache memory is requested by the CPU, the data is provided without inserting delay. Once all the cache memory lines are filled, the LRU (Least Recently Used) policy is used to determine the line to replace in the memory cache. This feature is particularly useful in case of code containing loops.

Note: Data in user configuration sector are not cacheable.

3.3.3 Flash program and erase operations

For any flash memory program operation (erase or program), the CPU clock frequency (HCLK) must be at least 1 MHz. The contents of the flash memory are not guaranteed if a device reset occurs during a flash memory operation.

Any attempt to read the flash memory while it is being written or erased, causes the bus to stall. Read operations are processed correctly once the program operation has completed. This means that code or data fetches cannot be performed while a write/erase operation is ongoing.

3.3.4 Unlocking the Flash control register

After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the flash memory against possible unwanted operations due, for example, to electric disturbances. The following sequence is used to unlock this register:

1. 1. Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR)
2. 2. Write KEY2 = 0xCDEF89AB in the Flash key register (FLASH_KEYR)

Any wrong sequence will return a bus error and lock up the FLASH_CR register until the next reset.

The FLASH_CR register can be locked again by software by setting the LOCK bit in the FLASH_CR register.

Note: The FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_SR register is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall until the BSY bit is cleared.

3.3.5 Maximum program/erase parallelism

The maximum parallelism size is configured through the PSIZE field in the FLASH_CR register. It represents the number of bytes to be programmed each time a write operation occurs to the flash memory. PSIZE is limited by the supply voltage and by whether the external V _PP supply is used or not. It must therefore be correctly configured in the FLASH_CR register before any programming/erasing operation.

A flash memory erase operation can only be performed by sector, bank or for the whole flash memory (mass erase). The erase time depends on PSIZE programmed value. For more details on the erase time, refer to the electrical characteristics section of the device datasheet.

Table 8 provides the correct PSIZE values.

Table 8. Maximum program/erase parallelism

Note: Any program or erase operation started with inconsistent program parallelism/voltage range settings may lead to unpredicted results. Even if a subsequent read operation indicates that the logical value was effectively written to the memory, this value may not be retained.

To use \( V_{PP} \) , an external high-voltage supply (between 8 and 9 V) must be applied to the \( V_{PP} \) pad. The external supply must be able to sustain this voltage range even if the DC consumption exceeds 10 mA. It is advised to limit the use of \( V_{PP} \) to initial programming on the factory line. The \( V_{PP} \) supply must not be applied for more than an hour, otherwise the flash memory might be damaged.

3.3.6 Switching from single bank to dual bank configuration

It is possible to use main Flash either in single bank mode (256 bits read width) or dual bank mode (128 bits read width) thanks to nDBANK option bit. However, it is highly recommended to use the following sequence when switching from a mode to an other.

Activating dual bank mode (switching from nDBANK=1 to nDBANK=0)

When switching from one Flash mode to another (single to dual Bank) it is recommended to execute code from SRAM or use bootloader. To avoid reading corrupted data from Flash when the memory organization is changed any access (CPU or DMAs) to flash memory should be avoided before reprogramming.

1. 1. Depending on execution path:

If ITCM path is used for code execution:

1. a) Disable ART accelerator and/or prefetch if they are enabled (for ART accelerator reset PRFTEN and ARTEN bits in FLASH_ACR register)
2. b) Flush ART accelerator if it was ON (set then reset ARTCRST bit in FLASH_ACR register)

If AXIM path is used for code execution Disable and Clean Cache (CPU internal caches clean and invalidation is needed).

1. 2. Change nDBANK option bit value from 0 to 1 and reset all write protection (refer to Section 3.4.2: Option bytes programming )

Note: The memory organization is changed and previously data in flash memory is corrupted.

1. 3. Program new application:
   1. a) Erase needed memory (Sectors, or Mass erase)
   2. b) Reprogram the flash memory
   3. c) If needed set write protection following write protection schema (refer to Section 3.5.2: Write protections )

-> the new software is ready to be run using bank configuration

De-activating dual bank mode (switching from nDBANK=0 to nDBANK=1)

When switching from one Flash mode to another (dual to single Bank) it is recommended to execute code from SRAM or use bootloader. To avoid reading corrupted data from Flash when memory organization is changed any access (CPU or DMAs) to flash memory should be avoided before reprogramming.

1. 1. Depending on execution path:

If ITCM path is used for code execution:

1. a) Disable ART accelerator and/or prefetch if they are enabled (for ART accelerator reset PRFTEN and ARTEN bits in FLASH_ACR register)
2. b) Flush ART accelerator if it was ON (set then reset ARTCRST bit in FLASH_ACR register)

If AXIM path is used for code execution Disable and Clean Cache (CPU internal caches clean and invalidation is needed)

1. 2. Change nDBANK option bit value from 0 to 1 and reset all write protection (refer to Section 3.4.2: Option bytes programming )

Note: The memory organization is changed and previously data in flash memory is corrupted.

1. 1. 3. Program new application:
      1. a) Erase needed memory (Sectors, or Mass erase)
      2. b) Reprogram the flash memory
      3. c) If needed set write protection following write protection schema (refer to Section 3.5.2: Write protections )
2. -> The new software is ready to be run using single bank configuration

3.3.7 Flash erase sequences

The flash memory erase operation can be performed at sector level, at bank level (bank mass erase when dual bank mode is enabled nDBANK=0) or on the whole flash memory (Mass Erase). Mass Erase does not affect the OTP sector or the configuration sector.

Sector Erase

To erase a sector, follow the procedure below:

1. 1. Check that no flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register
2. 2. Set the SER bit and select the sector number of the user memory block you wish to erase (SNB) in the FLASH_CR register
3. 3. Set the STRT bit in the FLASH_CR register
4. 4. Wait for the BSY bit to be cleared

Bank Mass Erase (available only in dual bank mode when nDBANK=0)

To perform mass erase on Bank 1 or Bank 2, the procedure below should be followed:

1. 1. Check that no flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register
2. 2. Set accordingly MER/MER1 OR MER2 bit in the FLASH_CR register
3. 3. Set the STRT bit in the FLASH_CR register
4. 4. Wait for the BSY bit to be reset
5. 5. Reset accordingly MER/MER1 OR MER2 bit in the FLASH_CR register

Mass Erase

To perform Mass Erase, the following sequence is recommended depending on nDBANK option bit:

• • When dual bank mode is active (nDBANK=0) :
  1. 1. Check that no flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register
  2. 2. Set the MER/MER1 AND MER2 bit in the FLASH_CR register
  3. 3. Set the STRT bit in the FLASH_CR register
  4. 4. Wait for the BSY bit to be reset
  5. 5. Reset the MER/MER1 AND MER2 bit in the FLASH_CR register


• • When single bank mode is active (nDBANK=1) :
  1. 1. Check that no flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register
  2. 2. Set the MER/MER1 bit in the FLASH_CR register
  3. 3. Set the STRT bit in the FLASH_CR register
  4. 4. Wait for the BSY bit to be cleared If MERx and SER bits are both set in the FLASH_CR register, mass erase is performed.

Note: If MERx and SER bits are both set in the FLASH_CR register, mass erase is performed. If both MERx and SER bits are reset and the STRT bit is set, an unpredictable behavior may occur without generating any error flag. This condition should be forbidden.

Note: When setting the STRT bit in the FLASH_CR register and before polling the BSY bit to be cleared, the software can issue a DSB instruction to guarantee the completion of a previous access to FLASH_CR register.

3.3.8 Flash programming sequences

Standard programming

The flash memory programming sequence is as follows:

1. 1. Check that no main flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register.
2. 2. Set the PG bit in the FLASH_CR register
3. 3. Perform the data write operation(s) to the desired memory address (inside main memory block or OTP area):
   • – Byte access in case of x8 parallelism
   • – Half-word access in case of x16 parallelism
   • – Word access in case of x32 parallelism
   • – Double word access in case of x64 parallelism
4. 4. Wait for the BSY bit to be cleared.

Note: Successive write operations are possible without the need of an erase operation when changing bits from '1' to '0'. Writing '1' requires a flash memory erase operation. If an erase and a program operation are requested simultaneously, the erase operation is performed first.

Note: After performing a data write operation and before polling the BSY bit to be cleared, the software can issue a DSB instruction to guarantee the completion of a previous data write operation.

Programming errors

In case of error, the Flash operation (programming or erasing) is aborted with one of the following errors:

• • PGAERR: Alignment Programming error
  It is not allowed to program data to the flash memory that would cross the 128-bit row boundary. In such a case, the write operation is not performed and the program alignment error flag (PGAERR) is set in the FLASH_SR register.
• • PGEPRR: Programming parallelism error
  The write access type (byte, half-word, word or double word) must correspond to the type of parallelism chosen (x8, x16, x32 or x64). If not, the write operation is not performed and the program parallelism error flag (PGPERR) is set in the FLASH_SR register.
• • ERSERR: Erase sequence error
  When an erase operation to the flash is performed by the code while the control register has not been correctly configured, the ERSERR error flag is set
• • WRPERR: Write Protection Error
  WRPERR is set if one of the following conditions occurs:
  • – Attempt to program or erase in a write protected area (WRP)
  • – Attempt to program or erase the system memory area.
  • – A write in the OTP area which is already locked
  • – Attempt to modify the option bytes when the read protection (RDP) is set to Level
  • – The flash memory is read protected and an intrusion is detected

If a part of code is programmed in the flash, the user must guarantee that this part of code has not been executed since the last reset. If this condition can not be filled safely, it is recommended to flush the Caches.

1. a) ART accelerator flush and/or deactivate is performed by setting respectively the bits ARTRST and/or ARTEN of the FLASH_ACR register.
2. b) Perform CPU Cache maintenance operations

If a flash program or erase operation hits one or several data section already loaded in the cache, it is the responsibility of the user to guarantee that these data will not be accessed during code execution. Therefore during these operations, it is recommended to flush and/or deactivate the Caches.

Note: Data coherency between caches and flash memory is the responsibility of the user code

Note: The ART cache can be flushed only if the ART accelerator is disabled (ARTEN = 0).

Read-while-write (RWW)

Thanks to the dual bank mode (active when nDBANK option bit is 0), the flash memory structure allows read-while-write operations. This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank.

Note: Write-while-write operations are not allowed. As an example, it is not possible to perform an erase or program operation on one bank while erasing or programming the other one, except mass erase which erases both banks at the same time

Read from bank 1 while erasing bank 2

While executing a program code from bank 1, it is possible to perform an erase operation on bank 2 (and vice versa). Follow the procedure below:

1. 1. Check that no flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register (BSY is active when erase/program operation is ongoing to bank 1 or bank 2)
2. 2. Set MER/MER1 or MER2 bit in the FLASH_CR register
3. 3. Set the STRT bit in the FLASH_CR register
4. 4. Wait for the BSY bit to be reset (or use the EOP interrupt).

Note: When setting the STRT bit in the FLASH_CR register and before polling the BSY bit to be cleared, the software can issue a DSB instruction to guarantee the completion of a previous access to FLASH_CR register.

Read from bank 1 while programming bank 2

While executing a program code (instruction fetch) from bank 1, it is possible to perform a program operation to the bank 2 (and vice versa). Follow the procedure below:

1. 1. Check that no flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register (BSY is active when erase/program operation is ongoing on bank 1 or bank 2)
2. 2. Set the PG bit in the FLASH_CR register
3. 3. Perform the data write operation(s) to the desired memory address inside main memory block or OTP area
4. 4. Wait for the BSY bit to be reset.

Note: After performing a data write operation and before polling the BSY bit to be cleared, the software can issue a DSB instruction to guarantee the completion of a previous data write operation.

3.3.9 Flash Interrupts

Setting the end of operation interrupt enable bit (EOPIE) in the FLASH_CR register enables interrupt generation when an erase or program operation ends, that is when the busy bit (BSY) in the FLASH_SR register is cleared (operation completed, correctly or not). In this case, the end of operation (EOP) bit in the FLASH_SR register is set.

If an error occurs during a program, an erase, or a read operation request, one of the following error flags is set in the FLASH_SR register:

• • PGAERR, PGPERR, ERSERR (Program error flags)
• • WRPERR (Protection error flag)

In this case, if the error interrupt enable bit (ERRIE) is set in the FLASH_CR register, an interrupt is generated and the operation error bit (OPERR) is set in the FLASH_SR register.

Note: If several successive errors are detected (for example, in case of DMA transfer to the flash memory), the error flags cannot be cleared until the end of the successive write requests.

Table 9. Flash interrupt request

3.4 FLASH Option bytes

3.4.1 Option bytes description

The option bytes are configured by the end user depending on the application requirements. Table 10 shows the organization of these bytes inside the information block.

The option bytes can be read from the user configuration memory locations or from the Option byte registers:

• • Flash option control register (FLASH_OPTCR)
• • Flash option control register (FLASH_OPTCR1)

Table 10. Option byte organization

User and read protection options bytes

Memory address: 0x1FFF 0000

ST programmed value: 0x5500AAFF

Bits 31:13 Not used.

Bits 15:8 RDP : Read Out Protection

The read protection helps the user protect the software code stored in flash memory.
0xAA: Level0, no Protection
0xCC: Level2, chip protection (debug & boot in RAM features disabled)
others: Level1, read protection of memories (debug features limited)

Bit 7 nRST_STDBY

0: Reset generated when entering Standby mode.
1: No reset generated.

Bit 6 nRST_STOP

0: Reset generated when entering Stop mode.
1: No reset generated.

Bit 5 IWDG_SW : Independant watchdog selection

0: Hardware independant watchdog.
1: Software independant watchdog.

Bit 4 WWDG_SW : Window watchdog selection

0: Hardware window watchdog.
1: Software window watchdog.

Bits 3:2 BOR_LEV : BOR reset Level

These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into flash memory.

00: BOR Level 3 (VBOR3), brownout threshold level 3
01: BOR Level 2 (VBOR2), brownout threshold level 2
10: BOR Level 1 (VBOR1), brownout threshold level 1
11: BOR off, POR/PDR reset threshold level is applied

Note: For full details on BOR characteristics, refer to the “Electrical characteristics” section of the product datasheet.

Bits 1:0 Not used

User and write protection options bytes

Memory address: 0x1FFF 0008

ST programmed value: 0x0000FFFF

Bits 31:16 Not used.

Bit 15 IWDG_STOP : Independent watchdog counter freeze in stop mode

0: Freeze IWDG counter in stop mode.

1: IWDG counter active in stop mode.

Bit 14 IWDG_STDBY : Independent watchdog counter freeze in Standby mode

1: IWDG counter active in standby mode.

Bit 13 nDBANK : Not dual bank mode

1: The Flash user area is seen as a single bank with 256 bits read access.

0: The Flash user area is seen as a dual bank with 128 bits read access (dual bank mode feature active)

Bit 12 nDBOOT : Dual Boot mode (valid only when nDBANK=0)

1: Dual Boot disabled. Boot according to boot address option (Default)

0: Dual Boot enabled. Boot always from system memory if boot address is in flash (Dual bank Boot mode), or RAM if Boot address option in RAM

Bits 11:0 nWRPi : Non Write Protection of sectors

0: Write protection active.

1: Write protection not active.

Note: Refer to Section 3.5.2: Write protections.

Boot address option bytes when Boot pin =0

Memory address: 0x1FFF 0010

ST programmed value: 0xFF7F 0080 (ITCM-FLASH base address)

Bits 31:16 Not used.

Bits 15:0 BOOT_ADD0[15:0] : Boot memory base address when Boot pin =0

BOOT_ADD0[15:0] correspond to address [29:14],

The boot base address supports address range only from 0x0000 0000 to 0x2007 FFFF with a granularity of 16 Kbytes.

Example:

BOOT_ADD0 = 0x0000: Boot from ITCM RAM (0x0000 0000)

BOOT_ADD0 = 0x0040: Boot from system memory bootloader (0x0010 0000)

BOOT_ADD0 = 0x0080: Boot from Flash on ITCM interface (0x0020 0000)

BOOT_ADD0 = 0x2000: Boot from Flash on AXIM interface (0x0800 0000)

BOOT_ADD0 = 0x8000: Boot from DTCM RAM (0x2000 0000)

BOOT_ADD0 = 0x8004: Boot from SRAM1 (0x2002 0000)

BOOT_ADD0 = 0x8013: Boot from SRAM2 (0x2007 C000)

Boot address option bytes when Boot pin =1

Memory address: 0x1FFF 0018

ST programmed value: 0xFFBF0040 (system memory bootloader address)

Bits 31:16 Not used

Bits 15:0 BOOT_ADD1[15:0] : Boot memory base address when Boot pin =1
BOOT_ADD1[15:0] correspond to address [29:14],
The boot base address supports address range only from 0x0000 0000 to 0x2004 FFFF
with a granularity of 16KB.
Example:
BOOT_ADD1 = 0x0000: Boot from ITCM RAM(0x0000 0000)
BOOT_ADD1 = 0x0040: Boot from system memory bootloader (0x0010 0000)
BOOT_ADD1 = 0x0080: Boot from Flash on ITCM interface (0x0020 0000)
BOOT_ADD1 = 0x2000: Boot from Flash on AXIM interface (0x0800 0000)
BOOT_ADD1 = 0x8000: Boot from DTCM RAM (0x2000 0000)
BOOT_ADD1 = 0x8008: Boot from SRAM1 (0x2002 0000)
BOOT_ADD1 = 0x801F: Boot from SRAM2 (0x2007 C000)

3.4.2 Option bytes programming

To run any operation on this sector, the option lock bit (OPTLOCK) in the Flash option control register (FLASH_OPTCR) must be cleared. To be allowed to clear this bit, you have to perform the following sequence:

1. 1. Write OPTKEY1 = 0x0819 2A3B in the Flash option key register (FLASH_OPTKEYR)
2. 2. Write OPTKEY2 = 0x4C5D 6E7F in the Flash option key register (FLASH_OPTKEYR)

The user option bytes can be protected against unwanted erase/program operations by setting the OPTLOCK bit by software.

Modifying user option bytes

To modify the user option value, follow the sequence below:

1. 1. Check that no flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register
2. 2. Write the desired option value in the FLASH_OPTCR register.
3. 3. Set the option start bit (OPTSTRT) in the FLASH_OPTCR register
4. 4. Wait for the BSY bit to be cleared.

Note: The value of an option is automatically modified by first erasing the information block and then programming all the option bytes with the values contained in the FLASH_OPTCR register.

Note: When setting the OPTSTRT bit in the FLASH_OPTCR register and before polling the BSY bit to be cleared, the software can issue a DSB instruction to guarantee the completion of a previous access to the FLASH_OPTCR register.

3.5 FLASH memory protection

3.5.1 Read protection (RDP)

The user area in the flash memory can be protected against read operations by an entrusted code. Three read protection levels are defined:

• • Level 0: no read protection

When the read protection level is set to Level 0 by writing 0xAA into the read protection option byte (RDP), all read/write operations (if no write protection is set) from/to the flash memory or the backup SRAM are possible in all boot configurations (Flash user boot, debug or boot from RAM).

• • Level 1: read protection enabled

It is the default read protection level after option byte erase. The read protection Level 1 is activated by writing any value (except for 0xAA and 0xCC used to set Level 0 and Level 2, respectively) into the RDP option byte. When the read protection Level 1 is set:

• – No access (read, erase, program) to flash memory or backup SRAM can be performed while the debug feature is connected or while booting from RAM or system memory bootloader. A bus error is generated in case of read request.
• – When booting from flash memory, accesses (read, erase, program) to flash memory and backup SRAM from user code are allowed.

When Level 1 is active, programming the protection option byte (RDP) to Level 0 causes the flash memory and the backup SRAM to be mass-erased. As a result the user code area is cleared before the read protection is removed. The mass erase only erases the user code area. The other option bytes including write protections remain unchanged from before the mass-erase operation. The OTP area is not affected by mass erase and remains unchanged. Mass erase is performed only when Level 1 is active and Level 0 requested. When the protection level is increased (0->1, 1->2, 0->2) there is no mass erase.

• • Level 2: debug/chip read disabled

The read protection Level 2 is activated by writing 0xCC to the RDP option byte. When the read protection Level 2 is set:

• – All protections provided by Level 1 are active.
• – Booting from RAM or system memory bootloader is no more allowed.
• – JTAG, SWV (serial-wire viewer), ETM, and boundary scan are disabled.
• – The option bytes can no longer be changed.
• – When booting from flash memory, accesses (read, erase and program) to flash memory and backup SRAM from user code are allowed.

Memory read protection Level 2 is an irreversible operation. When Level 2 is activated, the level of protection cannot be decreased to Level 0 or Level 1.

Note: The JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a consequence, boundary scan cannot be performed. STMicroelectronics is not able to perform analysis on defective parts on which the Level 2 protection has been set.

Note: If the read protection is set while the debugger is still connected through JTAG/SWD, apply a POR (power-on reset).

Table 11. Access versus read protection level

1. 1. The main flash memory and backup SRAM are only erased when the RDP changes from level 1 to 0. The OTP area remains unchanged.

Figure 4 shows how to go from one RDP level to another.

graph TD
    L1((Level 1
RDP != AAh
RDP != CCh
default)) -- "RDP != AAh & != CCh
Others options modified" --> L1
    L1 -- "Write options including
RDP = CCh" --> L2((Level 2
RDP = CCh))
    L1 -- "Write options including
RDP != CCh & != AAh" --> L0((Level 0
RDP = AAh))
    L2 -- "Write options including
RDP = CCh" --> L1
    L0 -- "Write options including
RDP = AAh" --> L1
    L0 -- "RDP = AAh
Others option(s) modified" --> L0
  

3.5.2 Write protections

User sectors in the flash memory can be protected against unwanted write operations due to loss of program counter contexts. When the non-write protection nWRPi bits in the FLASH_OPTCR register is low, the corresponding sector cannot be erased or programmed.

If an erase/program operation to a write-protected part of the flash memory is attempted (sector protected by write protection bit, OTP part locked or part of the flash memory that can never be written like the ICP), the write protection error flag (WRPERR) is set in the FLASH_SR register.

Write protection user options in single bank mode (nBANK=1)

The user sectors of bank 1 (sector 0 to sector 11) and bank 2 (sector 0 to sector 11) can be protected with following scheme:

nWRP[0] bit is write protection bit for sector 0

nWRP[1] bit is write protection bit for sector 1

...

nWRP[5] bit is write protection bit for sector 5

nWRP[6] bit is write protection bit for sector 6

nWRP[7] bit is write protection bit for sector 7

...

nWRP[11] bit is write protection bit for sector 11

When the Not Write Protection is active for one of the sectors pairs, the pairs of sectors can not be neither erased or programmed. Consequently a mass erase, or bank erase can not be performed if one of its sector pairs is write protected.

Note: When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase flash memory sector i if the CPU debug features are connected (JTAG or single wire) or boot code is being executed from RAM, even if nWRPi = 1.

Write protection user options in dual bank mode (nBANK=0)

The user sectors of bank 1 (sector 0 to sector 11) and bank 2 (sector 0 to sector 11) can be protected with following scheme:

nWRP[0] bit is write protection bit for bank 1 sector 0/ sector 1

nWRP[1] bit is write protection bit for bank 1 sector 2/ sector 3

...

nWRP[5] bit is write protection bit for bank 1 sector 10/ sector 11

nWRP[6] bit is write protection bit for bank 2 sector 12/ sector 13

nWRP[7] bit is write protection bit for bank 2 sector 14/ sector 15

...

nWRP[11] bit is write protection bit for bank 2 sector 22/ sector 23

When the Not Write Protection is active for one of the sectors pairs, the pairs of sectors can not be neither erased or programmed. Consequently a mass erase, or bank erase can not be performed if one of its sector pairs is write protected.

Note: When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase flash memory sector i if the CPU debug features are connected (JTAG or single wire) or boot code is being executed from RAM, even if nWRPi = 1.

Write protection error flag

If an erase/program operation to a write protected part of the flash memory is performed, the Write Protection Error flag (WRPERR) is set in the FLASH_SR register.

If an erase operation is requested, the WRPERR bit is set when:

When in single bank mode (nDBANK=1)

• • A sector erase is requested and the Sector Number SNB field is not valid
• • A mass erase is requested while at least one of the user sector is write protected by option bit (MER/MER1 = 1 and nWRPi = 0 with 0 ≤ i ≤ 11 bits in the FLASH_OPTCR register)
• • A sector erase is requested on a sector write protected by option bit (SER = 1, SNB = i and nWRPi = 0 with 0 ≤ i ≤ 11 bits in the FLASH_OPTCR register)
• • The flash memory is readout protected and an intrusion is detected

When in dual bank mode (nDBANK=0)

• • A sector erase is requested and the Sector Number SNB field is not valid
• • A mass erase is requested while at least one of the user sector is write protected by option bit (MER/MER1 = 1 and MER2 = 1 and nWRPi = 0 with \( 0 \le i \le 11 \) bits in the FLASH_OPTCR register)
• • A bank erase is requested on bank 1 while at least one of the user sector of the bank 1 is write protected
• • A bank erase is requested on bank 2 while at least one of the user sector of the bank 2 is write protected
• • A sector erase is requested on a sector write protected by option bit (SER = 1, SNB = i and nWRPi = 0 with \( 0 \le i \le 11 \) bits in the FLASH_OPTCR register). Note that SNB gives full granularity of sectors for bank 1 and bank 2 whereas nWRPi groups sectors by 2. An error is set if one of the two sectors is erased whereas write protection is enabled (example, nWRP[0]=0 and SNB = 0x00000 or SNB = 0x00001).
• • The flash memory is readout protected and an intrusion is detected

If a program operation is requested, the WRPERR bit is set when:

• • A write operation is performed on System memory or on the reserved part of the user specific sector
• • A write operation is performed to the information block
• • A write operation is performed on a sector write protected by option bit. For nDBANK=0 configuration, SNB gives full granularity of sectors for bank 1 and bank 2 whereas nWRPi groups sectors by 2. An error is set if one of the two sectors is programed whereas write protection is enabled (example, nWRP[0]=0 and trying to program bank 1 sector 0 or sector 1).
• • A write operation is requested on an OTP area which is already locked
• • The flash memory is read protected and an intrusion is detected.

3.6 One-time programmable bytes

Table 12 shows the organization of the one-time programmable (OTP) part of the OTP area.

Table 12. OTP area organization

Table 12. OTP area organization (continued)

The OTP area is divided into 16 OTP data blocks of 64 bytes and one lock OTP block of 16 bytes. The OTP data and lock blocks cannot be erased. The lock block contains 16 bytes LOCKBi (0 ≤ i ≤ 15) to lock the corresponding OTP data block (blocks 0 to 15). Each OTP data block can be programmed until the value 0x00 is programmed in the corresponding OTP lock byte. The lock bytes must only contain 0x00 and 0xFF values, otherwise the OTP bytes might not be taken into account correctly.

3.7 FLASH registers

3.7.1 Flash access control register (FLASH_ACR)

The Flash access control register is used to enable/disable the acceleration features and control the flash memory access time according to CPU frequency.

Address offset: 0x00

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Bits 31:12 Reserved, must be kept cleared.

Bit 11 ARTRST : ART Accelerator reset

0: ART Accelerator is not reset

1: ART Accelerator is reset

Bit 10 Reserved, must be kept cleared.

Bit 9 ARTEN : ART Accelerator Enable

0: ART Accelerator is disabled

1: ART Accelerator is enabled

Bit 8 PRFTEN : Prefetch enable

0: Prefetch is disabled

1: Prefetch is enabled

Bits 7:4 Reserved, must be kept cleared.

Bits 3:0 LATENCY[3:0] : Latency

These bits represent the ratio of the CPU clock period to the flash memory access time.

0000: Zero wait state

0001: One wait state

0010: Two wait states

-

-

-

1110: Fourteen wait states

1111: Fifteen wait states

3.7.2 Flash key register (FLASH_KEYR)

The Flash key register is used to allow access to the Flash control register and so, to allow program and erase operations.

Address offset: 0x04

Reset value: 0x0000 0000

Access: no wait state, word access

Bits 31:0 FKEYR : FPEC key

The following values must be programmed consecutively to unlock the FLASH_CR register and allow programming/erasing it:

1. KEY1 = 0x45670123
2. KEY2 = 0xCDEF89AB

3.7.3 Flash option key register (FLASH_OPTKEYR)

The Flash option key register is used to allow program and erase operations in the information block.

Address offset: 0x08

Reset value: 0x0000 0000

Access: no wait state, word access

Bits 31:0 OPTKEYR[31:0] : Option byte key

The following values must be programmed consecutively to unlock the FLASH_OPTCR register and allow programming it:

1. OPTKEY1 = 0x08192A3B
2. OPTKEY2 = 0x4C5D6E7F

3.7.4 Flash status register (FLASH_SR)

The Flash status register gives information on ongoing program and erase operations.

Address offset: 0x0C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Bits 31:17 Reserved, must be kept cleared.

Bit 16 BSY : Busy

This bit indicates that a flash memory operation is in progress. It is set at the beginning of a flash memory operation and cleared when the operation finishes or an error occurs.

1. 0: no flash memory operation ongoing
2. 1: Flash memory operation ongoing

Bits 15:8 Reserved, must be kept cleared.

Bit 7 ERSERR : Erase Sequence Error

Set by hardware when a write access to the flash memory is performed by the code while the control register has not been correctly configured.

Cleared by writing 1.

Bit 6 PGPERR : Programming parallelism error

Set by hardware when the size of the access (byte, half-word, word, double word) during the program sequence does not correspond to the parallelism configuration PSIZE (x8, x16, x32, x64).

Cleared by writing 1.

Bit 5 PGAERR : Programming alignment error

Set by hardware when the data to program cannot be contained in the same 128-bit flash memory row.

Cleared by writing 1.

Bit 4 WRPERR : Write protection error

Set by hardware when an address to be erased/programmed belongs to a write-protected part of the flash memory.

Cleared by writing 1.

Bits 3:2 Reserved, must be kept cleared.

Bit 1 OPERR : Operation error

Set by hardware when a flash operation (programming / erase / read) request is detected and can not be run because of parallelism, alignment, or write protection error. This bit is set only if error interrupts are enabled (ERRIE = 1).

Bit 0 EOP : End of operation

Set by hardware when one or more flash memory operations (program/erase) has/have completed successfully. It is set only if the end of operation interrupts are enabled (EOPIE = 1).

Cleared by writing a 1.

3.7.5 Flash control register (FLASH_CR)

The Flash control register is used to configure and start flash memory operations.

Address offset: 0x10

Reset value: 0x8000 0000

Access: no wait state when no flash memory operation is ongoing, word, half-word and byte access.

Bit 31 LOCK : Lock

Write to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence.

In the event of an unsuccessful unlock operation, this bit remains set until the next reset.

Bits 30:26 Reserved, must be kept cleared.

Bit 25 ERRIE : Error interrupt enable

This bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is set to 1.

0: Error interrupt generation disabled

1: Error interrupt generation enabled

Bit 24 EOPIE : End of operation interrupt enable

This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to 1.

0: Interrupt generation disabled

1: Interrupt generation enabled

Bits 23:17 Reserved, must be kept cleared.

This bit triggers an erase operation when set. It is set only by software and cleared when the BSY bit is cleared.

if nDBANK=1, this bit must be kept cleared

if nDBANK=0, this bit activates Erase for all user sectors in bank 2

Bits 14:10 Reserved, must be kept cleared.

These bits select the program parallelism.

00 program x8

01 program x16

10 program x32

11 program x64

if nDBANK=1 in single bank mode These bits select the sector to erase.

00000 sector 0

00001 sector 1

...

01011 sector 11

Others not allowed

if nDBANK=0 in dual bank mode These bits select the sector to erase from bank 1 or bank 2, where MSB bit selects the bank

00000 bank 1 sector 0

00001 bank 1 sector 1

...

01011 bank 1 sector 11

01100: not allowed

01101: not allowed

01110: not allowed

01111: not allowed

-----

10000 bank 2 sector 0

10001 bank 2 sector 1

...

11011 bank 2 sector 11

11100: not allowed

11101: not allowed

11110: not allowed

11111: not allowed

If nDBANK=1, MER activates erase of all user sectors in flash memory.

If nDBANK=0, MER1 in dual bank mode this bit activates Erase of all user sectors in bank 1

Sector Erase activated.

Flash programming activated.

3.7.6 Flash option control register (FLASH_OPTCR)

The FLASH_OPTCR register is used to modify the user option bytes.

Address offset: 0x14

Reset value: 0xFFFFFAFD. The option bytes are loaded with values from flash memory at reset release.

Access: no wait state when no flash memory operation is ongoing, word, half-word and byte access.

Bit 31 IWDG_STOP : Independent watchdog counter freeze in Stop mode

0: Freeze IWDG counter in STOP mode.

1: IWDG counter active in STOP mode.

Bit 30 IWDG_STDBY : Independent watchdog counter freeze in standby mode

0: Freeze IWDG counter in standby mode.

1: IWDG counter active in standby mode.

Bit 29 nDBANK : Not dual bank mode

1: The Flash user area is seen as a single bank with 256 bits read access.

0: The Flash user area is seen as a dual bank with 128 bits read access (dual bank mode feature active)

Bit 28 nDBOOT : Dual Boot mode (valid only when nDBANK=0)

Dual Boot mode (valid only when nDBANK=0)

1: Dual Boot disabled. Boot according to boot address option (Default)

0: Dual Boot enabled. Boot always from system memory if boot address is in flash (Dual bank Boot mode), or RAM if Boot address option in RAM

Bits 27:16 nWRP[11:0] : Not write protect

if nDBANK=1 (Single bank mode)

These bits contain the value of the write-protection option bytes for sectors 0 to 11 after reset.

They can be written to program a new write-protect into flash memory.

0: Write protection active on sector i

1: Write protection not active on sector i

if nDBANK=0 (Dual bank mode)

nWRP[11:0] bits are divided on two groups one group dedicated for bank 1 and a second one dedicated for bank 2

nWRP[5:0]: write protection for Bank 1 sectors

0: Write protection active on bank 1 sector \( 2*i \) and \( 2*i+1 \)

1: Write protection not active on bank 1 sector \( 2*i \) and \( 2*i+1 \)

nWRP[11:6]: write protection for Bank 2 sectors

0: Write protection active on bank 2 sector \( 2*i \) and \( 2*i+1 \)

1: Write protection not active on bank 1 sector \( 2*i \) and \( 2*i+1 \)

Bits 15:8 RDP[7:0] : Read protect

These bits contain the value of the read-protection option level after reset. They can be written to program a new read protection value into flash memory.

0xAA: Level 0, read protection not active

0xCC: Level 2, chip read protection active

Others: Level 1, read protection of memories active

Bits 7:4 USER : User option bytes

These bits contain the value of the user option byte after reset. They can be written to program a new user option byte value into flash memory.

Bit 7: nRST_STDBY

Bit 6: nRST_STOP

Bit 5: IWDG_SW

Bit 4: WWDOG_SW

Bits 3:2 BOR_LEV[1:0] : BOR reset Level

These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level. By default, BOR is off. When the supply voltage ( \( V_{DD} \) ) drops below the selected BOR level, a device reset is generated.

00: BOR Level 3 (VBOR3), brownout threshold level 3

01: BOR Level 2 (VBOR2), brownout threshold level 2

10: BOR Level 1 (VBOR1), brownout threshold level 1

11: BOR off, POR/PDR reset threshold level is applied

Note: For full details on BOR characteristics, refer to the “Electrical characteristics” section of the product datasheet.

Bit 1 OPTSTRT : Option start

This bit triggers a user option operation when set. It is set only by software and cleared when the BSY bit is cleared.

Bit 0 OPTLOCK : Option lock

Write to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked.

This bit is cleared by hardware after detecting the unlock sequence.

In the event of an unsuccessful unlock operation, this bit remains set until the next reset.

Note: When modifying the IWDG_SW, IWDG_STOP or IWDG_STDBY option byte, a system reset is required to make the change effective.

3.7.7 Flash option control register (FLASH_OPTCR1)

The FLASH_OPTCR1 register is used to modify the user option bytes.

Address offset: 0x18

Reset value: 0x0040 0080 (ITCM-FLASH). The option bytes are loaded with values from flash memory at reset release.

Access: no wait state when no flash memory operation is ongoing, word, half-word and byte access.

Bits 31:16 BOOT_ADD1[15:0] : Boot base address when Boot pin =1

BOOT_ADD1[15:0] correspond to address [29:14],

The boot memory address can be programmed to any address in the range 0x0000 0000 to 0x2007 FFFF with a granularity of 16 Kbytes.

Example:

BOOT_ADD1 = 0x0000: Boot from ITCM RAM (0x0000 0000)

BOOT_ADD1 = 0x0040: Boot from System memory bootloader (0x0010 0000)

BOOT_ADD1 = 0x0080: Boot from Flash on ITCM interface (0x0020 0000)

BOOT_ADD1 = 0x2000: Boot from Flash on AXIM interface (0x0800 0000)

BOOT_ADD1 = 0x8000: Boot from DTCM RAM (0x2000 0000)

BOOT_ADD1 = 0x8004: Boot from SRAM1 (0x2002 0000)

BOOT_ADD1 = 0x8013: Boot from SRAM2 (0x2007 C000)

Bits 15:0 BOOT_ADD0[15:0] : Boot base address when Boot pin =0

BOOT_ADD0[15:0] correspond to address [29:14],

The boot base address supports address range only from 0x0000 0000 to 0x2007 FFFF with a granularity of 16 Kbytes.

Example:

BOOT_ADD0 = 0x0000: Boot from ITCM RAM (0x0000 0000)

BOOT_ADD0 = 0x0040: Boot from System memory bootloader (0x0010 0000)

BOOT_ADD0 = 0x0080: Boot from Flash on ITCM interface (0x0020 0000)

BOOT_ADD0 = 0x2000: Boot from Flash on AXIM interface (0x0800 0000)

BOOT_ADD0 = 0x8000: Boot from DTCM RAM (0x2000 0000)

BOOT_ADD0 = 0x8004: Boot from SRAM1 (0x2002 0000)

BOOT_ADD0 = 0x8013: Boot from SRAM2 (0x2007 C000)

3.7.8 Flash interface register map

Table 13. Flash register map and reset values

Refer to Section 2.2 on page 76 for the register boundary addresses.