RM0410-STM32F76-77

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32F76xxx and STM32F77xxx microcontroller memory and peripherals.

The STM32F76xxx and STM32F77xxx is a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics refer to the datasheets.

For information on the Arm ® Cortex ® -M7 with FPU core, refer to the Cortex ® -M7 with FPU Technical Reference Manual.

STM32F76xxx and STM32F77xxx microcontrollers include ST state-of-the-art patented technology.

Available from STMicroelectronics web site www.st.com :

Contents

3.3.2Read access latency . . . . .90
3.3.3Flash program and erase operations . . . . .93
3.3.4Unlocking the Flash control register . . . . .93
3.3.5Maximum program/erase parallelism . . . . .93
3.3.6Switching from single bank to dual bank configuration . . . . .94
3.3.7Flash erase sequences . . . . .95
3.3.8Flash programming sequences . . . . .96
3.3.9Flash Interrupts . . . . .98
3.4FLASH Option bytes . . . . .99
3.4.1Option bytes description . . . . .99
3.4.2Option bytes programming . . . . .102
3.5FLASH memory protection . . . . .103
3.5.1Read protection (RDP) . . . . .103
3.5.2Write protections . . . . .105
3.6One-time programmable bytes . . . . .107
3.7FLASH registers . . . . .108
3.7.1Flash access control register (FLASH_ACR) . . . . .108
3.7.2Flash key register (FLASH_KEYR) . . . . .109
3.7.3Flash option key register (FLASH_OPTKEYR) . . . . .109
3.7.4Flash status register (FLASH_SR) . . . . .110
3.7.5Flash control register (FLASH_CR) . . . . .111
3.7.6Flash option control register (FLASH_OPTCR) . . . . .113
3.7.7Flash option control register (FLASH_OPTCR1) . . . . .115
3.7.8Flash interface register map . . . . .116
4Power controller (PWR) . . . . .117
4.1Power supplies . . . . .117
4.1.1Independent A/D converter supply and reference voltage . . . . .119
4.1.2Independent USB transceivers supply . . . . .119
4.1.3Independent SDMMC2 supply . . . . .120
4.1.4Independent DSI supply . . . . .120
4.1.5Battery backup domain . . . . .121
4.1.6Voltage regulator . . . . .123
4.2Power supply supervisor . . . . .126
4.2.1Power-on reset (POR)/power-down reset (PDR) . . . . .126
4.2.2Brownout reset (BOR) . . . . .127

5 Reset and clock control (RCC) . . . . . 151

5.3.1RCC clock control register (RCC_CR) . . . . .164
5.3.2RCC PLL configuration register (RCC_PLLCFGR) . . . . .166
5.3.3RCC clock configuration register (RCC_CFGR) . . . . .169
5.3.4RCC clock interrupt register (RCC_CIR) . . . . .171
5.3.5RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .174
5.3.6RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .177
5.3.7RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . .178
5.3.8RCC APB1 peripheral reset register (RCC_APB1RSTR) . . . . .178
5.3.9RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .182
5.3.10RCC AHB1 peripheral clock register (RCC_AHB1ENR) . . . . .185
5.3.11RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .187
5.3.12RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . .188
5.3.13RCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . .188
5.3.14RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .192
5.3.15RCC AHB1 peripheral clock enable in low-power mode register
(RCC_AHB1LPENR) . . . . .		195
5.3.16RCC AHB2 peripheral clock enable in low-power mode register
(RCC_AHB2LPENR) . . . . .		197
5.3.17RCC AHB3 peripheral clock enable in low-power mode register
(RCC_AHB3LPENR) . . . . .		198
5.3.18RCC APB1 peripheral clock enable in low-power mode register
(RCC_APB1LPENR) . . . . .		199
5.3.19RCC APB2 peripheral clock enabled in low-power mode register
(RCC_APB2LPENR) . . . . .		203
5.3.20RCC backup domain control register (RCC_BDCR) . . . . .205
5.3.21RCC clock control & status register (RCC_CSR) . . . . .206
5.3.22RCC spread spectrum clock generation register (RCC_SSCGR) . . . . .208
5.3.23RCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . .209
5.3.24RCC PLLSAI configuration register (RCC_PLLSAICFGR) . . . . .212
5.3.25RCC dedicated clocks configuration register (RCC_DCKCFGR1) . . . . .213
5.3.26RCC dedicated clocks configuration register (RCC_DCKCFGR2) . . . . .215
5.3.27RCC register map . . . . .218
6General-purpose I/Os (GPIO) . . . . .221
6.1Introduction . . . . .221
6.2GPIO main features . . . . .221
6.3GPIO functional description . . . . .221
6.3.1General-purpose I/O (GPIO) . . . . .224
6.3.2I/O pin alternate function multiplexer and mapping . . . . .224
6.3.3I/O port control registers . . . . .225
6.3.4I/O port data registers . . . . .225
6.3.5I/O data bitwise handling . . . . .225
6.3.6GPIO locking mechanism . . . . .226
6.3.7I/O alternate function input/output . . . . .226
6.3.8External interrupt/wake-up lines . . . . .226
6.3.9Input configuration . . . . .227
6.3.10Output configuration . . . . .227
6.3.11Alternate function configuration . . . . .228
6.3.12Analog configuration . . . . .229
6.3.13Using the HSE or LSE oscillator pins as GPIOs . . . . .230
6.3.14Using the GPIO pins in the backup supply domain . . . . .230
6.4GPIO registers . . . . .231
6.4.1GPIO port mode register (GPIOx_MODER)
(x = A to K) . . . . .		231
6.4.2GPIO port output type register (GPIOx_OTYPER)
(x = A to K) . . . . .		231
6.4.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to K) . . . . .		232
6.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to K) . . . . .		232
6.4.5GPIO port input data register (GPIOx_IDR)
(x = A to K) . . . . .		233
6.4.6GPIO port output data register (GPIOx_ODR)
(x = A to K) . . . . .		233
6.4.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to K) . . . . .		234
6.4.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to K) . . . . .		234
6.4.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to K) . . . . .		235
6.4.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to J) . . . . .		236
6.4.11GPIO register map . . . . .238
7System configuration controller (SYSCFG) . . . . .240
7.1I/O compensation cell . . . . .240
7.2SYSCFG registers . . . . .240
7.2.1SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .240
7.2.2SYSCFG peripheral mode configuration register (SYSCFG_PMC) . . .241
7.2.3SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . .		243
7.2.4SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . .		244
7.2.5SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . .		244
7.2.6SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . .		245
7.2.7Class B register (SYSCFG_CBR) . . . . .246
7.2.8Compensation cell control register (SYSCFG_CMPCR) . . . . .246
7.2.9SYSCFG register map . . . . .247
8Direct memory access controller (DMA) . . . . .248
8.1DMA introduction . . . . .248
8.2DMA main features . . . . .248
8.3DMA functional description . . . . .250
8.3.1DMA block diagram . . . . .250
8.3.2DMA overview . . . . .250
8.3.3DMA transactions . . . . .251
8.3.4Channel selection . . . . .251
8.3.5Arbiter . . . . .253
8.3.6DMA streams . . . . .253
8.3.7Source, destination and transfer modes . . . . .254
8.3.8Pointer incrementation . . . . .257
8.3.9Circular mode . . . . .258
8.3.10Double-buffer mode . . . . .258
8.3.11Programmable data width, packing/unpacking, endianness . . . . .259
8.3.12Single and burst transfers . . . . .260
8.3.13FIFO . . . . .261
8.3.14DMA transfer completion . . . . .264
8.3.15DMA transfer suspension . . . . .265
8.3.16Flow controller . . . . .266
8.3.17Summary of the possible DMA configurations . . . . .267
8.3.18Stream configuration procedure . . . . .267
8.3.19Error management . . . . .268
8.4DMA interrupts . . . . .269
8.5DMA registers . . . . .270

9 Chrom-ART Accelerator controller (DMA2D) . . . . . 284

9.5.3DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . .298
9.5.4DMA2D foreground memory address register (DMA2D_FGMAR) . . .299
9.5.5DMA2D foreground offset register (DMA2D_FGOR) . . . . .299
9.5.6DMA2D background memory address register (DMA2D_BGMAR) . .300
9.5.7DMA2D background offset register (DMA2D_BGOR) . . . . .300
9.5.8DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . .301
9.5.9DMA2D foreground color register (DMA2D_FGCOLR) . . . . .302
9.5.10DMA2D background PFC control register (DMA2D_BGPFCCR) . . . .303
9.5.11DMA2D background color register (DMA2D_BGCOLR) . . . . .304
9.5.12DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . .		305
9.5.13DMA2D background CLUT memory address register
(DMA2D_BGCMAR) . . . . .		305
9.5.14DMA2D output PFC control register (DMA2D_OPFCCR) . . . . .306
9.5.15DMA2D output color register (DMA2D_OCOLR) . . . . .307
9.5.16DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .307
9.5.17DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .308
9.5.18DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .308
9.5.19DMA2D output memory address register (DMA2D_OMAR) . . . . .309
9.5.20DMA2D output offset register (DMA2D_OOR) . . . . .309
9.5.21DMA2D number of line register (DMA2D_NLR) . . . . .310
9.5.22DMA2D line watermark register (DMA2D_LWR) . . . . .310
9.5.23DMA2D AHB master timer configuration register (DMA2D_AMTCR) .311
9.5.24DMA2D foreground CLUT (DMA2D_FGCLUTx) . . . . .311
9.5.25DMA2D background CLUT (DMA2D_BGCLUTx) . . . . .312
9.5.26DMA2D register map . . . . .312
10Nested vectored interrupt controller (NVIC) . . . . .314
10.1NVIC features . . . . .314
10.1.1SysTick calibration value register . . . . .314
10.1.2Interrupt and exception vectors . . . . .314
11Extended interrupts and events controller (EXTI) . . . . .320
11.1EXTI main features . . . . .320
11.2EXTI block diagram . . . . .320
11.3Wakeup event management . . . . .321
11.4Functional description . . . . .321
11.5Hardware interrupt selection . . . . .321
11.6Hardware event selection . . . . .321
11.7Software interrupt/event selection . . . . .322
11.8External interrupt/event line mapping . . . . .322
11.9EXTI registers . . . . .323
11.9.1Interrupt mask register (EXTI_IMR) . . . . .323
11.9.2Event mask register (EXTI_EMR) . . . . .323
11.9.3Rising trigger selection register (EXTI_RTSR) . . . . .324
11.9.4Falling trigger selection register (EXTI_FTSR) . . . . .324
11.9.5Software interrupt event register (EXTI_SWIER) . . . . .325
11.9.6Pending register (EXTI_PR) . . . . .325
11.9.7EXTI register map . . . . .326
12Cyclic redundancy check calculation unit (CRC) . . . . .327
12.1Introduction . . . . .327
12.2CRC main features . . . . .327
12.3CRC functional description . . . . .328
12.3.1CRC block diagram . . . . .328
12.3.2CRC internal signals . . . . .328
12.3.3CRC operation . . . . .328
12.4CRC registers . . . . .330
12.4.1CRC data register (CRC_DR) . . . . .330
12.4.2CRC independent data register (CRC_IDR) . . . . .330
12.4.3CRC control register (CRC_CR) . . . . .331
12.4.4CRC initial value (CRC_INIT) . . . . .332
12.4.5CRC polynomial (CRC_POL) . . . . .332
12.4.6CRC register map . . . . .333
13Flexible memory controller (FMC) . . . . .334
13.1Introduction . . . . .334
13.2FMC main features . . . . .334
13.3FMC block diagram . . . . .335
13.4AHB interface . . . . .336
13.4.1Supported memories and transactions . . . . .336
13.5External device address mapping . . . . .337
13.5.1NOR/PSRAM address mapping . . . . .338
13.5.2NAND flash memory address mapping . . . . .339
13.5.3SDRAM address mapping . . . . .340
13.6NOR flash/PSRAM controller . . . . .343
13.6.1External memory interface signals . . . . .344
13.6.2Supported memories and transactions . . . . .346
13.6.3General timing rules . . . . .348
13.6.4NOR flash/PSRAM controller asynchronous transactions . . . . .348
13.6.5Synchronous transactions . . . . .365
13.6.6NOR/PSRAM controller registers . . . . .372
13.7NAND flash controller . . . . .379
13.7.1External memory interface signals . . . . .379
13.7.2NAND flash supported memories and transactions . . . . .380
13.7.3Timing diagrams for NAND flash memory . . . . .381
13.7.4NAND flash operations . . . . .382
13.7.5NAND flash prewait functionality . . . . .382
13.7.6Computation of the error correction code (ECC)
in NAND flash memory . . . . .		383
13.7.7NAND flash controller registers . . . . .384
13.8SDRAM controller . . . . .390
13.8.1SDRAM controller main features . . . . .390
13.8.2SDRAM External memory interface signals . . . . .390
13.8.3SDRAM controller functional description . . . . .391
13.8.4Low-power modes . . . . .397
13.8.5SDRAM controller registers . . . . .401
13.8.6FMC register map . . . . .407
14Quad-SPI interface (QUADSPI) . . . . .410
14.1Introduction . . . . .410
14.2QUADSPI main features . . . . .410
14.3QUADSPI functional description . . . . .410
14.3.1QUADSPI block diagram . . . . .410
14.3.2QUADSPI pins . . . . .411
14.3.3QUADSPI command sequence . . . . .411
14.3.4QUADSPI signal interface protocol modes . . . . .414
14.3.5QUADSPI indirect mode . . . . .416
14.3.6QUADSPI automatic status-polling mode . . . . .418
14.3.7QUADSPI memory-mapped mode . . . . .418

15.3.9Scan mode . . . . .447
15.3.10Injected channel management . . . . .447
15.3.11Discontinuous mode . . . . .448
15.4Data alignment . . . . .449
15.5Channel-wise programmable sampling time . . . . .450
15.6Conversion on external trigger and trigger polarity . . . . .451
15.7Fast conversion mode . . . . .452
15.8Data management . . . . .453
15.8.1Using the DMA . . . . .453
15.8.2Managing a sequence of conversions without using the DMA . . . . .453
15.8.3Conversions without DMA and without overrun detection . . . . .454
15.9Multi ADC mode . . . . .454
15.9.1Injected simultaneous mode . . . . .457
15.9.2Regular simultaneous mode . . . . .458
15.9.3Interleaved mode . . . . .459
15.9.4Alternate trigger mode . . . . .461
15.9.5Combined regular/injected simultaneous mode . . . . .463
15.9.6Combined regular simultaneous + alternate trigger mode . . . . .463
15.10Temperature sensor . . . . .464
15.11Battery charge monitoring . . . . .466
15.12ADC interrupts . . . . .467
15.13ADC registers . . . . .468
15.13.1ADC status register (ADC_SR) . . . . .468
15.13.2ADC control register 1 (ADC_CR1) . . . . .469
15.13.3ADC control register 2 (ADC_CR2) . . . . .471
15.13.4ADC sample time register 1 (ADC_SMPR1) . . . . .472
15.13.5ADC sample time register 2 (ADC_SMPR2) . . . . .473
15.13.6ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . . . .473
15.13.7ADC watchdog higher threshold register (ADC_HTR) . . . . .474
15.13.8ADC watchdog lower threshold register (ADC_LTR) . . . . .474
15.13.9ADC regular sequence register 1 (ADC_SQR1) . . . . .475
15.13.10ADC regular sequence register 2 (ADC_SQR2) . . . . .475
15.13.11ADC regular sequence register 3 (ADC_SQR3) . . . . .476
15.13.12ADC injected sequence register (ADC_JSQR) . . . . .477
15.13.13ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . .477
15.13.14ADC regular data register (ADC_DR) . . . . .478
15.13.15ADC Common status register (ADC_CSR) . . . . .478
15.13.16ADC common control register (ADC_CCR) . . . . .479
15.13.17ADC common regular data register for dual and triple modes
(ADC_CDR) . . . . .		482
15.13.18ADC register map . . . . .482
16Digital-to-analog converter (DAC) . . . . .485
16.1DAC introduction . . . . .485
16.2DAC main features . . . . .485
16.3DAC functional description . . . . .486
16.3.1DAC channel enable . . . . .486
16.3.2DAC output buffer enable . . . . .487
16.3.3DAC data format . . . . .487
16.3.4DAC conversion . . . . .488
16.3.5DAC output voltage . . . . .489
16.3.6DAC trigger selection . . . . .489
16.3.7DMA request . . . . .490
16.3.8Noise generation . . . . .490
16.3.9Triangle-wave generation . . . . .491
16.4Dual DAC channel conversion . . . . .492
16.4.1Independent trigger without wave generation . . . . .493
16.4.2Independent trigger with single LFSR generation . . . . .493
16.4.3Independent trigger with different LFSR generation . . . . .493
16.4.4Independent trigger with single triangle generation . . . . .494
16.4.5Independent trigger with different triangle generation . . . . .494
16.4.6Simultaneous software start . . . . .494
16.4.7Simultaneous trigger without wave generation . . . . .495
16.4.8Simultaneous trigger with single LFSR generation . . . . .495
16.4.9Simultaneous trigger with different LFSR generation . . . . .495
16.4.10Simultaneous trigger with single triangle generation . . . . .496
16.4.11Simultaneous trigger with different triangle generation . . . . .496
16.5DAC registers . . . . .497
16.5.1DAC control register (DAC_CR) . . . . .497
16.5.2DAC software trigger register (DAC_SWTRIGR) . . . . .500
16.5.3DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . .		500
16.5.4DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . .501
16.5.5DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . .501
16.5.6DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . .502
16.5.7DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . .502
16.5.8DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . .502
16.5.9Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . .503
16.5.10DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . .503
16.5.11DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . .504
16.5.12DAC channel1 data output register (DAC_DOR1) . . . . .504
16.5.13DAC channel2 data output register (DAC_DOR2) . . . . .504
16.5.14DAC status register (DAC_SR) . . . . .505
16.5.15DAC register map . . . . .506
17Digital filter for sigma delta modulators (DFSDM) . . . . .507
17.1Introduction . . . . .507
17.2DFSDM main features . . . . .508
17.3DFSDM implementation . . . . .509
17.4DFSDM functional description . . . . .510
17.4.1DFSDM block diagram . . . . .510
17.4.2DFSDM pins and internal signals . . . . .511
17.4.3DFSDM reset and clocks . . . . .512
17.4.4Serial channel transceivers . . . . .513
17.4.5Configuring the input serial interface . . . . .522
17.4.6Parallel data inputs . . . . .522
17.4.7Channel selection . . . . .524
17.4.8Digital filter configuration . . . . .525
17.4.9Integrator unit . . . . .526
17.4.10Analog watchdog . . . . .526
17.4.11Short-circuit detector . . . . .529
17.4.12Extreme detector . . . . .529
17.4.13Data unit block . . . . .530
17.4.14Signed data format . . . . .531
17.4.15Launching conversions . . . . .531
17.4.16Continuous and fast continuous modes . . . . .532
17.4.17Request precedence . . . . .532
17.4.18Power optimization in run mode . . . . .533
17.5DFSDM interrupts . . . . .533
17.6DFSDM DMA transfer . . . . .535
17.7DFSDM channel y registers (y=0..7) . . . . .535
17.7.1DFSDM channel y configuration register (DFSDM_CHyCFGR1) . . . . .535
17.7.2DFSDM channel y configuration register (DFSDM_CHyCFGR2) . . . . .538
17.7.3DFSDM channel y analog watchdog and short-circuit detector register
(DFSDM_CHyAWSCDR) . . . . .		538
17.7.4DFSDM channel y watchdog filter data register
(DFSDM_CHyWDATR) . . . . .		539
17.7.5DFSDM channel y data input register (DFSDM_CHyDATINR) . . . . .540
17.8DFSDM filter x module registers (x=0..3) . . . . .541
17.8.1DFSDM filter x control register 1 (DFSDM_FLTxCR1) . . . . .541
17.8.2DFSDM filter x control register 2 (DFSDM_FLTxCR2) . . . . .543
17.8.3DFSDM filter x interrupt and status register (DFSDM_FLTxISR) . . . . .545
17.8.4DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) . . . . .546
17.8.5DFSDM filter x injected channel group selection register
(DFSDM_FLTxJCHGR) . . . . .		547
17.8.6DFSDM filter x control register (DFSDM_FLTxFCR) . . . . .548
17.8.7DFSDM filter x data register for injected group
(DFSDM_FLTxJDATAR) . . . . .		549
17.8.8DFSDM filter x data register for the regular channel
(DFSDM_FLTxRDATAR) . . . . .		549
17.8.9DFSDM filter x analog watchdog high threshold register
(DFSDM_FLTxAWHTR) . . . . .		550
17.8.10DFSDM filter x analog watchdog low threshold register
(DFSDM_FLTxAWLTR) . . . . .		551
17.8.11DFSDM filter x analog watchdog status register
(DFSDM_FLTxAWSR) . . . . .		551
17.8.12DFSDM filter x analog watchdog clear flag register
(DFSDM_FLTxAWCFR) . . . . .		552
17.8.13DFSDM filter x extremes detector maximum register
(DFSDM_FLTxEXMAX) . . . . .		552
17.8.14DFSDM filter x extremes detector minimum register
(DFSDM_FLTxEXMIN) . . . . .		553
17.8.15DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . . . . .553
17.8.16DFSDM register map . . . . .554
18Digital camera interface (DCMI) . . . . .564
18.1Introduction . . . . .564
18.2DCMI main features . . . . .564
18.3DCMI functional description . . . . .564
18.3.1DCMI block diagram . . . . .565
18.3.2DCMI pins . . . . .565
18.3.3DCMI clocks . . . . .565
18.3.4DCMI DMA interface . . . . .566
18.3.5DCMI physical interface . . . . .566
18.3.6DCMI synchronization . . . . .568
18.3.7DCMI capture modes . . . . .570
18.3.8DCMI crop feature . . . . .571
18.3.9DCMI JPEG format . . . . .572
18.3.10DCMI FIFO . . . . .572
18.3.11DCMI data format description . . . . .573
18.4DCMI interrupts . . . . .575
18.5DCMI registers . . . . .575
18.5.1DCMI control register (DCMI_CR) . . . . .575
18.5.2DCMI status register (DCMI_SR) . . . . .578
18.5.3DCMI raw interrupt status register (DCMI_RIS) . . . . .578
18.5.4DCMI interrupt enable register (DCMI_IER) . . . . .579
18.5.5DCMI masked interrupt status register (DCMI_MIS) . . . . .580
18.5.6DCMI interrupt clear register (DCMI_ICR) . . . . .581
18.5.7DCMI embedded synchronization code register (DCMI_ESCR) . . . . .582
18.5.8DCMI embedded synchronization unmask register (DCMI_ESUR) . . . . .582
18.5.9DCMI crop window start (DCMI_CWSTRT) . . . . .583
18.5.10DCMI crop window size (DCMI_CWSIZE) . . . . .584
18.5.11DCMI data register (DCMI_DR) . . . . .584
18.5.12DCMI register map . . . . .585
19LCD-TFT display controller (LTDC) . . . . .586
19.1Introduction . . . . .586
19.2LTDC main features . . . . .586
19.3LTDC functional description . . . . .587
19.3.1LTDC block diagram . . . . .587
19.3.2LTDC pins and external signal interface . . . . .587
19.3.3LTDC reset and clocks . . . . .588
19.4LTDC programmable parameters . . . . .589
19.4.1LTDC global configuration parameters . . . . .589
19.4.2Layer programmable parameters . . . . .592
19.5LTDC interrupts . . . . .597
19.6LTDC programming procedure . . . . .597
19.7LTDC registers . . . . .598
19.7.1LTDC synchronization size configuration register (LTDC_SSCR) . . . . .598
19.7.2LTDC back porch configuration register (LTDC_BPCR) . . . . .600
19.7.3LTDC active width configuration register (LTDC_AWCR) . . . . .601
19.7.4LTDC total width configuration register (LTDC_TWCR) . . . . .601
19.7.5LTDC global control register (LTDC_GCR) . . . . .602
19.7.6LTDC shadow reload configuration register (LTDC_SRCR) . . . . .603
19.7.7LTDC background color configuration register (LTDC_BCCR) . . . . .604
19.7.8LTDC interrupt enable register (LTDC_IER) . . . . .604
19.7.9LTDC interrupt status register (LTDC_ISR) . . . . .605
19.7.10LTDC Interrupt clear register (LTDC_ICR) . . . . .606
19.7.11LTDC line interrupt position configuration register (LTDC_LIPCR) . . . . .606
19.7.12LTDC current position status register (LTDC_CPSR) . . . . .607
19.7.13LTDC current display status register (LTDC_CDSR) . . . . .607
19.7.14LTDC layer x control register (LTDC_LxCR) . . . . .608
19.7.15LTDC layer x window horizontal position configuration register
(LTDC_LxWHPCR) . . . . .		609
19.7.16LTDC layer x window vertical position configuration register
(LTDC_LxWVPCR) . . . . .		610
19.7.17LTDC layer x color keying configuration register
(LTDC_LxCKCR) . . . . .		611
19.7.18LTDC layer x pixel format configuration register
(LTDC_LxPFCR) . . . . .		611
19.7.19LTDC layer x constant alpha configuration register
(LTDC_LxCACR) . . . . .		612
19.7.20LTDC layer x default color configuration register
(LTDC_LxDCCR) . . . . .		612
19.7.21LTDC layer x blending factors configuration register
(LTDC_LxBFCR) . . . . .		613
19.7.22LTDC layer x color frame buffer address register
(LTDC_LxCFBAR) . . . . .		614
19.7.23LTDC layer x color frame buffer length register (LTDC_LxCFBLR) . . . . .614
19.7.24LTDC layer x color frame buffer line number register (LTDC_LxCFBLNR) . . . . .615
19.7.25LTDC layer x CLUT write register (LTDC_LxCLUTWR) . . . . .615
19.7.26LTDC register map . . . . .616
20DSI Host (DSI) . . . . .619
20.1Introduction . . . . .619
20.2Standard and references . . . . .619
20.3DSI Host main features . . . . .620
20.4DSI Host functional description . . . . .621
20.4.1General description . . . . .621
20.4.2DSI Host pins and internal signals . . . . .621
20.4.3Supported resolutions and frame rates . . . . .622
20.4.4System level architecture . . . . .622
20.5Functional description: video mode on LTDC interface . . . . .625
20.5.1Video transmission mode . . . . .626
20.5.2Updating the LTDC interface configuration in video mode . . . . .628
20.6Functional description: adapted command mode on LTDC interface . . . . .630
20.7Functional description: APB slave generic interface . . . . .634
20.7.1Packet transmission using the generic interface . . . . .634
20.8Functional description: timeout counters . . . . .638
20.8.1Contention error detection timeout counters . . . . .638
20.8.2Peripheral response timeout counters . . . . .639
20.9Functional description: transmission of commands . . . . .644
20.9.1Transmission of commands in video mode . . . . .644
20.9.2Transmission of commands in low-power mode . . . . .646
20.9.3Transmission of commands in high-speed . . . . .650
20.9.4Read command transmission . . . . .650
20.9.5Clock lane in low-power mode . . . . .651
20.10Functional description: virtual channels . . . . .653
20.11Functional description: video mode pattern generator . . . . .654
20.11.1Color bar pattern . . . . .654
20.11.2Color coding . . . . .656
20.11.3BER testing pattern . . . . .656
20.11.4Video mode pattern generator resolution . . . . .657
20.12Functional description: D-PHY management . . . . .658
20.12.1D-PHY configuration . . . . .658
20.12.2D-PHY HS2LP and LP2HS durations . . . . .660
20.12.3Special D-PHY operations . . . . .660
20.12.4Special low-power D-PHY functions . . . . .660
20.12.5DSI PLL control . . . . .661
20.12.6Regulator control . . . . .662
20.13Functional description: interrupts and errors . . . . .662
20.13.1DSI Wrapper interrupts . . . . .662
20.13.2DSI Host interrupts and errors . . . . .663
20.14Programing procedure . . . . .670
20.14.1Programing procedure overview . . . . .670
20.14.2Configuring the D-PHY parameters . . . . .670
20.14.3Configuring the DSI Host timing . . . . .671
20.14.4Configuring flow control and DBI interface . . . . .672
20.14.5Configuring the DSI Host LTDC interface . . . . .672
20.14.6Configuring the video mode . . . . .673
20.14.7Configuring the adapted command mode . . . . .677
20.14.8Configuring the video mode pattern generator . . . . .677
20.14.9Managing ULPM . . . . .678
20.15DSI Host registers . . . . .681
20.15.1DSI Host version register (DSI_VR) . . . . .681
20.15.2DSI Host control register (DSI_CR) . . . . .681
20.15.3DSI Host clock control register (DSI_CCR) . . . . .681
20.15.4DSI Host LTDC VCID register (DSI_LVCIDR) . . . . .682
20.15.5DSI Host LTDC color coding register (DSI_LCOLCR) . . . . .682
20.15.6DSI Host LTDC polarity configuration register (DSI_LPCR) . . . . .683
20.15.7DSI Host low-power mode configuration register (DSI_LPMCR) . . . . .683
20.15.8DSI Host protocol configuration register (DSI_PCR) . . . . .684
20.15.9DSI Host generic VCID register (DSI_GVCIDR) . . . . .685
20.15.10DSI Host mode configuration register (DSI_MCR) . . . . .685
20.15.11DSI Host video mode configuration register (DSI_VMCR) . . . . .685
20.15.12DSI Host video packet configuration register (DSI_VPCR) . . . . .687
20.15.13DSI Host video chunks configuration register (DSI_VCCR) . . . . .687
20.15.14DSI Host video null packet configuration register (DSI_VNPCR) . . . . .688
20.15.15DSI Host video HSA configuration register (DSI_VHSACR) . . . . .688
20.15.16 DSI Host video HBP configuration register (DSI_VHBPCR) . . . . .689
20.15.17 DSI Host video line configuration register (DSI_VLCR) . . . . .689
20.15.18 DSI Host video VSA configuration register (DSI_VVSACR) . . . . .689
20.15.19 DSI Host video VBP configuration register (DSI_VVBPCR) . . . . .690
20.15.20 DSI Host video VFP configuration register (DSI_VVFPCCR) . . . . .690
20.15.21 DSI Host video VA configuration register (DSI_VVACR) . . . . .690
20.15.22 DSI Host LTDC command configuration register (DSI_LCCR) . . . . .691
20.15.23 DSI Host command mode configuration register (DSI_CMCR) . . . . .691
20.15.24 DSI Host generic header configuration register (DSI_GHCR) . . . . .693
20.15.25 DSI Host generic payload data register (DSI_GPCR) . . . . .693
20.15.26 DSI Host generic packet status register (DSI_GPSR) . . . . .694
20.15.27 DSI Host timeout counter configuration register 0 (DSI_TCCR0) . . . . .695
20.15.28 DSI Host timeout counter configuration register 1 (DSI_TCCR1) . . . . .695
20.15.29 DSI Host timeout counter configuration register 2 (DSI_TCCR2) . . . . .696
20.15.30 DSI Host timeout counter configuration register 3 (DSI_TCCR3) . . . . .696
20.15.31 DSI Host timeout counter configuration register 4 (DSI_TCCR4) . . . . .697
20.15.32 DSI Host timeout counter configuration register 5 (DSI_TCCR5) . . . . .697
20.15.33 DSI Host clock lane configuration register (DSI_CLCR) . . . . .698
20.15.34 DSI Host clock lane timer configuration register (DSI_CLTCR) . . . . .698
20.15.35 DSI Host data lane timer configuration register (DSI_DLTCR) . . . . .699
20.15.36 DSI Host PHY control register (DSI_PCTLR) . . . . .699
20.15.37 DSI Host PHY configuration register (DSI_PCONFGR) . . . . .700
20.15.38 DSI Host PHY ULPS control register (DSI_PUCR) . . . . .700
20.15.39 DSI Host PHY TX triggers configuration register (DSI_PTTCCR) . . . . .701
20.15.40 DSI Host PHY status register (DSI_PSR) . . . . .701
20.15.41 DSI Host interrupt and status register 0 (DSI_ISR0) . . . . .702
20.15.42 DSI Host interrupt and status register 1 (DSI_ISR1) . . . . .703
20.15.43 DSI Host interrupt enable register 0 (DSI_IER0) . . . . .705
20.15.44 DSI Host interrupt enable register 1 (DSI_IER1) . . . . .707
20.15.45 DSI Host force interrupt register 0 (DSI_FIR0) . . . . .708
20.15.46 DSI Host force interrupt register 1 (DSI_FIR1) . . . . .710
20.15.47 DSI Host video shadow control register (DSI_VSCR) . . . . .711
20.15.48 DSI Host LTDC current VCID register (DSI_LCVCIDR) . . . . .711
20.15.49 DSI Host LTDC current color coding register (DSI_LCCCR) . . . . .712
20.15.50 DSI Host low-power mode current configuration register
(DSI_LPMCCR) . . . . .		712
20.15.51 DSI Host video mode current configuration register
(DSI_VMCCR) . . . . .		713
20.15.52 DSI Host video packet current configuration register (DSI_VPCCR) . . . . .714
20.15.53 DSI Host video chunks current configuration register (DSI_VCCCR) . . . . .715
20.15.54 DSI Host video null packet current configuration register (DSI_VNPCCR) . . . . .715
20.15.55 DSI Host video HSA current configuration register (DSI_VHSACCR) . . . . .715
20.15.56 DSI Host video HBP current configuration register (DSI_VHBPCCR) . . . . .716
20.15.57 DSI Host video line current configuration register (DSI_VLCCR) . . . . .716
20.15.58 DSI Host video VSA current configuration register (DSI_VVSACCR) . . . . .717
20.15.59 DSI Host video VBP current configuration register (DSI_VVBPCCR) . . . . .717
20.15.60 DSI Host video VFP current configuration register (DSI_VVFPCCR) . . . . .717
20.15.61 DSI Host video VA current configuration register (DSI_VVACCR) . . . . .718
20.16 DSI Wrapper registers . . . . .719
20.16.1 DSI Wrapper configuration register (DSI_WCFGR) . . . . .719
20.16.2 DSI Wrapper control register (DSI_WCR) . . . . .720
20.16.3 DSI Wrapper interrupt enable register (DSI_WIER) . . . . .720
20.16.4 DSI Wrapper interrupt and status register (DSI_WISR) . . . . .721
20.16.5 DSI Wrapper interrupt flag clear register (DSI_WIFCR) . . . . .722
20.16.6 DSI Wrapper PHY configuration register 0 (DSI_WPCR0) . . . . .723
20.16.7 DSI Wrapper PHY configuration register 1 (DSI_WPCR1) . . . . .726
20.16.8 DSI Wrapper PHY configuration register 2 (DSI_WPCR2) . . . . .727
20.16.9 DSI Wrapper PHY configuration register 3 (DSI_WPCR3) . . . . .728
20.16.10 DSI Wrapper PHY configuration register 4 (DSI_WPCR4) . . . . .729
20.16.11 DSI Wrapper regulator and PLL control register (DSI_WRPCR) . . . . .730
20.16.12 DSI register map . . . . .731
21 JPEG codec (JPEG) . . . . .736
21.1 Introduction . . . . .736
21.2 JPEG codec main features . . . . .736
21.3 JPEG codec block functional description . . . . .737
21.3.1 General description . . . . .737
21.3.2 JPEG decoding procedure . . . . .737
21.3.3JPEG encoding procedure . . . . .739
21.4JPEG codec interrupts . . . . .742
21.5JPEG codec registers . . . . .742
21.5.1JPEG codec control register (JPEG_CONFR0) . . . . .742
21.5.2JPEG codec configuration register 1 (JPEG_CONFR1) . . . . .743
21.5.3JPEG codec configuration register 2 (JPEG_CONFR2) . . . . .744
21.5.4JPEG codec configuration register 3 (JPEG_CONFR3) . . . . .744
21.5.5JPEG codec configuration register x (JPEG_CONFRx) . . . . .745
21.5.6JPEG control register (JPEG_CR) . . . . .746
21.5.7JPEG status register (JPEG_SR) . . . . .747
21.5.8JPEG clear flag register (JPEG_CFR) . . . . .748
21.5.9JPEG data input register (JPEG_DIR) . . . . .749
21.5.10JPEG data output register (JPEG_DOR) . . . . .749
21.5.11JPEG quantization memory x (JPEG_QMEMx_y) . . . . .750
21.5.12JPEG Huffman min (JPEG_HUFFMINx_y) . . . . .750
21.5.13JPEG Huffman min x (JPEG_HUFFMINx_y) . . . . .751
21.5.14JPEG Huffman base (JPEG_HUFFBASEx) . . . . .751
21.5.15JPEG Huffman symbol (JPEG_HUFFSYMBx) . . . . .752
21.5.16JPEG DHT memory (JPEG_DHTMEMx) . . . . .753
21.5.17JPEG Huffman encoder ACx (JPEG_HUFFENC_ACx_y) . . . . .753
21.5.18JPEG Huffman encoder DCx (JPEG_HUFFENC_DCx_y) . . . . .754
21.5.19JPEG codec register map . . . . .755
22True random number generator (RNG) . . . . .757
22.1Introduction . . . . .757
22.2RNG main features . . . . .757
22.3RNG functional description . . . . .758
22.3.1RNG block diagram . . . . .758
22.3.2RNG internal signals . . . . .758
22.3.3Random number generation . . . . .759
22.3.4RNG initialization . . . . .761
22.3.5RNG operation . . . . .761
22.3.6RNG clocking . . . . .762
22.3.7Error management . . . . .762
22.3.8RNG low-power use . . . . .763
22.4RNG interrupts . . . . .763
22.5RNG processing time . . . . .763
22.6RNG entropy source validation . . . . .763
22.6.1Introduction . . . . .763
22.6.2Validation conditions . . . . .764
22.6.3Data collection . . . . .764
22.7RNG registers . . . . .764
22.7.1RNG control register (RNG_CR) . . . . .764
22.7.2RNG status register (RNG_SR) . . . . .765
22.7.3RNG data register (RNG_DR) . . . . .766
22.7.4RNG register map . . . . .767
23Cryptographic processor (CRYP) . . . . .768
23.1Introduction . . . . .768
23.2CRYP main features . . . . .768
23.3CRYP implementation . . . . .769
23.4CRYP functional description . . . . .770
23.4.1CRYP block diagram . . . . .770
23.4.2CRYP internal signals . . . . .770
23.4.3CRYP DES/TDES cryptographic core . . . . .771
23.4.4CRYP AES cryptographic core . . . . .772
23.4.5CRYP procedure to perform a cipher operation . . . . .778
23.4.6CRYP busy state . . . . .780
23.4.7Preparing the CRYP AES key for decryption . . . . .781
23.4.8CRYP stealing and data padding . . . . .781
23.4.9CRYP suspend/resume operations . . . . .783
23.4.10CRYP DES/TDES basic chaining modes (ECB, CBC) . . . . .784
23.4.11CRYP AES basic chaining modes (ECB, CBC) . . . . .789
23.4.12CRYP AES counter mode (AES-CTR) . . . . .794
23.4.13CRYP AES Galois/counter mode (GCM) . . . . .798
23.4.14CRYP AES Galois message authentication code (GMAC) . . . . .803
23.4.15CRYP AES Counter with CBC-MAC (CCM) . . . . .804
23.4.16CRYP data registers and data swapping . . . . .809
23.4.17CRYP key registers . . . . .813
23.4.18CRYP initialization vector registers . . . . .813
23.4.19CRYP DMA interface . . . . .814
23.4.20CRYP error management . . . . .816
23.5CRYP interrupts . . . . .817
23.6CRYP processing time . . . . .818
23.7CRYP registers . . . . .819
23.7.1CRYP control register (CRYP_CR) . . . . .819
23.7.2CRYP status register (CRYP_SR) . . . . .821
23.7.3CRYP data input register (CRYP_DIN) . . . . .822
23.7.4CRYP data output register (CRYP_DOUT) . . . . .822
23.7.5CRYP DMA control register (CRYP_DMACR) . . . . .823
23.7.6CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . .824
23.7.7CRYP raw interrupt status register (CRYP_RISR) . . . . .824
23.7.8CRYP masked interrupt status register (CRYP_MISR) . . . . .825
23.7.9CRYP key register 0L (CRYP_K0LR) . . . . .826
23.7.10CRYP key register 0R (CRYP_K0RR) . . . . .826
23.7.11CRYP key register 1L (CRYP_K1LR) . . . . .827
23.7.12CRYP key register 1R (CRYP_K1RR) . . . . .827
23.7.13CRYP key register 2L (CRYP_K2LR) . . . . .828
23.7.14CRYP key register 2R (CRYP_K2RR) . . . . .828
23.7.15CRYP key register 3L (CRYP_K3LR) . . . . .829
23.7.16CRYP key register 3R (CRYP_K3RR) . . . . .829
23.7.17CRYP initialization vector register 0L (CRYP_IV0LR) . . . . .830
23.7.18CRYP initialization vector register 0R (CRYP_IV0RR) . . . . .830
23.7.19CRYP initialization vector register 1L (CRYP_IV1LR) . . . . .831
23.7.20CRYP initialization vector register 1R (CRYP_IV1RR) . . . . .831
23.7.21CRYP register map . . . . .831
24Hash processor (HASH) . . . . .833
24.1Introduction . . . . .833
24.2HASH main features . . . . .833
24.3HASH implementation . . . . .834
24.4HASH functional description . . . . .834
24.4.1HASH block diagram . . . . .834
24.4.2HASH internal signals . . . . .835
24.4.3About secure hash algorithms . . . . .835
24.4.4Message data feeding . . . . .835
24.4.5Message digest computing . . . . .837
24.4.6Message padding . . . . .838

25 Advanced-control timers (TIM1/TIM8) . . . . . 855

25.3.186-step PWM generation . . . . .899
25.3.19One-pulse mode . . . . .900
25.3.20Retriggerable one pulse mode . . . . .901
25.3.21Encoder interface mode . . . . .902
25.3.22UIF bit remapping . . . . .904
25.3.23Timer input XOR function . . . . .905
25.3.24Interfacing with Hall sensors . . . . .905
25.3.25Timer synchronization . . . . .908
25.3.26ADC synchronization . . . . .912
25.3.27DMA burst mode . . . . .912
25.3.28Debug mode . . . . .913
25.4TIM1/TIM8 registers . . . . .914
25.4.1TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . .914
25.4.2TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . .915
25.4.3TIMx slave mode control register
(TIMx_SMCR)(x = 1, 8) . . . . .		918
25.4.4TIMx DMA/interrupt enable register
(TIMx_DIER)(x = 1, 8) . . . . .		920
25.4.5TIMx status register (TIMx_SR)(x = 1, 8) . . . . .922
25.4.6TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . .924
25.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 1, 8) . . . . .925
25.4.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . .		926
25.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 1, 8) . . . . .929
25.4.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . .		930
25.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 1, 8) . . . . .		932
25.4.12TIMx counter (TIMx_CNT)(x = 1, 8) . . . . .935
25.4.13TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . .935
25.4.14TIMx auto-reload register (TIMx_ARR)(x = 1, 8) . . . . .935
25.4.15TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . .936
25.4.16TIMx capture/compare register 1
(TIMx_CCR1)(x = 1, 8) . . . . .		936
25.4.17TIMx capture/compare register 2
(TIMx_CCR2)(x = 1, 8) . . . . .		937
25.4.18TIMx capture/compare register 3
(TIMx_CCR3)(x = 1, 8) . . . . .		937
25.4.19TIMx capture/compare register 4
(TIMx_CCR4)(x = 1, 8) . . . . .		938

26.3.19Timer synchronization . . . . .992
26.3.20DMA burst mode . . . . .997
26.3.21Debug mode . . . . .998
26.4TIM2/TIM3/TIM4/TIM5 registers . . . . .999
26.4.1TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . .999
26.4.2TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . .1000
26.4.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . .1002
26.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . .1005
26.4.5TIMx status register (TIMx_SR)(x = 2 to 5) . . . . .1006
26.4.6TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . .1007
26.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) . . . . .1008
26.4.8TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5) . . . . .		1010
26.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) . . . . .1012
26.4.10TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5) . . . . .		1013
26.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 5) . . . . .		1014
26.4.12TIMx counter (TIMx_CNT)(x = 2 to 5) . . . . .1015
26.4.13TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) . . . . .1016
26.4.14TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . .1016
26.4.15TIMx auto-reload register (TIMx_ARR)(x = 2 to 5) . . . . .1017
26.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) . . . . .1017
26.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) . . . . .1018
26.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) . . . . .1018
26.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) . . . . .1019
26.4.20TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . .1020
26.4.21TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . .1020
26.4.22TIM2 option register (TIM2_OR) . . . . .1021
26.4.23TIM5 option register (TIM5_OR) . . . . .1021
26.4.24TIMx register map . . . . .1022
27General-purpose timers (TIM9/TIM10/TIM11/TIM12/TIM13/TIM14) . . . . .1025
27.1TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 introduction . . . . .1025
27.2TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 main features . . . . .1025
27.2.1TIM9/TIM12 main features . . . . .1025
27.2.2TIM10/TIM11/TIM13/TIM14 main features . . . . .1026
27.3TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 functional description . . . . .1028
27.3.1Time-base unit . . . . .1028
27.3.2Counter modes . . . . .1030
27.3.3Clock selection . . . . .1033
27.3.4Capture/compare channels . . . . .1035
27.3.5Input capture mode . . . . .1037
27.3.6PWM input mode (only for TIM9/TIM12) . . . . .1038
27.3.7Forced output mode . . . . .1039
27.3.8Output compare mode . . . . .1039
27.3.9PWM mode . . . . .1040
27.3.10Combined PWM mode (TIM9/TIM12 only) . . . . .1041
27.3.11One-pulse mode . . . . .1043
27.3.12Retriggerable one pulse mode (TIM12 only) . . . . .1044
27.3.13UIF bit remapping . . . . .1045
27.3.14TIM9/TIM12 external trigger synchronization . . . . .1045
27.3.15Slave mode – combined reset + trigger mode . . . . .1048
27.3.16Timer synchronization (TIM9/TIM12) . . . . .1049
27.3.17Using timer output as trigger for other timers (TIM10/TIM11/TIM13/TIM14)
1049
27.3.18Debug mode . . . . .1049
27.4TIM9/TIM12 registers . . . . .1049
27.4.1TIMx control register 1 (TIMx_CR1)(x = 9, 12) . . . . .1049
27.4.2TIMx slave mode control register (TIMx_SMCR)(x = 9, 12) . . . . .1050
27.4.3TIMx Interrupt enable register (TIMx_DIER)(x = 9, 12) . . . . .1052
27.4.4TIMx status register (TIMx_SR)(x = 9, 12) . . . . .1052
27.4.5TIMx event generation register (TIMx_EGR)(x = 9, 12) . . . . .1054
27.4.6TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 9, 12) . . . . .1055
27.4.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 9, 12) . . . . .		1056
27.4.8TIMx capture/compare enable register (TIMx_CCER)(x = 9, 12) . . . . .1058
27.4.9TIMx counter (TIMx_CNT)(x = 9, 12) . . . . .1059
27.4.10TIMx prescaler (TIMx_PSC)(x = 9, 12) . . . . .1060
27.4.11TIMx auto-reload register (TIMx_ARR)(x = 9, 12) . . . . .1060
27.4.12TIMx capture/compare register 1 (TIMx_CCR1)(x = 9, 12) . . . . .1060
27.4.13TIMx capture/compare register 2 (TIMx_CCR2)(x = 9, 12) . . . . .1061
27.4.14TIM9/TIM12 register map . . . . .1062
27.5TIM10/TIM11/TIM13/TIM14 registers . . . . .1064
27.5.1TIMx control register 1 (TIMx_CR1)(x = 10, 11, 13, 14) . . . . .1064
27.5.2TIMx Interrupt enable register (TIMx_DIER)(x = 10, 11, 13, 14) . . . .1065
27.5.3TIMx status register (TIMx_SR)(x = 10, 11, 13, 14) . . . . .1065
27.5.4TIMx event generation register (TIMx_EGR)(x = 10, 11, 13, 14) . . . .1066
27.5.5TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 10, 11, 13, 14) . . . . .		1067
27.5.6TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 10, 11, 13, 14) . . . . .		1068
27.5.7TIMx capture/compare enable register
(TIMx_CCER)(x = 10, 11, 13, 14) . . . . .		1070
27.5.8TIMx counter (TIMx_CNT)(x = 10, 11, 13, 14) . . . . .1071
27.5.9TIMx prescaler (TIMx_PSC)(x = 10, 11, 13, 14) . . . . .1072
27.5.10TIMx auto-reload register (TIMx_ARR)(x = 10, 11, 13, 14) . . . . .1072
27.5.11TIMx capture/compare register 1 (TIMx_CCR1)(x = 10, 11, 13, 14) . . . .1072
27.5.12TIM11 option register 1 (TIM11_OR) . . . . .1073
27.5.13TIM10/TIM11/TIM13/TIM14 register map . . . . .1073
28Basic timers (TIM6/TIM7) . . . . .1075
28.1TIM6/TIM7 introduction . . . . .1075
28.2TIM6/TIM7 main features . . . . .1075
28.3TIM6/TIM7 functional description . . . . .1076
28.3.1Time-base unit . . . . .1076
28.3.2Counting mode . . . . .1078
28.3.3UIF bit remapping . . . . .1081
28.3.4Clock source . . . . .1081
28.3.5Debug mode . . . . .1082
28.4TIM6/TIM7 registers . . . . .1082
28.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . .1082
28.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . .1084
28.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . .1084
28.4.4TIMx status register (TIMx_SR)(x = 6 to 7) . . . . .1085
28.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . .1085
28.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . .1085
28.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . .1086
28.4.8TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . .1086
28.4.9TIMx register map . . . . .1087
29Low-power timer (LPTIM) . . . . .1088
29.1Introduction . . . . .1088
30.3.3Hardware watchdog . . . . .1111
30.3.4Low-power freeze . . . . .1111
30.3.5Register access protection . . . . .1111
30.3.6Debug mode . . . . .1111
30.4IWDG registers . . . . .1112
30.4.1IWDG key register (IWDG_KR) . . . . .1112
30.4.2IWDG prescaler register (IWDG_PR) . . . . .1113
30.4.3IWDG reload register (IWDG_RLR) . . . . .1114
30.4.4IWDG status register (IWDG_SR) . . . . .1115
30.4.5IWDG window register (IWDG_WINR) . . . . .1116
30.4.6IWDG register map . . . . .1117
31System window watchdog (WWDG) . . . . .1118
31.1Introduction . . . . .1118
31.2WWDG main features . . . . .1118
31.3WWDG functional description . . . . .1118
31.3.1WWDG block diagram . . . . .1119
31.3.2Enabling the watchdog . . . . .1119
31.3.3Controlling the down-counter . . . . .1119
31.3.4How to program the watchdog timeout . . . . .1119
31.3.5Debug mode . . . . .1121
31.4WWDG interrupts . . . . .1121
31.5WWDG registers . . . . .1121
31.5.1WWDG control register (WWDG_CR) . . . . .1121
31.5.2WWDG configuration register (WWDG_CFR) . . . . .1122
31.5.3WWDG status register (WWDG_SR) . . . . .1122
31.5.4WWDG register map . . . . .1123
32Real-time clock (RTC) . . . . .1124
32.1Introduction . . . . .1124
32.2RTC main features . . . . .1125
32.3RTC functional description . . . . .1126
32.3.1RTC block diagram . . . . .1126
32.3.2GPIOs controlled by the RTC . . . . .1127
32.3.3Clock and prescalers . . . . .1129
32.3.4Real-time clock and calendar . . . . .1130
33Inter-integrated circuit interface (I2C) . . . . .1169
33.1Introduction . . . . .1169
33.2I2C main features . . . . .1169
33.3I2C implementation . . . . .1170
33.4I2C functional description . . . . .1170
33.4.1I2C block diagram . . . . .1171
33.4.2I2C pins and internal signals . . . . .1171
33.4.3I2C clock requirements . . . . .1172
33.4.4I2C mode selection . . . . .1172
33.4.5I2C initialization . . . . .1173
33.4.6I2C reset . . . . .1177
33.4.7I2C data transfer . . . . .1177
33.4.8I2C slave mode . . . . .1179
33.4.9I2C master mode . . . . .1188
33.4.10I2C_TIMINGR register configuration examples . . . . .1199
33.4.11SMBus specific features . . . . .1201
33.4.12SMBus initialization . . . . .1204
33.4.13SMBus I2C_TIMEOUTR register configuration examples . . . . .1206
33.4.14SMBus slave mode . . . . .1206
33.4.15SMBus master mode . . . . .1210
33.4.16Error conditions . . . . .1213
33.5I2C in low-power modes . . . . .1215
33.6I2C interrupts . . . . .1215
33.7I2C DMA requests . . . . .1216
33.7.1Transmission using DMA . . . . .1216
33.7.2Reception using DMA . . . . .1216
33.8I2C debug modes . . . . .1217
33.9I2C registers . . . . .1217
33.9.1I2C control register 1 (I2C_CR1) . . . . .1217
33.9.2I2C control register 2 (I2C_CR2) . . . . .1220
33.9.3I2C own address 1 register (I2C_OAR1) . . . . .1222
33.9.4I2C own address 2 register (I2C_OAR2) . . . . .1223
33.9.5I2C timing register (I2C_TIMINGR) . . . . .1224
33.9.6I2C timeout register (I2C_TIMEOUTR) . . . . .1225
33.9.7I2C interrupt and status register (I2C_ISR) . . . . .1226
33.9.8I2C interrupt clear register (I2C_ICR) . . . . .1228

34 Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . . 1232

34.8.5USART guard time and prescaler register (USART_GTPR) . . . . .1287
34.8.6USART receiver timeout register (USART_RTOR) . . . . .1289
34.8.7USART request register (USART_RQR) . . . . .1290
34.8.8USART interrupt and status register (USART_ISR) . . . . .1291
34.8.9USART interrupt flag clear register (USART_ICR) . . . . .1295
34.8.10USART receive data register (USART_RDR) . . . . .1297
34.8.11USART transmit data register (USART_TDR) . . . . .1297
34.8.12USART register map . . . . .1298
35Serial peripheral interface / integrated interchip sound (SPI/I2S) .1300
35.1Introduction . . . . .1300
35.2SPI main features . . . . .1300
35.3I2S main features . . . . .1301
35.4SPI/I2S implementation . . . . .1301
35.5SPI functional description . . . . .1302
35.5.1General description . . . . .1302
35.5.2Communications between one master and one slave . . . . .1303
35.5.3Standard multislave communication . . . . .1305
35.5.4Multimaster communication . . . . .1306
35.5.5Slave select (NSS) pin management . . . . .1307
35.5.6Communication formats . . . . .1308
35.5.7Configuration of SPI . . . . .1310
35.5.8Procedure for enabling SPI . . . . .1311
35.5.9Data transmission and reception procedures . . . . .1311
35.5.10SPI status flags . . . . .1321
35.5.11SPI error flags . . . . .1322
35.5.12NSS pulse mode . . . . .1323
35.5.13TI mode . . . . .1323
35.5.14CRC calculation . . . . .1324
35.6SPI interrupts . . . . .1326
35.7I2S functional description . . . . .1327
35.7.1I2S general description . . . . .1327
35.7.2I2S full duplex . . . . .1328
35.7.3Supported audio protocols . . . . .1329
35.7.4Start-up description . . . . .1336
35.7.5Clock generator . . . . .1338
35.7.6I 2 S master mode .....1341
35.7.7I 2 S slave mode .....1342
35.7.8I2S status flags .....1344
35.7.9I2S error flags .....1345
35.7.10DMA features .....1346
35.8I2S interrupts .....1346
35.9SPI and I2S registers .....1347
35.9.1SPI control register 1 (SPIx_CR1) .....1347
35.9.2SPI control register 2 (SPIx_CR2) .....1349
35.9.3SPI status register (SPIx_SR) .....1351
35.9.4SPI data register (SPIx_DR) .....1353
35.9.5SPI CRC polynomial register (SPIx_CRCPR) .....1353
35.9.6SPI Rx CRC register (SPIx_RXCRCR) .....1353
35.9.7SPI Tx CRC register (SPIx_TXCRCR) .....1354
35.9.8SPIx_I2S configuration register (SPIx_I2SCFGR) .....1354
35.9.9SPIx_I2S prescaler register (SPIx_I2SPR) .....1356
35.9.10SPI/I2S register map .....1358
36Serial audio interface (SAI) .....1359
36.1Introduction .....1359
36.2SAI main features .....1359
36.3SAI functional description .....1360
36.3.1SAI block diagram .....1360
36.3.2SAI pins and internal signals .....1361
36.3.3Main SAI modes .....1362
36.3.4SAI synchronization mode .....1363
36.3.5Audio data size .....1364
36.3.6Frame synchronization .....1364
36.3.7Slot configuration .....1367
36.3.8SAI clock generator .....1369
36.3.9Internal FIFOs .....1371
36.3.10AC'97 link controller .....1373
36.3.11SPDIF output .....1375
36.3.12Specific features .....1377
36.3.13Error flags .....1381
36.3.14Disabling the SAI .....1384
36.3.15SAI DMA interface .....1384
36.4SAI interrupts . . . . .1385
36.5SAI registers . . . . .1387
36.5.1SAI global configuration register (SAI_GCR) . . . . .1387
36.5.2SAI configuration register 1 (SAI_ACR1) . . . . .1387
36.5.3SAI configuration register 2 (SAI_ACR2) . . . . .1390
36.5.4SAI frame configuration register (SAI_AFRCCR) . . . . .1392
36.5.5SAI slot register (SAI_ASLOTR) . . . . .1393
36.5.6SAI interrupt mask register (SAI_AIM) . . . . .1394
36.5.7SAI status register (SAI_ASR) . . . . .1395
36.5.8SAI clear flag register (SAI_ACLRFR) . . . . .1397
36.5.9SAI data register (SAI_ADR) . . . . .1398
36.5.10SAI configuration register 1 (SAI_BCR1) . . . . .1399
36.5.11SAI configuration register 2 (SAI_BCR2) . . . . .1401
36.5.12SAI frame configuration register (SAI_BFRCCR) . . . . .1403
36.5.13SAI slot register (SAI_BSLOTR) . . . . .1404
36.5.14SAI interrupt mask register (SAI_BIM) . . . . .1405
36.5.15SAI status register (SAI_BSR) . . . . .1406
36.5.16SAI clear flag register (SAI_BCLRFR) . . . . .1408
36.5.17SAI data register (SAI_BDR) . . . . .1409
36.5.18SAI register map . . . . .1410
37SPDIFRX receiver interface (SPDIFRX) . . . . .1412
37.1SPDIFRX interface introduction . . . . .1412
37.2SPDIFRX main features . . . . .1412
37.3SPDIFRX functional description . . . . .1412
37.3.1S/PDIF protocol (IEC-60958) . . . . .1413
37.3.2SPDIFRX decoder (SPDIFRX_DC) . . . . .1416
37.3.3SPDIFRX tolerance to clock deviation . . . . .1419
37.3.4SPDIFRX synchronization . . . . .1419
37.3.5SPDIFRX handling . . . . .1421
37.3.6Data reception management . . . . .1423
37.3.7Dedicated control flow . . . . .1425
37.3.8Reception errors . . . . .1426
37.3.9Clocking strategy . . . . .1428
37.3.10DMA interface . . . . .1428
37.3.11Interrupt generation . . . . .1429
37.3.12Register protection . . . . .1430
37.4Programming procedures . . . . .1431
37.4.1Initialization phase . . . . .1431
37.4.2Handling of interrupts coming from SPDIFRX . . . . .1432
37.4.3Handling of interrupts coming from DMA . . . . .1432
37.5SPDIFRX interface registers . . . . .1433
37.5.1SPDIFRX control register (SPDIFRX_CR) . . . . .1433
37.5.2SPDIFRX interrupt mask register (SPDIFRX_IMR) . . . . .1435
37.5.3SPDIFRX status register (SPDIFRX_SR) . . . . .1436
37.5.4SPDIFRX interrupt flag clear register (SPDIFRX_IFCR) . . . . .1438
37.5.5SPDIFRX data input register (SPDIFRX_FMT0_DR) . . . . .1439
37.5.6SPDIFRX data input register (SPDIFRX_FMT1_DR) . . . . .1439
37.5.7SPDIFRX data input register (SPDIFRX_FMT2_DR) . . . . .1440
37.5.8SPDIFRX channel status register (SPDIFRX_CSR) . . . . .1441
37.5.9SPDIFRX debug information register (SPDIFRX_DIR) . . . . .1441
37.5.10SPDIFRX interface register map . . . . .1442
38Management data input/output (MDIOS) . . . . .1443
38.1MDIOS introduction . . . . .1443
38.2MDIOS main features . . . . .1443
38.3MDIOS functional description . . . . .1444
38.3.1MDIOS block diagram . . . . .1444
38.3.2MDIOS protocol . . . . .1444
38.3.3MDIOS enabling and disabling . . . . .1445
38.3.4MDIOS data . . . . .1445
38.3.5MDIOS APB frequency . . . . .1447
38.3.6Write/read flags and interrupts . . . . .1447
38.3.7MDIOS error management . . . . .1447
38.3.8MDIOS in Stop mode . . . . .1448
38.3.9MDIOS interrupts . . . . .1448
38.4MDIOS registers . . . . .1449
38.4.1MDIOS configuration register (MDIOS_CR) . . . . .1449
38.4.2MDIOS write flag register (MDIOS_WRFR) . . . . .1450
38.4.3MDIOS clear write flag register (MDIOS_CWRFR) . . . . .1450
38.4.4MDIOS read flag register (MDIOS_RDFR) . . . . .1450
38.4.5MDIOS clear read flag register (MDIOS_CRDFR) . . . . .1451
38.4.6MDIOS status register (MDIOS_SR) . . . . .1451
38.4.7MDIOS clear flag register (MDIOS_CLRFR) . . . . .1452
38.4.8MDIOS input data register x (MDIOS_DINRx) . . . . .1452
38.4.9MDIOS output data register x (MDIOS_DOUTRx) . . . . .1453
38.4.10MDIOS register map . . . . .1453
39SD/SDIO/MMC card host interface (SDMMC) . . . . .1455
39.1SDMMC main features . . . . .1455
39.2SDMMC bus topology . . . . .1455
39.3SDMMC functional description . . . . .1457
39.3.1SDMMC adapter . . . . .1459
39.3.2SDMMC APB2 interface . . . . .1470
39.4Card functional description . . . . .1471
39.4.1Card identification mode . . . . .1471
39.4.2Card reset . . . . .1472
39.4.3Operating voltage range validation . . . . .1472
39.4.4Card identification process . . . . .1472
39.4.5Block write . . . . .1473
39.4.6Block read . . . . .1474
39.4.7Stream access, stream write and stream read
(MultiMediaCard only) . . . . .		1474
39.4.8Erase: group erase and sector erase . . . . .1476
39.4.9Wide bus selection or deselection . . . . .1476
39.4.10Protection management . . . . .1476
39.4.11Card status register . . . . .1480
39.4.12SD status register . . . . .1483
39.4.13SD I/O mode . . . . .1487
39.4.14Commands and responses . . . . .1488
39.5Response formats . . . . .1491
39.5.1R1 (normal response command) . . . . .1492
39.5.2R1b . . . . .1492
39.5.3R2 (CID, CSD register) . . . . .1492
39.5.4R3 (OCR register) . . . . .1493
39.5.5R4 (Fast I/O) . . . . .1493
39.5.6R4b . . . . .1493
39.5.7R5 (interrupt request) . . . . .1494
39.5.8R6 . . . . .1494
39.6SDIO I/O card-specific operations . . . . .1495
39.6.1SDIO I/O read wait operation by SDMMC_D2 signalling . . . . .1495
39.6.2SDIO read wait operation by stopping SDMMC_CK . . . . .1496
39.6.3SDIO suspend/resume operation . . . . .1496
39.6.4SDIO interrupts . . . . .1496
39.7HW flow control . . . . .1496
39.8SDMMC registers . . . . .1497
39.8.1SDMMC power control register (SDMMC_POWER) . . . . .1497
39.8.2SDMMC clock control register (SDMMC_CLKCR) . . . . .1497
39.8.3SDMMC argument register (SDMMC_ARG) . . . . .1500
39.8.4SDMMC command register (SDMMC_CMD) . . . . .1500
39.8.5SDMMC command response register (SDMMC_RESPCMD) . . . . .1501
39.8.6SDMMC response 1..4 register (SDMMC_RESPx) . . . . .1501
39.8.7SDMMC data timer register (SDMMC_DTIMER) . . . . .1502
39.8.8SDMMC data length register (SDMMC_DLEN) . . . . .1503
39.8.9SDMMC data control register (SDMMC_DCTRL) . . . . .1503
39.8.10SDMMC data counter register (SDMMC_DCOUNT) . . . . .1506
39.8.11SDMMC status register (SDMMC_STA) . . . . .1506
39.8.12SDMMC interrupt clear register (SDMMC_ICR) . . . . .1507
39.8.13SDMMC mask register (SDMMC_MASK) . . . . .1509
39.8.14SDMMC FIFO counter register (SDMMC_FIFOCNT) . . . . .1511
39.8.15SDMMC data FIFO register (SDMMC_FIFO) . . . . .1512
39.8.16SDMMC register map . . . . .1513
40Controller area network (bxCAN) . . . . .1515
40.1Introduction . . . . .1515
40.2bxCAN main features . . . . .1515
40.3bxCAN general description . . . . .1516
40.3.1CAN 2.0B active core . . . . .1516
40.3.2Control, status, and configuration registers . . . . .1517
40.3.3Tx mailboxes . . . . .1517
40.3.4Acceptance filters . . . . .1517
40.4bxCAN operating modes . . . . .1519
40.4.1Initialization mode . . . . .1519
40.4.2Normal mode . . . . .1520
40.4.3Sleep mode (low-power) . . . . .1520
40.5Test mode . . . . .1521
40.5.1Silent mode .....1521
40.5.2Loop back mode .....1522
40.5.3Loop back combined with silent mode .....1522
40.6Behavior in debug mode .....1523
40.7bxCAN functional description .....1523
40.7.1Transmission handling .....1523
40.7.2Time triggered communication mode .....1525
40.7.3Reception handling .....1525
40.7.4Identifier filtering .....1526
40.7.5Message storage .....1530
40.7.6Error management .....1531
40.7.7Bit timing .....1532
40.8bxCAN interrupts .....1535
40.9CAN registers .....1536
40.9.1Register access protection .....1536
40.9.2CAN control and status registers .....1536
40.9.3CAN mailbox registers .....1546
40.9.4CAN filter registers .....1552
40.9.5bxCAN register map .....1556
41USB on-the-go full-speed/high-speed
(OTG_FS/OTG_HS) .....		1560
41.1Introduction .....1560
41.2OTG_FS/OTG_HS main features .....1562
41.2.1General features .....1562
41.2.2Host-mode features .....1563
41.2.3Peripheral-mode features .....1563
41.3OTG_FS/OTG_HS implementation .....1564
41.4OTG_FS/OTG_HS functional description .....1565
41.4.1OTG_FS/OTG_HS block diagram .....1565
41.4.2OTG_FS/OTG_HS pin and internal signals .....1566
41.4.3OTG_FS/OTG_HS core .....1567
41.4.4Embedded full-speed OTG PHY connected to OTG_FS .....1567
41.4.5Embedded full-speed OTG PHY connected to OTG_HS .....1568
41.4.6OTG detections .....1568
41.4.7High-speed OTG PHY connected to OTG_HS .....1568
41.5OTG_FS/OTG_HS dual role device (DRD) . . . . .1569
41.5.1ID line detection . . . . .1569
41.5.2HNP dual role device . . . . .1569
41.5.3SRP dual role device . . . . .1570
41.6OTG_FS/OTG_HS as a USB peripheral . . . . .1570
41.6.1SRP-capable peripheral . . . . .1571
41.6.2Peripheral states . . . . .1571
41.6.3Peripheral endpoints . . . . .1572
41.7OTG_FS/OTG_HS as a USB host . . . . .1574
41.7.1SRP-capable host . . . . .1575
41.7.2USB host states . . . . .1575
41.7.3Host channels . . . . .1577
41.7.4Host scheduler . . . . .1578
41.8OTG_FS/OTG_HS SOF trigger . . . . .1579
41.8.1Host SOFs . . . . .1579
41.8.2Peripheral SOFs . . . . .1579
41.9OTG_FS/OTG_HS low-power modes . . . . .1580
41.10OTG_FS/OTG_HS Dynamic update of the OTG_HFIR register . . . . .1581
41.11OTG_FS/OTG_HS data FIFOs . . . . .1581
41.11.1Peripheral FIFO architecture . . . . .1582
41.11.2Host FIFO architecture . . . . .1583
41.11.3FIFO RAM allocation . . . . .1584
41.12OTG_FS system performance . . . . .1586
41.13OTG_FS/ OTG_HS interrupts . . . . .1586
41.14OTG_FS/ OTG_HS control and status registers . . . . .1588
41.14.1CSR memory map . . . . .1588
41.15OTG_FS/ OTG_HS registers . . . . .1594
41.15.1OTG control and status register (OTG_GOTGCTL) . . . . .1594
41.15.2OTG interrupt register (OTG_GOTGINT) . . . . .1597
41.15.3OTG AHB configuration register (OTG_GAHBCFG) . . . . .1599
41.15.4OTG USB configuration register (OTG_GUSBCFG) . . . . .1601
41.15.5OTG reset register (OTG_GRSTCTL) . . . . .1604
41.15.6OTG core interrupt register (OTG_GINTSTS) . . . . .1607
41.15.7OTG interrupt mask register (OTG_GINTMSK) . . . . .1612
41.15.8OTG receive status debug read register (OTG_GRXSTSR) . . . . .1615
41.15.9OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . .1616
41.15.10OTG status read and pop registers (OTG_GRXSTSP) . . . . .1617
41.15.11OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . .1618
41.15.12OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .1619
41.15.13OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . .		1620
41.15.14OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . .		1621
41.15.15OTG general core configuration register (OTG_GCCFG) . . . . .1622
41.15.16OTG core ID register (OTG_CID) . . . . .1623
41.15.17OTG core LPM configuration register (OTG_GLPMCFG) . . . . .1624
41.15.18OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . .		1628
41.15.19OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . .		1628
41.15.20Host-mode registers . . . . .1629
41.15.21OTG host configuration register (OTG_HCFG) . . . . .1629
41.15.22OTG host frame interval register (OTG_HFIR) . . . . .1630
41.15.23OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . .		1631
41.15.24OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . .		1631
41.15.25OTG host all channels interrupt register (OTG_HAINT) . . . . .1632
41.15.26OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . .		1633
41.15.27OTG host port control and status register (OTG_HPRT) . . . . .1634
41.15.28OTG host channel x characteristics register (OTG_HCCHARx) . . . . .1636
41.15.29OTG host channel x split control register (OTG_HCSPLTx) . . . . .1637
41.15.30OTG host channel x interrupt register (OTG_HCINTx) . . . . .1638
41.15.31OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . . . .1640
41.15.32OTG host channel x transfer size register (OTG_HCTSIZx) . . . . .1641
41.15.33OTG host channel x DMA address register (OTG_HCDMAx) . . . . .1642
41.15.34Device-mode registers . . . . .1643
41.15.35OTG device configuration register (OTG_DCFG) . . . . .1643
41.15.36OTG device control register (OTG_DCTL) . . . . .1645
41.15.37OTG device status register (OTG_DSTS) . . . . .1647
41.15.38OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . .		1648
41.15.39OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . .		1649
41.15.40OTG device all endpoints interrupt register (OTG_DAININT) . . . . .1651
41.15.41OTG all endpoints interrupt mask register
(OTG_DAININTMSK) . . . . .		1651
41.15.42OTG device V BUS discharge time register
(OTG_DVBUSDIS) . . . . .		1652
41.15.43OTG device V BUS pulsing time register
(OTG_DVBUSPULSE) . . . . .		1652
41.15.44OTG device threshold control register (OTG_DTHRCTL) . . . . .1653
41.15.45OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) . . . . .		1654
41.15.46OTG device each endpoint interrupt register (OTG_DEACHINT) . . . . .1654
41.15.47OTG device each endpoint interrupt mask register
(OTG_DEACHINTMSK) . . . . .		1655
41.15.48OTG device each IN endpoint-1 interrupt mask register
(OTG_HS_DIEPEACHMSK1) . . . . .		1655
41.15.49OTG device each OUT endpoint-1 interrupt mask register
(OTG_HS_DOEPEACHMSK1) . . . . .		1656
41.15.50OTG device control IN endpoint 0 control register
(OTG_DIEPCTL0) . . . . .		1658
41.15.51OTG device IN endpoint x control register (OTG_DIEPCTLx) . . . . .1659
41.15.52OTG device IN endpoint x interrupt register (OTG_DIEPINTx) . . . . .1661
41.15.53OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) . . . . .		1663
41.15.54OTG device IN endpoint x DMA address register
(OTG_DIEPDMAx) . . . . .		1664
41.15.55OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) . . . . .		1664
41.15.56OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) . . . . .1665
41.15.57OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0) . . . . .		1666
41.15.58OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . . . . .1667
41.15.59OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0) . . . . .		1669
41.15.60OTG device OUT endpoint x DMA address register
(OTG_DOEPDMAx) . . . . .		1670
41.15.61OTG device OUT endpoint x control register
(OTG_DOEPCTLx) . . . . .		1670
41.15.62OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx) . . . . .		1672
41.15.63OTG power and clock gating control register (OTG_PCGCCTL) . . . . .1673
41.15.64OTG_FS/OTG_HS register map . . . . .1674
41.16OTG_FS/OTG_HS programming model . . . . .1687
41.16.1Core initialization .....1687
41.16.2Host initialization .....1688
41.16.3Device initialization .....1689
41.16.4DMA mode .....1689
41.16.5Host programming model .....1689
41.16.6Device programming model .....1723
41.16.7Worst case response time .....1743
41.16.8OTG programming model .....1745
42Ethernet (ETH): media access control (MAC) with DMA controller .....1751
42.1Ethernet introduction .....1751
42.2Ethernet main features .....1751
42.2.1MAC core features .....1752
42.2.2DMA features .....1753
42.2.3PTP features .....1753
42.3Ethernet pins .....1754
42.4Ethernet functional description: SMI, MII and RMII .....1755
42.4.1Station management interface: SMI .....1755
42.4.2Media-independent interface: MII .....1759
42.4.3Reduced media-independent interface: RMII .....1761
42.4.4MII/RMII selection .....1762
42.5Ethernet functional description: MAC 802.3 .....1763
42.5.1MAC 802.3 frame format .....1763
42.5.2MAC frame transmission .....1767
42.5.3MAC frame reception .....1774
42.5.4MAC interrupts .....1780
42.5.5MAC filtering .....1780
42.5.6MAC loopback mode .....1783
42.5.7MAC management counters: MMC .....1783
42.5.8Power management: PMT .....1784
42.5.9Precision time protocol (IEEE1588 PTP) .....1787
42.6Ethernet functional description: DMA controller operation .....1793
42.6.1Initialization of a transfer using DMA .....1794
42.6.2Host bus burst access .....1794
42.6.3Host data buffer alignment .....1795
42.6.4Buffer size calculations .....1795

43.7.5CEC interrupt and status register (CEC_ISR) .....1886
43.7.6CEC interrupt enable register (CEC_IER) .....1888
43.7.7HDMI-CEC register map .....1890
44Debug support (DBG) .....1891
44.1Overview .....1891
44.2Reference Arm® documentation .....1892
44.3SWJ debug port (serial wire and JTAG) .....1892
44.3.1Mechanism to select the JTAG-DP or the SW-DP .....1893
44.4Pinout and debug port pins .....1893
44.4.1SWJ debug port pins .....1894
44.4.2Flexible SWJ-DP pin assignment .....1894
44.4.3Internal pull-up and pull-down on JTAG pins .....1895
44.4.4Using serial wire and releasing the unused debug pins as GPIOs ..1896
44.5STM32F76xxx and STM32F77xxx JTAG Debug Port connection .....1896
44.6ID codes and locking mechanism .....1898
44.6.1MCU device ID code .....1898
44.6.2Boundary scan Debug Port .....1898
44.6.3Cortex®-M7 with FPU Debug Port .....1898
44.6.4Cortex®-M7 with FPU JEDEC-106 ID code .....1899
44.7JTAG debug port .....1899
44.8SW debug port .....1901
44.8.1SW protocol introduction .....1901
44.8.2SW protocol sequence .....1901
44.8.3SW-DP state machine (reset, idle states, ID code) .....1902
44.8.4DP and AP read/write accesses .....1903
44.8.5SW-DP registers .....1903
44.8.6SW-AP registers .....1904
44.9AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP .....		1905
44.10Core debug .....1906
44.11Capability of the debugger host to connect under system reset .....1907
44.12FPB (Flash patch breakpoint) .....1907
44.13DWT (data watchpoint trigger) .....1908
44.14ITM (instrumentation trace macrocell) .....1908
44.14.1General description .....1908
44.14.2Time stamp packets, synchronization and overflow packets . . . . .1908
44.15ETM (Embedded trace macrocell) . . . . .1910
44.15.1General description . . . . .1910
44.15.2Signal protocol, packet types . . . . .1910
44.15.3Main ETM registers . . . . .1911
44.15.4Configuration example . . . . .1911
44.16MCU debug component (DBGMCU) . . . . .1911
44.16.1Debug support for low-power modes . . . . .1911
44.16.2Debug support for timers, watchdog, bxCAN and I 2 C . . . . .1912
44.16.3Debug MCU configuration register . . . . .1912
44.16.4DBGMCU_CR register . . . . .1912
44.16.5Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . .1914
44.16.6Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . .1916
44.17Pelican TPIU (trace port interface unit) . . . . .1917
44.17.1Introduction . . . . .1917
44.17.2TRACE pin assignment . . . . .1918
44.17.3TPIU formatter . . . . .1920
44.17.4TPIU frame synchronization packets . . . . .1920
44.17.5Transmission of the synchronization frame packet . . . . .1920
44.17.6Synchronous mode . . . . .1921
44.17.7Asynchronous mode . . . . .1921
44.17.8TRACECLKIN connection inside the
STM32F76xxx and STM32F77xxx . . . . .		1921
44.17.9TPIU registers . . . . .1922
44.17.10Example of configuration . . . . .1922
44.18DBG register map . . . . .1923
45Device electronic signature . . . . .1924
45.1Unique device ID register (96 bits) . . . . .1924
45.2Flash size . . . . .1925
45.3Package data register . . . . .1926
46Important security notice . . . . .1927
47Revision history . . . . .1935

List of tables

Table 1.STM32F76xxx and STM32F77xxx register boundary addresses . . . . .78
Table 2.Boot modes . . . . .82
Table 3.2 Mbytes of flash memory single bank organization (256 bits read width) . . . . .88
Table 4.2 Mbytes of flash memory dual bank organization (128 bits read width) . . . . .88
Table 5.1 Mbyte flash memory single bank organization (256 bits read width) . . . . .89
Table 6.1 Mbyte flash memory dual bank organization (128 bits read width) . . . . .90
Table 7.Number of wait states according to CPU clock (HCLK) frequency . . . . .91
Table 8.Maximum program/erase parallelism . . . . .93
Table 9.Flash interrupt request . . . . .99
Table 10.Option byte organization . . . . .99
Table 11.Access versus read protection level . . . . .104
Table 12.OTP area organization . . . . .107
Table 13.Flash register map and reset values . . . . .116
Table 14.Voltage regulator configuration mode versus device operating mode . . . . .124
Table 15.Low-power mode summary . . . . .129
Table 16.Features over all modes . . . . .130
Table 17.Sleep-now entry and exit . . . . .134
Table 18.Sleep-on-exit entry and exit . . . . .135
Table 19.Stop operating modes . . . . .135
Table 20.Stop mode entry and exit (STM32F76xxx and STM32F77xxx) . . . . .137
Table 21.Standby mode entry and exit . . . . .139
Table 22.PWR - register map and reset values . . . . .150
Table 23.RCC register map and reset values . . . . .218
Table 24.Port bit configuration table . . . . .223
Table 25.GPIO register map and reset values . . . . .238
Table 26.SYSCFG register map and reset values . . . . .247
Table 27.DMA1 request mapping . . . . .252
Table 28.DMA2 request mapping . . . . .252
Table 29.Source and destination address . . . . .254
Table 30.Source and destination address registers in double-buffer mode (DBM = 1) . . . . .259
Table 31.Packing/unpacking and endian behavior (bit PINC = MINC = 1) . . . . .260
Table 32.Restriction on NDT versus PSIZE and MSIZE . . . . .260
Table 33.FIFO threshold configurations . . . . .263
Table 34.Possible DMA configurations . . . . .267
Table 35.DMA interrupt requests . . . . .269
Table 36.DMA register map and reset values . . . . .279
Table 37.Supported color mode in input . . . . .286
Table 38.Data order in memory . . . . .287
Table 39.Alpha mode configuration . . . . .288
Table 40.Supported CLUT color mode . . . . .289
Table 41.CLUT data order in system memory . . . . .289
Table 42.Supported color mode in output . . . . .290
Table 43.Data order in memory . . . . .291
Table 44.DMA2D interrupt requests . . . . .296
Table 45.DMA2D register map and reset values . . . . .312
Table 46.STM32F76xxx and STM32F77xxx vector table . . . . .314
Table 47.External interrupt/event controller register map and reset values . . . . .326
Table 48.CRC internal input/output signals . . . . .328
Table 49.CRC register map and reset values . . . . .333
Table 50.NOR/PSRAM bank selection . . . . .338
Table 51.NOR/PSRAM External memory address . . . . .339
Table 52.NAND memory mapping and timing registers. . . . .339
Table 53.NAND bank selection . . . . .339
Table 54.SDRAM bank selection. . . . .340
Table 55.SDRAM address mapping . . . . .340
Table 56.SDRAM address mapping with 8-bit data bus width. . . . .341
Table 57.SDRAM address mapping with 16-bit data bus width. . . . .341
Table 58.SDRAM address mapping with 32-bit data bus width. . . . .342
Table 59.Programmable NOR/PSRAM access parameters . . . . .344
Table 60.Non-multiplexed I/O NOR flash memory. . . . .345
Table 61.16-bit multiplexed I/O NOR flash memory . . . . .345
Table 62.Non-multiplexed I/Os PSRAM/SRAM . . . . .345
Table 63.16-Bit multiplexed I/O PSRAM . . . . .346
Table 64.NOR flash/PSRAM: example of supported memories
and transactions . . . . .		347
Table 65.FMC_BCRx bitfields (mode 1) . . . . .350
Table 66.FMC_BTRx bitfields (mode 1) . . . . .350
Table 67.FMC_BCRx bitfields (mode A) . . . . .352
Table 68.FMC_BTRx bitfields (mode A) . . . . .352
Table 69.FMC_BWTRx bitfields (mode A). . . . .353
Table 70.FMC_BCRx bitfields (mode 2/B). . . . .355
Table 71.FMC_BTRx bitfields (mode 2/B). . . . .355
Table 72.FMC_BWTRx bitfields (mode 2/B) . . . . .356
Table 73.FMC_BCRx bitfields (mode C) . . . . .357
Table 74.FMC_BTRx bitfields (mode C) . . . . .358
Table 75.FMC_BWTRx bitfields (mode C). . . . .358
Table 76.FMC_BCRx bitfields (mode D) . . . . .360
Table 77.FMC_BTRx bitfields (mode D) . . . . .360
Table 78.FMC_BWTRx bitfields (mode D). . . . .361
Table 79.FMC_BCRx bitfields (Muxed mode) . . . . .362
Table 80.FMC_BTRx bitfields (Muxed mode) . . . . .363
Table 81.FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .368
Table 82.FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .369
Table 83.FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .370
Table 84.FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .371
Table 85.Programmable NAND flash access parameters . . . . .379
Table 86.8-bit NAND flash . . . . .379
Table 87.16-bit NAND flash . . . . .380
Table 88.Supported memories and transactions . . . . .380
Table 89.ECC result relevant bits . . . . .389
Table 90.SDRAM signals. . . . .390
Table 91.FMC register map and reset values . . . . .407
Table 92.QUADSPI pins . . . . .411
Table 93.QUADSPI interrupt requests. . . . .425
Table 94.QUADSPI register map and reset values . . . . .436
Table 95.ADC pins. . . . .440
Table 96.Analog watchdog channel selection . . . . .446
Table 97.Configuring the trigger polarity . . . . .451
Table 98.External trigger for regular channels. . . . .451
Table 99.External trigger for injected channels . . . . .452
Table 100.ADC interrupts . . . . .467
Table 101.ADC global register map. . . . .482
Table 102.ADC register map and reset values for each ADC . . . . .482
Table 103.ADC register map and reset values (common ADC registers) . . . . .484
Table 104.DAC pins. . . . .486
Table 105.External triggers . . . . .489
Table 106.DAC register map . . . . .506
Table 107.DFSDM1 implementation . . . . .509
Table 108.DFSDM external pins . . . . .511
Table 109.DFSDM internal signals . . . . .511
Table 110.DFSDM triggers connection . . . . .511
Table 111.DFSDM break connection. . . . .512
Table 112.Filter maximum output resolution (peak data values from filter output)
for some FOSR values . . . . .		526
Table 113.Integrator maximum output resolution (peak data values from integrator
output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . . .		526
Table 114.DFSDM interrupt requests . . . . .534
Table 115.DFSDM register map and reset values. . . . .554
Table 116.DCMI input/output pins . . . . .565
Table 117.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .567
Table 118.Positioning of captured data bytes in 32-bit words (10-bit width) . . . . .567
Table 119.Positioning of captured data bytes in 32-bit words (12-bit width) . . . . .567
Table 120.Positioning of captured data bytes in 32-bit words (14-bit width) . . . . .568
Table 121.Data storage in monochrome progressive video format. . . . .573
Table 122.Data storage in RGB progressive video format . . . . .574
Table 123.Data storage in YCbCr progressive video format . . . . .574
Table 124.Data storage in YCbCr progressive video format - Y extraction mode . . . . .574
Table 125.DCMI interrupts. . . . .575
Table 126.DCMI register map and reset values . . . . .585
Table 127.LTDC pins and signal interface. . . . .587
Table 128.Clock domain for each register . . . . .588
Table 129.Pixel data mapping versus color format . . . . .593
Table 130.LTDC interrupt requests . . . . .597
Table 131.LTDC register map and reset values . . . . .616
Table 132.DSI pins . . . . .621
Table 133.DSI internal input/output signals . . . . .622
Table 134.Location of color components in the LTDC interface . . . . .625
Table 135.Multiplicity of the payload size in pixels for each data type . . . . .626
Table 136.Contention detection timeout counters configuration . . . . .638
Table 137.List of events of different categories of the PRESP_TO counter . . . . .639
Table 138.PRESP_TO counter configuration . . . . .642
Table 139.Frame requirement configuration registers. . . . .654
Table 140.RGB components . . . . .656
Table 141.Slew-rate and delay tuning . . . . .658
Table 142.Custom lane configuration . . . . .659
Table 143.Custom timing parameters . . . . .659
Table 144.HS2LP and LP2HS values . . . . .660
Table 145.DSI Wrapper interrupt requests . . . . .663
Table 146.Error causes and recovery . . . . .664
Table 147.DSI register map and reset values . . . . .731
Table 148.JPEG codec interrupt requests . . . . .742
Table 149.JPEG codec register map and reset values . . . . .755
Table 150.RNG internal input/output signals . . . . .758
Table 151.RNG interrupt requests . . . . .763
Table 152.RNG configurations . . . . .764
Table 153.RNG register map and reset map . . . . .767
Table 154.CRYP internal input/output signals . . . . .770
Table 155.Counter mode initialization vector . . . . .796
Table 156.GCM last block definition . . . . .799
Table 157.GCM mode IV registers initialization . . . . .799
Table 158.CCM mode IV registers initialization . . . . .806
Table 159.DES/TDES data swapping example . . . . .810
Table 160.AES data swapping example . . . . .811
Table 161.Key endianness in CRYP_KxR/LR registers (AES 128/192/256-bit keys) . . . . .813
Table 162.Key endianness in CRYP_KxR/LR registers (DES K1 and TDES K1/2/3) . . . . .813
Table 163.Initialization vector endianness in CRYP_IVx(L/R)R registers (AES) . . . . .814
Table 164.Initialization vector endianness in CRYP_IVx(L/R)R registers (DES/TDES) . . . . .814
Table 165.Cryptographic processor configuration for memory-to-peripheral DMA transfers . . . . .814
Table 166.Cryptographic processor configuration for peripheral-to-memory DMA transfers . . . . .815
Table 167.CRYP interrupt requests . . . . .817
Table 168.Processing latency for ECB, CBC and CTR . . . . .818
Table 169.Processing time (in clock cycle) for GCM and CCM per 128-bit block . . . . .818
Table 170.CRYP register map and reset values . . . . .831
Table 171.HASH internal input/output signals . . . . .835
Table 172.Hash processor outputs . . . . .838
Table 173.Processing time (in clock cycle) . . . . .844
Table 174.HASH interrupt requests . . . . .845
Table 175.HASH register map and reset values . . . . .853
Table 176.Behavior of timer outputs versus BRK/BRK2 inputs . . . . .896
Table 177.Counting direction versus encoder signals . . . . .903
Table 178.TIMx internal trigger connection . . . . .920
Table 179.Output control bits for complementary OCx and OCxN channels with break feature . . . . .934
Table 180.TIM1 register map and reset values . . . . .948
Table 181.TIM8 register map and reset values . . . . .950
Table 182.Counting direction versus encoder signals . . . . .987
Table 183.TIMx internal trigger connection . . . . .1005
Table 184.Output control bit for standard OCx channels . . . . .1015
Table 185.TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . .1022
Table 186.TIMx internal trigger connection . . . . .1052
Table 187.Output control bit for standard OCx channels . . . . .1059
Table 188.TIM9/TIM12 register map and reset values . . . . .1062
Table 189.Output control bit for standard OCx channels . . . . .1071
Table 190.TIM10/TIM11/TIM13/TIM14 register map and reset values . . . . .1073
Table 191.TIMx register map and reset values . . . . .1087
Table 192.STM32F76xxx and STM32F77xxx LPTIM features . . . . .1089
Table 193.LPTIM1 external trigger connection . . . . .1090
Table 194.Prescaler division ratios . . . . .1091
Table 195.Encoder counting scenarios . . . . .1097
Table 196.Effect of low-power modes on the LPTIM . . . . .1098
Table 197.Interrupt events . . . . .1099
Table 198.LPTIM register map and reset values . . . . .1108
Table 199.IWDG register map and reset values . . . . .1117
Table 200.WWDG register map and reset values . . . . .1123
Table 201.RTC pin PC13 configuration . . . . .1127
Table 202.RTC pin PI8 configuration . . . . .1128
Table 203.RTC pin PC2 configuration . . . . .1129
Table 204.RTC functions over modes . . . . .1129
Table 205.Effect of low-power modes on RTC . . . . .1141
Table 206.Interrupt control bits . . . . .1142
Table 207.RTC register map and reset values . . . . .1167
Table 208.I2C implementation . . . . .1170
Table 209.I2C input/output pins . . . . .1171
Table 210.I2C internal input/output signals . . . . .1171
Table 211.Comparison of analog and digital filters . . . . .1173
Table 212.I 2 C-bus and SMBus specification data setup and hold times . . . . .1176
Table 213.I2C configuration . . . . .1179
Table 214.I 2 C-bus and SMBus specification clock timings . . . . .1190
Table 215.Timing settings for f I2CCLK of 8 MHz . . . . .1200
Table 216.Timing settings for f I2CCLK of 16 MHz . . . . .1200
Table 217.Timing settings for f I2CCLK of 48 MHz . . . . .1201
Table 218.SMBus timeout specifications . . . . .1203
Table 219.SMBus with PEC configuration . . . . .1204
Table 220.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms . . . . .1206
Table 221.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .1206
Table 222.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .1206
Table 223.Effect of low-power modes to I2C . . . . .1215
Table 224.I2C interrupt requests . . . . .1215
Table 225.I2C register map and reset values . . . . .1231
Table 226.STM32F76xxx and STM32F77xxx USART features . . . . .1234
Table 227.Noise detection from sampled data . . . . .1246
Table 228.Error calculation for programmed baud rates at f CK = 216 MHz
in both cases of oversampling by 8 (OVER8 = 1) . . . . .		1249
Table 229.Error calculation for programmed baud rates at f CK = 216 MHz
in both cases of oversampling by 16 (OVER8 = 0) . . . . .		1249
Table 230.Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .1251
Table 231.Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . .1251
Table 232.Frame formats . . . . .1255
Table 233.Effect of low-power modes on the USART . . . . .1274
Table 234.USART interrupt requests . . . . .1274
Table 235.USART register map and reset values . . . . .1298
Table 236.STM32F76xxx and STM32F77xxx SPI and SPI/I2S implementation . . . . .1301
Table 237.SPI interrupt requests . . . . .1326
Table 238.Audio-frequency precision using 48 MHz clock derived from HSE . . . . .1340
Table 239.I2S interrupt requests . . . . .1346
Table 240.SPI/I2S register map and reset values . . . . .1358
Table 241.SAI internal input/output signals . . . . .1361
Table 242.SAI input/output pins . . . . .1361
Table 243.External synchronization selection . . . . .1364
Table 244.Example of possible audio frequency sampling range . . . . .1370
Table 245.SOPD pattern . . . . .1375
Table 246.Parity bit calculation . . . . .1376
Table 247.Audio sampling frequency versus symbol rates . . . . .1377
Table 248.SAI interrupt sources . . . . .1385
Table 249.SAI register map and reset values . . . . .1410
Table 250.Transition sequence for preamble . . . . .1418
Table 251.Minimum SPDIFRX_CLK frequency versus audio sampling rate . . . . .1428
Table 252.Bit field property versus SPDIFRX state . . . . .1430
Table 253.SPDIFRX interface register map and reset values . . . . .1442
Table 254.Interrupt control bits . . . . .1448
Table 255.MDIOS register map and reset values . . . . .1453
Table 256.SDMMC I/O definitions . . . . .1458
Table 257.Command format . . . . .1463
Table 258.Short response format . . . . .1464
Table 259.Long response format . . . . .1464
Table 260.Command path status flags . . . . .1464
Table 261.Data token format . . . . .1467
Table 262.DPSM flags . . . . .1468
Table 263.Transmit FIFO status flags . . . . .1469
Table 264.Receive FIFO status flags . . . . .1469
Table 265.Card status . . . . .1480
Table 266.SD status . . . . .1483
Table 267.Speed class code field . . . . .1484
Table 268.Performance move field . . . . .1485
Table 269.AU_SIZE field . . . . .1485
Table 270.Maximum AU size . . . . .1485
Table 271.Erase size field . . . . .1486
Table 272.Erase timeout field . . . . .1486
Table 273.Erase offset field . . . . .1486
Table 274.Block-oriented write commands . . . . .1489
Table 275.Block-oriented write protection commands . . . . .1490
Table 276.Erase commands . . . . .1490
Table 277.I/O mode commands . . . . .1490
Table 278.Lock card . . . . .1491
Table 279.Application-specific commands . . . . .1491
Table 280.R1 response . . . . .1492
Table 281.R2 response . . . . .1492
Table 282.R3 response . . . . .1493
Table 283.R4 response . . . . .1493
Table 284.R4b response . . . . .1493
Table 285.R5 response . . . . .1494
Table 286.R6 response . . . . .1495
Table 287.Response type and SDMMC_RESPx registers . . . . .1502
Table 288.SDMMC register map . . . . .1513
Table 289.CAN implementation . . . . .1516
Table 290.Transmit mailbox mapping . . . . .1531
Table 291.Receive mailbox mapping . . . . .1531
Table 292.bxCAN register map and reset values . . . . .1556
Table 293.OTG_HS speeds supported . . . . .1561
Table 294.OTG_FS speeds supported . . . . .1561
Table 295.OTG_FS/OTG_HS implementation . . . . .1564
Table 296.OTG_FS input/output pins . . . . .1566
Table 297.OTG_HS input/output pins . . . . .1566
Table 298.OTG_FS/OTG_HS input/output signals . . . . .1567
Table 299.Compatibility of STM32 low power modes with the OTG . . . . .1580
Table 300.Core global control and status registers (CSRs) . . . . .1588
Table 301.Host-mode control and status registers (CSRs) . . . . .1589
Table 302.Device-mode control and status registers . . . . .1591
Table 303.Data FIFO (DFIFO) access register map . . . . .1594
Table 304.Power and clock gating control and status registers . . . . .1594
Table 305.TRDT values (FS). . . . .1604
Table 306.TRDT values (HS) . . . . .1604
Table 307.Minimum duration for soft disconnect . . . . .1646
Table 308.OTG_FS/OTG_HS register map and reset values . . . . .1674
Table 309.Alternate function mapping . . . . .1754
Table 310.Management frame format . . . . .1756
Table 311.Clock range . . . . .1758
Table 312.TX interface signal encoding . . . . .1760
Table 313.RX interface signal encoding . . . . .1760
Table 314.Frame statuses . . . . .1776
Table 315.Destination address filtering . . . . .1782
Table 316.Source address filtering . . . . .1783
Table 317.Receive descriptor 0 - encoding for bits 7, 5 and 0 (normal descriptor format only, EDFE=0). . . . .1814
Table 318.Time stamp snapshot dependency on registers bits . . . . .1848
Table 319.Ethernet register map and reset values . . . . .1869
Table 320.HDMI pin . . . . .1874
Table 321.Error handling timing parameters . . . . .1880
Table 322.TXERR timing parameters . . . . .1881
Table 323.HDMI-CEC interrupts . . . . .1882
Table 324.HDMI-CEC register map and reset values . . . . .1890
Table 325.SWJ debug port pins . . . . .1894
Table 326.Flexible SWJ-DP pin assignment . . . . .1894
Table 327.JTAG debug port data registers . . . . .1899
Table 328.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .1901
Table 329.Packet request (8-bits) . . . . .1902
Table 330.ACK response (3 bits). . . . .1902
Table 331.DATA transfer (33 bits). . . . .1902
Table 332.SW-DP registers . . . . .1903
Table 333.Cortex ® -M7 with FPU AHB-AP registers . . . . .1905
Table 334.Core debug registers . . . . .1906
Table 335.Main ITM registers . . . . .1909
Table 336.Asynchronous TRACE pin assignment . . . . .1918
Table 337.Synchronous TRACE pin assignment . . . . .1918
Table 338.Flexible TRACE pin assignment . . . . .1919
Table 339.Important TPIU registers . . . . .1922
Table 340.DBG register map and reset values . . . . .1923
Table 341.Document revision history . . . . .1935

List of figures

Figure 1.System architecture for STM32F76xxx and STM32F77xxx devices . . . . .72
Figure 2.Memory map . . . . .77
Figure 3.Flash memory interface connection inside system architecture
(STM32F76xxx and STM32F77xxx) . . . . .		85
Figure 4.RDP levels . . . . .105
Figure 5.Power supply overview (STM32F769xx and STM32F779xx devices) . . . . .118
Figure 6.VDDUSB connected to VDD power supply . . . . .119
Figure 7.VDDUSB connected to external independent power supply . . . . .120
Figure 8.Backup domain . . . . .123
Figure 9.Power-on reset/power-down reset waveform . . . . .126
Figure 10.BOR thresholds . . . . .127
Figure 11.PVD thresholds . . . . .128
Figure 12.Simplified diagram of the reset circuit . . . . .152
Figure 13.Clock tree . . . . .154
Figure 14.HSE/ LSE clock sources . . . . .157
Figure 15.Frequency measurement with TIM5 in Input capture mode . . . . .162
Figure 16.Frequency measurement with TIM11 in Input capture mode . . . . .163
Figure 17.Basic structure of an I/O port bit . . . . .222
Figure 18.Basic structure of a 5-Volt tolerant I/O port bit . . . . .222
Figure 19.Input floating / pull up / pull down configurations . . . . .227
Figure 20.Output configuration . . . . .228
Figure 21.Alternate function configuration . . . . .229
Figure 22.High impedance-analog configuration . . . . .229
Figure 23.DMA block diagram . . . . .250
Figure 24.Channel selection . . . . .252
Figure 25.Peripheral-to-memory mode . . . . .255
Figure 26.Memory-to-peripheral mode . . . . .256
Figure 27.Memory-to-memory mode . . . . .257
Figure 28.FIFO structure . . . . .262
Figure 29.DMA2D block diagram . . . . .285
Figure 30.External interrupt/event controller block diagram . . . . .320
Figure 31.External interrupt/event GPIO mapping . . . . .322
Figure 32.CRC calculation unit block diagram . . . . .328
Figure 33.FMC block diagram . . . . .335
Figure 34.FMC memory banks . . . . .338
Figure 35.Mode 1 read access waveforms . . . . .349
Figure 36.Mode 1 write access waveforms . . . . .349
Figure 37.Mode A read access waveforms . . . . .351
Figure 38.Mode A write access waveforms . . . . .351
Figure 39.Mode 2 and mode B read access waveforms . . . . .353
Figure 40.Mode 2 write access waveforms . . . . .354
Figure 41.Mode B write access waveforms . . . . .354
Figure 42.Mode C read access waveforms . . . . .356
Figure 43.Mode C write access waveforms . . . . .357
Figure 44.Mode D read access waveforms . . . . .359
Figure 45.Mode D write access waveforms . . . . .359
Figure 46.Muxed read access waveforms . . . . .361
Figure 47.Muxed write access waveforms . . . . .362
Figure 48.Asynchronous wait during a read access waveforms . . . . .364
Figure 49.Asynchronous wait during a write access waveforms . . . . .365
Figure 50.Wait configuration waveforms . . . . .367
Figure 51.Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . .368
Figure 52.Synchronous multiplexed write mode waveforms - PSRAM (CRAM) . . . . .370
Figure 53.NAND flash controller waveforms for common memory access . . . . .381
Figure 54.Access to non 'CE don't care' NAND-flash . . . . .383
Figure 55.Burst write SDRAM access waveforms . . . . .392
Figure 56.Burst read SDRAM access . . . . .393
Figure 57.Logic diagram of Read access with RBURST bit set (CAS=1, RPIPE=0) . . . . .394
Figure 58.Read access crossing row boundary . . . . .396
Figure 59.Write access crossing row boundary . . . . .396
Figure 60.Self-refresh mode . . . . .399
Figure 61.Power-down mode . . . . .400
Figure 62.QUADSPI block diagram when dual-flash mode is disabled . . . . .410
Figure 63.QUADSPI block diagram when dual-flash mode is enabled . . . . .411
Figure 64.Example of read command in quad-SPI mode . . . . .412
Figure 65.Example of a DDR command in quad-SPI mode . . . . .415
Figure 66.NCS when CKMODE = 0 (T = CLK period) . . . . .423
Figure 67.NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .423
Figure 68.NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . .424
Figure 69.NCS when CKMODE = 1 with an abort (T = CLK period) . . . . .424
Figure 70.Single ADC block diagram . . . . .439
Figure 71.ADC1 connectivity . . . . .441
Figure 72.ADC2 connectivity . . . . .442
Figure 73.ADC3 connectivity . . . . .443
Figure 74.Timing diagram . . . . .446
Figure 75.Analog watchdog's guarded area . . . . .446
Figure 76.Injected conversion latency . . . . .448
Figure 77.Right alignment of 12-bit data . . . . .450
Figure 78.Left alignment of 12-bit data . . . . .450
Figure 79.Left alignment of 6-bit data . . . . .450
Figure 80.Multi ADC block diagram (1) . . . . .455
Figure 81.Injected simultaneous mode on 4 channels: dual ADC mode . . . . .458
Figure 82.Injected simultaneous mode on 4 channels: triple ADC mode . . . . .458
Figure 83.Regular simultaneous mode on 16 channels: dual ADC mode . . . . .459
Figure 84.Regular simultaneous mode on 16 channels: triple ADC mode . . . . .459
Figure 85.Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode . . . . .460
Figure 86.Interleaved mode on 1 channel in continuous conversion mode: triple ADC mode . . . . .461
Figure 87.Alternate trigger: injected group of each ADC . . . . .462
Figure 88.Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . .462
Figure 89.Alternate trigger: injected group of each ADC . . . . .463
Figure 90.Alternate + regular simultaneous . . . . .464
Figure 91.Case of trigger occurring during injected conversion . . . . .464
Figure 92.Temperature sensor and VREFINT channel block diagram . . . . .465
Figure 93.DAC channel block diagram . . . . .486
Figure 94.DAC output buffer connection . . . . .487
Figure 95.Data registers in single DAC channel mode . . . . .488
Figure 96.Data registers in dual DAC channel mode . . . . .488
Figure 97.Timing diagram for conversion with trigger disabled TEN = 0 . . . . .489
Figure 98.DAC LFSR register calculation algorithm . . . . .491
Figure 99.DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .491
Figure 100. DAC triangle wave generation . . . . .492
Figure 101. DAC conversion (SW trigger enabled) with triangle wave generation . . . . .492
Figure 102. Single DFSDM block diagram. . . . .510
Figure 103. Input channel pins redirection. . . . .514
Figure 104. Channel transceiver timing diagrams . . . . .516
Figure 105. Clock absence timing diagram for SPI . . . . .517
Figure 106. Clock absence timing diagram for Manchester coding . . . . .518
Figure 107. First conversion for Manchester coding (Manchester synchronization) . . . . .520
Figure 108. DFSDM_CHyDATINR registers operation modes and assignment . . . . .524
Figure 109. Example: Sinc3 filter response . . . . .525
Figure 110. DCMI block diagram . . . . .565
Figure 111. Top-level block diagram . . . . .565
Figure 112. DCMI signal waveforms . . . . .566
Figure 113. Timing diagram . . . . .568
Figure 114. Frame capture waveforms in snapshot mode. . . . .570
Figure 115. Frame capture waveforms in continuous grab mode . . . . .571
Figure 116. Coordinates and size of the window after cropping . . . . .571
Figure 117. Data capture waveforms. . . . .572
Figure 118. Pixel raster scan order . . . . .573
Figure 119. LTDC block diagram . . . . .587
Figure 120. LCD-TFT synchronous timings . . . . .590
Figure 121. Layer window programmable parameters . . . . .593
Figure 122. Blending two layers with background . . . . .596
Figure 123. Interrupt events. . . . .597
Figure 124. DSI block diagram . . . . .621
Figure 125. DSI Host architecture . . . . .623
Figure 126. Flow to update the LTDC interface configuration using shadow registers . . . . .628
Figure 127. Immediate update procedure . . . . .629
Figure 128. Configuration update during the transmission of a frame. . . . .629
Figure 129. Adapted command mode usage flow . . . . .631
Figure 130. 24 bpp APB pixel to byte organization . . . . .635
Figure 131. 18 bpp APB pixel to byte organization . . . . .636
Figure 132. 16 bpp APB pixel to byte organization . . . . .636
Figure 133. 12 bpp APB pixel to byte organization . . . . .637
Figure 134. 8 bpp APB pixel to byte organization . . . . .637
Figure 135. Timing of PRESP_TO after a bus-turn-around. . . . .640
Figure 136. Timing of PRESP_TO after a read request (HS or LP). . . . .641
Figure 137. Timing of PRESP_TO after a write request (HS or LP) . . . . .642
Figure 138. Effect of prep mode at 1 . . . . .643
Figure 139. Command transmission periods within the image area . . . . .644
Figure 140. Transmission of commands on the last line of a frame. . . . .645
Figure 141. LPSIZE for non-burst with sync pulses. . . . .646
Figure 142. LPSIZE for burst or non-burst with sync events . . . . .646
Figure 143. VLPSIZE for non-burst with sync pulses . . . . .648
Figure 144. VLPSIZE for non-burst with sync events . . . . .648
Figure 145. VLPSIZE for burst mode. . . . .648
Figure 146. Location of LPSIZE and VLPSIZE in the image area . . . . .650
Figure 147. Clock lane and data lane in HS . . . . .651
Figure 148. Clock lane in HS and data lanes in LP . . . . .652
Figure 149. Clock lane and data lane in LP. . . . .652
Figure 150. Command transmission by the generic interface . . . . .653
Figure 151. Vertical color bar mode. . . . .655
Figure 152. Horizontal color bar mode. . . . .655
Figure 153. RGB888 BER testing pattern . . . . .656
Figure 154. Vertical pattern (103x15) . . . . .657
Figure 155. Horizontal pattern (103x15) . . . . .657
Figure 156. PLL block diagram . . . . .661
Figure 157. Error sources . . . . .664
Figure 158. Video packet transmission configuration flow diagram. . . . .675
Figure 159. Programming sequence to send a test pattern. . . . .677
Figure 160. Frame configuration registers. . . . .678
Figure 161. JPEG codec block diagram . . . . .737
Figure 162. RNG block diagram . . . . .758
Figure 163. Entropy source model. . . . .759
Figure 164. CRYPT block diagram . . . . .770
Figure 165. AES-ECB mode overview. . . . .773
Figure 166. AES-CBC mode overview. . . . .774
Figure 167. AES-CTR mode overview. . . . .775
Figure 168. AES-GCM mode overview . . . . .776
Figure 169. AES-GMAC mode overview . . . . .776
Figure 170. AES-CCM mode overview . . . . .777
Figure 171. Example of suspend mode management. . . . .783
Figure 172. DES/TDES-ECB mode encryption . . . . .784
Figure 173. DES/TDES-ECB mode decryption . . . . .785
Figure 174. DES/TDES-CBC mode encryption . . . . .786
Figure 175. DES/TDES-CBC mode decryption . . . . .787
Figure 176. AES-ECB mode encryption . . . . .789
Figure 177. AES-ECB mode decryption . . . . .790
Figure 178. AES-CBC mode encryption . . . . .791
Figure 179. AES-CBC mode decryption . . . . .792
Figure 180. Message construction for the Counter mode . . . . .794
Figure 181. AES-CTR mode encryption . . . . .795
Figure 182. AES-CTR mode decryption . . . . .796
Figure 183. Message construction for the Galois/counter mode . . . . .798
Figure 184. Message construction for the Galois Message Authentication Code mode . . . . .803
Figure 185. Message construction for the Counter with CBC-MAC mode. . . . .804
Figure 186. 64-bit block construction according to the data type (IN FIFO). . . . .811
Figure 187. 128-bit block construction according to the data type. . . . .812
Figure 188. HASH block diagram . . . . .834
Figure 189. Message data swapping feature. . . . .836
Figure 190. HASH suspend/resume mechanism. . . . .842
Figure 191. Advanced-control timer block diagram . . . . .856
Figure 192. Counter timing diagram with prescaler division change from 1 to 2. . . . .858
Figure 193. Counter timing diagram with prescaler division change from 1 to 4. . . . .858
Figure 194. Counter timing diagram, internal clock divided by 1 . . . . .860
Figure 195. Counter timing diagram, internal clock divided by 2 . . . . .860
Figure 196. Counter timing diagram, internal clock divided by 4 . . . . .861
Figure 197. Counter timing diagram, internal clock divided by N. . . . .861
Figure 198. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .862
Figure 199. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .862
Figure 200. Counter timing diagram, internal clock divided by 1 . . . . .864
Figure 201. Counter timing diagram, internal clock divided by 2 . . . . .864
Figure 202. Counter timing diagram, internal clock divided by 4 . . . . .865
Figure 203. Counter timing diagram, internal clock divided by N. . . . .865
Figure 204. Counter timing diagram, update event when repetition counter is not used . . . . .866
Figure 205. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .867
Figure 206. Counter timing diagram, internal clock divided by 2 . . . . .868
Figure 207. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .868
Figure 208. Counter timing diagram, internal clock divided by N . . . . .869
Figure 209. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .869
Figure 210. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .870
Figure 211. Update rate examples depending on mode and TIMx_RCR register settings . . . . .871
Figure 212. External trigger input block . . . . .872
Figure 213. Control circuit in normal mode, internal clock divided by 1 . . . . .873
Figure 214. TI2 external clock connection example . . . . .874
Figure 215. Control circuit in external clock mode 1 . . . . .875
Figure 216. External trigger input block . . . . .875
Figure 217. Control circuit in external clock mode 2 . . . . .876
Figure 218. Capture/compare channel (example: channel 1 input stage) . . . . .877
Figure 219. Capture/compare channel 1 main circuit . . . . .878
Figure 220. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .878
Figure 221. Output stage of capture/compare channel (channel 4) . . . . .879
Figure 222. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .879
Figure 223. PWM input mode timing . . . . .881
Figure 224. Output compare mode, toggle on OC1 . . . . .883
Figure 225. Edge-aligned PWM waveforms (ARR=8) . . . . .884
Figure 226. Center-aligned PWM waveforms (ARR=8) . . . . .885
Figure 227. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .887
Figure 228. Combined PWM mode on channel 1 and 3 . . . . .888
Figure 229. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .889
Figure 230. Complementary output with dead-time insertion . . . . .890
Figure 231. Dead-time waveforms with delay greater than the negative pulse . . . . .890
Figure 232. Dead-time waveforms with delay greater than the positive pulse . . . . .891
Figure 233. Break and Break2 circuitry overview . . . . .893
Figure 234. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .895
Figure 235. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .896
Figure 236. PWM output state following BRK assertion (OSSI=0) . . . . .897
Figure 237. Clearing TIMx_OCxREF . . . . .898
Figure 238. 6-step generation, COM example (OSSR=1) . . . . .899
Figure 239. Example of one pulse mode . . . . .900
Figure 240. Retriggerable one pulse mode . . . . .902
Figure 241. Example of counter operation in encoder interface mode . . . . .903
Figure 242. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .904
Figure 243. Measuring time interval between edges on 3 signals . . . . .905
Figure 244. Example of Hall sensor interface . . . . .907
Figure 245. Control circuit in reset mode . . . . .908
Figure 246. Control circuit in Gated mode . . . . .909
Figure 247. Control circuit in trigger mode . . . . .910
Figure 248. Control circuit in external clock mode 2 + trigger mode . . . . .911
Figure 249. General-purpose timer block diagram . . . . .954
Figure 250. Counter timing diagram with prescaler division change from 1 to 2 . . . . .956
Figure 251. Counter timing diagram with prescaler division change from 1 to 4 . . . . .956
Figure 252. Counter timing diagram, internal clock divided by 1 . . . . .957
Figure 253. Counter timing diagram, internal clock divided by 2 . . . . .958
Figure 254. Counter timing diagram, internal clock divided by 4 . . . . .958
Figure 255. Counter timing diagram, internal clock divided by N . . . . .959
Figure 256. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .959
Figure 257. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .960
Figure 258. Counter timing diagram, internal clock divided by 1 . . . . .961
Figure 259. Counter timing diagram, internal clock divided by 2 . . . . .961
Figure 260. Counter timing diagram, internal clock divided by 4 . . . . .962
Figure 261. Counter timing diagram, internal clock divided by N . . . . .962
Figure 262. Counter timing diagram, Update event . . . . .963
Figure 263. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .964
Figure 264. Counter timing diagram, internal clock divided by 2 . . . . .965
Figure 265. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .965
Figure 266. Counter timing diagram, internal clock divided by N . . . . .966
Figure 267. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .966
Figure 268. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .967
Figure 269. Control circuit in normal mode, internal clock divided by 1 . . . . .968
Figure 270. TI2 external clock connection example. . . . .968
Figure 271. Control circuit in external clock mode 1 . . . . .969
Figure 272. External trigger input block . . . . .970
Figure 273. Control circuit in external clock mode 2 . . . . .971
Figure 274. Capture/Compare channel (example: channel 1 input stage) . . . . .972
Figure 275. Capture/Compare channel 1 main circuit . . . . .972
Figure 276. Output stage of Capture/Compare channel (channel 1). . . . .973
Figure 277. PWM input mode timing . . . . .975
Figure 278. Output compare mode, toggle on OC1 . . . . .977
Figure 279. Edge-aligned PWM waveforms (ARR=8). . . . .978
Figure 280. Center-aligned PWM waveforms (ARR=8). . . . .979
Figure 281. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .980
Figure 282. Combined PWM mode on channels 1 and 3 . . . . .982
Figure 283. Clearing TIMx_OCxREF . . . . .983
Figure 284. Example of one-pulse mode. . . . .984
Figure 285. Retriggerable one-pulse mode . . . . .986
Figure 286. Example of counter operation in encoder interface mode . . . . .987
Figure 287. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .988
Figure 288. Control circuit in reset mode . . . . .989
Figure 289. Control circuit in gated mode . . . . .990
Figure 290. Control circuit in trigger mode. . . . .991
Figure 291. Control circuit in external clock mode 2 + trigger mode . . . . .992
Figure 292. Master/Slave timer example . . . . .993
Figure 293. Master/slave connection example with 1 channel only timers . . . . .993
Figure 294. Gating TIM with OC1REF of TIM3 . . . . .994
Figure 295. Gating TIM with Enable of TIM3 . . . . .995
Figure 296. Triggering TIM with update of TIM3 . . . . .996
Figure 297. Triggering TIM with Enable of TIM3 . . . . .996
Figure 298. Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . .997
Figure 299. General-purpose timer block diagram (TIM9/TIM12) . . . . .1026
Figure 300. General-purpose timer block diagram (TIM10/TIM11/TIM13/TIM14). . . . .1027
Figure 301. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1029
Figure 302. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1029
Figure 303. Counter timing diagram, internal clock divided by 1 . . . . .1030
Figure 304. Counter timing diagram, internal clock divided by 2 . . . . .1031
Figure 305. Counter timing diagram, internal clock divided by 4 . . . . .1031
Figure 306. Counter timing diagram, internal clock divided by N . . . . .1032
Figure 307. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . .1032
Figure 308. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . .		1033
Figure 309. Control circuit in normal mode, internal clock divided by 1 . . . . .1034
Figure 310. TI2 external clock connection example. . . . .1034
Figure 311. Control circuit in external clock mode 1 . . . . .1035
Figure 312. Capture/compare channel (example: channel 1 input stage) . . . . .1036
Figure 313. Capture/compare channel 1 main circuit . . . . .1036
Figure 314. Output stage of capture/compare channel (channel 1). . . . .1037
Figure 315. PWM input mode timing . . . . .1039
Figure 316. Output compare mode, toggle on OC1. . . . .1040
Figure 317. Edge-aligned PWM waveforms (ARR=8) . . . . .1041
Figure 318. Combined PWM mode on channel 1 and 2 . . . . .1042
Figure 319. Example of one pulse mode. . . . .1043
Figure 320. Retriggerable one pulse mode . . . . .1045
Figure 321. Control circuit in reset mode . . . . .1046
Figure 322. Control circuit in gated mode . . . . .1047
Figure 323. Control circuit in trigger mode. . . . .1047
Figure 324. Basic timer block diagram. . . . .1075
Figure 325. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1077
Figure 326. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1077
Figure 327. Counter timing diagram, internal clock divided by 1 . . . . .1078
Figure 328. Counter timing diagram, internal clock divided by 2 . . . . .1079
Figure 329. Counter timing diagram, internal clock divided by 4 . . . . .1079
Figure 330. Counter timing diagram, internal clock divided by N. . . . .1080
Figure 331. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . .		1080
Figure 332. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . .		1081
Figure 333. Control circuit in normal mode, internal clock divided by 1 . . . . .1082
Figure 334. Low-power timer block diagram . . . . .1089
Figure 335. Glitch filter timing diagram . . . . .1091
Figure 336. LPTIM output waveform, single counting mode configuration . . . . .1093
Figure 337. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set). . . . .		1093
Figure 338. LPTIM output waveform, Continuous counting mode configuration . . . . .1094
Figure 339. Waveform generation . . . . .1095
Figure 340. Encoder mode counting sequence . . . . .1098
Figure 341. Independent watchdog block diagram . . . . .1109
Figure 342. Watchdog block diagram . . . . .1119
Figure 343. Window watchdog timing diagram . . . . .1120
Figure 344. RTC block diagram . . . . .1126
Figure 345. Block diagram . . . . .1171
Figure 346. I 2 C-bus protocol . . . . .1173
Figure 347. Setup and hold timings . . . . .1174
Figure 348. I2C initialization flow . . . . .1177
Figure 349. Data reception . . . . .1178
Figure 350. Data transmission . . . . .1178
Figure 351. Slave initialization flow . . . . .1182
Figure 352. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0. . . . .1183
Figure 353. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1. . . . .1184
Figure 354. Transfer bus diagrams for I2C slave transmitter (mandatory events only). . . . .1185
Figure 355.Transfer sequence flow for I2C slave receiver, NOSTRETCH = 01186
Figure 356.Transfer sequence flow for I2C slave receiver, NOSTRETCH = 11187
Figure 357.Transfer bus diagrams for I2C slave receiver
(mandatory events only)		1187
Figure 358.Master clock generation1189
Figure 359.Master initialization flow1191
Figure 360.10-bit address read access with HEAD10R = 01191
Figure 361.10-bit address read access with HEAD10R = 11192
Figure 362.Transfer sequence flow for I2C master transmitter, N ≤ 255 bytes1193
Figure 363.Transfer sequence flow for I2C master transmitter, N > 255 bytes1194
Figure 364.Transfer bus diagrams for I2C master transmitter
(mandatory events only)		1195
Figure 365.Transfer sequence flow for I2C master receiver, N ≤ 255 bytes1197
Figure 366.Transfer sequence flow for I2C master receiver, N > 255 bytes1198
Figure 367.Transfer bus diagrams for I2C master receiver
(mandatory events only)		1199
Figure 368.Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \)1203
Figure 369.Transfer sequence flow for SMBus slave transmitter N bytes + PEC1207
Figure 370.Transfer bus diagram for SMBus slave transmitter (SBC = 1)1207
Figure 371.Transfer sequence flow for SMBus slave receiver N bytes + PEC1209
Figure 372.Bus transfer diagrams for SMBus slave receiver (SBC = 1)1210
Figure 373.Bus transfer diagrams for SMBus master transmitter1211
Figure 374.Bus transfer diagrams for SMBus master receiver1213
Figure 375.USART block diagram1236
Figure 376.Word length programming1238
Figure 377.Configurable stop bits1240
Figure 378.TC/TXE behavior when transmitting1241
Figure 379.Start bit detection when oversampling by 16 or 81242
Figure 380.Data sampling when oversampling by 161245
Figure 381.Data sampling when oversampling by 81246
Figure 382.Mute mode using Idle line detection1253
Figure 383.Mute mode using address mark detection1254
Figure 384.Break detection in LIN mode (11-bit break length - LBDL bit is set)1257
Figure 385.Break detection in LIN mode vs. Framing error detection1258
Figure 386.USART example of synchronous transmission1259
Figure 387.USART data clock timing diagram (M bits = 00)1259
Figure 388.USART data clock timing diagram (M bits = 01)1260
Figure 389.RX data setup/hold time1260
Figure 390.ISO 7816-3 asynchronous protocol1262
Figure 391.Parity error detection using the 1.5 stop bits1263
Figure 392.IrDA SIR ENDEC- block diagram1267
Figure 393.IrDA data modulation (3/16) - normal mode1267
Figure 394.Transmission using DMA1269
Figure 395.Reception using DMA1270
Figure 396.Hardware flow control between 2 USARTs1270
Figure 397.RS232 RTS flow control1271
Figure 398.RS232 CTS flow control1272
Figure 399.USART interrupt mapping diagram1275
Figure 400.SPI block diagram1302
Figure 401.Full-duplex single master/ single slave application1303
Figure 402.Half-duplex single master/ single slave application1304
Figure 403.Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .1305
Figure 404. Master and three independent slaves. . . . .1306
Figure 405. Multimaster application . . . . .1307
Figure 406. Hardware/software slave select management . . . . .1308
Figure 407. Data clock timing diagram . . . . .1309
Figure 408. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .1310
Figure 409. Packing data in FIFO for transmission and reception . . . . .1314
Figure 410. Master full-duplex communication . . . . .1317
Figure 411. Slave full-duplex communication . . . . .1318
Figure 412. Master full-duplex communication with CRC . . . . .1319
Figure 413. Master full-duplex communication in packed mode . . . . .1320
Figure 414. NSSP pulse generation in Motorola SPI master mode. . . . .1323
Figure 415. TI mode transfer . . . . .1324
Figure 416. I2S block diagram . . . . .1327
Figure 417. Full-duplex communication. . . . .1329
Figure 418. I 2 S Philips protocol waveforms (16/32-bit full accuracy). . . . .1330
Figure 419. I 2 S Philips standard waveforms (24-bit frame) . . . . .1330
Figure 420. Transmitting 0x8EAA33 . . . . .1331
Figure 421. Receiving 0x8EAA33 . . . . .1331
Figure 422. I 2 S Philips standard (16-bit extended to 32-bit packet frame) . . . . .1331
Figure 423. Example of 16-bit data frame extended to 32-bit channel frame . . . . .1331
Figure 424. MSB Justified 16-bit or 32-bit full-accuracy length . . . . .1332
Figure 425. MSB justified 24-bit frame length . . . . .1332
Figure 426. MSB justified 16-bit extended to 32-bit packet frame . . . . .1333
Figure 427. LSB justified 16-bit or 32-bit full-accuracy . . . . .1333
Figure 428. LSB justified 24-bit frame length . . . . .1333
Figure 429. Operations required to transmit 0x3478AE. . . . .1334
Figure 430. Operations required to receive 0x3478AE . . . . .1334
Figure 431. LSB justified 16-bit extended to 32-bit packet frame . . . . .1334
Figure 432. Example of 16-bit data frame extended to 32-bit channel frame . . . . .1335
Figure 433. PCM standard waveforms (16-bit) . . . . .1335
Figure 434. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .1336
Figure 435. Start sequence in master mode . . . . .1337
Figure 436. Audio sampling frequency definition . . . . .1338
Figure 437. I 2 S clock generator architecture . . . . .1338
Figure 438. SAI functional block diagram . . . . .1360
Figure 439. Audio frame . . . . .1364
Figure 440. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .1366
Figure 441. FS role is start of frame (FSDEF = 0). . . . .1367
Figure 442. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .1368
Figure 443. First bit offset . . . . .1368
Figure 444. Audio block clock generator overview . . . . .1369
Figure 445. AC'97 audio frame . . . . .1373
Figure 446. Example of typical AC'97 configuration on devices featuring at least
2 embedded SAIs (three external AC'97 decoders) . . . . .		1374
Figure 447. SPDIF format . . . . .1375
Figure 448. SAI_xDR register ordering . . . . .1376
Figure 449. Data companding hardware in an audio block in the SAI. . . . .1379
Figure 450. Tristate strategy on SD output line on an inactive slot . . . . .1380
Figure 451. Tristate on output data line in a protocol like I2S . . . . .1381
Figure 452. Overrun detection error. . . . .1382
Figure 453. FIFO underrun event . . . . .1382
Figure 454. SPDIFRX block diagram . . . . .1413
Figure 455. S/PDIF sub-frame format . . . . .1414
Figure 456. S/PDIF block format . . . . .1414
Figure 457. S/PDIF Preambles . . . . .1415
Figure 458. Channel coding example . . . . .1415
Figure 459. SPDIFRX decoder . . . . .1416
Figure 460. Noise filtering and edge detection . . . . .1417
Figure 461. Thresholds . . . . .1418
Figure 462. Synchronization flowchart. . . . .1420
Figure 463. Synchronization process scheduling . . . . .1421
Figure 464. SPDIFRX States . . . . .1422
Figure 465. SPDIFRX_FMTx_DR register format . . . . .1424
Figure 466. Channel/user data format . . . . .1425
Figure 467. S/PDIF overrun error when RXSTEO = 0 . . . . .1427
Figure 468. S/PDIF overrun error when RXSTEO = 1 . . . . .1428
Figure 469. SPDIFRX interface interrupt mapping diagram . . . . .1429
Figure 470. MDIOS block diagram . . . . .1444
Figure 471. MDIO protocol write frame waveform . . . . .1445
Figure 472. MDIO protocol read frame waveform . . . . .1445
Figure 473. “No response” and “no data” operations. . . . .1456
Figure 474. (Multiple) block read operation . . . . .1456
Figure 475. (Multiple) block write operation . . . . .1456
Figure 476. Sequential read operation. . . . .1457
Figure 477. Sequential write operation . . . . .1457
Figure 478. SDMMC block diagram. . . . .1457
Figure 479. SDMMC adapter . . . . .1459
Figure 480. Control unit . . . . .1460
Figure 481. SDMMC_CK clock dephasing (BYPASS = 0). . . . .1461
Figure 482. SDMMC adapter command path . . . . .1461
Figure 483. Command path state machine (SDMMC). . . . .1462
Figure 484. SDMMC command transfer . . . . .1463
Figure 485. Data path . . . . .1465
Figure 486. Data path state machine (DPSM). . . . .1466
Figure 487. CAN network topology . . . . .1516
Figure 488. Dual-CAN block diagram . . . . .1518
Figure 489. Single-CAN block diagram . . . . .1519
Figure 490. bxCAN operating modes. . . . .1521
Figure 491. bxCAN in silent mode . . . . .1522
Figure 492. bxCAN in Loop back mode . . . . .1522
Figure 493. bxCAN in combined mode . . . . .1523
Figure 494. Transmit mailbox states . . . . .1524
Figure 495. Receive FIFO states . . . . .1525
Figure 496. Filter bank scale configuration - Register organization. . . . .1528
Figure 497. Example of filter numbering . . . . .1529
Figure 498. Filtering mechanism example. . . . .1530
Figure 499. CAN error state diagram. . . . .1531
Figure 500. Bit timing . . . . .1533
Figure 501. CAN frames . . . . .1534
Figure 502. Event flags and interrupt generation. . . . .1535
Figure 503. CAN mailbox registers . . . . .1547
Figure 504. OTG_FS full-speed block diagram . . . . .1565
Figure 505. OTG_HS high-speed block diagram. . . . .1566
Figure 506. OTG_FS/OTG_HS A-B device connection . . . . .1569
Figure 507. OTG_FS/OTG_HS peripheral-only connection . . . . .1571
Figure 508. OTG_FS/OTG_HS host-only connection . . . . .1575
Figure 509. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .1579
Figure 510. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .1581
Figure 511. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .1582
Figure 512. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . .1583
Figure 513. Interrupt hierarchy . . . . .1587
Figure 514. Transmit FIFO write task . . . . .1692
Figure 515. Receive FIFO read task . . . . .1693
Figure 516. Normal bulk/control OUT/SETUP . . . . .1695
Figure 517. Bulk/control IN transactions . . . . .1699
Figure 518. Normal interrupt OUT . . . . .1702
Figure 519. Normal interrupt IN . . . . .1707
Figure 520. Isochronous OUT transactions . . . . .1709
Figure 521. Isochronous IN transactions . . . . .1712
Figure 522. Normal bulk/control OUT/SETUP transactions - DMA . . . . .1714
Figure 523. Normal bulk/control IN transaction - DMA . . . . .1716
Figure 524. Normal interrupt OUT transactions - DMA mode . . . . .1717
Figure 525. Normal interrupt IN transactions - DMA mode . . . . .1718
Figure 526. Normal isochronous OUT transaction - DMA mode . . . . .1719
Figure 527. Normal isochronous IN transactions - DMA mode . . . . .1720
Figure 528. Receive FIFO packet read . . . . .1726
Figure 529. Processing a SETUP packet . . . . .1728
Figure 530. Bulk OUT transaction . . . . .1735
Figure 531. TRDT max timing case . . . . .1744
Figure 532. A-device SRP . . . . .1745
Figure 533. B-device SRP . . . . .1746
Figure 534. A-device HNP . . . . .1747
Figure 535. B-device HNP . . . . .1749
Figure 536. ETH block diagram . . . . .1755
Figure 537. SMI interface signals . . . . .1756
Figure 538. MDIO timing and frame structure - Write cycle . . . . .1757
Figure 539. MDIO timing and frame structure - Read cycle . . . . .1758
Figure 540. Media independent interface signals . . . . .1759
Figure 541. MII clock sources . . . . .1761
Figure 542. Reduced media-independent interface signals . . . . .1761
Figure 543. RMII clock sources- . . . . .1762
Figure 544. Clock scheme . . . . .1762
Figure 545. Address field format . . . . .1764
Figure 546. MAC frame format . . . . .1766
Figure 547. Tagged MAC frame format . . . . .1766
Figure 548. Transmission bit order . . . . .1773
Figure 549. Transmission with no collision . . . . .1773
Figure 550. Transmission with collision . . . . .1774
Figure 551. Frame transmission in MMI and RMII modes . . . . .1774
Figure 552. Receive bit order . . . . .1778
Figure 553. Reception with no error . . . . .1779
Figure 554. Reception with errors . . . . .1779
Figure 555. Reception with false carrier indication . . . . .1779
Figure 556. MAC core interrupt masking scheme . . . . .1780
Figure 557. Wakeup frame filter register . . . . .1785
Figure 558. Networked time synchronization . . . . .1788
Figure 559. System time update using the Fine correction method. . . . .1790
Figure 560. PTP trigger output to TIM2 ITR1 connection . . . . .1792
Figure 561. PPS output . . . . .1793
Figure 562. Descriptor ring and chain structure. . . . .1794
Figure 563. TxDMA operation in default mode . . . . .1798
Figure 564. TxDMA operation in OSF mode . . . . .1800
Figure 565. Normal transmit descriptor . . . . .1801
Figure 566. Enhanced transmit descriptor . . . . .1807
Figure 567. Receive DMA operation . . . . .1809
Figure 568. Normal Rx DMA descriptor structure . . . . .1811
Figure 569. Enhanced receive descriptor field format with IEEE1588 time stamp enabled. . . . .1817
Figure 570. Interrupt scheme. . . . .1820
Figure 571. Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR). . . . .1831
Figure 572. HDMI-CEC block diagram . . . . .1874
Figure 573. Message structure . . . . .1875
Figure 574. Blocks . . . . .1875
Figure 575. Bit timings . . . . .1876
Figure 576. Signal free time. . . . .1876
Figure 577. Arbitration phase. . . . .1877
Figure 578. SFT of three nominal bit periods. . . . .1877
Figure 579. Error bit timing . . . . .1878
Figure 580. Error handling . . . . .1879
Figure 581. TXERR detection . . . . .1881
Figure 582. Block diagram of STM32 MCU and Cortex ® -M7 with FPU -level
debug support . . . . .		1891
Figure 583. SWJ debug port . . . . .1893
Figure 584. JTAG Debug Port connections . . . . .1897
Figure 585. TPIU block diagram . . . . .1917

Chapters