33. Revision history

• – Table 1: Register boundary addresses
• – Table 24: RCC register map and reset values for STM32F412xx
• – Figure 2: Memory map
• – Section 6.3: RCC registers
• – Section 9.5.5: DMA stream x configuration register (DMA_SxCR)
• – Section 14.4.4: Serial channel transceivers
• – Section 30.6.1: MCU device ID code
• – Section 30.16.2: Debug support for timers, watchdog, bxCAN and I ² C

• – Table 149: Error calculation for programmed baud rates at f _PCLK = 100 MHz or f _PCLK = 50 MHz, oversampling by 16
• – Table 150: Error calculation for programmed baud rates at f _PCLK = 100 MHz or f _PCLK = 50 MHz, oversampling by 8

• – Table 91: DFSDM register map and reset values
• – Section 30.6.1: MCU device ID code

• – Section 6.3.13: RCC APB1 peripheral clock enable register (RCC_APB1ENR)
• – Section 6.3.23: RCC PLLI2S configuration register (RCC_PLLI2SCFGR)
• – Section 6.3.24: RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)
• – Section 6.3.26: RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR2)
• – Section 14: Digital filter for sigma delta modulators (DFSDM)
• – Section 23.4.9: FMPI2C controller mode
• – Section 23.7.2: Control register 2 (FMPI2C_CR2)

• – Section 6.3.25: RCC clocks gated enable register (CKGATENR)

Updated Section 6.3.18: RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR) .

Updated Section 6.3.19: RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) .

Updated Section 6.3.20: RCC Backup domain control register (RCC_BDCR) .

Updated Section 6.3.22: RCC spread spectrum clock generation register (RCC_SSCGR) .

Updated Section 6.3.24: RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR) .

Updated Section 6.3.26: RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR2) .

GPIO:

Updated Section 7.3.2: I/O pin multiplexer and mapping .

Updated Table 27: RTC additional functions .

Updated Table 7.4.1: GPIO port mode register (GPIOx_MODER) (x = A...H) .

DMA:

Updated Table 9.3.19: Error management .

INTERRUPTS

Updated Section 10.3.6: Pending register (EXTI_PR) .

FSMC

Updated Figure 50: Synchronous multiplexed write mode waveforms - PSRAM (CRAM) .

QUADSPI:

Whole section re-edited.

ADC:

Updated Section 13.2: ADC main features .

Updated Figure 59: Single ADC block diagram .

Updated Section 13.3.5: Continuous conversion mode .

Updated Section 13.6: Conversion on external trigger and trigger polarity .

Updated Table 77: External trigger for regular channels .

Updated Section 13.9: Temperature sensor .

Updated Section 13.12.1: ADC status register (ADC_SR) .

DFSDM:

Updated Section 14.3: DFSDM implementation .

Updated Section 14.4.3: DFSDM reset and clocks .

Updated Section : Manchester coded data input format operation .

Updated Section : Clock absence detection .

Updated Section : Manchester/SPI code synchronization .

Updated Section 14.7.1: DFSDM channel y configuration register (DFSDM_CHyCFGR1) .

Updated introduction to Section 26.7: SPI and I ² S registers .

SDIO:
Updated Section 27.8.2: SDIO clock control register (SDIO_CLKCR) .

OTG:
Updated Section 29.7: OTG_FS as a USB host .
Updated Section 29.15.17: OTG core LPM configuration register (OTG_GLPMCFG) .
Updated Section 29.15.29: OTG host channel x interrupt register (OTG_HCINTx) .
Updated Section 29.15.52: OTG device OUT endpoint x control register (OTG_DOEPCTLx) .

DEBUG:
Updated Section 30.4.2: Flexible SWJ-DP pin assignment .
Updated Section 30.6.1: MCU device ID code .

SECURITY:
Added Section 32: Important security notice .