19. Basic timers (TIM6/7)

19.1 Introduction

The basic timers TIM6, TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler.

19.2 TIM6/7 main features

Basic timer (TIM6/TIM7) features include:

• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536
• Interrupt/DMA generation on the update event: counter overflow

Figure 194. Basic timer block diagram

The diagram illustrates the internal architecture of a basic timer (TIM6/7). It consists of several interconnected components:

Input: TIMxCLK from RCC enters the system.
Internal clock (CK_INT): Derived from TIMxCLK, it is fed into the Trigger Controller.
Trigger Controller: Contains a Control block. It receives CK_INT and control signals (Reset, enable, Count). It generates the TRGO output and provides control signals to the PSC prescaler and CNT counter.
CK_PSC: Input to the PSC prescaler.
PSC prescaler: Divides the CK_PSC signal to produce CK_CNT.
CNT counter: Receives CK_CNT and control signals. It generates the UI (Update Interrupt) output.
Auto-reload register: Receives input U and control signals (Stop, clear or up). It provides preload data to the CNT counter.
Output: UI (Update Interrupt) is generated by the CNT counter.

Notes:

Reg (Preload registers transferred to active registers on U event according to control bit)
Event (indicated by a dashed arrow)
Interrupt & DMA output (indicated by a solid arrow with a squiggle)

MSv34754V1

Figure 194. Basic timer block diagram

19.3 TIM6/7 functional description

19.3.1 Time-base unit

The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter Register (TIMx_CNT)
• Prescaler Register (TIMx_PSC)
• Auto-Reload Register (TIMx_ARR)

The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set.

Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 195 and Figure 196 give some examples of the counter behavior when the prescaler ratio is changed on the fly.

Figure 195. Counter timing diagram with prescaler division change from 1 to 2

Timing diagram for Figure 195 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates the effect of changing the prescaler division from 1 to 2.

This timing diagram shows the relationship between several signals over time. The signals are:

CK_PSC : A periodic clock signal.
CEN : Counter Enable signal, which goes high to start counting.
Timerclock = CK_CNT : The clock signal for the counter, derived from CK_PSC.
Counter register : Shows hexadecimal values F7, F8, F9, FA, FB, FC, followed by 00, 01, 02, 03.
Update event (UEV) : A pulse generated when the counter reaches FC and overflows.
Prescaler control register : Initially 0, then changed to 1. An arrow points to the change with the text "Write a new value in TIMx_PSC".
Prescaler buffer : Initially 0, then changes to 1 upon the UEV.
Prescaler counter : Shows a sequence of values 0, 1, 0, 1, 0, 1, 0, 1, indicating a division of 2 after the change.

Vertical dashed lines indicate key timing points: the start of counting, the update event, and the subsequent change in prescaler division. The text "MS31076V2" is in the bottom right corner.

Timing diagram for Figure 195 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates the effect of changing the prescaler division from 1 to 2.

Figure 196. Counter timing diagram with prescaler division change from 1 to 4

Timing diagram for Figure 196 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates the effect of changing the prescaler division from 1 to 4.

This timing diagram is similar to Figure 195 but shows a prescaler division change from 1 to 4. The signals are:

CK_PSC and CEN : Same as in Figure 195.
Timerclock = CK_CNT : The clock signal for the counter.
Counter register : Shows hexadecimal values F7, F8, F9, FA, FB, FC, followed by 00, 01.
Update event (UEV) : Generated at the FC overflow.
Prescaler control register : Initially 0, then changed to 3 (which corresponds to a division of 4). An arrow points to the change with the text "Write a new value in TIMx_PSC".
Prescaler buffer : Initially 0, then changes to 3 upon the UEV.
Prescaler counter : Shows a sequence of values 0, 1, 2, 3, 0, 1, 2, 3, indicating a division of 4 after the change.

Vertical dashed lines indicate key timing points. The text "MS31077V2" is in the bottom right corner.

Timing diagram for Figure 196 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates the effect of changing the prescaler division from 1 to 4.

19.3.2 Counting mode

The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent).

When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register)
• The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36.

Figure 197. Counter timing diagram, internal clock divided by 1

Timing diagram for a counter in counting mode. The diagram shows the relationship between the prescaler clock (CK_PSC), counter enable (CNT_EN), timer clock (CK_CNT), counter register values, counter overflow, update event (UEV), and update interrupt flag (UIF).

The timing diagram illustrates the counter's behavior over time. The top signal, CK_PSC, is a periodic square wave. Below it, CNT_EN is a signal that goes high to enable the counter. The third signal, Timerclock = CK_CNT, is a square wave that is active only when CNT_EN is high. The fourth signal shows the Counter register values, which increment from 31 to 32, 33, 34, 35, 36, then overflow to 00, 01, 02, 03, 04, 05, 06, 07. The fifth signal, Counter overflow, is a pulse that goes high when the counter reaches 36 and returns low when it overflows to 00. The sixth signal, Update event (UEV), is a pulse that goes high at the overflow point. The bottom signal, Update interrupt flag (UIF), is a pulse that goes high at the overflow point and returns low after a short duration. Vertical dashed lines indicate the timing relationships between the signals.

MS31078V2

Timing diagram for a counter in counting mode. The diagram shows the relationship between the prescaler clock (CK_PSC), counter enable (CNT_EN), timer clock (CK_CNT), counter register values, counter overflow, update event (UEV), and update interrupt flag (UIF).

Figure 198. Counter timing diagram, internal clock divided by 2

This timing diagram illustrates the operation of a basic timer with the internal clock divided by 2. The top signal, CK_PSC, is a periodic square wave. Below it, CNT_EN is a high-level signal that enables the counter. The Timerclock = CK_CNT signal is a square wave with a frequency half that of CK_PSC. The Counter register shows a sequence of values: 0034, 0035, 0036, 0000, 0001, 0002, and 0003. Vertical dashed lines indicate the rising edges of the Timerclock. The Counter overflow signal goes high when the counter reaches 0036 and returns low at 0000. The Update event (UEV) and Update interrupt flag (UIF) signals also go high at the 0036 mark and return low at the 0000 mark. The identifier MS31079V2 is located in the bottom right corner.

Timing diagram for internal clock divided by 2. It shows CK_PSC, CNT_EN, Timerclock = CK_CNT, Counter register values (0034, 0035, 0036, 0000, 0001, 0002, 0003), Counter overflow, Update event (UEV), and Update interrupt flag (UIF) over time.

Figure 199. Counter timing diagram, internal clock divided by 4

This timing diagram illustrates the operation of a basic timer with the internal clock divided by 4. The top signal, CK_PSC, is a periodic square wave. Below it, CNT_EN is a high-level signal that enables the counter. The Timerclock = CK_CNT signal is a square wave with a frequency one-quarter that of CK_PSC. The Counter register shows a sequence of values: 0035, 0036, 0000, and 0001. Vertical dashed lines indicate the rising edges of the Timerclock. The Counter overflow signal goes high when the counter reaches 0036 and returns low at 0000. The Update event (UEV) and Update interrupt flag (UIF) signals also go high at the 0036 mark and return low at the 0000 mark. The identifier MS31080V2 is located in the bottom right corner.

Timing diagram for internal clock divided by 4. It shows CK_PSC, CNT_EN, Timerclock = CK_CNT, Counter register values (0035, 0036, 0000, 0001), Counter overflow, Update event (UEV), and Update interrupt flag (UIF) over time.

Figure 200. Counter timing diagram, internal clock divided by N

This timing diagram illustrates the operation of a basic timer with an internal clock divided by N. The top signal, CK_PSC, is a periodic square wave. Below it, the Timerclock = CK_CNT is shown as a series of pulses, with a break indicating a division. The Counter register is shown in three states: 1F, 20, and 00. The counter increments from 1F to 20, then overflows to 00. The Counter overflow signal is a pulse that goes high when the counter reaches 00. The Update event (UEV) and Update interrupt flag (UIF) are also shown as pulses that go high at the overflow point. The diagram is labeled MS31081V2 in the bottom right corner.

Timing diagram for Figure 200 showing CK_PSC, Timerclock = CK_CNT, Counter register (values 1F, 20, 00), Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

Figure 201. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded)

This timing diagram shows the counter operation when ARPE = 0 and the TIMx_ARR register is not preloaded. The signals shown are CK_PSC, CEN (Counter Enable), Timerclock = CK_CNT, Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), and the Auto-reload preload register. The counter starts at 31, increments through 32, 33, 34, 35, 36, overflows to 00, and continues through 01, 02, 03, 04, 05, 06, 07. The Counter overflow signal is a pulse that goes high at the 36 to 00 transition. The Update event (UEV) and Update interrupt flag (UIF) are also shown as pulses that go high at this transition. The Auto-reload preload register is shown with values FF and 36. An arrow points to the transition from FF to 36 with the text 'Write a new value in TIMx_ARR'. The diagram is labeled MS31082V2 in the bottom right corner.

Timing diagram for Figure 201 showing CK_PSC, CEN, Timerclock = CK_CNT, Counter register (values 31 to 07), Counter overflow, Update event (UEV), Update interrupt flag (UIF), and Auto-reload preload register (values FF, 36).

Figure 202. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)

Figure 202: Counter timing diagram showing the relationship between CK_PSC, CEN, Timerclock (CK_CNT), Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), Auto-reload preload register, and Auto-reload shadow register. The diagram illustrates the counter sequence from F0 to 07, the overflow point at F5, and the update event triggered by the overflow. The Auto-reload preload register is shown with values F5 and 36, and the Auto-reload shadow register is shown with values F5 and 36. A note indicates that a new value can be written in TIMx_ARR.

The timing diagram shows the following signals and their states over time:

CK_PSC : A periodic square wave clock signal.
CEN : Counter Enable signal, which is initially low and then goes high to enable the counter.
Timerclock = CK_CNT : The counter clock, which is derived from CK_PSC and starts when CEN goes high.
Counter register : Shows the counter values: F0, F1, F2, F3, F4, F5, 00, 01, 02, 03, 04, 05, 06, 07. The counter increments on each rising edge of the timer clock.
Counter overflow : A signal that goes high when the counter reaches F5 and is about to roll over to 00.
Update event (UEV) : A pulse that occurs at the counter overflow point.
Update interrupt flag (UIF) : A flag that is set by the update event.
Auto-reload preload register : Shows the value F5 being written, then later the value 36 being written. An arrow points to the F5 value with the text "Write a new value in TIMx_ARR".
Auto-reload shadow register : Shows the value F5 being loaded from the preload register, then later the value 36 being loaded.

MS31083V2

Figure 202: Counter timing diagram showing the relationship between CK_PSC, CEN, Timerclock (CK_CNT), Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), Auto-reload preload register, and Auto-reload shadow register. The diagram illustrates the counter sequence from F0 to 07, the overflow point at F5, and the update event triggered by the overflow. The Auto-reload preload register is shown with values F5 and 36, and the Auto-reload shadow register is shown with values F5 and 36. A note indicates that a new value can be written in TIMx_ARR.

19.3.3 Clock source

The counter clock is provided by the Internal clock (CK_INT) source.

The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 203 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Figure 203. Control circuit in normal mode, internal clock divided by 1

Timing diagram for Figure 203 showing control circuit in normal mode. The diagram illustrates the relationship between the Internal clock, CEN=CNT_EN, UG, CNT_INIT, Counter clock = CK_CNT = CK_PSC, and the Counter register. The Internal clock is a high-frequency square wave. CEN=CNT_EN is a high-level signal. UG and CNT_INIT are low-level signals. The Counter clock is a square wave derived from the Internal clock. The Counter register shows a sequence of values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. Vertical dashed lines indicate synchronization points between the clock and the counter register updates.

Timing diagram showing the control circuit in normal mode, internal clock divided by 1. The diagram illustrates the relationship between the Internal clock, CEN=CNT_EN, UG, CNT_INIT, Counter clock = CK_CNT = CK_PSC, and the Counter register.

Internal clock: A high-frequency square wave.
CEN=CNT_EN: A high-level signal.
UG: A low-level signal.
CNT_INIT: A low-level signal.
Counter clock = CK_CNT = CK_PSC: A square wave derived from the Internal clock.
Counter register: Shows a sequence of values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. The counter increments by 1 at each rising edge of the Counter clock.

Vertical dashed lines indicate synchronization points between the clock and the counter register updates.

MS31085V2

Timing diagram for Figure 203 showing control circuit in normal mode. The diagram illustrates the relationship between the Internal clock, CEN=CNT_EN, UG, CNT_INIT, Counter clock = CK_CNT = CK_PSC, and the Counter register. The Internal clock is a high-frequency square wave. CEN=CNT_EN is a high-level signal. UG and CNT_INIT are low-level signals. The Counter clock is a square wave derived from the Internal clock. The Counter register shows a sequence of values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. Vertical dashed lines indicate synchronization points between the clock and the counter register updates.

19.3.4 Debug mode

When the microcontroller enters the debug mode (Cortex ^®-M4 with FPU core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to Section 30.16.2: Debug support for timers, watchdog, bxCAN and I ²C .

19.4 TIM6/7 registers

Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions.

The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

19.4.1 TIM6/7 control register 1 (TIMx_CR1)

Address offset: 0x00

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ARPE	Res.	Res.	Res.	OPM	URS	UDIS	CEN
								rw				rw	rw	rw	rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered.

1: TIMx_ARR register is buffered.

Bits 6:4 Reserved, must be kept at reset value.

Bit 3 OPM : One-pulse mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the CEN bit).

Bit 2 URS : Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generates an update interrupt or DMA request if enabled.

These events can be:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS : Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN : Counter enable

0: Counter disabled

1: Counter enabled

Note: Gated mode can work only if the CEN bit has been previously set by software.

However trigger mode can set the CEN bit automatically by hardware.

CEN is cleared automatically in one-pulse mode, when an update event occurs.

19.4.2 TIM6/7 control register 2 (TIMx_CR2)

Address offset: 0x04

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MMS[2:0]				Res.	Res.	Res.
									rw	rw	rw

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 MMS : Master mode selection

These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:

000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.

001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.

When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register).

010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

Bits 3:0 Reserved, must be kept at reset value.

19.4.3 TIM6/7 DMA/Interrupt enable register (TIMx_DIER)

Address offset: 0x0C

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	UDE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIE
							rw								rw

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 UDE : Update DMA request enable

0: Update DMA request disabled.

1: Update DMA request enabled.

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 UIE : Update interrupt enable

0: Update interrupt disabled.

1: Update interrupt enabled.

19.4.4 TIM6/7 status register (TIMx_SR)

Address offset: 0x10

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIF
															rc_w0

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UIF : Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register.

19.4.5 TIM6/7 event generation register (TIMx_EGR)

Address offset: 0x14

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UG
															w

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UG : Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action.

1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).

19.4.6 TIM6/7 counter (TIMx_CNT)

Address offset: 0x24

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 CNT[15:0] : Counter value

19.4.7 TIM6/7 prescaler (TIMx_PSC)

Address offset: 0x28

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency (CK_CNT) is equal to $f_{CK\_PSC} / (PSC[15:0] + 1)$ .

PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).

19.4.8 TIM6/7 auto-reload register (TIMx_ARR)

Address offset: 0x2C

Reset value: 0xFFFF

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 ARR[15:0] : Auto-reload value

ARR is the value to be loaded into the actual auto-reload register.

Refer to Section 19.3.1: Time-base unit on page 590 for more details about ARR update and behavior.

The counter is blocked while the auto-reload value is null.

19.4.9 TIM6/7 register map

TIMx registers are mapped as 16-bit addressable registers as described in the table below:

Table 109. TIM6/7 register map and reset values

Offset	Register	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	TIMx_CR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ARPE	Res.	Res.	Res.	OPM	URS	UDIS	CEN
0x00	Reset value									0				0	0	0	0
0x04	TIMx_CR2	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MMS[2:0]			Res.	Res.	Res.	Res.
0x04	Reset value										0	0	0
0x08	Res.
0x0C	TIMx_DIER	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UDE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIE
0x0C	Reset value								0								0
0x10	TIMx_SR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIF
0x10	Reset value																0
0x14	TIMx_EGR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UG
0x14	Reset value																0
0x18	Res.
0x1C	Res.
0x20	Res.
0x24	TIMx_CNT	CNT[15:0]
0x24	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x28	TIMx_PSC	PSC[15:0]
0x28	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x2C	TIMx_ARR	ARR[15:0]
0x2C	Reset value	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

Refer to Section 2.2 on page 49 for the register boundary addresses.