11. Flexible static memory controller (FSMC)

11.1 Introduction

The flexible static memory controller (FSMC) includes one memory controller:

• • The NOR/PSRAM memory controller

11.2 FSMC main features

The FSMC functional block makes the interface with: synchronous and asynchronous static memories. Its main purposes are:

• • to translate AHB transactions into the appropriate external device protocol
• • to meet the access time requirements of the external memory devices

All external memories share the addresses, data and control signals with the controller. Each external device is accessed by means of a unique chip select. The FSMC performs only one access at a time to an external device.

The main features of the FSMC controller are the following:

• • Interface with static-memory mapped devices including:
  • – Static random access memory (SRAM)
  • – NOR flash memory/OneNAND flash memory
  • – PSRAM (4 memory banks)
• • Interface with parallel LCD modules, supporting Intel 8080 and Motorola 6800 modes.
• • Burst mode support for faster access to synchronous devices such as NOR flash memory, PSRAM)
• • Programmable continuous clock output for asynchronous and synchronous accesses
• • 8-,16-bit wide data bus
• • Independent chip select control for each memory bank
• • Independent configuration for each memory bank
• • Write enable and byte lane select outputs for use with PSRAM, SRAM devices
• • External asynchronous wait control
• • Write FIFO with 16 x32-bit depth

The Write FIFO is common to all memory controllers and consists of:

• • a Write Data FIFO which stores the AHB data to be written to the memory (up to 32 bits) plus one bit for the AHB transfer (burst or not sequential mode)
• • a Write Address FIFO which stores the AHB address (up to 28 bits) plus the AHB data size (up to 2 bits). When operating in burst mode, only the start address is stored except when crossing a page boundary (for PSRAM). In this case, the AHB burst is broken into two FIFO entries.

The Write FIFO can be disabled by setting the WFDIS bit in the FSMC_BCR1 register.

At startup the FSMC pins must be configured by the user application. The FSMC I/O pins which are not used by the application can be used for other purposes.

The FSMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. However, the settings can be changed at any time.

11.3 FMC block diagram

The FSMC consists of the following main blocks:

• • The AHB interface (including the FSMC configuration registers)
• • The NOR flash/PSRAM/SRAM controller

The block diagram is shown in the figure below.

Figure 31. FSMC block diagram

11.4 AHB interface

The AHB slave interface allows internal CPUs and other bus master peripherals to access the external memories.

AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses. The FSMC chip select (FSMC_NEx) does not toggle between the consecutive accesses except in case of Access mode D when the Extended mode is enabled.

The FSMC generates an AHB error in the following conditions:

• • When reading or writing to a FSMC bank (Bank 1 to 4) which is not enabled.
• • When reading or writing to the NOR flash bank while the FACEN bit is reset in the FSMC_BCRx register.

The effect of an AHB error depends on the AHB master which has attempted the R/W access:

• • If the access has been attempted by the Cortex ^® -M4 with FPU CPU, a hard fault interrupt is generated.
• • If the access has been performed by a DMA controller, a DMA transfer error is generated and the corresponding DMA channel is automatically disabled.

The AHB clock (HCLK) is the reference clock for the FSMC.

11.4.1 Supported memories and transactions

General transaction rules

The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the accessed external device has a fixed data width. This may lead to inconsistent transfers.

Therefore, some simple transaction rules must be followed:

• • AHB transaction size and memory data size are equal

There is no issue in this case.

• • AHB transaction size is greater than the memory size:

In this case, the FSMC splits the AHB transaction into smaller consecutive memory accesses to meet the external data width. The FSMC chip select (FSMC_NEx) does not toggle between the consecutive accesses.

• • AHB transaction size is smaller than the memory size:

The transfer may or not be consistent depending on the type of external device:

• – Accesses to devices that have the byte select feature (SRAM, ROM, PSRAM)

In this case, the FSMC allows read/write transactions and accesses to the right data through its byte lanes NBL[1:0].

Bytes to be written are addressed by NBL[1:0].

All memory bytes are read (NBL[1:0] are driven low during read transaction) and the useless ones are discarded.

• – Accesses to devices that do not have the byte select feature (NOR)

This situation occurs when a byte access is requested to a 16-bit wide flash memory. Since the device cannot be accessed in Byte mode (only 16-bit words can be read/written from/to the flash memory), Write transactions and Read transactions are allowed (the controller reads the entire 16-bit memory word and uses only the required byte).

Wrap support for NOR flash/PSRAM

Wrap burst mode for synchronous memories is not supported. The memories must be configured in Linear burst mode of undefined length.

Configuration registers

The FSMC can be configured through a set of registers. Refer to Section 11.6.6 , for a detailed description of the NOR flash/PSRAM controller registers.

11.5 External device address mapping

From the FSMC point of view, the external memory is divided into fixed-size banks of 256 Mbytes each (see Figure 32 ):

• • Bank 1 used to address up to 4 NOR flash memory or PSRAM devices. This bank is split into 4 NOR/PSRAM subbanks with 4 dedicated chip selects, as follows:
  • – Bank 1 - NOR/PSRAM 1
  • – Bank 1 - NOR/PSRAM 2
  • – Bank 1 - NOR/PSRAM 3
  • – Bank 1 - NOR/PSRAM 4
• • Bank 3 used to address NAND flash memory devices. The MPU memory attribute for this space must be reconfigured by software to Device.

For each bank the type of memory to be used can be configured by the user application through the Configuration register.

Figure 32. FSMC memory banks

11.5.1 NOR/PSRAM address mapping

HADDR[27:26] bits are used to select one of the four memory banks as shown in Table 42 .

Table 42. NOR/PSRAM bank selection

1. HADDR are internal AHB address lines that are translated to external memory.

The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte address whereas the memory is addressed at word level, the address actually issued to the memory varies according to the memory data width, as shown in the following table.

Table 43. NOR/PSRAM External memory address

1. 1. In case of a 16-bit external memory width, the FSMC internally uses HADDR[25:1] to generate the address for external memory FSMC_A[24:0]. Whatever the external memory width, FSMC_A[0] must be connected to external memory address A[0].

11.6 NOR flash/PSRAM controller

The FSMC generates the appropriate signal timings to drive the following types of memories:

• • Asynchronous SRAM and ROM
  • – 8 bits
  • – 16 bits
• • PSRAM (CellularRAM™)
  • – Asynchronous mode
  • – Burst mode for synchronous accesses
  • – Multiplexed or non-multiplexed
• • NOR flash memory
  • – Asynchronous mode
  • – Burst mode for synchronous accesses
  • – Multiplexed or non-multiplexed

The FSMC outputs a unique chip select signal, NE[4:1], per bank. All the other signals (addresses, data and control) are shared.

The FSMC supports a wide range of devices through a programmable timings among which:

• • Programmable wait states (up to 15)
• • Programmable bus turnaround cycles (up to 15)
• • Programmable output enable and write enable delays (up to 15)
• • Independent read and write timings and protocol to support the widest variety of memories and timings
• • Programmable continuous clock (FSMC_CLK) output.

The FSMC Clock (FSMC_CLK) is a submultiple of the HCLK clock. It can be delivered to the selected external device either during synchronous accesses only or during asynchronous and synchronous accesses depending on the CCKEN bit configuration in the FSMC_BCR1 register:

• • If the CCKEN bit is reset, the FSMC generates the clock (CLK) only during synchronous accesses (Read/write transactions).
• • If the CCKEN bit is set, the FSMC generates a continuous clock during asynchronous and synchronous accesses. To generate the FSMC_CLK continuous clock, Bank 1 must be configured in Synchronous mode (see Section 11.6.6: NOR/PSRAM controller registers ). Since the same clock is used for all synchronous memories, when a continuous output clock is generated and synchronous accesses are performed, the AHB data size has to be the same as the memory data width (MWID) otherwise the FSMC_CLK frequency is changed depending on AHB data transaction (refer to Section 11.6.5: Synchronous transactions for FSMC_CLK divider ratio formula).

The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through dedicated registers (see Section 11.6.6: NOR/PSRAM controller registers ).

The programmable memory parameters include access times (see Table 44 ) and support for wait management (for PSRAM and NOR flash accessed in Burst mode).

Table 44. Programmable NOR/PSRAM access parameters

11.6.1 External memory interface signals

Table 45 , Table 46 and Table 47 list the signals that are typically used to interface with NOR flash memory, SRAM and PSRAM.

Note: The prefix “N” identifies the signals that are active low.

NOR flash memory, non-multiplexed I/Os

Table 45. Non-multiplexed I/O NOR flash memory

The maximum capacity is 512 Mbits (26 address lines).

The maximum capacity is 512 Mbits.

The maximum capacity is 512 Mbits.

Table 48. 16-Bit multiplexed I/O PSRAM (continued)

The maximum capacity is 512 Mbits (26 address lines).

11.6.2 Supported memories and transactions

Table 49 below shows an example of the supported devices, access modes and transactions when the memory data bus is 16-bit wide for NOR flash memory, PSRAM and SRAM. The transactions not allowed (or not supported) by the FSMC are shown in gray in this example.

Table 49. NOR flash/PSRAM: example of supported memories and transactions

11.6.3 General timing rules

Signals synchronization

• All controller output signals change on the rising edge of the internal clock (HCLK)
• In Synchronous mode (read or write), all output signals change on the rising edge of HCLK. Whatever the CLKDIV value, all outputs change as follows:
  • NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the falling edge of FSMC_CLK clock.
  • NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising edge of FSMC_CLK clock.

11.6.4 NOR flash/PSRAM controller asynchronous transactions

Asynchronous static memories (NOR flash, PSRAM, SRAM)

• Signals are synchronized by the internal clock HCLK. This clock is not issued to the memory

• • The FSMC always samples the data before de-asserting the NOE signal. This guarantees that the memory data hold timing constraint is met (minimum Chip Enable high to data transition is usually 0 ns)
• • If the Extended mode is enabled (EXTMOD bit is set in the FSMC_BCRx register), up to four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D modes for read and write operations. For example, read operation can be performed in mode A and write in mode B.
• • If the Extended mode is disabled (EXTMOD bit is reset in the FSMC_BCRx register), the FSMC can operate in mode 1 or mode 2 as follows:
  • – Mode 1 is the default mode when SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01 in the FSMC_BCRx register)
  • – Mode 2 is the default mode when NOR memory type is selected (MTYP = 0x10 in the FSMC_BCRx register).

Mode 1 - SRAM/PSRAM (CRAM)

The next figures show the read and write transactions for the supported modes followed by the required configuration of FSMC_BCRx, and FSMC_BTRx/FSMC_BWTRx registers.

Figure 33. Mode 1 read access waveforms

Figure 34. Mode 1 write access waveforms

The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the DATAST value must be greater than zero (DATAST > 0).

Table 50. FSMC_BCRx bitfields (mode 1)

Mode A - SRAM/PSRAM (CRAM) OE toggling

Figure 35. Mode A read access waveforms

• 1. NBL[1:0] are driven low during the read access

Figure 36. Mode A write access waveforms

The differences compared with Mode 1 are the toggling of NOE and the independent read and write timings.

Table 52. FSMC_BCRx bitfields (mode A)

Table 53. FSMC_BTRx bitfields (mode A)

Table 54. FSMC_BWTRx bitfields (mode A)

Mode 2/B - NOR flash

Figure 37. Mode 2 and mode B read access waveforms

Figure 38. Mode 2 write access waveforms

MS34482V2

Figure 39. Mode B write access waveforms

MSV40114V1

The differences with mode 1 are the toggling of NWE and the independent read and write timings when extended mode is set (mode B).

Table 57. FSMC_BWTRx bitfields (mode 2/B)

Note: The FSMC_BWTRx register is valid only if the Extended mode is set (mode B), otherwise its content is don't care.

Mode C - NOR flash - OE toggling

Figure 40. Mode C read access waveforms

Figure 41. Mode C write access waveforms

The differences compared with mode 1 are the toggling of NOE and the independent read and write timings.

Table 58. FSMC_BCRx bitfields (mode C)

Mode D - asynchronous access with extended address

Figure 42. Mode D read access waveforms

Figure 43. Mode D write access waveforms

The differences with mode 1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings.

Table 61. FSMC_BCRx bitfields (mode D)

Table 62. FSMC_BTRx bitfields (mode D)

Table 63. FSMC_BWTRx bitfields (mode D)

Muxed mode - multiplexed asynchronous access to NOR flash memory

Figure 44. Muxed read access waveforms

Figure 45. Muxed write access waveforms

The difference with mode D is the drive of the lower address byte(s) on the data bus.

Table 64. FSMC_BCRx bitfields (Muxed mode)

WAIT management in asynchronous accesses

If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to accept or to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register.

If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT becomes inactive. Unlike the data setup phase, the first access phases (Address setup and Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT sensitive and so they are not prolonged.

The data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles before the end of the memory transaction. The following cases must be considered:

1. 1. The memory asserts the WAIT signal aligned to NOE/NWE which toggles:

1. 2. The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
   if

then:

otherwise

where \( \text{max\_wait\_assertion\_time} \) is the maximum time taken by the memory to assert the WAIT signal once NEx/NOE/NWE is low.

Figure 46 and Figure 47 show the number of HCLK clock cycles that are added to the memory access phase after WAIT is released by the asynchronous memory (independently of the above cases).

Figure 46. Asynchronous wait during a read access waveforms

1. 1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.

Figure 47. Asynchronous wait during a write access waveforms

1. 1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.

11.6.5 Synchronous transactions

The memory clock, FSMC_CLK, is a submultiple of HCLK. It depends on the value of CLKDIV and the MWID/ AHB data size, following the formula given below:

Whatever MWID size: 16 or 8-bit, the FSMC_CLK divider ratio is always defined by the programmed CLKDIV value.

Example:

• • If CLKDIV=1, MWID = 16 bits, AHB data size=8 bits, FSMC_CLK=HCLK/2.

NOR flash memories specify a minimum time from NADV assertion to CLK high. To meet this constraint, the FSMC does not issue the clock to the memory during the first internal clock cycle of the synchronous access (before NADV assertion). This guarantees that the rising edge of the memory clock occurs in the middle of the NADV low pulse.

Data latency versus NOR memory latency

The data latency is the number of cycles to wait before sampling the data. The DATLAT value must be consistent with the latency value specified in the NOR flash configuration register. The FSMC does not include the clock cycle when NADV is low in the data latency count.

Caution: Some NOR flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR flash latency and the FSMC DATLAT parameter can be either:

• • NOR flash latency = (DATLAT + 2) CLK clock cycles
• • or NOR flash latency = (DATLAT + 3) CLK clock cycles

Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can be set to its minimum value. As a result, the FSMC samples the data and waits long enough to evaluate if the data are valid. Thus the FSMC detects when the memory exits latency and real data are processed.

Other memories do not assert NWAIT during latency. In this case the latency must be set correctly for both the FSMC and the memory, otherwise invalid data are mistaken for good data, or valid data are lost in the initial phase of the memory access.

Single-burst transfer

When the selected bank is configured in Burst mode for synchronous accesses, if for example an AHB single-burst transaction is requested on 16-bit memories, the FSMC performs a burst transaction of length 1 (if the AHB transfer is 16 bits), or length 2 (if the AHB transfer is 32 bits) and de-assert the chip select signal when the last data is strobed.

Such transfers are not the most efficient in terms of cycles compared to asynchronous read operations. Nevertheless, a random asynchronous access would first require to re-program the memory access mode, which would altogether last longer.

Cross boundary page for CellularRAM™ 1.5

CellularRAM™ 1.5 does not allow burst access to cross the page boundary. The FSMC controller is used to split automatically the burst access when the memory page size is reached by configuring the CPSIZE bits in the FSMC_BCR1 register following the memory page size.

Wait management

For synchronous NOR flash memories, NWAIT is evaluated after the programmed latency period, which corresponds to (DATLAT+2) CLK clock cycles.

If NWAIT is active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait states are inserted until NWAIT is inactive (high level when WAITPOL = 0, low level when WAITPOL = 1).

When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1) or on the next clock edge (bit WAITCFG = 0).

During wait-state insertion via the NWAIT signal, the controller continues to send clock pulses to the memory, keeping the chip select and output enable signals valid. It does not consider the data as valid.

In Burst mode, there are two timing configurations for the NOR flash NWAIT signal:

• • The flash memory asserts the NWAIT signal one data cycle before the wait state (default after reset).
• • The flash memory asserts the NWAIT signal during the wait state

The FSMC supports both NOR flash wait state configurations, for each chip select, thanks to the WAITCFG bit in the FSMC_BCRx registers (x = 0..3).

Figure 48. Wait configuration waveforms

Figure 49. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)

1. 1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low.

Table 66. FSMC_BCRx bitfields (Synchronous multiplexed read mode)

Figure 50. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)

1. 1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. 2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.

Table 68. FSMC_BCRx bitfields (Synchronous multiplexed write mode)

11.6.6 NOR/PSRAM controller registers

SRAM/NOR-flash chip-select control register for bank x (FSMC_BCRx)

Address offset: \( 0x00 + 0x8 * (x - 1) \) , ( \( x = 1 \) to \( 4 \) )

Reset value: 0x0000 30DB, 0x0000 30D2, 0x0000 30D2, 0x0000 30D2

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR flash memories.

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 WFDIS: Write FIFO disable

This bit disables the Write FIFO used by the FSMC controller.

0: Write FIFO enabled (Default after reset)

1: Write FIFO disabled

Note: The WFDIS bit of the FSMC_BCR2..4 registers is don't care. It is only enabled through the FSMC_BCR1 register.

Bit 20 CCLKEN: Continuous clock enable

This bit enables the FSMC_CLK clock output to external memory devices.

0: The FSMC_CLK is only generated during the synchronous memory access (read/write transaction). The FSMC_CLK clock ratio is specified by the programmed CLKDIV value in the FSMC_BCRx register (default after reset).

1: The FSMC_CLK is generated continuously during asynchronous and synchronous access. The FSMC_CLK clock is activated when the CCLKEN is set.

Note: The CCLKEN bit of the FSMC_BCR2..4 registers is don't care. It is only enabled through the FSMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FSMC_CLK continuous clock.

Note: If CCLKEN bit is set, the FSMC_CLK clock ratio is specified by CLKDIV value in the FSMC_BTR1 register. CLKDIV in FSMC_BWTR1 is don't care.

Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FSMC_BTR2..4 and FSMC_BWTR2..4 registers for other banks has no effect.)

Bit 19 CBURSTRW: Write burst enable

For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FSMC_BCRx register.

0: Write operations are always performed in Asynchronous mode.

1: Write operations are performed in Synchronous mode.

These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FSMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size).

000: No burst split when crossing page boundary (default after reset)

001: 128 bytes

010: 256 bytes

011: 512 bytes

100: 1024 bytes

Others: Reserved, must not be used

This bit enables/disables the FSMC to use the wait signal even during an asynchronous protocol.

0: NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset).

1: NWAIT signal is taken in to account when running an asynchronous protocol.

This bit enables the FSMC to program the write timings for non multiplexed asynchronous accesses inside the FSMC_BWTR register, thus resulting in different timings for read and write operations.

0: values inside FSMC_BWTR register are not taken into account (default after reset)

1: values inside FSMC_BWTR register are taken into account

Note: When the Extended mode is disabled, the FSMC can operate in mode 1 or mode 2 as follows:

• – Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01)
• – Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).

This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode.

0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed flash latency period).

1: NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset).

This bit indicates whether write operations are enabled/disabled in the bank by the FSMC.

0: Write operations are disabled in the bank by the FSMC, an AHB error is reported.

1: Write operations are enabled for the bank by the FSMC (default after reset).

The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:

0: NWAIT signal is active one data cycle before wait state (default after reset).

1: NWAIT signal is active during wait state (not used for PSRAM).

Bit 10 Reserved, must be kept at reset value.

Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode.

0: NWAIT active low (default after reset)

1: NWAIT active high

Bit 8 BURSTEN : Burst enable bit

This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode.

• 0: Burst mode disabled (default after reset). Read accesses are performed in Asynchronous mode.
• 1: Burst mode enable. Read accesses are performed in Synchronous mode.

Bit 7 Reserved, must be kept at reset value.

Bit 6 FACCEN : Flash access enable

Enables NOR flash memory access operations.

• 0: Corresponding NOR flash memory access is disabled.
• 1: Corresponding NOR flash memory access is enabled (default after reset).

Bits 5:4 MWID[1:0] : Memory data bus width

Defines the external memory device width, valid for all type of memories.

• 00: 8 bits
• 01: 16 bits (default after reset)
• 10: reserved
• 11: reserved

Bits 3:2 MTYP[1:0] : Memory type

Defines the type of external memory attached to the corresponding memory bank.

• 00: SRAM (default after reset for Bank 2...4)
• 01: PSRAM (CRAM)
• 10: NOR flash/OneNAND flash (default after reset for Bank 1)
• 11: reserved

Bit 1 MUXEN : Address/data multiplexing enable bit

When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:

• 0: Address/data non multiplexed
• 1: Address/data multiplexed on databus (default after reset)

Bit 0 MBKEN : Memory bank enable bit

Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus.

• 0: Corresponding memory bank is disabled.
• 1: Corresponding memory bank is enabled.

SRAM/NOR-flash chip-select timing register for bank x (FSMC_BTRx)

Address offset: \( 0x04 + 0x8 * (x - 1) \) , ( \( x = 1 \) to \( 4 \) )

Reset value: 0x0FFF FFFF

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR flash memories. If the EXTMOD bit is set in the FSMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available:

one to configure read accesses (this register) and one to configure write accesses (FSMC_BWTRx registers).

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 ACCMOD[1:0] : Access mode

Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.

00: Access mode A

01: Access mode B

10: Access mode C

11: Access mode D

Bits 27:24 DATLAT[3:0] : (see note below bit descriptions): Data latency for synchronous memory

For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data:

This timing parameter is not expressed in HCLK periods, but in FSMC_CLK periods.

For asynchronous access, this value is don't care.

0000: Data latency of 2 CLK clock cycles for first burst access

1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)

Bits 23:20 CLKDIV[3:0] : Clock divide ratio (for FSMC_CLK signal)

Defines the period of FSMC_CLK clock output signal, expressed in number of HCLK cycles:

0000: FSMC_CLK period= 1x HCLK period

0001: FSMC_CLK period = 2 × HCLK periods

0010: FSMC_CLK period = 3 × HCLK periods

1111: FSMC_CLK period = 16 × HCLK periods (default value after reset)

In asynchronous NOR flash, SRAM or PSRAM accesses, this value is don't care.

Note: Refer to Section 11.6.5: Synchronous transactions for FSMC_CLK divider ratio formula

Bits 19:16 BUSTURN[3:0] : Bus turnaround phase duration

These bits are written by software to add a delay at the end of a write-to-read (and read-to-write) transaction. This delay enables to match the minimum time between consecutive transactions ( \( t_{\text{EHEL}} \) from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access ( \( t_{\text{EHQZ}} \) ). The programmed bus turnaround delay is inserted between an asynchronous read (muxed or mode D) or write transaction and any other asynchronous /synchronous read or write to or from a static bank. The bank can be the same or different in case of read, in case of write the bank can be different except for muxed or mode D.

In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is fixed as follows:

• • The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D.
• • There is a bus turnaround delay of 1 HCLK clock cycle between:
  • – Two consecutive asynchronous read transfers to the same static memory bank except for muxed mode and mode D.
  • – An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except for muxed mode and mode D.
  • – An asynchronous (modes 1, 2, A, B or C) read and a read from another static bank.
• • There is a bus turnaround delay of 2 HCLK clock cycle between:
  • – Two consecutive synchronous writes (burst or single) to the same bank.
  • – A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or different for the case of read).
  • – Two consecutive synchronous reads (burst or single) followed by any synchronous/asynchronous read or write from/to another static memory bank.
• • There is a bus turnaround delay of 3 HCLK clock cycle between:
  • – Two consecutive synchronous writes (burst or single) to different static bank.
  • – A synchronous write (burst or single) access and a synchronous read from the same or a different bank.

0000: BUSTURN phase duration = 0 HCLK clock cycle added

...

1111: BUSTURN phase duration = 15 x HCLK clock cycles added (default value after reset)

Bits 15:8 DATAST[7:0] : Data-phase duration

These bits are written by software to define the duration of the data phase (refer to Figure 33 to Figure 45 ), used in asynchronous accesses:

0000 0000: Reserved

0000 0001: DATAST phase duration = 1 × HCLK clock cycles

0000 0010: DATAST phase duration = 2 × HCLK clock cycles

...

1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)

For each memory type and access mode data-phase duration, refer to the respective figure ( Figure 33 to Figure 45 ).

Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles.

Note: In synchronous accesses, this value is don't care.

Bits 7:4 ADDHLD[3:0] : Address-hold phase duration

These bits are written by software to define the duration of the address hold phase (refer to Figure 33 to Figure 45 ), used in mode D or multiplexed accesses:

0000: Reserved

0001: ADDHLD phase duration = 1 × HCLK clock cycle

0010: ADDHLD phase duration = 2 × HCLK clock cycle

...

1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)

For each access mode address-hold phase duration, refer to the respective figure ( Figure 33 to Figure 45 ).

Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.

Bits 3:0 ADDSET[3:0] : Address setup phase duration

These bits are written by software to define the duration of the address setup phase (refer to Figure 33 to Figure 45 ), used in SRAMs, ROMs, asynchronous NOR flash and PSRAM:

0000: ADDSET phase duration = 0 × HCLK clock cycle

...

1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)

For each access mode address setup phase duration, refer to the respective figure ( Figure 33 to Figure 45 ).

Note: In synchronous accesses, this value is don't care.

In Muxed mode or mode D, the minimum value for ADDSET is 1.

In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.

Note: PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these memories issue the NWAIT signal during the whole latency phase to prolong the latency as needed. With PSRAMs (CRAMs) the filled DATLAT must be set to 0, so that the FSMC exits its latency phase soon and starts sampling NWAIT from memory, then starts to read or write when the memory is ready. This method can be used also with the latest generation of synchronous flash memories that issue the NWAIT signal, unlike older flash memories (check the datasheet of the specific flash memory being used).

SRAM/NOR-flash write timing registers x (FSMC_BWTRx)

Address offset: 0x104 + 0x8 * (x - 1), (x = 1 to 4)

Reset value: 0x0FFF FFFF

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR flash memories. When the EXTMOD bit is set in the FSMC_BCRx register, then this register is active for write access.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 ACCMOD[1:0] : Access mode.

Specifies the asynchronous access modes as shown in the next timing diagrams. These bits are taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.

00: Access mode A

01: Access mode B

10: Access mode C

11: Access mode D

Bits 27:20 Reserved, must be kept at reset value.

Bits 19:16 BUSTURN[3:0] : Bus turnaround phase duration

The programmed bus turnaround delay is inserted between an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. The bank can be the same or different in case of read, in case of write the bank can be different except for muxed or mode D.

In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is fixed as follows:

• • The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed and D modes.
• • There is a bus turnaround delay of 2 HCLK clock cycle between:
  • –Two consecutive synchronous writes (burst or single) to the same bank.
  • –A synchronous write (burst or single) transfer and an asynchronous write or read transfer to or from static memory bank.
• • There is a bus turnaround delay of 3 HCLK clock cycle between:
  • –Two consecutive synchronous writes (burst or single) to different static bank.
  • –A synchronous write (burst or single) transfer and a synchronous read from the same or a different bank.

0000: BUSTURN phase duration = 0 HCLK clock cycle added

...

1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)

Bits 15:8 DATAST[7:0] : Data-phase duration.

These bits are written by software to define the duration of the data phase (refer to Figure 33 to Figure 45 ), used in asynchronous SRAM, PSRAM and NOR flash memory accesses:

0000 0000: Reserved

0000 0001: DATAST phase duration = 1 × HCLK clock cycles

0000 0010: DATAST phase duration = 2 × HCLK clock cycles

...

1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)

Bits 7:4 ADDHLD[3:0] : Address-hold phase duration.

These bits are written by software to define the duration of the address hold phase (refer to Figure 42 to Figure 45 ), used in asynchronous multiplexed accesses:

0000: Reserved

0001: ADDHLD phase duration = 1 × HCLK clock cycle

0010: ADDHLD phase duration = 2 × HCLK clock cycle

...

1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)

Note: In synchronous NOR flash accesses, this value is not used, the address hold phase is always 1 flash clock period duration.

Bits 3:0 ADDSET[3:0] : Address setup phase duration.

These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 33 to Figure 45 ), used in asynchronous accesses:

0000: ADDSET phase duration = 0 × HCLK clock cycle

...

1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)

Note: In synchronous accesses, this value is not used, the address setup phase is always 1 flash clock period duration. In muxed mode, the minimum ADDSET value is 1.

11.6.7 FSMC register map

Table 70. FSMC register map and reset values

Table 70. FSMC register map and reset values (continued)