10. Interrupts and events

10.1 Nested vectored interrupt controller (NVIC)

10.1.1 NVIC features

The nested vector interrupt controller NVIC includes the following features:

• • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex ^® -M4 with FPU)
• • 16 programmable priority levels (4 bits of interrupt priority are used)
• • low-latency exception and interrupt handling
• • power management control
• • implementation of system control registers

The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts.

All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to programming manual PM0214.

10.1.2 SysTick calibration value register

The SysTick calibration value is fixed to 10500, which gives a reference time base of 1 ms with the SysTick clock set to 10.5 MHz (HCLK/8, with HCLK set to 84 MHz).

10.1.3 Interrupt and exception vectors

See Table 40 , for the vector table for the STM32F412xx devices.

10.2 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of up to 23 edge detectors for generating event/interrupt requests. Each input line can be independently configured to select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). Each line can also be masked independently. A pending register maintains the status line of the interrupt requests.

Table 40. Vector table for STM32F412xx

Table 40. Vector table for STM32F412xx (continued)

Table 40. Vector table for STM32F412xx (continued)

Table 40. Vector table for STM32F412xx (continued)

10.2.1 EXTI main features

The main features of the EXTI controller are the following:

• • independent trigger and mask on each interrupt/event line
• • dedicated status bit for each interrupt line
• • generation of up to 23 software event/interrupt requests
• • detection of external signals with a pulse width lower than the APB2 clock period. Refer to the electrical characteristics section of the STM32F4xx datasheets for details on this parameter.

10.2.2 EXTI block diagram

Figure 29 shows the block diagram.

Figure 29. External interrupt/event controller block diagram

10.2.3 Wakeup event management

The STM32F4xx are able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated either by:

• • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex®-M4 with FPU System Control register. When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
• • or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set.

To use an external line as a wakeup event, refer to Section 10.2.4: Functional description .

10.2.4 Functional description

To generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a '1' to the corresponding bit in the interrupt mask register. When the selected edge occurs on the external interrupt line, an interrupt request is generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a '1' in the pending register.

To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a '1' to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set.

An interrupt/event request can also be generated by software by writing a '1' in the software interrupt/event register.

Hardware interrupt selection

To configure the 23 lines as interrupt sources, use the following procedure:

• • Configure the mask bits of the 23 interrupt lines (EXTI_IMR)
• • Configure the Trigger selection bits of the interrupt lines (EXTI_RTSR and EXTI_FTSR)
• • Configure the enable and mask bits that control the NVIC IRQ channel mapped to the external interrupt controller (EXTI) so that an interrupt coming from one of the 23 lines can be correctly acknowledged.

Hardware event selection

To configure the 23 lines as event sources, use the following procedure:

• • Configure the mask bits of the 23 event lines (EXTI_EMR)
• • Configure the Trigger selection bits of the event lines (EXTI_RTSR and EXTI_FTSR)

Software interrupt/event selection

The 23 lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt.

• • Configure the mask bits of the 23 interrupt/event lines (EXTI_IMR, EXTI_EMR)
• • Set the required bit in the software interrupt register (EXTI_SWIER)

10.2.5 External interrupt/event line mapping

Up to STM32F412xx are connected to the 16 external interrupt/event lines in the following manner:

Figure 30. External interrupt/event GPIO mapping

The five other EXTI lines are connected as follows:

• • EXTI line 16 is connected to the PVD output
• • EXTI line 17 is connected to the RTC Alarm event
• • EXTI line 18 is connected to the USB OTG FS Wakeup event
• • EXTI line 21 is connected to the RTC Tamper and TimeStamp events
• • EXTI line 22 is connected to the RTC Wakeup event

10.3 EXTI registers

Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions.

10.3.1 Interrupt mask register (EXTI_IMR)

Address offset: 0x00

Reset value: 0x0000 0000

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 MR[22:21] : Interrupt mask on line x

0: Interrupt request from line x is masked

1: Interrupt request from line x is not masked

Bits 20:19 Reserved, must be kept at reset value.

Bits 18:0 MR[18:0] : Interrupt mask on line x

0: Interrupt request from line x is masked

1: Interrupt request from line x is not masked

10.3.2 Event mask register (EXTI_EMR)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 MR[22:21] : Event mask on line x

0: Interrupt request from line x is masked

1: Interrupt request from line x is not masked

Bits 20:19 Reserved, must be kept at reset value.

Bits 18:0 MR[18:0] : Event mask on line x

0: Interrupt request from line x is masked

1: Interrupt request from line x is not masked

10.3.3 Rising trigger selection register (EXTI_RTSR)

Address offset: 0x08

Reset value: 0x0000 0000

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 TR[22:21] : Rising trigger event configuration bit of line x

0: Rising trigger disabled (for Event and Interrupt) for input line

1: Rising trigger enabled (for Event and Interrupt) for input line

Bits 20:19 Reserved, must be kept at reset value.

Bits 18:0 TR[18:0] : Rising trigger event configuration bit of line x

0: Rising trigger disabled (for Event and Interrupt) for input line

1: Rising trigger enabled (for Event and Interrupt) for input line

Note: The external wakeup lines are edge triggered, no glitch must be generated on these lines. If a rising edge occurs on the external interrupt line while writing to the EXTI_RTSR register, the pending bit is set.

Rising and falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition.

10.3.4 Falling trigger selection register (EXTI_FTSR)

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 TR[22:21] : Falling trigger event configuration bit of line x

• 0: Falling trigger disabled (for Event and Interrupt) for input line
• 1: Falling trigger enabled (for Event and Interrupt) for input line.

Bits 20:19 Reserved, must be kept at reset value.

Bits 18:0 TR[18:0] : Falling trigger event configuration bit of line x

• 0: Falling trigger disabled (for Event and Interrupt) for input line
• 1: Falling trigger enabled (for Event and Interrupt) for input line.

Note: The external wakeup lines are edge triggered, no glitch must be generated on these lines. If a falling edge occurs on the external interrupt line while writing to the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition.

10.3.5 Software interrupt event register (EXTI_SWIER)

Address offset: 0x10

Reset value: 0x0000 0000

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 SWIER[22:21] : Software Interrupt on line x

If interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is set at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an interrupt request generation.

This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).

Bits 20:19 Reserved, must be kept at reset value.

Bits 18:0 SWIER[18:0] : Software Interrupt on line x

If interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is set at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an interrupt request generation.

This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).

10.3.6 Pending register (EXTI_PR)

Address offset: 0x14

Reset value: 0x0000 0000

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 PR[22:21] : Pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line.

This bit is cleared by programming it to '1'.

Bits 20:19 Reserved, must be kept at reset value.

Bits 18:0 PR[18:0] : Pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line.

This bit is cleared by programming it to '1'.

10.3.7 EXTI register map

Table 41 gives the EXTI register map and the reset values.

Table 41. External interrupt/event controller register map and reset values

Refer to Section 2.2 on page 49 for the register boundary addresses.