RM0402-STM32F412

This reference manual targets application developers. It provides complete information on how to use the memory and the peripherals of the STM32F412 microcontrollers.

The STM32F412 is a line of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics refer to the datasheet.

For information on the Arm ^®Cortex ^®-M4 with FPU core, refer to the Cortex ^®-M4 with FPU Technical Reference Manual.

The STM32F412xx microcontrollers include ST state-of-the-art patented technology.

Available from STMicroelectronics web site www.st.com :

• STM32F412xE STM32F412xG datasheet (DS11139)
• STM32 Cortex ^®-M4 MCUs and MPUs programming manual (PM0214)
• STM32F412xE and STM32F412xG device errata (ES0305)

1 Documentation conventions . . . . . 45
- 1.1 General information . . . . . 45
- 1.2 List of abbreviations for registers . . . . . 45
- 1.3 Register reset value . . . . . 45
- 1.4 Glossary . . . . . 46
- 1.5 Availability of peripherals . . . . . 46

2 System and memory overview . . . . . 47
- 2.1 System architecture . . . . . 47
  - 2.1.1 I-bus . . . . . 48
  - 2.1.2 D-bus . . . . . 48
  - 2.1.3 S-bus . . . . . 48
  - 2.1.4 DMA memory bus . . . . . 48
  - 2.1.5 DMA peripheral bus . . . . . 48
  - 2.1.6 BusMatrix . . . . . 48
  - 2.1.7 AHB/APB bridges (APB) . . . . . 48
- 2.2 Memory organization . . . . . 49
  - 2.2.1 Introduction . . . . . 49
  - 2.2.2 Memory map and register boundary addresses . . . . . 50
- 2.3 Embedded SRAM . . . . . 53
- 2.4 Flash memory overview . . . . . 54
- 2.5 Bit banding . . . . . 54
- 2.6 Boot configuration . . . . . 55

3 Embedded flash memory interface . . . . . 58
- 3.1 Introduction . . . . . 58
- 3.2 Main features . . . . . 58
- 3.3 Embedded flash memory . . . . . 59
- 3.4 Read interface . . . . . 60
  - 3.4.1 Relation between CPU clock frequency and flash memory read time . . . . . 60
  - 3.4.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . 61
- 3.5 Erase and program operations . . . . . 63
  - 3.5.1 Unlocking the flash control register . . . . . 63

3.5.2	Program/erase parallelism . . . . .	64
3.5.3	Erase . . . . .	64
3.5.4	Programming . . . . .	65
3.5.5	Interrupts . . . . .	66
3.6	Option bytes . . . . .	66
3.6.1	Description of user option bytes . . . . .	66
3.6.2	Programming user option bytes . . . . .	68
3.6.3	Read protection (RDP) . . . . .	68
3.6.4	Write protections . . . . .	70
3.6.5	Proprietary code readout protection (PCROP) . . . . .	71
3.7	One-time programmable bytes . . . . .	73
3.8	Flash interface registers . . . . .	74
3.8.1	Flash access control register (FLASH_ACR) . . . . .	74
3.8.2	Flash key register (FLASH_KEYR) . . . . .	75
3.8.3	Flash option key register (FLASH_OPTKEYR) . . . . .	75
3.8.4	Flash status register (FLASH_SR) . . . . .	76
3.8.5	Flash control register (FLASH_CR) . . . . .	77
3.8.6	Flash option control register (FLASH_OPTCR) . . . . .	78
3.8.7	Flash interface register map . . . . .	81
4	CRC calculation unit . . . . .	82
4.1	CRC introduction . . . . .	82
4.2	CRC main features . . . . .	82
4.3	CRC functional description . . . . .	82
4.4	CRC registers . . . . .	83
4.4.1	Data register (CRC_DR) . . . . .	83
4.4.2	Independent data register (CRC_IDR) . . . . .	84
4.4.3	Control register (CRC_CR) . . . . .	84
4.4.4	CRC register map . . . . .	85
5	Power controller (PWR) . . . . .	86
5.1	Power supplies . . . . .	86
5.1.1	Independent A/D converter supply and reference voltage . . . . .	87
5.1.2	Battery backup domain . . . . .	87
5.1.3	Voltage regulator . . . . .	89
5.2	Power supply supervisor . . . . .	90

- - 5.2.1 Power-on reset (POR)/power-down reset (PDR) . . . . . 90
  - 5.2.2 Brownout reset (BOR) . . . . . 90
  - 5.2.3 Programmable voltage detector (PVD) . . . . . 91
- 5.3 Low-power modes . . . . . 92
  - 5.3.1 Slowing down system clocks . . . . . 94
  - 5.3.2 Peripheral clock gating . . . . . 94
  - 5.3.3 Sleep mode . . . . . 95
  - 5.3.4 Batch acquisition mode . . . . . 96
  - 5.3.5 Stop mode . . . . . 97
  - 5.3.6 Standby mode . . . . . 100
  - 5.3.7 Programming the RTC alternate functions to wake up the device from the Stop and Standby modes . . . . . 101
- 5.4 Power control registers . . . . . 104
  - 5.4.1 PWR power control register (PWR_CR) . . . . . 104
  - 5.4.2 PWR power control/status register (PWR_CSR) . . . . . 106
- 5.5 PWR register map . . . . . 108
6 Reset and clock control (RCC) for STM32F412xx . . . . . 109
- 6.1 Reset . . . . . 109
  - 6.1.1 System reset . . . . . 109
  - 6.1.2 Power reset . . . . . 110
  - 6.1.3 Backup domain reset . . . . . 110
- 6.2 Clocks . . . . . 111
  - 6.2.1 HSE clock . . . . . 113
  - 6.2.2 HSI clock . . . . . 114
  - 6.2.3 PLL configuration . . . . . 115
  - 6.2.4 LSE clock . . . . . 115
  - 6.2.5 LSI clock . . . . . 116
  - 6.2.6 System clock (SYSCLK) selection . . . . . 116
  - 6.2.7 Clock security system (CSS) . . . . . 116
  - 6.2.8 RTC/AWU clock . . . . . 117
  - 6.2.9 Watchdog clock . . . . . 117
  - 6.2.10 Clock-out capability . . . . . 118
  - 6.2.11 Internal/external clock measurement using TIM5/TIM11 . . . . . 118
- 6.3 RCC registers . . . . . 121
  - 6.3.1 RCC clock control register (RCC_CR) . . . . . 121
  - 6.3.2 RCC PLL configuration register (RCC_PLLCFGR) . . . . . 123

6.3.3	RCC clock configuration register (RCC_CFGR) . . . . .	125
6.3.4	RCC clock interrupt register (RCC_CIR) . . . . .	128
6.3.5	RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .	130
6.3.6	RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .	132
6.3.7	RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . .	133
6.3.8	RCC APB1 peripheral reset register for (RCC_APB1RSTR) . . . . .	133
6.3.9	RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .	136
6.3.10	RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .	138
6.3.11	RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .	140
6.3.12	RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . .	141
6.3.13	RCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . .	141
6.3.14	RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .	144
6.3.15	RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR) . . . . .	146
6.3.16	RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR) . . . . .	148
6.3.17	RCC AHB3 peripheral clock enable in low power mode register (RCC_AHB3LPENR) . . . . .	148
6.3.18	RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR) . . . . .	150
6.3.19	RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) . . . . .	153
6.3.20	RCC Backup domain control register (RCC_BDCR) . . . . .	155
6.3.21	RCC clock control & status register (RCC_CSR) . . . . .	156
6.3.22	RCC spread spectrum clock generation register (RCC_SSCGR) . . . . .	159
6.3.23	RCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . .	160
6.3.24	RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR) . . . . .	162
6.3.25	RCC clocks gated enable register (CKGATENR) . . . . .	163
6.3.26	RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR2) . . . . .	164
6.3.27	RCC register map . . . . .	165
7	General-purpose I/Os (GPIO) . . . . .	168
7.1	GPIO introduction . . . . .	168
7.2	GPIO main features . . . . .	168
7.3	GPIO functional description . . . . .	168
7.3.1	General-purpose I/O (GPIO) . . . . .	170
7.3.2	I/O pin multiplexer and mapping . . . . .	171
7.3.3	I/O port control registers . . . . .	174

7.3.4	I/O port data registers . . . . .	174
7.3.5	I/O data bitwise handling . . . . .	174
7.3.6	GPIO locking mechanism . . . . .	174
7.3.7	I/O alternate function input/output . . . . .	175
7.3.8	External interrupt/wakeup lines . . . . .	175
7.3.9	Input configuration . . . . .	175
7.3.10	Output configuration . . . . .	176
7.3.11	Alternate function configuration . . . . .	177
7.3.12	Analog configuration . . . . .	178
7.3.13	Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins . . . . .	178
7.3.14	Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins . . . . .	178
7.3.15	Selection of RTC additional functions . . . . .	179
7.4	GPIO registers . . . . .	180
7.4.1	GPIO port mode register (GPIOx_MODER) (x = A...H) . . . . .	180
7.4.2	GPIO port output type register (GPIOx_OTYPER) (x = A...H) . . . . .	180
7.4.3	GPIO port output speed register (GPIOx_OSPEEDR) (x = A...H) . . . . .	181
7.4.4	GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A...H) . . . . .	181
7.4.5	GPIO port input data register (GPIOx_IDR) (x = A...H) . . . . .	182
7.4.6	GPIO port output data register (GPIOx_ODR) (x = A...H) . . . . .	182
7.4.7	GPIO port bit set/reset register (GPIOx_BSRR) (x = A...H) . . . . .	182
7.4.8	GPIO port configuration lock register (GPIOx_LCKR) (x = A...H) . . . . .	183
7.4.9	GPIO alternate function low register (GPIOx_AFRL) (x = A...H) . . . . .	184
7.4.10	GPIO alternate function high register (GPIOx_AFRH) (x = A...H) . . . . .	185
7.4.11	GPIO register map . . . . .	185
8	System configuration controller (SYSCFG) . . . . .	188
8.1	I/O compensation cell . . . . .	188
8.2	SYSCFG registers . . . . .	188
8.2.1	SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .	188
8.2.2	SYSCFG peripheral mode configuration register (SYSCFG_PMC) . . . . .	189
8.2.3	SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . .	190

8.2.4	SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) .....	190
8.2.5	SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) .....	191
8.2.6	SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) .....	192
8.2.7	SYSCFG configuration register 2 (SYSCFG_CFGR2) .....	192
8.2.8	Compensation cell control register (SYSCFG_CMPCR) .....	193
8.2.9	SYSCFG configuration register (SYSCFG_CFGR) .....	194
8.2.10	SYSCFG register map .....	195
9	Direct memory access controller (DMA) .....	196
9.1	DMA introduction .....	196
9.2	DMA main features .....	196
9.3	DMA functional description .....	198
9.3.1	DMA block diagram .....	198
9.3.2	DMA overview .....	198
9.3.3	DMA transactions .....	199
9.3.4	Channel selection .....	199
9.3.5	Arbiter .....	201
9.3.6	DMA streams .....	201
9.3.7	Source, destination and transfer modes .....	201
9.3.8	Pointer incrementation .....	205
9.3.9	Circular mode .....	206
9.3.10	Double-buffer mode .....	206
9.3.11	Programmable data width, packing/unpacking, endianness .....	207
9.3.12	Single and burst transfers .....	208
9.3.13	FIFO .....	209
9.3.14	DMA transfer completion .....	212
9.3.15	DMA transfer suspension .....	213
9.3.16	Flow controller .....	214
9.3.17	Summary of the possible DMA configurations .....	215
9.3.18	Stream configuration procedure .....	215
9.3.19	Error management .....	216
9.4	DMA interrupts .....	217
9.5	DMA registers .....	218
9.5.1	DMA low interrupt status register (DMA_LISR) .....	218

9.5.2 DMA high interrupt status register (DMA_HISR) . . . . . 219
9.5.3 DMA low interrupt flag clear register (DMA_LIFCR) . . . . . 220
9.5.4 DMA high interrupt flag clear register (DMA_HIFCR) . . . . . 220
9.5.5 DMA stream x configuration register (DMA_SxCR) . . . . . 221
9.5.6 DMA stream x number of data register (DMA_SxNDTR) . . . . . 224
9.5.7 DMA stream x peripheral address register (DMA_SxPAR) . . . . . 225
9.5.8 DMA stream x memory 0 address register
(DMA_SxM0AR) . . . . . 225
9.5.9 DMA stream x memory 1 address register
(DMA_SxM1AR) . . . . . 225
9.5.10 DMA stream x FIFO control register (DMA_SxFCR) . . . . . 226
9.5.11 DMA register map . . . . . 227

10 Interrupts and events . . . . . 231

10.1 Nested vectored interrupt controller (NVIC) . . . . . 231
- 10.1.1 NVIC features . . . . . 231
- 10.1.2 SysTick calibration value register . . . . . 231
- 10.1.3 Interrupt and exception vectors . . . . . 231
10.2 External interrupt/event controller (EXTI) . . . . . 231
- 10.2.1 EXTI main features . . . . . 235
- 10.2.2 EXTI block diagram . . . . . 236
- 10.2.3 Wakeup event management . . . . . 236
- 10.2.4 Functional description . . . . . 237
- 10.2.5 External interrupt/event line mapping . . . . . 238
10.3 EXTI registers . . . . . 239
- 10.3.1 Interrupt mask register (EXTI_IMR) . . . . . 239
- 10.3.2 Event mask register (EXTI_EMR) . . . . . 239
- 10.3.3 Rising trigger selection register (EXTI_RTSR) . . . . . 241
- 10.3.4 Falling trigger selection register (EXTI_FTSR) . . . . . 242
- 10.3.5 Software interrupt event register (EXTI_SWIER) . . . . . 243
- 10.3.6 Pending register (EXTI_PR) . . . . . 244
- 10.3.7 EXTI register map . . . . . 245

11 Flexible static memory controller (FSMC) . . . . . 246

11.1 Introduction . . . . . 246
11.2 FSMC main features . . . . . 246
11.3 FMC block diagram . . . . . 247

11.4	AHB interface . . . . .	247
11.4.1	Supported memories and transactions . . . . .	248
11.5	External device address mapping . . . . .	249
11.5.1	NOR/PSRAM address mapping . . . . .	249
11.6	NOR flash/PSRAM controller . . . . .	250
11.6.1	External memory interface signals . . . . .	251
11.6.2	Supported memories and transactions . . . . .	253
11.6.3	General timing rules . . . . .	254
11.6.4	NOR flash/PSRAM controller asynchronous transactions . . . . .	254
11.6.5	Synchronous transactions . . . . .	272
11.6.6	NOR/PSRAM controller registers . . . . .	279
11.6.7	FSMC register map . . . . .	286
12	Quad-SPI interface (QUADSPI) . . . . .	288
12.1	Introduction . . . . .	288
12.2	QUADSPI main features . . . . .	288
12.3	QUADSPI functional description . . . . .	288
12.3.1	QUADSPI block diagram . . . . .	288
12.3.2	QUADSPI pins . . . . .	289
12.3.3	QUADSPI command sequence . . . . .	289
12.3.4	QUADSPI signal interface protocol modes . . . . .	292
12.3.5	QUADSPI indirect mode . . . . .	294
12.3.6	QUADSPI automatic status-polling mode . . . . .	296
12.3.7	QUADSPI memory-mapped mode . . . . .	296
12.3.8	QUADSPI flash memory configuration . . . . .	297
12.3.9	QUADSPI delayed data sampling . . . . .	297
12.3.10	QUADSPI configuration . . . . .	297
12.3.11	QUADSPI use . . . . .	298
12.3.12	Sending the instruction only once . . . . .	300
12.3.13	QUADSPI error management . . . . .	300
12.3.14	QUADSPI busy bit and abort functionality . . . . .	300
12.3.15	NCS behavior . . . . .	301
12.4	QUADSPI interrupts . . . . .	303
12.5	QUADSPI registers . . . . .	303
12.5.1	QUADSPI control register (QUADSPI_CR) . . . . .	303
12.5.2	QUADSPI device configuration register (QUADSPI_DCR) . . . . .	306

- 12.5.3 QUADSPI status register (QUADSPI_SR) . . . . . 307
- 12.5.4 QUADSPI flag clear register (QUADSPI_FCR) . . . . . 308
- 12.5.5 QUADSPI data length register (QUADSPI_DLR) . . . . . 308
- 12.5.6 QUADSPI communication configuration register (QUADSPI_CCR) . . 309
- 12.5.7 QUADSPI address register (QUADSPI_AR) . . . . . 311
- 12.5.8 QUADSPI alternate-byte register (QUADSPI_ABR) . . . . . 311
- 12.5.9 QUADSPI data register (QUADSPI_DR) . . . . . 312
- 12.5.10 QUADSPI polling status mask register (QUADSPI_PSMKR) . . . . . 312
- 12.5.11 QUADSPI polling status match register (QUADSPI_PSMAR) . . . . . 313
- 12.5.12 QUADSPI polling interval register (QUADSPI_PIR) . . . . . 313
- 12.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR) . . . . . 314
- 12.5.14 QUADSPI register map . . . . . 314

13 Analog-to-digital converter (ADC) . . . . . 316
13.1 ADC introduction . . . . . 316
13.2 ADC main features . . . . . 316
13.3 ADC functional description . . . . . 317
- 13.3.1 ADC on-off control . . . . . 318
- 13.3.2 ADC clock . . . . . 318
- 13.3.3 Channel selection . . . . . 318
- 13.3.4 Single conversion mode . . . . . 319
- 13.3.5 Continuous conversion mode . . . . . 319
- 13.3.6 Timing diagram . . . . . 320
- 13.3.7 Analog watchdog . . . . . 320
- 13.3.8 Scan mode . . . . . 321
- 13.3.9 Injected channel management . . . . . 321
- 13.3.10 Discontinuous mode . . . . . 322
13.4 Data alignment . . . . . 323
13.5 Channel-wise programmable sampling time . . . . . 324
13.6 Conversion on external trigger and trigger polarity . . . . . 325
13.7 Fast conversion mode . . . . . 326
13.8 Data management . . . . . 327
- 13.8.1 Using the DMA . . . . . 327
- 13.8.2 Managing a sequence of conversions without using the DMA . . . . . 327
- 13.8.3 Conversions without DMA and without overrun detection . . . . . 328
13.9 Temperature sensor . . . . . 328

13.10	Battery charge monitoring . . . . .	329
13.11	ADC interrupts . . . . .	330
13.12	ADC registers . . . . .	331
13.12.1	ADC status register (ADC_SR) . . . . .	331
13.12.2	ADC control register 1 (ADC_CR1) . . . . .	332
13.12.3	ADC control register 2 (ADC_CR2) . . . . .	334
13.12.4	ADC sample time register 1 (ADC_SMPR1) . . . . .	336
13.12.5	ADC sample time register 2 (ADC_SMPR2) . . . . .	337
13.12.6	ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . . . .	337
13.12.7	ADC watchdog higher threshold register (ADC_HTR) . . . . .	337
13.12.8	ADC watchdog lower threshold register (ADC_LTR) . . . . .	338
13.12.9	ADC regular sequence register 1 (ADC_SQR1) . . . . .	338
13.12.10	ADC regular sequence register 2 (ADC_SQR2) . . . . .	339
13.12.11	ADC regular sequence register 3 (ADC_SQR3) . . . . .	340
13.12.12	ADC injected sequence register (ADC_JSQR) . . . . .	341
13.12.13	ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . .	341
13.12.14	ADC regular data register (ADC_DR) . . . . .	342
13.12.15	ADC Common status register (ADC_CSR) . . . . .	342
13.12.16	ADC common control register (ADC_CCR) . . . . .	343
13.12.17	ADC register map . . . . .	344
14	Digital filter for sigma delta modulators (DFSDM) . . . . .	346
14.1	Introduction . . . . .	346
14.2	DFSDM main features . . . . .	347
14.3	DFSDM implementation . . . . .	348
14.4	DFSDM functional description . . . . .	349
14.4.1	DFSDM block diagram . . . . .	349
14.4.2	DFSDM pins and internal signals . . . . .	350
14.4.3	DFSDM reset and clocks . . . . .	351
14.4.4	Serial channel transceivers . . . . .	352
14.4.5	Configuring the input serial interface . . . . .	362
14.4.6	Parallel data inputs . . . . .	362
14.4.7	Channel selection . . . . .	364
14.4.8	Digital filter configuration . . . . .	364
14.4.9	Integrator unit . . . . .	366
14.4.10	Analog watchdog . . . . .	366

14.4.11	Short-circuit detector . . . . .	369
14.4.12	Extreme detector . . . . .	369
14.4.13	Data unit block . . . . .	370
14.4.14	Signed data format . . . . .	371
14.4.15	Launching conversions . . . . .	371
14.4.16	Continuous and fast continuous modes . . . . .	372
14.4.17	Request precedence . . . . .	372
14.4.18	Power optimization in run mode . . . . .	373
14.5	DFSDM interrupts . . . . .	373
14.6	DFSDM DMA transfer . . . . .	375
14.7	DFSDM channel y registers (y=0..3) . . . . .	375
14.7.1	DFSDM channel y configuration register (DFSDM_CHyCFGR1) . . . . .	375
14.7.2	DFSDM channel y configuration register (DFSDM_CHyCFGR2) . . . . .	378
14.7.3	DFSDM channel y analog watchdog and short-circuit detector register (DFSDM_CHyAWSCDR) . . . . .	378
14.7.4	DFSDM channel y watchdog filter data register (DFSDM_CHyWDATR) . . . . .	379
14.7.5	DFSDM channel y data input register (DFSDM_CHyDATINR) . . . . .	380
14.8	DFSDM filter x module registers (x=0..1) . . . . .	381
14.8.1	DFSDM filter x control register 1 (DFSDM_FLTxCR1) . . . . .	381
14.8.2	DFSDM filter x control register 2 (DFSDM_FLTxCR2) . . . . .	383
14.8.3	DFSDM filter x interrupt and status register (DFSDM_FLTxISR) . . . . .	385
14.8.4	DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) . . . . .	386
14.8.5	DFSDM filter x injected channel group selection register (DFSDM_FLTxJCHGR) . . . . .	387
14.8.6	DFSDM filter x control register (DFSDM_FLTxFCR) . . . . .	388
14.8.7	DFSDM filter x data register for injected group (DFSDM_FLTxJDATAR) . . . . .	389
14.8.8	DFSDM filter x data register for the regular channel (DFSDM_FLTxRDATAR) . . . . .	390
14.8.9	DFSDM filter x analog watchdog high threshold register (DFSDM_FLTxAWHTR) . . . . .	390
14.8.10	DFSDM filter x analog watchdog low threshold register (DFSDM_FLTxAWLTR) . . . . .	391
14.8.11	DFSDM filter x analog watchdog status register (DFSDM_FLTxAWSR) . . . . .	392
14.8.12	DFSDM filter x analog watchdog clear flag register (DFSDM_FLTxAWCFR) . . . . .	392

14.8.13	DFSDM filter x extremes detector maximum register (DFSDM_FLTxEXMAX) . . . . .	393
14.8.14	DFSDM filter x extremes detector minimum register (DFSDM_FLTxEXMIN) . . . . .	393
14.8.15	DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . . . . .	394
14.8.16	DFSDM register map . . . . .	395
15	True random number generator (RNG) . . . . .	400
15.1	Introduction . . . . .	400
15.2	RNG main features . . . . .	400
15.3	RNG functional description . . . . .	401
15.3.1	RNG block diagram . . . . .	401
15.3.2	RNG internal signals . . . . .	401
15.3.3	Random number generation . . . . .	402
15.3.4	RNG initialization . . . . .	404
15.3.5	RNG operation . . . . .	404
15.3.6	RNG clocking . . . . .	405
15.3.7	Error management . . . . .	405
15.3.8	RNG low-power use . . . . .	406
15.4	RNG interrupts . . . . .	406
15.5	RNG processing time . . . . .	406
15.6	RNG entropy source validation . . . . .	406
15.6.1	Introduction . . . . .	406
15.6.2	Validation conditions . . . . .	407
15.6.3	Data collection . . . . .	407
15.7	RNG registers . . . . .	407
15.7.1	RNG control register (RNG_CR) . . . . .	407
15.7.2	RNG status register (RNG_SR) . . . . .	408
15.7.3	RNG data register (RNG_DR) . . . . .	409
15.7.4	RNG register map . . . . .	410
16	Advanced-control timers (TIM1&TIM8) . . . . .	411
16.1	TIM1&TIM8 introduction . . . . .	411
16.2	TIM1&TIM8 main features . . . . .	411
16.3	TIM1&TIM8 functional description . . . . .	413
16.3.1	Time-base unit . . . . .	413
16.3.2	Counter modes . . . . .	415

16.3.3	Repetition counter . . . . .	424
16.3.4	Clock selection . . . . .	426
16.3.5	Capture/compare channels . . . . .	429
16.3.6	Input capture mode . . . . .	432
16.3.7	PWM input mode . . . . .	433
16.3.8	Forced output mode . . . . .	433
16.3.9	Output compare mode . . . . .	434
16.3.10	PWM mode . . . . .	435
16.3.11	Complementary outputs and dead-time insertion . . . . .	438
16.3.12	Using the break function . . . . .	440
16.3.13	Clearing the OCxREF signal on an external event . . . . .	443
16.3.14	6-step PWM generation . . . . .	444
16.3.15	One-pulse mode . . . . .	445
16.3.16	Encoder interface mode . . . . .	446
16.3.17	Timer input XOR function . . . . .	449
16.3.18	Interfacing with Hall sensors . . . . .	449
16.3.19	TIMx and external trigger synchronization . . . . .	451
16.3.20	Timer synchronization . . . . .	454
16.3.21	Debug mode . . . . .	454
16.4	TIM1&TIM8 registers . . . . .	455
16.4.1	TIM1&TIM8 control register 1 (TIMx_CR1) . . . . .	455
16.4.2	TIM1&TIM8 control register 2 (TIMx_CR2) . . . . .	456
16.4.3	TIM1&TIM8 slave mode control register (TIMx_SMCR) . . . . .	458
16.4.4	TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . .	460
16.4.5	TIM1&TIM8 status register (TIMx_SR) . . . . .	462
16.4.6	TIM1&TIM8 event generation register (TIMx_EGR) . . . . .	463
16.4.7	TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . .	464
16.4.8	TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . .	467
16.4.9	TIM1&TIM8 capture/compare enable register (TIMx_CCER) . . . . .	469
16.4.10	TIM1&TIM8 counter (TIMx_CNT) . . . . .	473
16.4.11	TIM1&TIM8 prescaler (TIMx_PSC) . . . . .	473
16.4.12	TIM1&TIM8 auto-reload register (TIMx_ARR) . . . . .	473
16.4.13	TIM1&TIM8 repetition counter register (TIMx_RCR) . . . . .	473
16.4.14	TIM1&TIM8 capture/compare register 1 (TIMx_CCR1) . . . . .	474
16.4.15	TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) . . . . .	474
16.4.16	TIM1&TIM8 capture/compare register 3 (TIMx_CCR3) . . . . .	475
16.4.17	TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) . . . . .	475

16.4.18	TIM1&TIM8 break and dead-time register (TIMx_BDTR) . . . . .	475
16.4.19	TIM1&TIM8 DMA control register (TIMx_DCR) . . . . .	477
16.4.20	TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) . . . . .	478
16.4.21	TIM1&TIM8 register map . . . . .	479
17	General-purpose timers (TIM2 to TIM5) . . . . .	481
17.1	TIM2 to TIM5 introduction . . . . .	481
17.2	TIM2 to TIM5 main features . . . . .	481
17.3	TIM2 to TIM5 functional description . . . . .	482
17.3.1	Time-base unit . . . . .	482
17.3.2	Counter modes . . . . .	484
17.3.3	Clock selection . . . . .	493
17.3.4	Capture/compare channels . . . . .	496
17.3.5	Input capture mode . . . . .	498
17.3.6	PWM input mode . . . . .	499
17.3.7	Forced output mode . . . . .	500
17.3.8	Output compare mode . . . . .	500
17.3.9	PWM mode . . . . .	502
17.3.10	One-pulse mode . . . . .	505
17.3.11	Clearing the OCxREF signal on an external event . . . . .	506
17.3.12	Encoder interface mode . . . . .	507
17.3.13	Timer input XOR function . . . . .	509
17.3.14	Timers and external trigger synchronization . . . . .	509
17.3.15	Timer synchronization . . . . .	513
17.3.16	Debug mode . . . . .	518
17.4	TIM2 to TIM5 registers . . . . .	519
17.4.1	TIMx control register 1 (TIMx_CR1) . . . . .	519
17.4.2	TIMx control register 2 (TIMx_CR2) . . . . .	521
17.4.3	TIMx slave mode control register (TIMx_SMCR) . . . . .	522
17.4.4	TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . .	524
17.4.5	TIMx status register (TIMx_SR) . . . . .	525
17.4.6	TIMx event generation register (TIMx_EGR) . . . . .	527
17.4.7	TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . .	528
17.4.8	TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . .	531
17.4.9	TIMx capture/compare enable register (TIMx_CCER) . . . . .	532
17.4.10	TIMx counter (TIMx_CNT) . . . . .	534
17.4.11	TIMx prescaler (TIMx_PSC) . . . . .	534

17.4.12	TIMx auto-reload register (TIMx_ARR) . . . . .	534
17.4.13	TIMx capture/compare register 1 (TIMx_CCR1) . . . . .	535
17.4.14	TIMx capture/compare register 2 (TIMx_CCR2) . . . . .	535
17.4.15	TIMx capture/compare register 3 (TIMx_CCR3) . . . . .	536
17.4.16	TIMx capture/compare register 4 (TIMx_CCR4) . . . . .	536
17.4.17	TIMx DMA control register (TIMx_DCR) . . . . .	537
17.4.18	TIMx DMA address for full transfer (TIMx_DMAR) . . . . .	537
17.4.19	TIM2 option register (TIM2_OR) . . . . .	538
17.4.20	TIM5 option register (TIM5_OR) . . . . .	539
17.4.21	TIMx register map . . . . .	540
18	General-purpose timers (TIM9 to TIM14) . . . . .	542
18.1	TIM9 to TIM14 introduction . . . . .	542
18.2	TIM9 to TIM14 main features . . . . .	542
18.2.1	TIM9/TIM12 main features . . . . .	542
18.2.2	TIM10/TIM11 and TIM13/TIM14 main features . . . . .	543
18.3	TIM9 to TIM14 functional description . . . . .	545
18.3.1	Time-base unit . . . . .	545
18.3.2	Counter modes . . . . .	547
18.3.3	Clock selection . . . . .	550
18.3.4	Capture/compare channels . . . . .	552
18.3.5	Input capture mode . . . . .	553
18.3.6	PWM input mode (only for TIM9/12) . . . . .	554
18.3.7	Forced output mode . . . . .	555
18.3.8	Output compare mode . . . . .	556
18.3.9	PWM mode . . . . .	557
18.3.10	One-pulse mode . . . . .	558
18.3.11	TIM9/12 external trigger synchronization . . . . .	560
18.3.12	Timer synchronization (TIM9/12) . . . . .	563
18.3.13	Debug mode . . . . .	563
18.4	TIM9 and TIM12 registers . . . . .	563
18.4.1	TIM9/12 control register 1 (TIMx_CR1) . . . . .	563
18.4.2	TIM9/12 slave mode control register (TIMx_SMCR) . . . . .	565
18.4.3	TIM9/12 Interrupt enable register (TIMx_DIER) . . . . .	566
18.4.4	TIM9/12 status register (TIMx_SR) . . . . .	567
18.4.5	TIM9/12 event generation register (TIMx_EGR) . . . . .	569
18.4.6	TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) . . . . .	569

18.4.7	TIM9/12 capture/compare enable register (TIMx_CCER) . . . . .	573
18.4.8	TIM9/12 counter (TIMx_CNT) . . . . .	574
18.4.9	TIM9/12 prescaler (TIMx_PSC) . . . . .	574
18.4.10	TIM9/12 auto-reload register (TIMx_ARR) . . . . .	574
18.4.11	TIM9/12 capture/compare register 1 (TIMx_CCR1) . . . . .	575
18.4.12	TIM9/12 capture/compare register 2 (TIMx_CCR2) . . . . .	575
18.4.13	TIM9/12 register map . . . . .	576
18.5	TIM10/11/13/14 registers . . . . .	578
18.5.1	TIM10/11/13/14 control register 1 (TIMx_CR1) . . . . .	578
18.5.2	TIM10/11/13/14 Interrupt enable register (TIMx_DIER) . . . . .	579
18.5.3	TIM10/11/13/14 status register (TIMx_SR) . . . . .	579
18.5.4	TIM10/11/13/14 event generation register (TIMx_EGR) . . . . .	580
18.5.5	TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) . . . . .	581
18.5.6	TIM10/11/13/14 capture/compare enable register (TIMx_CCER) . . . . .	584
18.5.7	TIM10/11/13/14 counter (TIMx_CNT) . . . . .	585
18.5.8	TIM10/11/13/14 prescaler (TIMx_PSC) . . . . .	585
18.5.9	TIM10/11/13/14 auto-reload register (TIMx_ARR) . . . . .	585
18.5.10	TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) . . . . .	586
18.5.11	TIM11 option register 1 (TIM11_OR) . . . . .	586
18.5.12	TIM10/11/13/14 register map . . . . .	587
19	Basic timers (TIM6/7) . . . . .	589
19.1	Introduction . . . . .	589
19.2	TIM6/7 main features . . . . .	589
19.3	TIM6/7 functional description . . . . .	590
19.3.1	Time-base unit . . . . .	590
19.3.2	Counting mode . . . . .	592
19.3.3	Clock source . . . . .	595
19.3.4	Debug mode . . . . .	596
19.4	TIM6/7 registers . . . . .	597
19.4.1	TIM6/7 control register 1 (TIMx_CR1) . . . . .	597
19.4.2	TIM6/7 control register 2 (TIMx_CR2) . . . . .	598
19.4.3	TIM6/7 DMA/Interrupt enable register (TIMx_DIER) . . . . .	598
19.4.4	TIM6/7 status register (TIMx_SR) . . . . .	599
19.4.5	TIM6/7 event generation register (TIMx_EGR) . . . . .	599

- 19.4.6 TIM6/7 counter (TIMx_CNT) . . . . . 599
- 19.4.7 TIM6/7 prescaler (TIMx_PSC) . . . . . 600
- 19.4.8 TIM6/7 auto-reload register (TIMx_ARR) . . . . . 600
- 19.4.9 TIM6/7 register map . . . . . 601
20 Independent watchdog (IWDG) . . . . . 602
- 20.1 IWDG introduction . . . . . 602
- 20.2 IWDG main features . . . . . 602
- 20.3 IWDG functional description . . . . . 602
  - 20.3.1 Hardware watchdog . . . . . 602
  - 20.3.2 Register access protection . . . . . 602
  - 20.3.3 Debug mode . . . . . 603
- 20.4 IWDG registers . . . . . 604
  - 20.4.1 Key register (IWDG_KR) . . . . . 604
  - 20.4.2 Prescaler register (IWDG_PR) . . . . . 605
  - 20.4.3 Reload register (IWDG_RLR) . . . . . 606
  - 20.4.4 Status register (IWDG_SR) . . . . . 606
  - 20.4.5 IWDG register map . . . . . 607
21 Window watchdog (WWDG) . . . . . 608
- 21.1 WWDG introduction . . . . . 608
- 21.2 WWDG main features . . . . . 608
- 21.3 WWDG functional description . . . . . 608
- 21.4 How to program the watchdog timeout . . . . . 610
- 21.5 Debug mode . . . . . 611
- 21.6 WWDG registers . . . . . 612
  - 21.6.1 Control register (WWDG_CR) . . . . . 612
  - 21.6.2 Configuration register (WWDG_CFR) . . . . . 613
  - 21.6.3 Status register (WWDG_SR) . . . . . 613
  - 21.6.4 WWDG register map . . . . . 614
22 Real-time clock (RTC) . . . . . 615
- 22.1 Introduction . . . . . 615
- 22.2 RTC main features . . . . . 615
- 22.3 RTC functional description . . . . . 617
  - 22.3.1 Clock and prescalers . . . . . 617

22.3.2	Real-time clock and calendar . . . . .	617
22.3.3	Programmable alarms . . . . .	618
22.3.4	Periodic auto-wakeup . . . . .	618
22.3.5	RTC initialization and configuration . . . . .	619
22.3.6	Reading the calendar . . . . .	621
22.3.7	Resetting the RTC . . . . .	622
22.3.8	RTC synchronization . . . . .	622
22.3.9	RTC reference clock detection . . . . .	623
22.3.10	RTC coarse digital calibration . . . . .	623
22.3.11	RTC smooth digital calibration . . . . .	624
22.3.12	Timestamp function . . . . .	626
22.3.13	Tamper detection . . . . .	627
22.3.14	Calibration clock output . . . . .	628
22.3.15	Alarm output . . . . .	629
22.4	RTC and low power modes . . . . .	629
22.5	RTC interrupts . . . . .	630
22.6	RTC registers . . . . .	631
22.6.1	RTC time register (RTC_TR) . . . . .	631
22.6.2	RTC date register (RTC_DR) . . . . .	632
22.6.3	RTC control register (RTC_CR) . . . . .	633
22.6.4	RTC initialization and status register (RTC_ISR) . . . . .	635
22.6.5	RTC prescaler register (RTC_PRER) . . . . .	637
22.6.6	RTC wakeup timer register (RTC_WUTR) . . . . .	638
22.6.7	RTC calibration register (RTC_CALIBR) . . . . .	639
22.6.8	RTC alarm A register (RTC_ALRMAR) . . . . .	640
22.6.9	RTC alarm B register (RTC_ALRMBR) . . . . .	641
22.6.10	RTC write protection register (RTC_WPR) . . . . .	642
22.6.11	RTC sub second register (RTC_SSR) . . . . .	642
22.6.12	RTC shift control register (RTC_SHIFT) . . . . .	643
22.6.13	RTC time stamp time register (RTC_TSTR) . . . . .	644
22.6.14	RTC time stamp date register (RTC_TSDR) . . . . .	644
22.6.15	RTC timestamp sub second register (RTC_TSSSR) . . . . .	645
22.6.16	RTC calibration register (RTC_CALR) . . . . .	645
22.6.17	RTC tamper and alternate function configuration register (RTC_TAFCR) . . . . .	646
22.6.18	RTC alarm A sub second register (RTC_ALRMASSR) . . . . .	648
22.6.19	RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .	649

22.6.20	RTC backup registers (RTC_BKPxR) . . . . .	650
22.6.21	RTC register map . . . . .	650
23	Fast-mode Plus Inter-integrated circuit interface (FMPI2C) . . . . .	653
23.1	Introduction . . . . .	653
23.2	FMPI2C main features . . . . .	653
23.3	FMPI2C implementation . . . . .	654
23.4	FMPI2C functional description . . . . .	654
23.4.1	FMPI2C block diagram . . . . .	655
23.4.2	FMPI2C pins and internal signals . . . . .	655
23.4.3	FMPI2C clock requirements . . . . .	656
23.4.4	FMPI2C mode selection . . . . .	656
23.4.5	FMPI2C initialization . . . . .	657
23.4.6	FMPI2C reset . . . . .	661
23.4.7	FMPI2C data transfer . . . . .	662
23.4.8	FMPI2C target mode . . . . .	664
23.4.9	FMPI2C controller mode . . . . .	673
23.4.10	FMPI2C_TIMINGR register configuration examples . . . . .	684
23.4.11	SMBus specific features . . . . .	686
23.4.12	SMBus initialization . . . . .	688
23.4.13	SMBus FMPI2C_TIMEOUTR register configuration examples . . . . .	690
23.4.14	SMBus target mode . . . . .	691
23.4.15	SMBus controller mode . . . . .	694
23.4.16	Error conditions . . . . .	697
23.5	FMPI2C in low-power modes . . . . .	699
23.6	FMPI2C interrupts . . . . .	699
23.7	FMPI2C DMA requests . . . . .	700
23.7.1	Transmission using DMA . . . . .	700
23.7.2	Reception using DMA . . . . .	700
23.8	FMPI2C debug modes . . . . .	701
23.9	FMPI2C registers . . . . .	701
23.9.1	FMPI2C control register 1 (FMPI2C_CR1) . . . . .	701
23.9.2	FMPI2C control register 2 (FMPI2C_CR2) . . . . .	704
23.9.3	FMPI2C own address 1 register (FMPI2C_OAR1) . . . . .	706
23.9.4	FMPI2C own address 2 register (FMPI2C_OAR2) . . . . .	706
23.9.5	FMPI2C timing register (FMPI2C_TIMINGR) . . . . .	707

23.9.6	FMPI2C timeout register (FMPI2C_TIMEOUTR) . . . . .	708
23.9.7	FMPI2C interrupt and status register (FMPI2C_ISR) . . . . .	709
23.9.8	FMPI2C interrupt clear register (FMPI2C_ICR) . . . . .	712
23.9.9	FMPI2C PEC register (FMPI2C_PECR) . . . . .	713
23.9.10	FMPI2C receive data register (FMPI2C_RXDR) . . . . .	713
23.9.11	FMPI2C transmit data register (FMPI2C_TXDR) . . . . .	714
23.9.12	FMPI2C register map . . . . .	715
24	Inter-integrated circuit (I ²C) interface . . . . .	716
24.1	I ²C introduction . . . . .	716
24.2	I ²C main features . . . . .	717
24.3	I ²C functional description . . . . .	718
24.3.1	Mode selection . . . . .	718
24.3.2	I2C target mode . . . . .	719
24.3.3	I2C controller mode . . . . .	721
24.3.4	Error conditions . . . . .	726
24.3.5	Programmable noise filter . . . . .	727
24.3.6	SDA/SCL line control . . . . .	728
24.3.7	SMBus . . . . .	728
24.3.8	DMA requests . . . . .	730
24.3.9	Packet error checking . . . . .	732
24.4	I ²C interrupts . . . . .	733
24.5	I ²C debug mode . . . . .	734
24.6	I ²C registers . . . . .	735
24.6.1	I ²C control register 1 (I2C_CR1) . . . . .	735
24.6.2	I ²C control register 2 (I2C_CR2) . . . . .	737
24.6.3	I ²C own address register 1 (I2C_OAR1) . . . . .	738
24.6.4	I ²C own address register 2 (I2C_OAR2) . . . . .	739
24.6.5	I ²C data register (I2C_DR) . . . . .	739
24.6.6	I ²C status register 1 (I2C_SR1) . . . . .	739
24.6.7	I ²C status register 2 (I2C_SR2) . . . . .	742
24.6.8	I ²C clock control register (I2C_CCR) . . . . .	743
24.6.9	I ²C TRISE register (I2C_TRISE) . . . . .	744
24.6.10	I ²C FLTR register (I2C_FLTR) . . . . .	745
24.6.11	I2C register map . . . . .	746

25 Universal synchronous receiver transmitter (USART)
/universal asynchronous receiver transmitter (UART) . . . . . 747

25.1 USART introduction . . . . . 747

25.2 USART main features . . . . . 748

25.3 USART implementation . . . . . 749

25.4 USART functional description . . . . . 749

25.4.1 USART character description . . . . . 752

25.4.2 Transmitter . . . . . 753

25.4.3 Receiver . . . . . 756

25.4.4 Fractional baud rate generation . . . . . 761

25.4.5 USART receiver tolerance to clock deviation . . . . . 771

25.4.6 Multiprocessor communication . . . . . 772

25.4.7 Parity control . . . . . 774

25.4.8 LIN (local interconnection network) mode . . . . . 775

25.4.9 USART synchronous mode . . . . . 777

25.4.10 Single-wire half-duplex communication . . . . . 779

25.4.11 Smartcard . . . . . 780

25.4.12 IrDA SIR ENDEC block . . . . . 782

25.4.13 Continuous communication using DMA . . . . . 784

25.4.14 Hardware flow control . . . . . 786

25.5 USART interrupts . . . . . 788

25.6 USART registers . . . . . 789

25.6.1 Status register (USART_SR) . . . . . 789

25.6.2 Data register (USART_DR) . . . . . 792

25.6.3 Baud rate register (USART_BRR) . . . . . 792

25.6.4 Control register 1 (USART_CR1) . . . . . 793

25.6.5 Control register 2 (USART_CR2) . . . . . 795

25.6.6 Control register 3 (USART_CR3) . . . . . 796

25.6.7 Guard time and prescaler register (USART_GTPR) . . . . . 798

25.6.8 USART register map . . . . . 799

26 Serial peripheral interface/ inter-IC sound (SPI/I2S) . . . . . 800

26.1 Introduction . . . . . 800

26.1.1 SPI main features . . . . . 801

26.1.2 SPI extended features . . . . . 802

26.1.3 I2S features . . . . . 802

26.2	SPI/I2S implementation . . . . .	802
26.3	SPI functional description . . . . .	803
26.3.1	General description . . . . .	803
26.3.2	Communications between one master and one slave . . . . .	804
26.3.3	Standard multislave communication . . . . .	807
26.3.4	Multimaster communication . . . . .	808
26.3.5	Slave select (NSS) pin management . . . . .	808
26.3.6	Communication formats . . . . .	810
26.3.7	SPI configuration . . . . .	812
26.3.8	Procedure for enabling SPI . . . . .	812
26.3.9	Data transmission and reception procedures . . . . .	813
26.3.10	Procedure for disabling the SPI . . . . .	815
26.3.11	Communication using DMA (direct memory addressing) . . . . .	816
26.3.12	SPI status flags . . . . .	818
26.3.13	SPI error flags . . . . .	819
26.4	SPI special features . . . . .	820
26.4.1	TI mode . . . . .	820
26.4.2	CRC calculation . . . . .	821
26.5	SPI interrupts . . . . .	823
26.6	I ²S functional description . . . . .	824
26.6.1	I ²S general description . . . . .	824
26.6.2	I2S full-duplex . . . . .	825
26.6.3	Supported audio protocols . . . . .	826
26.6.4	Clock generator . . . . .	832
26.6.5	I ²S master mode . . . . .	835
26.6.6	I ²S slave mode . . . . .	837
26.6.7	I ²S status flags . . . . .	838
26.6.8	I ²S error flags . . . . .	839
26.6.9	I ²S interrupts . . . . .	840
26.6.10	DMA features . . . . .	840
26.7	SPI and I ²S registers . . . . .	841
26.7.1	SPI control register 1 (SPI_CR1) (not used in I ²S mode) . . . . .	841
26.7.2	SPI control register 2 (SPI_CR2) . . . . .	843
26.7.3	SPI status register (SPI_SR) . . . . .	844
26.7.4	SPI data register (SPI_DR) . . . . .	846
26.7.5	SPI CRC polynomial register (SPI_CRCPR) (not used in I ²S mode) . . . . .	846

26.7.6	SPI RX CRC register (SPI_RXCRCR) (not used in I ²S mode) . . . . .	847
26.7.7	SPI TX CRC register (SPI_TXCRCR) (not used in I ²S mode) . . . . .	847
26.7.8	SPI_I ²S configuration register (SPI_I2SCFGR) . . . . .	848
26.7.9	SPI_I ²S prescaler register (SPI_I2SPR) . . . . .	849
26.7.10	SPI register map . . . . .	851
27	Secure digital input/output interface (SDIO) . . . . .	852
27.1	SDIO main features . . . . .	852
27.2	SDIO bus topology . . . . .	852
27.3	SDIO functional description . . . . .	854
27.3.1	SDIO adapter . . . . .	856
27.3.2	SDIO APB2 interface . . . . .	867
27.4	Card functional description . . . . .	868
27.4.1	Card identification mode . . . . .	868
27.4.2	Card reset . . . . .	869
27.4.3	Operating voltage range validation . . . . .	869
27.4.4	Card identification process . . . . .	869
27.4.5	Block write . . . . .	870
27.4.6	Block read . . . . .	871
27.4.7	Stream access, stream write and stream read (MultiMediaCard only) . . . . .	871
27.4.8	Erase: group erase and sector erase . . . . .	873
27.4.9	Wide bus selection or deselection . . . . .	873
27.4.10	Protection management . . . . .	873
27.4.11	Card status register . . . . .	877
27.4.12	SD status register . . . . .	880
27.4.13	SD I/O mode . . . . .	884
27.4.14	Commands and responses . . . . .	885
27.5	Response formats . . . . .	888
27.5.1	R1 (normal response command) . . . . .	889
27.5.2	R1b . . . . .	889
27.5.3	R2 (CID, CSD register) . . . . .	889
27.5.4	R3 (OCR register) . . . . .	890
27.5.5	R4 (Fast I/O) . . . . .	890
27.5.6	R4b . . . . .	890
27.5.7	R5 (interrupt request) . . . . .	891
27.5.8	R6 . . . . .	891

27.6	SDIO I/O card-specific operations . . . . .	892
27.6.1	SDIO I/O read wait operation by SDIO_D2 signalling . . . . .	892
27.6.2	SDIO read wait operation by stopping SDIO_CK . . . . .	893
27.6.3	SDIO suspend/resume operation . . . . .	893
27.6.4	SDIO interrupts . . . . .	893
27.7	HW flow control . . . . .	893
27.8	SDIO registers . . . . .	894
27.8.1	SDIO power control register (SDIO_POWER) . . . . .	894
27.8.2	SDIO clock control register (SDIO_CLKCR) . . . . .	894
27.8.3	SDIO argument register (SDIO_ARG) . . . . .	896
27.8.4	SDIO command register (SDIO_CMD) . . . . .	896
27.8.5	SDIO command response register (SDIO_RESPCMD) . . . . .	897
27.8.6	SDIO response 1..4 register (SDIO_RESPx) . . . . .	897
27.8.7	SDIO data timer register (SDIO_DTIMER) . . . . .	898
27.8.8	SDIO data length register (SDIO_DLEN) . . . . .	899
27.8.9	SDIO data control register (SDIO_DCTRL) . . . . .	899
27.8.10	SDIO data counter register (SDIO_DCOUNT) . . . . .	902
27.8.11	SDIO status register (SDIO_STA) . . . . .	902
27.8.12	SDIO interrupt clear register (SDIO_ICR) . . . . .	903
27.8.13	SDIO mask register (SDIO_MASK) . . . . .	905
27.8.14	SDIO FIFO counter register (SDIO_FIFOCNT) . . . . .	907
27.8.15	SDIO data FIFO register (SDIO_FIFO) . . . . .	908
27.8.16	SDIO register map . . . . .	909
28	Controller area network (bxCAN) . . . . .	911
28.1	Introduction . . . . .	911
28.2	bxCAN main features . . . . .	911
28.3	bxCAN general description . . . . .	912
28.3.1	CAN 2.0B active core . . . . .	912
28.3.2	Control, status, and configuration registers . . . . .	912
28.3.3	Tx mailboxes . . . . .	912
28.3.4	Acceptance filters . . . . .	913
28.4	bxCAN operating modes . . . . .	914
28.4.1	Initialization mode . . . . .	914
28.4.2	Normal mode . . . . .	914
28.4.3	Sleep mode (low-power) . . . . .	915

28.5 Test mode . . . . . 916
- 28.5.1 Silent mode . . . . . 916
- 28.5.2 Loop back mode . . . . . 916
- 28.5.3 Loop back combined with silent mode . . . . . 917
28.6 Behavior in debug mode . . . . . 917
28.7 bxCAN functional description . . . . . 917
- 28.7.1 Transmission handling . . . . . 917
- 28.7.2 Time triggered communication mode . . . . . 919
- 28.7.3 Reception handling . . . . . 919
- 28.7.4 Identifier filtering . . . . . 921
- 28.7.5 Message storage . . . . . 925
- 28.7.6 Error management . . . . . 926
- 28.7.7 Bit timing . . . . . 926
28.8 bxCAN interrupts . . . . . 930
28.9 CAN registers . . . . . 931
- 28.9.1 Register access protection . . . . . 931
- 28.9.2 CAN control and status registers . . . . . 931
- 28.9.3 CAN mailbox registers . . . . . 941
- 28.9.4 CAN filter registers . . . . . 947
- 28.9.5 bxCAN register map . . . . . 951

29 USB on-the-go full-speed (OTG_FS) . . . . . 955
- 29.1 Introduction . . . . . 955
- 29.2 OTG_FS main features . . . . . 956
  - 29.2.1 General features . . . . . 956
  - 29.2.2 Host-mode features . . . . . 957
  - 29.2.3 Peripheral-mode features . . . . . 957
  - 29.2.4 Split rail for USB . . . . . 957
- 29.3 OTG_FS implementation . . . . . 958
- 29.4 OTG_FS functional description . . . . . 959
  - 29.4.1 OTG_FS block diagram . . . . . 959
  - 29.4.2 OTG_FS pin and internal signals . . . . . 959
  - 29.4.3 OTG_FS core . . . . . 960
  - 29.4.4 Embedded full-speed OTG PHY connected to OTG_FS . . . . . 960
  - 29.4.5 OTG detections . . . . . 961
- 29.5 OTG_FS dual role device (DRD) . . . . . 961

29.5.1	ID line detection . . . . .	961
29.5.2	HNP dual role device . . . . .	962
29.5.3	SRP dual role device . . . . .	962
29.6	OTG_FS as a USB peripheral . . . . .	962
29.6.1	SRP-capable peripheral . . . . .	963
29.6.2	Peripheral states . . . . .	963
29.6.3	Peripheral endpoints . . . . .	964
29.7	OTG_FS as a USB host . . . . .	966
29.7.1	SRP-capable host . . . . .	967
29.7.2	USB host states . . . . .	967
29.7.3	Host channels . . . . .	969
29.7.4	Host scheduler . . . . .	970
29.8	OTG_FS SOF trigger . . . . .	971
29.8.1	Host SOFs . . . . .	971
29.8.2	Peripheral SOFs . . . . .	971
29.9	OTG_FS low-power modes . . . . .	972
29.10	OTG_FS Dynamic update of the OTG_HFIR register . . . . .	973
29.11	OTG_FS data FIFOs . . . . .	973
29.11.1	Peripheral FIFO architecture . . . . .	974
29.11.2	Host FIFO architecture . . . . .	975
29.11.3	FIFO RAM allocation . . . . .	976
29.12	OTG_FS system performance . . . . .	978
29.13	OTG_FS interrupts . . . . .	978
29.14	OTG_FS control and status registers . . . . .	980
29.14.1	CSR memory map . . . . .	980
29.15	OTG_FS registers . . . . .	984
29.15.1	OTG control and status register (OTG_GOTGCTL) . . . . .	985
29.15.2	OTG interrupt register (OTG_GOTGINT) . . . . .	988
29.15.3	OTG AHB configuration register (OTG_GAHBCFG) . . . . .	989
29.15.4	OTG USB configuration register (OTG_GUSBCFG) . . . . .	990
29.15.5	OTG reset register (OTG_GRSTCTL) . . . . .	992
29.15.6	OTG core interrupt register (OTG_GINTSTS) . . . . .	994
29.15.7	OTG interrupt mask register (OTG_GINTMSK) . . . . .	998
29.15.8	OTG receive status debug read register (OTG_GRXSTSR) . . . . .	1001
29.15.9	OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . .	1002
29.15.10	OTG status read and pop registers (OTG_GRXSTSP) . . . . .	1003

29.15.11	OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . .	1004
29.15.12	OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .	1005
29.15.13	OTG host non-periodic transmit FIFO size register (OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0) . . . . .	1005
29.15.14	OTG non-periodic transmit FIFO/queue status register (OTG_HNPTXSTS) . . . . .	1006
29.15.15	OTG general core configuration register (OTG_GCCFG) . . . . .	1007
29.15.16	OTG core ID register (OTG_CID) . . . . .	1009
29.15.17	OTG core LPM configuration register (OTG_GLPMCFG) . . . . .	1009
29.15.18	OTG host periodic transmit FIFO size register (OTG_HPTXFSIZ) . . . . .	1013
29.15.19	OTG device IN endpoint transmit FIFO x size register (OTG_DIEPTXFx) . . . . .	1013
29.15.20	Host-mode registers . . . . .	1014
29.15.21	OTG host configuration register (OTG_HCFG) . . . . .	1014
29.15.22	OTG host frame interval register (OTG_HFIR) . . . . .	1015
29.15.23	OTG host frame number/frame time remaining register (OTG_HFNUM) . . . . .	1016
29.15.24	OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS) . . . . .	1016
29.15.25	OTG host all channels interrupt register (OTG_HAINT) . . . . .	1017
29.15.26	OTG host all channels interrupt mask register (OTG_HAINTMSK) . . . . .	1018
29.15.27	OTG host port control and status register (OTG_HPRT) . . . . .	1019
29.15.28	OTG host channel x characteristics register (OTG_HCCHARx) . . . . .	1021
29.15.29	OTG host channel x interrupt register (OTG_HCINTx) . . . . .	1022
29.15.30	OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . . . .	1023
29.15.31	OTG host channel x transfer size register (OTG_HCTSIZx) . . . . .	1024
29.15.32	Device-mode registers . . . . .	1025
29.15.33	OTG device configuration register (OTG_DCFG) . . . . .	1025
29.15.34	OTG device control register (OTG_DCTL) . . . . .	1026
29.15.35	OTG device status register (OTG_DSTS) . . . . .	1029
29.15.36	OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) . . . . .	1030
29.15.37	OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) . . . . .	1031
29.15.38	OTG device all endpoints interrupt register (OTG_DAINT) . . . . .	1032
29.15.39	OTG all endpoints interrupt mask register (OTG_DaintMSK) . . . . .	1033

29.15.40

OTG device V _BUSdischarge time register (OTG_DVBUSDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

30.4	Pinout and debug port pins . . . . .	1113
30.4.1	SWJ debug port pins . . . . .	1114
30.4.2	Flexible SWJ-DP pin assignment . . . . .	1114
30.4.3	Internal pull-up and pull-down on JTAG pins . . . . .	1114
30.4.4	Using serial wire and releasing the unused debug pins as GPIOs . . . . .	1116
30.5	JTAG TAP connection . . . . .	1116
30.6	ID codes and locking mechanism . . . . .	1118
30.6.1	MCU device ID code . . . . .	1118
30.6.2	Boundary scan TAP . . . . .	1118
30.6.3	Cortex ^®-M4 with FPU TAP . . . . .	1118
30.6.4	Cortex ^®-M4 with FPU JEDEC-106 ID code . . . . .	1119
30.7	JTAG debug port . . . . .	1119
30.8	SW debug port . . . . .	1121
30.8.1	SW protocol introduction . . . . .	1121
30.8.2	SW protocol sequence . . . . .	1121
30.8.3	SW-DP state machine (reset, idle states, ID code) . . . . .	1122
30.8.4	DP and AP read/write accesses . . . . .	1122
30.8.5	SW-DP registers . . . . .	1123
30.8.6	SW-AP registers . . . . .	1124
30.9	AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP . . . . .	1124
30.10	Core debug . . . . .	1125
30.11	Capability of the debugger host to connect under system reset . . . . .	1126
30.12	FPB (flash patch breakpoint) . . . . .	1126
30.13	DWT (data watchpoint trigger) . . . . .	1127
30.14	ITM (instrumentation trace macrocell) . . . . .	1127
30.14.1	General description . . . . .	1127
30.14.2	Time stamp packets, synchronization and overflow packets . . . . .	1127
30.15	ETM (Embedded trace macrocell) . . . . .	1129
30.15.1	General description . . . . .	1129
30.15.2	Signal protocol, packet types . . . . .	1129
30.15.3	Main ETM registers . . . . .	1129
30.15.4	Configuration example . . . . .	1130
30.16	MCU debug component (DBGMCU) . . . . .	1130
30.16.1	Debug support for low-power modes . . . . .	1130
30.16.2	Debug support for timers, watchdog, bxCAN and I ²C . . . . .	1131

30.16.3	Debug MCU configuration register . . . . .	1131
30.16.4	Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . .	1132
30.16.5	Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . .	1134
30.17	TPIU (trace port interface unit) . . . . .	1134
30.17.1	Introduction . . . . .	1134
30.17.2	TRACE pin assignment . . . . .	1136
30.17.3	TPUI formatter . . . . .	1137
30.17.4	TPUI frame synchronization packets . . . . .	1138
30.17.5	Transmission of the synchronization frame packet . . . . .	1138
30.17.6	Synchronous mode . . . . .	1138
30.17.7	Asynchronous mode . . . . .	1139
30.17.8	TRACECLKIN connection . . . . .	1139
30.17.9	TPIU registers . . . . .	1139
30.17.10	Example of configuration . . . . .	1140
30.18	DBG register map . . . . .	1141
31	Device electronic signature . . . . .	1142
31.1	Unique device ID register (96 bits) . . . . .	1142
31.2	Flash size . . . . .	1143
31.3	Package data register . . . . .	1143
32	Important security notice . . . . .	1145
33	Revision history . . . . .	1146

List of tables

Table 1.	Register boundary addresses . . . . .	51
Table 2.	Boot modes . . . . .	55
Table 3.	Embedded bootloader interfaces . . . . .	56
Table 4.	Memory mapping vs. Boot mode/physical remap in STM32F412xx. . . . .	56
Table 5.	Flash module organization . . . . .	59
Table 6.	Number of wait states according to CPU clock (HCLK) frequency. . . . .	60
Table 7.	Maximum program/erase parallelism . . . . .	64
Table 8.	Flash interrupt request . . . . .	66
Table 9.	Option byte organization. . . . .	66
Table 10.	Description of the option bytes . . . . .	67
Table 11.	Access versus read protection level . . . . .	70
Table 12.	OTP area organization . . . . .	73
Table 13.	Flash register map and reset values. . . . .	81
Table 14.	CRC calculation unit register map and reset values. . . . .	85
Table 15.	Low-power mode summary . . . . .	94
Table 16.	Sleep-now entry and exit . . . . .	95
Table 17.	Sleep-on-exit entry and exit . . . . .	95
Table 18.	BAM-now entry and exit . . . . .	96
Table 19.	BAM-on-exit entry and exit . . . . .	97
Table 20.	Stop operating modes. . . . .	98
Table 21.	Stop mode entry and exit . . . . .	99
Table 22.	Standby mode entry and exit . . . . .	101
Table 23.	PWR - register map and reset values. . . . .	108
Table 24.	RCC register map and reset values for STM32F412xx . . . . .	165
Table 25.	Port bit configuration table . . . . .	169
Table 26.	Flexible SWJ-DP pin assignment . . . . .	172
Table 27.	RTC additional functions. . . . .	179
Table 28.	GPIO register map and reset values . . . . .	185
Table 29.	SYSCFG register map and reset values. . . . .	195
Table 30.	DMA1 request mapping . . . . .	200
Table 31.	DMA2 request mapping . . . . .	200
Table 32.	Source and destination address . . . . .	201
Table 33.	Source and destination address registers in double-buffer mode (DBM = 1). . . . .	207
Table 34.	Packing/unpacking and endian behavior (bit PINC = MINC = 1) . . . . .	208
Table 35.	Restriction on NDT versus PSIZE and MSIZE . . . . .	208
Table 36.	FIFO threshold configurations . . . . .	211
Table 37.	Possible DMA configurations . . . . .	215
Table 38.	DMA interrupt requests. . . . .	217
Table 39.	DMA register map and reset values . . . . .	227
Table 40.	Vector table for STM32F412xx . . . . .	232
Table 41.	External interrupt/event controller register map and reset values. . . . .	245
Table 42.	NOR/PSRAM bank selection . . . . .	249
Table 43.	NOR/PSRAM External memory address . . . . .	249
Table 44.	Programmable NOR/PSRAM access parameters . . . . .	251
Table 45.	Non-multiplexed I/O NOR flash memory. . . . .	251
Table 46.	16-bit multiplexed I/O NOR flash memory . . . . .	252
Table 47.	Non-multiplexed I/Os PSRAM/SRAM . . . . .	252
Table 48.	16-Bit multiplexed I/O PSRAM . . . . .	252

Table 49.	NOR flash/PSRAM: example of supported memories and transactions . . . . .	253
Table 50.	FSMC_BCRx bitfields (mode 1) . . . . .	256
Table 51.	FSMC_BTRx bitfields (mode 1) . . . . .	257
Table 52.	FSMC_BCRx bitfields (mode A) . . . . .	259
Table 53.	FSMC_BTRx bitfields (mode A) . . . . .	259
Table 54.	FSMC_BWTRx bitfields (mode A) . . . . .	260
Table 55.	FSMC_BCRx bitfields (mode 2/B) . . . . .	262
Table 56.	FSMC_BTRx bitfields (mode 2/B) . . . . .	262
Table 57.	FSMC_BWTRx bitfields (mode 2/B) . . . . .	263
Table 58.	FSMC_BCRx bitfields (mode C) . . . . .	264
Table 59.	FSMC_BTRx bitfields (mode C) . . . . .	265
Table 60.	FSMC_BWTRx bitfields (mode C) . . . . .	265
Table 61.	FSMC_BCRx bitfields (mode D) . . . . .	267
Table 62.	FSMC_BTRx bitfields (mode D) . . . . .	267
Table 63.	FSMC_BWTRx bitfields (mode D) . . . . .	268
Table 64.	FSMC_BCRx bitfields (Muxed mode) . . . . .	269
Table 65.	FSMC_BTRx bitfields (Muxed mode) . . . . .	270
Table 66.	FSMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .	275
Table 67.	FSMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .	276
Table 68.	FSMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .	277
Table 69.	FSMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .	278
Table 70.	FSMC register map and reset values . . . . .	286
Table 71.	QUADSPI pins . . . . .	289
Table 72.	QUADSPI interrupt requests . . . . .	303
Table 73.	QUADSPI register map and reset values . . . . .	314
Table 74.	ADC pins . . . . .	318
Table 75.	Analog watchdog channel selection . . . . .	321
Table 76.	Configuring the trigger polarity . . . . .	325
Table 77.	External trigger for regular channels . . . . .	325
Table 78.	External trigger for injected channels . . . . .	326
Table 79.	ADC interrupts . . . . .	330
Table 80.	ADC global register map . . . . .	344
Table 81.	ADC register map and reset values . . . . .	344
Table 82.	ADC register map and reset values (common ADC registers) . . . . .	345
Table 83.	DFSDM1 implementation . . . . .	348
Table 84.	DFSDM external pins . . . . .	350
Table 85.	DFSDM internal signals . . . . .	350
Table 86.	DFSDM triggers connection . . . . .	350
Table 87.	DFSDM break connection . . . . .	351
Table 88.	Filter maximum output resolution (peak data values from filter output) for some FOSR values . . . . .	366
Table 89.	Integrator maximum output resolution (peak data values from integrator output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . . .	366
Table 90.	DFSDM interrupt requests . . . . .	374
Table 91.	DFSDM register map and reset values . . . . .	395
Table 92.	RNG internal input/output signals . . . . .	401
Table 93.	RNG interrupt requests . . . . .	406
Table 94.	RNG configurations . . . . .	407
Table 95.	RNG register map and reset map . . . . .	410
Table 96.	Counting direction versus encoder signals . . . . .	447
Table 97.	TIMx Internal trigger connection . . . . .	460

Table 98.	Output control bits for complementary OCx and OCxN channels with break feature . . . . .	472
Table 99.	TIM1&TIM8 register map and reset values. . . . .	479
Table 100.	Counting direction versus encoder signals . . . . .	508
Table 101.	TIMx internal trigger connections . . . . .	523
Table 102.	Output control bit for standard OCx channels. . . . .	533
Table 103.	TIM2 to TIM5 register map and reset values . . . . .	540
Table 104.	TIMx internal trigger connections . . . . .	566
Table 105.	Output control bit for standard OCx channels. . . . .	574
Table 106.	TIM9/12 register map and reset values . . . . .	576
Table 107.	Output control bit for standard OCx channels. . . . .	584
Table 108.	TIM10/11/13/14 register map and reset values . . . . .	587
Table 109.	TIM6/7 register map and reset values . . . . .	601
Table 110.	Min/max IWDG timeout periods (ms) at 32 kHz (LSI). . . . .	603
Table 111.	IWDG register map and reset values . . . . .	607
Table 112.	WWDG register map and reset values . . . . .	614
Table 113.	Effect of low power modes on RTC . . . . .	629
Table 114.	Interrupt control bits . . . . .	630
Table 115.	RTC register map and reset values . . . . .	650
Table 116.	FMPI2C implementation . . . . .	654
Table 117.	FMPI2C input/output pins . . . . .	655
Table 118.	FMPI2C internal input/output signals . . . . .	655
Table 119.	Comparison of analog and digital filters . . . . .	658
Table 120.	I ²C-bus and SMBus specification data setup and hold times . . . . .	660
Table 121.	FMPI2C configuration . . . . .	664
Table 122.	I ²C-bus and SMBus specification clock timings . . . . .	675
Table 123.	Timing settings for f _I2CCLKof 8 MHz. . . . .	685
Table 124.	Timing settings for f _I2CCLKof 16 MHz. . . . .	685
Table 125.	SMBus timeout specifications . . . . .	687
Table 126.	SMBus with PEC configuration . . . . .	689
Table 127.	TIMEOUTA[11:0] for maximum t _TIMEOUTof 25 ms. . . . .	690
Table 128.	TIMEOUTB[11:0] for maximum t _LOW:SEXTand t _LOW:MEXTof 8 ms . . . . .	690
Table 129.	TIMEOUTA[11:0] for maximum t _IDLEof 50 µs . . . . .	690
Table 130.	Effect of low-power modes to FMPI2C . . . . .	699
Table 131.	FMPI2C interrupt requests . . . . .	699
Table 132.	FMPI2C register map and reset values . . . . .	715
Table 133.	Maximum DNF[3:0] value to be compliant with Thd:dat(max) . . . . .	727
Table 134.	SMBus vs. I ²C . . . . .	728
Table 135.	I ²C interrupt requests . . . . .	733
Table 136.	I ²C register map and reset values . . . . .	746
Table 137.	USART features . . . . .	749
Table 138.	Noise detection from sampled data . . . . .	760
Table 139.	Error calculation for programmed baud rates at f _PCLK= 8 MHz or f _PCLK= 12 MHz, oversampling by 16. . . . .	763
Table 140.	Error calculation for programmed baud rates at f _PCLK= 8 MHz or f _PCLK= 12 MHz, oversampling by 8. . . . .	763
Table 141.	Error calculation for programmed baud rates at f _PCLK= 16 MHz or f _PCLK= 24 MHz, oversampling by 16. . . . .	764
Table 142.	Error calculation for programmed baud rates at f _PCLK= 16 MHz or f _PCLK= 24 MHz, oversampling by 8. . . . .	765
Table 143.	Error calculation for programmed baud rates at f _PCLK= 8 MHz or f _PCLK= 16 MHz, oversampling by 16. . . . .	765

Table 144.	Error calculation for programmed baud rates at $f_{PCLK} = 8$ MHz or $f_{PCLK} = 16$ MHz, oversampling by 8. . . . .	766
Table 145.	Error calculation for programmed baud rates at $f_{PCLK} = 30$ MHz or $f_{PCLK} = 60$ MHz, oversampling by 16. . . . .	767
Table 146.	Error calculation for programmed baud rates at $f_{PCLK} = 30$ MHz or $f_{PCLK} = 60$ MHz, oversampling by 8 . . . . .	767
Table 147.	Error calculation for programmed baud rates at $f_{PCLK} = 42$ MHz or $f_{PCLK} = 84$ Hz, oversampling by 16. . . . .	768
Table 148.	Error calculation for programmed baud rates at $f_{PCLK} = 42$ MHz or $f_{PCLK} = 84$ MHz, oversampling by 8. . . . .	769
Table 149.	Error calculation for programmed baud rates at $f_{PCLK} = 100$ MHz or $f_{PCLK} = 50$ MHz, oversampling by 16. . . . .	770
Table 150.	Error calculation for programmed baud rates at $f_{PCLK} = 100$ MHz or $f_{PCLK} = 50$ MHz, oversampling by 8. . . . .	771
Table 151.	USART receiver tolerance when DIV fraction is 0 . . . . .	772
Table 152.	USART receiver tolerance when DIV_Fraction is different from 0 . . . . .	772
Table 153.	Frame formats . . . . .	774
Table 154.	USART interrupt requests. . . . .	788
Table 155.	USART register map and reset values . . . . .	799
Table 156.	STM32F412xx SPI implementation . . . . .	802
Table 157.	SPI interrupt requests. . . . .	823
Table 158.	Audio-frequency precision using standard 8 MHz HSE . . . . .	834
Table 159.	I ²S interrupt requests . . . . .	840
Table 160.	SPI register map and reset values . . . . .	851
Table 161.	SDIO I/O definitions . . . . .	855
Table 162.	Command format . . . . .	860
Table 163.	Short response format . . . . .	861
Table 164.	Long response format. . . . .	861
Table 165.	Command path status flags . . . . .	861
Table 166.	Data token format . . . . .	864
Table 167.	DPSM flags. . . . .	865
Table 168.	Transmit FIFO status flags . . . . .	866
Table 169.	Receive FIFO status flags . . . . .	866
Table 170.	Card status . . . . .	877
Table 171.	SD status . . . . .	880
Table 172.	Speed class code field . . . . .	881
Table 173.	Performance move field . . . . .	882
Table 174.	AU_SIZE field . . . . .	882
Table 175.	Maximum AU size. . . . .	882
Table 176.	Erase size field . . . . .	883
Table 177.	Erase timeout field . . . . .	883
Table 178.	Erase offset field . . . . .	883
Table 179.	Block-oriented write commands . . . . .	886
Table 180.	Block-oriented write protection commands. . . . .	887
Table 181.	Erase commands . . . . .	887
Table 182.	I/O mode commands . . . . .	887
Table 183.	Lock card . . . . .	888
Table 184.	Application-specific commands . . . . .	888
Table 185.	R1 response . . . . .	889
Table 186.	R2 response . . . . .	889
Table 187.	R3 response . . . . .	890
Table 188.	R4 response . . . . .	890

Table 189.	R4b response . . . . .	890
Table 190.	R5 response . . . . .	891
Table 191.	R6 response . . . . .	892
Table 192.	Response type and SDIO_RESPx registers. . . . .	898
Table 193.	SDIO register map . . . . .	909
Table 194.	Transmit mailbox mapping . . . . .	925
Table 195.	Receive mailbox mapping. . . . .	925
Table 196.	bxCAN register map and reset values . . . . .	951
Table 197.	OTG_FS speeds supported . . . . .	955
Table 198.	OTG_FS implementation . . . . .	958
Table 199.	OTG_FS input/output pins . . . . .	959
Table 200.	OTG_FS input/output signals . . . . .	960
Table 201.	Compatibility of STM32 low power modes with the OTG . . . . .	972
Table 202.	Core global control and status registers (CSRs). . . . .	980
Table 203.	Host-mode control and status registers (CSRs) . . . . .	981
Table 204.	Device-mode control and status registers . . . . .	982
Table 205.	Data FIFO (DFIFO) access register map . . . . .	984
Table 206.	Power and clock gating control and status registers . . . . .	984
Table 207.	TRDT values . . . . .	991
Table 208.	Minimum duration for soft disconnect . . . . .	1028
Table 209.	OTG_FS register map and reset values . . . . .	1051
Table 210.	SWJ debug port pins . . . . .	1114
Table 211.	Flexible SWJ-DP pin assignment . . . . .	1114
Table 212.	JTAG debug port data registers . . . . .	1119
Table 213.	32-bit debug port registers addressed through the shifted value A[3:2] . . . . .	1120
Table 214.	Packet request (8-bits) . . . . .	1121
Table 215.	ACK response (3 bits). . . . .	1122
Table 216.	DATA transfer (33 bits). . . . .	1122
Table 217.	SW-DP registers . . . . .	1123
Table 218.	Cortex®-M4 with FPU AHB-AP registers . . . . .	1124
Table 219.	Core debug registers . . . . .	1125
Table 220.	Main ITM registers . . . . .	1128
Table 221.	Main ETM registers. . . . .	1130
Table 222.	Asynchronous TRACE pin assignment. . . . .	1136
Table 223.	Synchronous TRACE pin assignment . . . . .	1136
Table 224.	Flexible TRACE pin assignment . . . . .	1137
Table 225.	Important TPIU registers. . . . .	1139
Table 226.	DBG register map and reset values . . . . .	1141
Table 227.	Document revision history . . . . .	1146

List of figures

Figure 1.	System architecture . . . . .	47
Figure 2.	Memory map . . . . .	50
Figure 3.	Flash memory interface connection inside system architecture . . . . .	58
Figure 4.	Sequential 32-bit instruction execution . . . . .	62
Figure 5.	RDP levels . . . . .	70
Figure 6.	PCROP levels . . . . .	72
Figure 7.	CRC calculation unit block diagram . . . . .	82
Figure 8.	Power supply overview . . . . .	87
Figure 9.	Power-on reset/power-down reset waveform . . . . .	90
Figure 10.	BOR thresholds . . . . .	91
Figure 11.	PVD thresholds . . . . .	92
Figure 12.	Simplified diagram of the reset circuit . . . . .	110
Figure 13.	Clock tree . . . . .	112
Figure 14.	HSE/ LSE clock sources . . . . .	114
Figure 15.	Frequency measurement with TIM5 in Input capture mode . . . . .	119
Figure 16.	Frequency measurement with TIM11 in Input capture mode . . . . .	120
Figure 17.	Basic structure of a five-volt tolerant I/O port bit . . . . .	169
Figure 18.	Selecting an alternate function on STM32F412xx . . . . .	173
Figure 19.	Input floating/pull up/pull down configurations . . . . .	176
Figure 20.	Output configuration . . . . .	177
Figure 21.	Alternate function configuration . . . . .	177
Figure 22.	High impedance-analog configuration . . . . .	178
Figure 23.	DMA block diagram . . . . .	198
Figure 24.	Channel selection . . . . .	199
Figure 25.	Peripheral-to-memory mode . . . . .	203
Figure 26.	Memory-to-peripheral mode . . . . .	204
Figure 27.	Memory-to-memory mode . . . . .	205
Figure 28.	FIFO structure . . . . .	210
Figure 29.	External interrupt/event controller block diagram . . . . .	236
Figure 30.	External interrupt/event GPIO mapping . . . . .	238
Figure 31.	FSMC block diagram . . . . .	247
Figure 32.	FSMC memory banks . . . . .	249
Figure 33.	Mode 1 read access waveforms . . . . .	255
Figure 34.	Mode 1 write access waveforms . . . . .	256
Figure 35.	Mode A read access waveforms . . . . .	258
Figure 36.	Mode A write access waveforms . . . . .	258
Figure 37.	Mode 2 and mode B read access waveforms . . . . .	260
Figure 38.	Mode 2 write access waveforms . . . . .	261
Figure 39.	Mode B write access waveforms . . . . .	261
Figure 40.	Mode C read access waveforms . . . . .	263
Figure 41.	Mode C write access waveforms . . . . .	264
Figure 42.	Mode D read access waveforms . . . . .	266
Figure 43.	Mode D write access waveforms . . . . .	266
Figure 44.	Muxed read access waveforms . . . . .	268
Figure 45.	Muxed write access waveforms . . . . .	269
Figure 46.	Asynchronous wait during a read access waveforms . . . . .	271
Figure 47.	Asynchronous wait during a write access waveforms . . . . .	272
Figure 48.	Wait configuration waveforms . . . . .	274

Figure 49.	Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . .	275
Figure 50.	Synchronous multiplexed write mode waveforms - PSRAM (CRAM) . . . . .	277
Figure 51.	QUADSPI block diagram when dual-flash mode is disabled . . . . .	288
Figure 52.	QUADSPI block diagram when dual-flash mode is enabled . . . . .	289
Figure 53.	Example of read command in quad-SPI mode . . . . .	290
Figure 54.	Example of a DDR command in quad-SPI mode . . . . .	293
Figure 55.	NCS when CKMODE = 0 (T = CLK period) . . . . .	301
Figure 56.	NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .	301
Figure 57.	NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . .	302
Figure 58.	NCS when CKMODE = 1 with an abort (T = CLK period) . . . . .	302
Figure 59.	Single ADC block diagram . . . . .	317
Figure 60.	Timing diagram . . . . .	320
Figure 61.	Analog watchdog's guarded area . . . . .	320
Figure 62.	Injected conversion latency . . . . .	322
Figure 63.	Right alignment of 12-bit data . . . . .	324
Figure 64.	Left alignment of 12-bit data . . . . .	324
Figure 65.	Left alignment of 6-bit data . . . . .	324
Figure 66.	Temperature sensor and VREFINT channel block diagram . . . . .	328
Figure 67.	Single DFSDM block diagram . . . . .	349
Figure 68.	Input channel pins redirection . . . . .	353
Figure 69.	Channel transceiver timing diagrams . . . . .	356
Figure 70.	Clock absence timing diagram for SPI . . . . .	357
Figure 71.	Clock absence timing diagram for Manchester coding . . . . .	358
Figure 72.	First conversion for Manchester coding (Manchester synchronization) . . . . .	360
Figure 73.	DFSDM_CHyDATINR registers operation modes and assignment . . . . .	363
Figure 74.	Example: Sinc3 filter response . . . . .	365
Figure 75.	RNG block diagram . . . . .	401
Figure 76.	Entropy source model . . . . .	402
Figure 77.	Advanced-control timer block diagram . . . . .	412
Figure 78.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	414
Figure 79.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	414
Figure 80.	Counter timing diagram, internal clock divided by 1 . . . . .	415
Figure 81.	Counter timing diagram, internal clock divided by 2 . . . . .	416
Figure 82.	Counter timing diagram, internal clock divided by 4 . . . . .	416
Figure 83.	Counter timing diagram, internal clock divided by N . . . . .	416
Figure 84.	Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	417
Figure 85.	Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	417
Figure 86.	Counter timing diagram, internal clock divided by 1 . . . . .	419
Figure 87.	Counter timing diagram, internal clock divided by 2 . . . . .	419
Figure 88.	Counter timing diagram, internal clock divided by 4 . . . . .	420
Figure 89.	Counter timing diagram, internal clock divided by N . . . . .	420
Figure 90.	Counter timing diagram, update event when repetition counter is not used . . . . .	421
Figure 91.	Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .	422
Figure 92.	Counter timing diagram, internal clock divided by 2 . . . . .	422
Figure 93.	Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	423
Figure 94.	Counter timing diagram, internal clock divided by N . . . . .	423
Figure 95.	Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .	424
Figure 96.	Counter timing diagram, update event with ARPE=1 (counter overflow) . . . . .	424
Figure 97.	Update rate examples depending on mode and TIMx_RCR register settings . . . . .	425
Figure 98.	Control circuit in normal mode, internal clock divided by 1 . . . . .	426

Figure 99.	TI2 external clock connection example. . . . .	427
Figure 100.	Control circuit in external clock mode 1 . . . . .	428
Figure 101.	External trigger input block . . . . .	428
Figure 102.	Control circuit in external clock mode 2 . . . . .	429
Figure 103.	Capture/compare channel (example: channel 1 input stage) . . . . .	430
Figure 104.	Capture/compare channel 1 main circuit . . . . .	430
Figure 105.	Output stage of capture/compare channel (channels 1 to 3) . . . . .	431
Figure 106.	Output stage of capture/compare channel (channel 4). . . . .	431
Figure 107.	PWM input mode timing . . . . .	433
Figure 108.	Output compare mode, toggle on OC1. . . . .	435
Figure 109.	Edge-aligned PWM waveforms (ARR=8) . . . . .	436
Figure 110.	Center-aligned PWM waveforms (ARR=8). . . . .	437
Figure 111.	Complementary output with dead-time insertion . . . . .	439
Figure 112.	Dead-time waveforms with delay greater than the negative pulse . . . . .	439
Figure 113.	Dead-time waveforms with delay greater than the positive pulse. . . . .	439
Figure 114.	Output behavior in response to a break . . . . .	442
Figure 115.	Clearing TIMx_OCxREF . . . . .	443
Figure 116.	6-step generation, COM example (OSSR=1) . . . . .	444
Figure 117.	Example of one pulse mode . . . . .	445
Figure 118.	Example of counter operation in encoder interface mode . . . . .	448
Figure 119.	Example of encoder interface mode with TI1FP1 polarity inverted. . . . .	448
Figure 120.	Example of Hall sensor interface . . . . .	450
Figure 121.	Control circuit in reset mode . . . . .	451
Figure 122.	Control circuit in gated mode . . . . .	452
Figure 123.	Control circuit in trigger mode . . . . .	453
Figure 124.	Control circuit in external clock mode 2 + trigger mode . . . . .	454
Figure 125.	General-purpose timer block diagram . . . . .	482
Figure 126.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	483
Figure 127.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	484
Figure 128.	Counter timing diagram, internal clock divided by 1 . . . . .	485
Figure 129.	Counter timing diagram, internal clock divided by 2 . . . . .	485
Figure 130.	Counter timing diagram, internal clock divided by 4 . . . . .	485
Figure 131.	Counter timing diagram, internal clock divided by N. . . . .	486
Figure 132.	Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .	486
Figure 133.	Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .	487
Figure 134.	Counter timing diagram, internal clock divided by 1 . . . . .	488
Figure 135.	Counter timing diagram, internal clock divided by 2 . . . . .	488
Figure 136.	Counter timing diagram, internal clock divided by 4 . . . . .	488
Figure 137.	Counter timing diagram, internal clock divided by N. . . . .	489
Figure 138.	Counter timing diagram, Update event . . . . .	489
Figure 139.	Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .	490
Figure 140.	Counter timing diagram, internal clock divided by 2 . . . . .	491
Figure 141.	Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	491
Figure 142.	Counter timing diagram, internal clock divided by N. . . . .	491
Figure 143.	Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .	492
Figure 144.	Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .	492
Figure 145.	Control circuit in normal mode, internal clock divided by 1 . . . . .	493
Figure 146.	TI2 external clock connection example. . . . .	494
Figure 147.	Control circuit in external clock mode 1 . . . . .	495
Figure 148.	External trigger input block . . . . .	495
Figure 149.	Control circuit in external clock mode 2 . . . . .	496
Figure 150.	Capture/compare channel (example: channel 1 input stage) . . . . .	497

Figure 151. Capture/compare channel 1 main circuit . . . . .	497
Figure 152. Output stage of capture/compare channel (channel 1). . . . .	498
Figure 153. PWM input mode timing . . . . .	500
Figure 154. Output compare mode, toggle on OC1 . . . . .	501
Figure 155. Edge-aligned PWM waveforms (ARR=8) . . . . .	503
Figure 156. Center-aligned PWM waveforms (ARR=8). . . . .	504
Figure 157. Example of one-pulse mode . . . . .	505
Figure 158. Clearing TIMx_OCxREF . . . . .	507
Figure 159. Example of counter operation in encoder interface mode . . . . .	508
Figure 160. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	509
Figure 161. Control circuit in reset mode . . . . .	510
Figure 162. Control circuit in gated mode . . . . .	511
Figure 163. Control circuit in trigger mode . . . . .	511
Figure 164. Control circuit in external clock mode 2 + trigger mode . . . . .	512
Figure 165. Master/Slave timer example . . . . .	513
Figure 166. Gating timer 2 with OC1REF of timer 1 . . . . .	514
Figure 167. Gating timer 2 with Enable of timer 1 . . . . .	515
Figure 168. Triggering timer 2 with update of timer 1 . . . . .	516
Figure 169. Triggering timer 2 with Enable of timer 1 . . . . .	516
Figure 170. Triggering timer 1 and 2 with timer 1 TI1 input . . . . .	518
Figure 171. General-purpose timer block diagram (TIM9 and TIM12) . . . . .	543
Figure 172. General-purpose timer block diagram (TIM10/11/13/14) . . . . .	544
Figure 173. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	546
Figure 174. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	546
Figure 175. Counter timing diagram, internal clock divided by 1 . . . . .	547
Figure 176. Counter timing diagram, internal clock divided by 2 . . . . .	548
Figure 177. Counter timing diagram, internal clock divided by 4 . . . . .	548
Figure 178. Counter timing diagram, internal clock divided by N . . . . .	548
Figure 179. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	549
Figure 180. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	549
Figure 181. Control circuit in normal mode, internal clock divided by 1 . . . . .	550
Figure 182. TI2 external clock connection example . . . . .	551
Figure 183. Control circuit in external clock mode 1 . . . . .	551
Figure 184. Capture/compare channel (example: channel 1 input stage) . . . . .	552
Figure 185. Capture/compare channel 1 main circuit . . . . .	553
Figure 186. Output stage of capture/compare channel (channel 1). . . . .	553
Figure 187. PWM input mode timing . . . . .	555
Figure 188. Output compare mode, toggle on OC1 . . . . .	557
Figure 189. Edge-aligned PWM waveforms (ARR=8) . . . . .	558
Figure 190. Example of One-pulse mode . . . . .	559
Figure 191. Control circuit in reset mode . . . . .	561
Figure 192. Control circuit in gated mode . . . . .	562
Figure 193. Control circuit in trigger mode . . . . .	562
Figure 194. Basic timer block diagram . . . . .	589
Figure 195. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	591
Figure 196. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	591
Figure 197. Counter timing diagram, internal clock divided by 1 . . . . .	592
Figure 198. Counter timing diagram, internal clock divided by 2 . . . . .	593
Figure 199. Counter timing diagram, internal clock divided by 4 . . . . .	593
Figure 200. Counter timing diagram, internal clock divided by N . . . . .	594

Figure 201. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) . . . . .	594
Figure 202. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	595
Figure 203. Control circuit in normal mode, internal clock divided by 1 . . . . .	596
Figure 204. Independent watchdog block diagram . . . . .	603
Figure 205. Watchdog block diagram . . . . .	609
Figure 206. Window watchdog timing diagram . . . . .	610
Figure 207. RTC block diagram . . . . .	616
Figure 208. Block diagram . . . . .	655
Figure 209. I ²C-bus protocol . . . . .	657
Figure 210. Setup and hold timings . . . . .	658
Figure 211. FMPI2C initialization flow . . . . .	661
Figure 212. Data reception . . . . .	662
Figure 213. Data transmission . . . . .	663
Figure 214. Target initialization flow . . . . .	666
Figure 215. Transfer sequence flow for FMPI2C target transmitter, NOSTRETCH = 0 . . . . .	668
Figure 216. Transfer sequence flow for FMPI2C target transmitter, NOSTRETCH = 1 . . . . .	669
Figure 217. Transfer bus diagrams for FMPI2C target transmitter (mandatory events only) . . . . .	670
Figure 218. Transfer sequence flow for FMPI2C target receiver, NOSTRETCH = 0 . . . . .	671
Figure 219. Transfer sequence flow for FMPI2C target receiver, NOSTRETCH = 1 . . . . .	672
Figure 220. Transfer bus diagrams for FMPI2C target receiver (mandatory events only) . . . . .	672
Figure 221. Controller clock generation . . . . .	674
Figure 222. Controller initialization flow . . . . .	676
Figure 223. 10-bit address read access with HEAD10R = 0 . . . . .	676
Figure 224. 10-bit address read access with HEAD10R = 1 . . . . .	677
Figure 225. Transfer sequence flow for FMPI2C controller transmitter, N ≤ 255 bytes . . . . .	678
Figure 226. Transfer sequence flow for FMPI2C controller transmitter, N > 255 bytes . . . . .	679
Figure 227. Transfer bus diagrams for FMPI2C controller transmitter (mandatory events only) . . . . .	680
Figure 228. Transfer sequence flow for FMPI2C controller receiver, N ≤ 255 bytes . . . . .	682
Figure 229. Transfer sequence flow for FMPI2C controller receiver, N > 255 bytes . . . . .	683
Figure 230. Transfer bus diagrams for FMPI2C controller receiver (mandatory events only) . . . . .	684
Figure 231. Timeout intervals for t _LOW:SEXT, t _LOW:MEXT. . . . .	688
Figure 232. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .	691
Figure 233. Transfer bus diagram for SMBus target transmitter (SBC = 1) . . . . .	692
Figure 234. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .	693
Figure 235. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .	694
Figure 236. Bus transfer diagrams for SMBus controller transmitter . . . . .	695
Figure 237. Bus transfer diagrams for SMBus controller receiver . . . . .	697
Figure 238. I2C bus protocol . . . . .	718
Figure 239. I2C block diagram . . . . .	719
Figure 240. Transfer sequence diagram for target transmitter . . . . .	720
Figure 241. Transfer sequence diagram for target receiver . . . . .	721
Figure 242. Transfer sequence diagram for controller transmitter . . . . .	724
Figure 243. Transfer sequence diagram for controller receiver . . . . .	725
Figure 244. I2C interrupt mapping diagram . . . . .	734
Figure 245. USART block diagram . . . . .	751
Figure 246. Word length programming . . . . .	752
Figure 247. Configurable stop bits . . . . .	754

Figure 248. TC/TXE behavior when transmitting . . . . .	755
Figure 249. Start bit detection when oversampling by 16 or 8. . . . .	756
Figure 250. Data sampling when oversampling by 16 . . . . .	759
Figure 251. Data sampling when oversampling by 8 . . . . .	760
Figure 252. Mute mode using Idle line detection . . . . .	773
Figure 253. Mute mode using address mark detection . . . . .	774
Figure 254. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .	776
Figure 255. Break detection in LIN mode vs. Framing error detection. . . . .	777
Figure 256. USART example of synchronous transmission. . . . .	778
Figure 257. USART data clock timing diagram (M=0) . . . . .	778
Figure 258. USART data clock timing diagram (M=1) . . . . .	779
Figure 259. RX data setup/hold time . . . . .	779
Figure 260. ISO 7816-3 asynchronous protocol . . . . .	780
Figure 261. Parity error detection using the 1.5 stop bits . . . . .	781
Figure 262. IrDA SIR ENDEC- block diagram . . . . .	783
Figure 263. IrDA data modulation (3/16) -Normal mode . . . . .	783
Figure 264. Transmission using DMA . . . . .	785
Figure 265. Reception using DMA . . . . .	786
Figure 266. Hardware flow control between 2 USARTs . . . . .	786
Figure 267. RTS flow control . . . . .	787
Figure 268. CTS flow control . . . . .	787
Figure 269. USART interrupt mapping diagram . . . . .	789
Figure 270. SPI block diagram. . . . .	803
Figure 271. Full-duplex single master/ single slave application. . . . .	804
Figure 272. Half-duplex single master/ single slave application . . . . .	805
Figure 273. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . .	806
Figure 274. Master and three independent slaves. . . . .	807
Figure 275. Multimaster application. . . . .	808
Figure 276. Hardware/software slave select management . . . . .	809
Figure 277. Data clock timing diagram . . . . .	811
Figure 278. TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers . . . . .	814
Figure 279. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers . . . . .	815
Figure 280. Transmission using DMA . . . . .	817
Figure 281. Reception using DMA. . . . .	818
Figure 282. TI mode transfer . . . . .	821
Figure 283. I ²S block diagram . . . . .	824
Figure 284. I2S full-duplex block diagram . . . . .	825
Figure 285. I ²S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . .	827
Figure 286. I ²S Philips standard waveforms (24-bit frame with CPOL = 0). . . . .	827
Figure 287. Transmitting 0x8EAA33 . . . . .	827
Figure 288. Receiving 0x8EAA33 . . . . .	828
Figure 289. I ²S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . .	828
Figure 290. Example of 16-bit data frame extended to 32-bit channel frame . . . . .	828
Figure 291. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . .	829
Figure 292. MSB justified 24-bit frame length with CPOL = 0 . . . . .	829
Figure 293. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .	829
Figure 294. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . .	830
Figure 295. LSB justified 24-bit frame length with CPOL = 0. . . . .	830
Figure 296. Operations required to transmit 0x3478AE. . . . .	830

Figure 297. Operations required to receive 0x3478AE . . . . .	831
Figure 298. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .	831
Figure 299. Example of 16-bit data frame extended to 32-bit channel frame . . . . .	831
Figure 300. PCM standard waveforms (16-bit) . . . . .	832
Figure 301. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .	832
Figure 302. Audio sampling frequency definition . . . . .	833
Figure 303. I ²S clock generator architecture . . . . .	833
Figure 304. “No response” and “no data” operations . . . . .	853
Figure 305. (Multiple) block read operation . . . . .	853
Figure 306. (Multiple) block write operation . . . . .	853
Figure 307. Sequential read operation. . . . .	854
Figure 308. Sequential write operation . . . . .	854
Figure 309. SDIO block diagram . . . . .	854
Figure 310. SDIO adapter . . . . .	856
Figure 311. Control unit . . . . .	857
Figure 312. SDIO_CK clock dephasing (BYPASS = 0) . . . . .	857
Figure 313. SDIO adapter command path . . . . .	858
Figure 314. Command path state machine (SDIO) . . . . .	859
Figure 315. SDIO command transfer . . . . .	860
Figure 316. Data path . . . . .	862
Figure 317. Data path state machine (DPSM) . . . . .	863
Figure 318. CAN network topology . . . . .	912
Figure 319. Dual-CAN block diagram . . . . .	913
Figure 320. bxCAN operating modes. . . . .	915
Figure 321. bxCAN in silent mode . . . . .	916
Figure 322. bxCAN in Loop back mode . . . . .	916
Figure 323. bxCAN in combined mode . . . . .	917
Figure 324. Transmit mailbox states . . . . .	919
Figure 325. Receive FIFO states . . . . .	920
Figure 326. Filter bank scale configuration - Register organization. . . . .	922
Figure 327. Example of filter numbering . . . . .	923
Figure 328. Filtering mechanism example . . . . .	924
Figure 329. CAN error state diagram. . . . .	926
Figure 330. Bit timing . . . . .	928
Figure 331. CAN frames . . . . .	929
Figure 332. Event flags and interrupt generation. . . . .	930
Figure 333. CAN mailbox registers . . . . .	942
Figure 334. OTG_FS full-speed block diagram . . . . .	959
Figure 335. OTG_FS A-B device connection. . . . .	961
Figure 336. OTG_FS peripheral-only connection . . . . .	963
Figure 337. OTG_FS host-only connection . . . . .	967
Figure 338. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .	971
Figure 339. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .	973
Figure 340. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .	974
Figure 341. Host-mode FIFO address mapping and AHB FIFO access mapping. . . . .	975
Figure 342. Interrupt hierarchy. . . . .	979
Figure 343. Transmit FIFO write task . . . . .	1062
Figure 344. Receive FIFO read task . . . . .	1063
Figure 345. Normal bulk/control OUT/SETUP . . . . .	1064
Figure 346. Bulk/control IN transactions . . . . .	1068
Figure 347. Normal interrupt OUT . . . . .	1071
Figure 348. Normal interrupt IN . . . . .	1076

Figure 349. Isochronous OUT transactions . . . . . 1078
Figure 350. Isochronous IN transactions . . . . . 1081
Figure 351. Receive FIFO packet read . . . . . 1085
Figure 352. Processing a SETUP packet . . . . . 1087
Figure 353. Bulk OUT transaction . . . . . 1094
Figure 354. TRDT max timing case . . . . . 1104
Figure 355. A-device SRP . . . . . 1105
Figure 356. B-device SRP . . . . . 1106
Figure 357. A-device HNP . . . . . 1107
Figure 358. B-device HNP . . . . . 1109
Figure 359. Block diagram of STM32 MCU and Cortex®-M4 with FPU-level
debug support. . . . . 1111
Figure 360. SWJ debug port . . . . . 1113
Figure 361. JTAG TAP connections . . . . . 1117
Figure 362. TPIU block diagram . . . . . 1135

RM0402-STM32F412

Contents

List of tables

List of figures

Chapters

RM0402-STM32F412

Related documents

Contents

List of tables

List of figures

Chapters