29. Revision history

System and memory overview
Updated Figure 2: Memory map .

Interrupts and events (EXTI)
Updated Section 9.1.2: SysTick calibration value register .

Analog-to-digital converted (ADC)
Removed note in Section : Temperature sensor, V _REFINT and V _BAT internal channels .

Digital-to-analog converted (DAC)
Updated Section 12.5.3: DAC output voltage .

Timer 11 (TIM11)
Updated TI1_RMP in Section 16.5.11: TIM11 option register 1 (TIM11_OR) .

Real-time clock (RTC)
Updated Figure 175: RTC block diagram .

Universal synchronous asynchronous receiver transmitter (USART)
Replaced section USART mode configuration by Section 24.3: USART implementation .

Fast-mode Plus Inter-integrated circuit interface (FMPI2C)
Updated Section 22.4.5: FMPI2C initialization , including Figure 179: Setup and hold timings .
Updated Section 22.7.5: Timing register (FMPI2C_TIMINGR) .

Serial peripheral interface/ inter-IC sound (SPI/I2S)
Updated Figure 240 , Figure 241 , Figure 242 and Figure 243 .
Updated and added notes below Figure 240 , Figure 241 and Figure 242 .
Added Section 25.3.4: Multi-master communication .

Updated:

• – Table 3: Embedded bootloader interfaces
• – Table 5: Flash module organization
• – Section 13: True random number generator (RNG)
• – Section 18: Low-power timer (LPTIM)
• – Section 22.6: FMPI2C interrupts

Cover page:
Added patented technology statement.
Updated Related documents .

Document conventions:
Added Section 1.3: Register reset value .

System and memory overview
Updated Figure 2: Memory map .

FLASH:
Updated Table 5: Flash module organization .
Added Note: .

PWR:
Updated Section 4.1.2: Battery backup domain .
Updated Section 4.2.3: Programmable voltage detector (PVD) .
Updated Section 4.4.2: PWR power control/status register (PWR_CSR) .

RCC:
Updated Section 5.1.1: System reset .
Updated Section 5.1.3: Backup domain reset .
Updated Section 5.3.4: RCC clock interrupt register (RCC_CIR) .
Updated Section 5.3.10: RCC APB2 peripheral clock enable register (RCC_APB2ENR) .
Updated Section 5.3.14: RCC Backup domain control register (RCC_BDCR) .

GPIO:
Updated Section 6.3.2: I/O pin multiplexer and mapping .
Updated Section 6.4.1: GPIO port mode register (GPIOx_MODER) (x = A..C and H) .

DMA:
Updated Table 8.1: DMA introduction .
Added Caution: .
Updated Table 29: DMA1 request mapping .

INTERRUPTS
Updated Section 9.3: EXTI registers .

ADC:
Updated Section 11.2: ADC main features .
Updated Figure 32: Single ADC block diagram .
Updated Table 42: ADC pins .
Updated Section 11.6: Conversion on external trigger and trigger polarity .
Updated Table 45: External trigger for regular channels .
Updated Section 11.8.1: Using the DMA
Updated Section 11.9: Temperature sensor .
Updated Section 11.12.1: ADC status register (ADC_SR) .

DAC:
Updated Table 51: DAC pins .

RNG:
Updated Section 13.1: Introduction .