17. Basic timers (TIM6)

17.1 Introduction

The basic timer TIM6 consists of a 16-bit auto-reload counter driven by a programmable prescaler.

IT can be used as generic timer for timebase generation but it is also specifically used to drive the digital-to-analog converter (DAC). In fact, the timer is internally connected to the DAC and is able to drive it through its trigger output.

The timers are completely independent, and do not share any resources.

They can be used as generic timers for timebase generation but they are also specifically used to drive the digital-to-analog converter (DAC). In fact, the timers are internally connected to the DAC and are able to drive it through their trigger outputs.

The timers are completely independent, and do not share any resources.

17.2 TIM6 main features

Basic timer (TIM6) features include:

• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536
• Synchronization circuit to trigger the DAC
• Interrupt/DMA generation on the update event: counter overflow

Figure 156. Basic timer block diagram

Notes:
Reg Preload registers transferred to active registers on U event according to control bit
~~~~~ Event
⚡ Interrupt & DMA output

MS33142V1

Figure 156. Basic timer block diagram. The diagram shows the internal architecture of the TIM6 basic timer. At the top, TIMxCLK from RCC is connected to a 'Trigger controller' block, which also receives 'Internal clock (CK_INT)'. The 'Trigger controller' has a 'Control' block and outputs 'TRGO' to the DAC. Below it, a 'PSC prescaler' block receives 'CK_PSC' and outputs 'CK_CNT' to a 'CNT counter' block. The 'CNT counter' is connected to an 'Auto-reload register' block. The 'Auto-reload register' has a 'Stop, clear or up' input and outputs 'U' (Update) and 'UI' (Interrupt & DMA output) signals. The 'CNT counter' also outputs 'U' (Update) and 'UI' (Interrupt & DMA output) signals. A legend at the bottom left explains the symbols: 'Reg' for preload registers transferred to active registers on U event according to control bit, a wavy arrow for 'Event', and a jagged arrow for 'Interrupt & DMA output'. The diagram is labeled MS33142V1.

17.3 TIM6 functional description

17.3.1 Time-base unit

The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter Register (TIMx_CNT)
• Prescaler Register (TIMx_PSC)
• Auto-Reload Register (TIMx_ARR)

The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set.

Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 157 and Figure 158 give some examples of the counter behavior when the prescaler ratio is changed on the fly.

Figure 157. Counter timing diagram with prescaler division change from 1 to 2

Figure 157 is a timing diagram illustrating the counter behavior when the prescaler division changes from 1 to 2. The diagram shows the following signals and registers over time:

CK_PSC : Prescaler clock signal, a periodic square wave.
CEN : Counter enable signal, active high.
Timerclock = CK_CNT : Counter clock signal, derived from CK_PSC. Its frequency changes when the prescaler division changes.
Counter register : Shows hexadecimal values F7, F8, F9, FA, FB, FC, followed by 00, 01, 02, 03. The counter increments by 1 for every 2 CK_PSC cycles after the first update event.
Update event (UEV) : Generated when the counter reaches its maximum value (0xFF). The first UEV occurs after 256 CK_PSC cycles.
Prescaler control register : Contains the prescaler division value. It is initially 0 (division by 1) and is updated to 1 (division by 2) at the first UEV. An arrow points to the write operation: "Write a new value in TIMx_PSC".
Prescaler buffer : Latches the new prescaler value (1) at the first UEV.
Prescaler counter : Counts CK_PSC cycles. It resets to 0 at each UEV. The sequence shown is 0, 1, 0, 1, 0, 1, 0, 1, indicating a division of 2.

MS31076V2

Figure 157: Counter timing diagram with prescaler division change from 1 to 2. The diagram shows the relationship between CK_PSC, CEN, Timerclock (CK_CNT), Counter register, Update event (UEV), Prescaler control register, Prescaler buffer, and Prescaler counter over time. The prescaler division changes from 1 to 2 at the first update event.

Figure 158. Counter timing diagram with prescaler division change from 1 to 4

Figure 158 is a timing diagram illustrating the counter behavior when the prescaler division changes from 1 to 4. The diagram shows the following signals and registers over time:

CK_PSC : Prescaler clock signal, a periodic square wave.
CEN : Counter enable signal, active high.
Timerclock = CK_CNT : Counter clock signal, derived from CK_PSC. Its frequency changes when the prescaler division changes.
Counter register : Shows hexadecimal values F7, F8, F9, FA, FB, FC, followed by 00, 01. The counter increments by 1 for every 4 CK_PSC cycles after the first update event.
Update event (UEV) : Generated when the counter reaches its maximum value (0xFF). The first UEV occurs after 256 CK_PSC cycles.
Prescaler control register : Contains the prescaler division value. It is initially 0 (division by 1) and is updated to 3 (division by 4) at the first UEV. An arrow points to the write operation: "Write a new value in TIMx_PSC".
Prescaler buffer : Latches the new prescaler value (3) at the first UEV.
Prescaler counter : Counts CK_PSC cycles. It resets to 0 at each UEV. The sequence shown is 0, 1, 2, 3, 0, 1, 2, 3, indicating a division of 4.

MS31077V2

Figure 158: Counter timing diagram with prescaler division change from 1 to 4. The diagram shows the relationship between CK_PSC, CEN, Timerclock (CK_CNT), Counter register, Update event (UEV), Prescaler control register, Prescaler buffer, and Prescaler counter over time. The prescaler division changes from 1 to 4 at the first update event.

17.3.2 Counting mode

The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent).

When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register)
• The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36.

Figure 159. Counter timing diagram, internal clock divided by 1

The timing diagram illustrates the operation of a counter in counting mode. The top signal, CK_PSC, is a periodic square wave representing the prescaler clock. Below it, CNT_EN is a signal that goes high to enable the counter. The third signal, Timerclock = CK_CNT, is a square wave that is active only when CNT_EN is high. The fourth signal, Counter register, shows a sequence of values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. The counter increments by 1 at each rising edge of the timer clock. When the counter reaches 36 (0x24), it overflows to 00. The fifth signal, Counter overflow, is a pulse that goes high when the counter reaches 36 and returns low when it reaches 00. The sixth signal, Update event (UEV), is a pulse that goes high when the counter overflows. The bottom signal, Update interrupt flag (UIF), is a pulse that goes high when the counter overflows and returns low when the counter reaches 00. Vertical dashed lines indicate the timing relationships between the signals.

Timing diagram for a counter in counting mode. The diagram shows the relationship between the prescaler clock (CK_PSC), counter enable (CNT_EN), timer clock (CK_CNT), counter register values, counter overflow, update event (UEV), and update interrupt flag (UIF).

MS31078V2

Figure 160. Counter timing diagram, internal clock divided by 2

Timing diagram for internal clock divided by 2. It shows CK_PSC, CNT_EN, Timerclock = CK_CNT, Counter register values (0034 to 0003), Counter overflow, Update event (UEV), and Update interrupt flag (UIF) over time.

This timing diagram illustrates the operation of a basic timer with the internal clock divided by 2. The signals shown are:

CK_PSC : Prescaler clock signal, shown as a continuous square wave.
CNT_EN : Counter enable signal, which goes high to start counting.
Timerclock = CK_CNT : The clock signal for the counter, which is the CK_PSC signal divided by 2.
Counter register : Shows the sequence of values: 0034, 0035, 0036, 0000, 0001, 0002, 0003. The counter increments on each rising edge of the timer clock.
Counter overflow : A pulse that goes high when the counter reaches 0036 and rolls over to 0000.
Update event (UEV) : A pulse that goes high when the counter reaches 0036 and rolls over to 0000.
Update interrupt flag (UIF) : A signal that goes high when the counter reaches 0036 and rolls over to 0000.

Vertical dashed lines indicate the timing relationships between the counter register values and the overflow, UEV, and UIF signals. The MS31079V2 identifier is present in the bottom right corner.

Timing diagram for internal clock divided by 2. It shows CK_PSC, CNT_EN, Timerclock = CK_CNT, Counter register values (0034 to 0003), Counter overflow, Update event (UEV), and Update interrupt flag (UIF) over time.

Figure 161. Counter timing diagram, internal clock divided by 4

Timing diagram for internal clock divided by 4. It shows CK_PSC, CNT_EN, Timerclock = CK_CNT, Counter register values (0035 to 0001), Counter overflow, Update event (UEV), and Update interrupt flag (UIF) over time.

This timing diagram illustrates the operation of a basic timer with the internal clock divided by 4. The signals shown are:

CK_PSC : Prescaler clock signal, shown as a continuous square wave.
CNT_EN : Counter enable signal, which goes high to start counting.
Timerclock = CK_CNT : The clock signal for the counter, which is the CK_PSC signal divided by 4.
Counter register : Shows the sequence of values: 0035, 0036, 0000, 0001. The counter increments on each rising edge of the timer clock.
Counter overflow : A pulse that goes high when the counter reaches 0036 and rolls over to 0000.
Update event (UEV) : A pulse that goes high when the counter reaches 0036 and rolls over to 0000.
Update interrupt flag (UIF) : A signal that goes high when the counter reaches 0036 and rolls over to 0000.

Vertical dashed lines indicate the timing relationships between the counter register values and the overflow, UEV, and UIF signals. The MS31080V2 identifier is present in the bottom right corner.

Timing diagram for internal clock divided by 4. It shows CK_PSC, CNT_EN, Timerclock = CK_CNT, Counter register values (0035 to 0001), Counter overflow, Update event (UEV), and Update interrupt flag (UIF) over time.

Figure 162. Counter timing diagram, internal clock divided by N

Timing diagram for Figure 162 showing CK_PSC, Timerclock = CK_CNT, Counter register (values 1F, 20, 00), Counter overflow, Update event (UEV), and Update interrupt flag (UIF) signals over time.

This timing diagram illustrates the operation of a basic timer with an internal clock divided by N. The signals shown are:

CK_PSC: Prescaler clock signal, shown as a square wave.
Timerclock = CK_CNT: Counter clock signal, derived from CK_PSC. It is a square wave with a frequency divided by N.
Counter register: Shows the counter value. It starts at 1F, increments to 20, and then overflows to 00. The overflow occurs on a rising edge of the timer clock.
Counter overflow: A pulse generated when the counter reaches its maximum value and rolls over to 00.
Update event (UEV): A pulse generated when the counter overflows.
Update interrupt flag (UIF): A flag that is set when an update event occurs.

The diagram shows the counter register transitioning from 1F to 20, then overflowing to 00. The overflow, UEV, and UIF signals are shown as pulses that coincide with the counter's rollover. The source identifier MS31081V2 is visible in the bottom right corner.

Timing diagram for Figure 162 showing CK_PSC, Timerclock = CK_CNT, Counter register (values 1F, 20, 00), Counter overflow, Update event (UEV), and Update interrupt flag (UIF) signals over time.

Figure 163. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded)

Timing diagram for Figure 163 showing CK_PSC, CEN, Timerclock = CK_CNT, Counter register (values 31 to 07), Counter overflow, Update event (UEV), Update interrupt flag (UIF), and Auto-reload preload register (values FF, 36).

This timing diagram illustrates the operation of a basic timer when ARPE = 0 and the TIMx_ARR register is not preloaded. The signals shown are:

CK_PSC: Prescaler clock signal, shown as a square wave.
CEN: Counter Enable signal, shown as a high-level signal.
Timerclock = CK_CNT: Counter clock signal, shown as a square wave.
Counter register: Shows the counter values 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. The overflow occurs when the counter transitions from 36 to 00.
Counter overflow: A pulse generated when the counter reaches its maximum value (36) and rolls over to 00.
Update event (UEV): A pulse generated when the counter overflows.
Update interrupt flag (UIF): A flag that is set when an update event occurs.
Auto-reload preload register: Shows the register value changing from FF to 36. An arrow points to the transition with the text "Write a new value in TIMx_ARR".

The diagram shows the counter incrementing from 31 to 36, then overflowing to 00. The overflow, UEV, and UIF signals are shown as pulses that coincide with the counter's rollover. The auto-reload preload register is shown being updated from FF to 36. The source identifier MS31082V2 is visible in the bottom right corner.

Timing diagram for Figure 163 showing CK_PSC, CEN, Timerclock = CK_CNT, Counter register (values 31 to 07), Counter overflow, Update event (UEV), Update interrupt flag (UIF), and Auto-reload preload register (values FF, 36).

Figure 164. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)

Figure 164: Counter timing diagram showing the relationship between CK_PSC, CEN, Timerclock (CK_CNT), Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), Auto-reload preload register, and Auto-reload shadow register. The diagram illustrates the counter sequence from F0 to 07, the overflow at F5, and the update event when the auto-reload value is preloaded from F5 to 36.

The timing diagram shows the following signals and their states over time:

CK_PSC : A periodic square wave clock signal.
CEN : Counter Enable signal, which is initially low and then goes high to enable the counter.
Timerclock = CK_CNT : The clock signal for the counter, which is derived from CK_PSC.
Counter register : Shows the sequence of counter values: F0, F1, F2, F3, F4, F5, 00, 01, 02, 03, 04, 05, 06, 07. The counter increments on each rising edge of the timer clock.
Counter overflow : A signal that goes high when the counter reaches the value F5.
Update event (UEV) : A signal that goes high when the counter overflows (at F5).
Update interrupt flag (UIF) : A signal that goes high when the update event occurs.
Auto-reload preload register : Shows the value F5 being written to the register, and then the value 36 being loaded into the register after the update event.
Auto-reload shadow register : Shows the value F5 being loaded into the shadow register, and then the value 36 being loaded into the shadow register after the update event.

An annotation "Write a new value in TIMx_ARR" points to the initial value F5 in the Auto-reload preload register. The diagram is labeled MS31083V2.

Figure 164: Counter timing diagram showing the relationship between CK_PSC, CEN, Timerclock (CK_CNT), Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), Auto-reload preload register, and Auto-reload shadow register. The diagram illustrates the counter sequence from F0 to 07, the overflow at F5, and the update event when the auto-reload value is preloaded from F5 to 36.

17.3.3 Clock source

The counter clock is provided by the Internal clock (CK_INT) source.

The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 165 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Figure 165. Control circuit in normal mode, internal clock divided by 1

Timing diagram for Figure 165 showing the control circuit in normal mode with internal clock divided by 1. The diagram illustrates the relationship between the internal clock, counter enable (CEN=CNT_EN), update generation (UG), counter initialization (CNT_INIT), counter clock (CK_CNT = CK_PSC), and the counter register values over time.

The timing diagram shows five signal levels over time, separated by vertical dashed lines. The signals are:

Internal clock: A continuous square wave.
CEN=CNT_EN: A signal that is initially low, then goes high, and remains high.
UG: A signal that is initially low, then goes high at the second dashed line, and remains high.
CNT_INIT: A signal that is initially low, then goes high at the third dashed line, and remains high.
Counter clock = CK_CNT = CK_PSC: A signal that is initially low, then goes high at the second dashed line, and remains high.
Counter register: A sequence of values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. The values 31 through 36 are shown before the second dashed line, and the values 00 through 07 are shown after the third dashed line.

MS31085V2

Timing diagram for Figure 165 showing the control circuit in normal mode with internal clock divided by 1. The diagram illustrates the relationship between the internal clock, counter enable (CEN=CNT_EN), update generation (UG), counter initialization (CNT_INIT), counter clock (CK_CNT = CK_PSC), and the counter register values over time.

17.3.4 Debug mode

When the microcontroller enters the debug mode (Cortex ^®-M4 with FPU core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBGMCU module. For more details, refer to Section 26.16.2: Debug support for timers, watchdog, and I ²C .

17.4 TIM6 registers

Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions.

The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

17.4.1 TIM6 control register 1 (TIMx_CR1)

Address offset: 0x00

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ARPE	Res.	Res.	Res.	OPM	URS	UDIS	CEN
								rw				rw	rw	rw	rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered.

1: TIMx_ARR register is buffered.

Bits 6:4 Reserved, must be kept at reset value.

Bit 3 OPM : One-pulse mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the CEN bit).

Bit 2 URS : Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generates an update interrupt or DMA request if enabled.

These events can be:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS : Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN : Counter enable

0: Counter disabled

1: Counter enabled

Note: Gated mode can work only if the CEN bit has been previously set by software.

However trigger mode can set the CEN bit automatically by hardware.

CEN is cleared automatically in one-pulse mode, when an update event occurs.

17.4.2 TIM6 control register 2 (TIMx_CR2)

Address offset: 0x04

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MMS[2:0]				Res.	Res.	Res.
									rw	rw	rw

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 MMS : Master mode selection

These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:

000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.

001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.

When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register).

010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

Bits 3:0 Reserved, must be kept at reset value.

17.4.3 TIM6 DMA/Interrupt enable register (TIMx_DIER)

Address offset: 0x0C

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	UDE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIE
							rw								rw

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 UDE : Update DMA request enable

0: Update DMA request disabled.

1: Update DMA request enabled.

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 UIE : Update interrupt enable

0: Update interrupt disabled.

1: Update interrupt enabled.

17.4.4 TIM6 status register (TIMx_SR)

Address offset: 0x10

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIF
															rc_w0

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UIF : Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register.

17.4.5 TIM6 event generation register (TIMx_EGR)

Address offset: 0x14

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UG
															w

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UG : Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action.

1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).

17.4.6 TIM6 counter (TIMx_CNT)

Address offset: 0x24

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 CNT[15:0] : Counter value

17.4.7 TIM6 prescaler (TIMx_PSC)

Address offset: 0x28

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency (CK_CNT) is equal to $f_{CK\_PSC} / (PSC[15:0] + 1)$ .

PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).

17.4.8 TIM6 auto-reload register (TIMx_ARR)

Address offset: 0x2C

Reset value: 0xFFFF

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 ARR[15:0] : Auto-reload value

ARR is the value to be loaded into the actual auto-reload register.

Refer to Section 17.3.1: Time-base unit on page 438 for more details about ARR update and behavior.

The counter is blocked while the auto-reload value is null.

17.4.9 TIM6 register map

TIMx registers are mapped as 16-bit addressable registers as described in the table below:

Table 71. TIM6 register map and reset values

Offset	Register	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	TIMx_CR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ARPE	Res.	Res.	Res.	OPM	URS	UDIS	CEN
0x00	Reset value									0				0	0	0	0
0x04	TIMx_CR2	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MMS[2:0]			Res.	Res.	Res.	Res.
0x04	Reset value										0	0	0
0x08	Res.
0x0C	TIMx_DIER	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UDE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIE
0x0C	Reset value								0								0
0x10	TIMx_SR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIF
0x10	Reset value																0
0x14	TIMx_EGR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UG
0x14	Reset value																0
0x18	Res.
0x1C	Res.
0x20	Res.
0x24	TIMx_CNT	CNT[15:0]
0x24	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x28	TIMx_PSC	PSC[15:0]
0x28	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x2C	TIMx_ARR	ARR[15:0]
0x2C	Reset value	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

Refer to Section 2.2 on page 39 for the register boundary addresses.