7. System configuration controller (SYSCFG)

The system configuration controller is mainly used to remap the memory accessible in the code area and manage the external interrupt line connection to the GPIOs.

7.1 I/O compensation cell

By default the I/O compensation cell is not used. However when the I/O output buffer speed is configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell for slew rate control on I/O \( t_{f(IO)out}/t_{r(IO)out} \) commutation to reduce the I/O noise on power supply.

When the compensation cell is enabled, a READY flag is set to indicate that the compensation cell is ready and can be used. The I/O compensation cell can be used only when the supply voltage ranges from 2.4 to 3.6 V.

7.2 SYSCFG registers

7.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)

This register is used for specific configurations on memory remap:

• • Two bits are used to configure the type of memory accessible at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the BOOT pins.
• • After reset these bits take the value selected by the BOOT pins. When booting from main flash memory with BOOT0 pin set to 0, this register takes the value 0x00.

In remap mode, the CPU can access the external memory via ICode bus instead of System bus which boosts up the performance.

Address offset: 0x00

Reset value: 0x0000 000X (X is the memory mode selected by the BOOT pins)

Bits 31:2 Reserved, must be kept at reset value.

Bits 1:0 MEM_MODE : Memory mapping selection

Set and cleared by software. This bit controls the memory internal mapping at address 0x0000 0000. After reset these bits take the value selected by the Boot pins.

00: Main flash memory mapped at 0x0000 0000

01: System flash memory mapped at 0x0000 0000

10: reserved

11: Embedded SRAM mapped at 0x0000 0000

Note: Refer to Figure 2: Memory map for details about the memory mapping at address 0x0000 0000.

7.2.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 ADC1DC2 :

0: No effect.

1: Refer to AN4073 on how to use this bit

Note: These bits can be set only if the following conditions are met:

• - ADC clock higher or equal to 30 MHz.
• - Only one ADC1DC2 bit must be selected if ADC conversions do not start at the same time and the sampling times differ.
• - These bits must not be set when the ADCDC1 bit is set in PWR_CR register.

Bits 15:0 Reserved, must be kept at reset value.

7.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)

Address offset: 0x08

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0111: PH[x] pin

Other configurations: reserved

7.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0111: PH[x] pin

Other configurations: reserved

7.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)

Address offset: 0x10

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 8 to 11)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0101: Reserved

0110: Reserved

0111: PH[x] pin

Other configurations: reserved

7.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)

Address offset: 0x14

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 12 to 15)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0101: Reserved

0110: Reserved

0111: PH[x] pin

7.2.7 SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x1C

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bit 8 PVDL: PVD lock

This bit is set by software. It can be cleared only by a system reset. It enables and locks the PVD connection to TIM1 Break input. It also locks (write protection) the PVDE and PVDS[2:0] bits of PWR_CR register.

0: PVD interrupt not connected to TIM1 Break input. PVDE and PVDS[2:0] can be read and modified

1: PVD interrupt connected to TIM1 Break input. PVDE and PVDS[2:0] are read-only

Bit 1 Reserved, must be kept at reset value.

Bit 0 CLL: core lockup lock

This bit is set and cleared by software. It enables and locks the LOCKUP (Hardfault) output of the Cortex-M4 core with TIM1 Break input.

0: Cortex-M4 LOCKUP output not connected to TIM1 Break input

1: Cortex-M4 LOCKUP output connected to TIM1 Break input

7.2.8 Compensation cell control register (SYSCFG_CMPCR)

Address offset: 0x20

Reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 READY : Compensation cell ready flag

0: I/O compensation cell not ready

1: I/O compensation cell ready

Bits 7:2 Reserved, must be kept at reset value.

Bit 0 CMP_PD : Compensation cell power-down

0: I/O compensation cell power-down mode

1: I/O compensation cell enabled

7.2.9 Compensation cell control register (SYSCFG_CFGR)

Address offset: 0x2C

Reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 FMPI2C4_SDA

Set and cleared by software. When this bit is set, it forces FM+ drive capability on FMPI2C4_SDA pin selected through GPIO port mode register and GPIO alternate function selection bits.

Bit 0 FMPI2C4_SCL

Set and cleared by software. When this bit is set, it forces FM+ drive capability on FMPI2C4_SCL pin selected through GPIO port mode register and GPIO alternate function selection bits.

7.2.10 SYSCFG register map

The following table gives the SYSCFG register map and the reset values.

Table 28. SYSCFG register map and reset values

Refer to Section 2.2 on page 39 for the register boundary addresses.