RM0401-STM32F410

This reference manual targets application developers. It provides complete information on how to use the memory and the peripherals of the STM32F410 microcontrollers.

The STM32F410 is a line of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics refer to the datasheets.

For information on the Arm ® Cortex ® -M4 with FPU core, refer to the Cortex ® -M4 with FPU Technical Reference Manual .

The STM32F410 microcontrollers include ST state-of-the-art patented technology.

Available from STMicroelectronics web site www.st.com :

Contents

3.5.2Program/erase parallelism . . . . .53
3.5.3Erase . . . . .53
3.5.4Programming . . . . .54
3.5.5Interrupts . . . . .55
3.6Option bytes . . . . .55
3.6.1Description of user option bytes . . . . .55
3.6.2Programming user option bytes . . . . .57
3.6.3Read protection (RDP) . . . . .57
3.6.4Write protections . . . . .59
3.6.5Proprietary code readout protection (PCROP) . . . . .60
3.7One-time programmable bytes . . . . .62
3.8Flash interface registers . . . . .63
3.8.1Flash access control register (FLASH_ACR) . . . . .63
3.8.2Flash key register (FLASH_KEYR) . . . . .64
3.8.3Flash option key register (FLASH_OPTKEYR) . . . . .64
3.8.4Flash status register (FLASH_SR) . . . . .65
3.8.5Flash control register (FLASH_CR) . . . . .66
3.8.6Flash option control register (FLASH_OPTCR) . . . . .67
3.8.7Flash interface register map . . . . .70
4Power controller (PWR) . . . . .71
4.1Power supplies . . . . .71
4.1.1Independent A/D converter supply and reference voltage . . . . .72
4.1.2Battery backup domain . . . . .72
4.1.3Voltage regulator . . . . .73
4.2Power supply supervisor . . . . .74
4.2.1Power-on reset (POR)/power-down reset (PDR) . . . . .74
4.2.2Brownout reset (BOR) . . . . .75
4.2.3Programmable voltage detector (PVD) . . . . .76
4.3Low-power modes . . . . .76
4.3.1Optimizing PLL VCO frequency . . . . .78
4.3.2Slowing down system clocks . . . . .78
4.3.3Peripheral clock gating . . . . .78
4.3.4Flash memory in low-power mode for code execution from RAM . . . . .79
4.3.5Sleep mode . . . . .79
4.3.6Batch acquisition mode . . . . .80
4.3.7Stop mode . . . . .81
4.3.8Standby mode . . . . .84
4.3.9Programming the RTC alternate functions to wake up the device from the Stop and Standby modes . . . . .86
4.4Power control registers . . . . .89
4.4.1PWR power control register (PWR_CR) . . . . .89
4.4.2PWR power control/status register (PWR_CSR) . . . . .91
4.5PWR register map . . . . .93
5Reset and clock control (RCC) . . . . .94
5.1Reset . . . . .94
5.1.1System reset . . . . .94
5.1.2Power reset . . . . .95
5.1.3Backup domain reset . . . . .95
5.2Clocks . . . . .96
5.2.1HSE clock . . . . .99
5.2.2HSI clock . . . . .100
5.2.3PLL configuration . . . . .100
5.2.4LSE clock . . . . .100
5.2.5LSI clock . . . . .101
5.2.6System clock (SYSCLK) selection . . . . .101
5.2.7Clock security system (CSS) . . . . .101
5.2.8RTC/AWU clock . . . . .102
5.2.9Watchdog clock . . . . .102
5.2.10Clock-out capability . . . . .103
5.2.11Internal/external clock measurement using TIM5/TIM11 . . . . .103
5.3RCC registers . . . . .105
5.3.1RCC clock control register (RCC_CR) . . . . .105
5.3.2RCC PLL configuration register (RCC_PLLCFGR) . . . . .107
5.3.3RCC clock configuration register (RCC_CFGR) . . . . .109
5.3.4RCC clock interrupt register (RCC_CIR) . . . . .112
5.3.5RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .114
5.3.6RCC APB1 peripheral reset register for (RCC_APB1RSTR) . . . . .115
5.3.7RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .117
5.3.8RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .119
5.3.9RCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . .120
5.3.10RCC APB2 peripheral clock enable register (RCC_APB2ENR) .....122
5.3.11RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR) .....124
5.3.12RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR) .....126
5.3.13RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) .....128
5.3.14RCC Backup domain control register (RCC_BDCR) .....130
5.3.15RCC clock control & status register (RCC_CSR) .....131
5.3.16RCC spread spectrum clock generation register (RCC_SSCGR) .....133
5.3.17RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR) ..134
5.3.18RCC dedicated Clocks Configuration Register 2 (RCC_DCKCFGR2)135
5.3.19RCC register map .....136
6General-purpose I/Os (GPIO) .....138
6.1GPIO introduction .....138
6.2GPIO main features .....138
6.3GPIO functional description .....138
6.3.1General-purpose I/O (GPIO) .....140
6.3.2I/O pin multiplexer and mapping .....141
6.3.3I/O port control registers .....143
6.3.4I/O port data registers .....144
6.3.5I/O data bitwise handling .....144
6.3.6GPIO locking mechanism .....144
6.3.7I/O alternate function input/output .....145
6.3.8External interrupt/wakeup lines .....145
6.3.9Input configuration .....145
6.3.10Output configuration .....146
6.3.11Alternate function configuration .....146
6.3.12Analog configuration .....147
6.3.13Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins .....148
6.3.14Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins .....148
6.3.15Selection of RTC additional functions .....148
6.4GPIO registers .....150
6.4.1GPIO port mode register (GPIOx_MODER) (x = A..C and H) .....150
6.4.2GPIO port output type register (GPIOx_OTYPER)
(x = A..C and H) . . . . .		150
6.4.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A..C and H) . . . . .		151
6.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A..C and H) . . . . .		151
6.4.5GPIO port input data register (GPIOx_IDR) (x = A..C and H) . . . . .152
6.4.6GPIO port output data register (GPIOx_ODR) (x = A..C and H) . . . . .152
6.4.7GPIO port bit set/reset register (GPIOx_BRR) (x = A..C and H) . . . . .152
6.4.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A..C and H) . . . . .		153
6.4.9GPIO alternate function low register (GPIOx_AFRL) (x = A..C and H)154
6.4.10GPIO alternate function high register (GPIOx_AFRH)
(x = A..C and H) . . . . .		155
6.4.11GPIO register map . . . . .155
7System configuration controller (SYSCFG) . . . . .158
7.1I/O compensation cell . . . . .158
7.2SYSCFG registers . . . . .158
7.2.1SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .158
7.2.2SYSCFG peripheral mode configuration register (SYSCFG_PMC) . . . . .159
7.2.3SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . .		160
7.2.4SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . .		160
7.2.5SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . .		161
7.2.6SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . .		161
7.2.7SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .162
7.2.8Compensation cell control register (SYSCFG_CMPCR) . . . . .162
7.2.9Compensation cell control register (SYSCFG_CFGR) . . . . .163
7.2.10SYSCFG register map . . . . .164
8Direct memory access controller (DMA) . . . . .165
8.1DMA introduction . . . . .165
8.2DMA main features . . . . .165
8.3DMA functional description . . . . .167
8.3.1DMA block diagram . . . . .167
8.3.2DMA overview .....167
8.3.3DMA transactions .....168
8.3.4Channel selection .....169
8.3.5Arbiter .....170
8.3.6DMA streams .....171
8.3.7Source, destination and transfer modes .....171
8.3.8Pointer incrementation .....174
8.3.9Circular mode .....175
8.3.10Double-buffer mode .....175
8.3.11Programmable data width, packing/unpacking, endianness .....176
8.3.12Single and burst transfers .....177
8.3.13FIFO .....178
8.3.14DMA transfer completion .....181
8.3.15DMA transfer suspension .....182
8.3.16Flow controller .....183
8.3.17Summary of the possible DMA configurations .....184
8.3.18Stream configuration procedure .....184
8.3.19Error management .....185
8.4DMA interrupts .....186
8.5DMA registers .....187
8.5.1DMA low interrupt status register (DMA_LISR) .....187
8.5.2DMA high interrupt status register (DMA_HISR) .....188
8.5.3DMA low interrupt flag clear register (DMA_LIFCR) .....189
8.5.4DMA high interrupt flag clear register (DMA_HIFCR) .....189
8.5.5DMA stream x configuration register (DMA_SxCR) .....190
8.5.6DMA stream x number of data register (DMA_SxNDTR) .....193
8.5.7DMA stream x peripheral address register (DMA_SxPAR) .....194
8.5.8DMA stream x memory 0 address register
(DMA_SxM0AR) .....		194
8.5.9DMA stream x memory 1 address register
(DMA_SxM1AR) .....		194
8.5.10DMA stream x FIFO control register (DMA_SxFCR) .....195
8.5.11DMA register map .....196
9Interrupts and events .....200
9.1Nested vectored interrupt controller (NVIC) .....200
9.1.1NVIC features .....200
9.1.2SysTick calibration value register . . . . .200
9.1.3Interrupt and exception vectors . . . . .200
9.2External interrupt/event controller (EXTI) . . . . .200
9.2.1EXTI main features . . . . .204
9.2.2EXTI block diagram . . . . .205
9.2.3Wakeup event management . . . . .205
9.2.4Functional description . . . . .205
9.2.5External interrupt/event line mapping . . . . .207
9.3EXTI registers . . . . .208
9.3.1Interrupt mask register (EXTI_IMR) . . . . .208
9.3.2Event mask register (EXTI_EMR) . . . . .208
9.3.3Rising trigger selection register (EXTI_RTSR) . . . . .209
9.3.4Falling trigger selection register (EXTI_FTSR) . . . . .209
9.3.5Software interrupt event register (EXTI_SWIER) . . . . .210
9.3.6Pending register (EXTI_PR) . . . . .210
9.3.7EXTI register map . . . . .212
10CRC calculation unit . . . . .213
10.1CRC introduction . . . . .213
10.2CRC main features . . . . .213
10.3CRC functional description . . . . .213
10.4CRC registers . . . . .214
10.4.1Data register (CRC_DR) . . . . .214
10.4.2Independent data register (CRC_IDR) . . . . .215
10.4.3Control register (CRC_CR) . . . . .215
10.4.4CRC register map . . . . .216
11Analog-to-digital converter (ADC) . . . . .217
11.1ADC introduction . . . . .217
11.2ADC main features . . . . .217
11.3ADC functional description . . . . .218
11.3.1ADC on-off control . . . . .219
11.3.2ADC clock . . . . .219
11.3.3Channel selection . . . . .219
11.3.4Single conversion mode . . . . .220
11.3.5Continuous conversion mode . . . . .220
11.3.6Timing diagram . . . . .221
11.3.7Analog watchdog . . . . .221
11.3.8Scan mode . . . . .222
11.3.9Injected channel management . . . . .222
11.3.10Discontinuous mode . . . . .223
11.4Data alignment . . . . .224
11.5Channel-wise programmable sampling time . . . . .225
11.6Conversion on external trigger and trigger polarity . . . . .226
11.7Fast conversion mode . . . . .227
11.8Data management . . . . .227
11.8.1Using the DMA . . . . .227
11.8.2Managing a sequence of conversions without using the DMA . . . . .228
11.8.3Conversions without DMA and without overrun detection . . . . .228
11.9Temperature sensor . . . . .228
11.10Battery charge monitoring . . . . .230
11.11ADC interrupts . . . . .230
11.12ADC registers . . . . .231
11.12.1ADC status register (ADC_SR) . . . . .231
11.12.2ADC control register 1 (ADC_CR1) . . . . .232
11.12.3ADC control register 2 (ADC_CR2) . . . . .234
11.12.4ADC sample time register 1 (ADC_SMPR1) . . . . .236
11.12.5ADC sample time register 2 (ADC_SMPR2) . . . . .236
11.12.6ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . . . .237
11.12.7ADC watchdog higher threshold register (ADC_HTR) . . . . .237
11.12.8ADC watchdog lower threshold register (ADC_LTR) . . . . .237
11.12.9ADC regular sequence register 1 (ADC_SQR1) . . . . .238
11.12.10ADC regular sequence register 2 (ADC_SQR2) . . . . .239
11.12.11ADC regular sequence register 3 (ADC_SQR3) . . . . .239
11.12.12ADC injected sequence register (ADC_JSQR) . . . . .240
11.12.13ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . .240
11.12.14ADC regular data register (ADC_DR) . . . . .241
11.12.15ADC Common status register (ADC_CSR) . . . . .241
11.12.16ADC common control register (ADC_CCR) . . . . .242
11.12.17ADC register map . . . . .243
12Digital-to-analog converter (DAC) . . . . .245
13.4RNG interrupts . . . . .265
13.5RNG processing time . . . . .265
13.6RNG entropy source validation . . . . .265
13.6.1Introduction . . . . .265
13.6.2Validation conditions . . . . .266
13.6.3Data collection . . . . .266
13.7RNG registers . . . . .266
13.7.1RNG control register (RNG_CR) . . . . .266
13.7.2RNG status register (RNG_SR) . . . . .267
13.7.3RNG data register (RNG_DR) . . . . .268
13.7.4RNG register map . . . . .269
14Advanced-control timers (TIM1) . . . . .270
14.1TIM1 introduction . . . . .270
14.2TIM1 main features . . . . .270
14.3TIM1 functional description . . . . .272
14.3.1Time-base unit . . . . .272
14.3.2Counter modes . . . . .274
14.3.3Repetition counter . . . . .283
14.3.4Clock selection . . . . .285
14.3.5Capture/compare channels . . . . .288
14.3.6Input capture mode . . . . .291
14.3.7PWM input mode . . . . .292
14.3.8Forced output mode . . . . .292
14.3.9Output compare mode . . . . .293
14.3.10PWM mode . . . . .294
14.3.11Complementary outputs and dead-time insertion . . . . .297
14.3.12Using the break function . . . . .299
14.3.13Clearing the OCxREF signal on an external event . . . . .302
14.3.146-step PWM generation . . . . .303
14.3.15One-pulse mode . . . . .304
14.3.16Encoder interface mode . . . . .305
14.3.17Timer input XOR function . . . . .308
14.3.18Interfacing with Hall sensors . . . . .308
14.3.19TIMx and external trigger synchronization . . . . .310
14.3.20Debug mode . . . . .313
14.4TIM1 registers . . . . .314
14.4.1TIM1 control register 1 (TIMx_CR1) . . . . .314
14.4.2TIM1 control register 2 (TIMx_CR2) . . . . .315
14.4.3TIM1 slave mode control register (TIMx_SMCR) . . . . .317
14.4.4TIM1 DMA/interrupt enable register (TIMx_DIER) . . . . .319
14.4.5TIM1 status register (TIMx_SR) . . . . .321
14.4.6TIM1 event generation register (TIMx_EGR) . . . . .322
14.4.7TIM1 capture/compare mode register 1 (TIMx_CCMR1) . . . . .323
14.4.8TIM1 capture/compare mode register 2 (TIMx_CCMR2) . . . . .326
14.4.9TIM1 capture/compare enable register (TIMx_CCER) . . . . .328
14.4.10TIM1 counter (TIMx_CNT) . . . . .332
14.4.11TIM1 prescaler (TIMx_PSC) . . . . .332
14.4.12TIM1 auto-reload register (TIMx_ARR) . . . . .332
14.4.13TIM1 repetition counter register (TIMx_RCR) . . . . .332
14.4.14TIM1 capture/compare register 1 (TIMx_CCR1) . . . . .333
14.4.15TIM1 capture/compare register 2 (TIMx_CCR2) . . . . .333
14.4.16TIM1 capture/compare register 3 (TIMx_CCR3) . . . . .334
14.4.17TIM1 capture/compare register 4 (TIMx_CCR4) . . . . .334
14.4.18TIM1 break and dead-time register (TIMx_BDTR) . . . . .334
14.4.19TIM1 DMA control register (TIMx_DCR) . . . . .336
14.4.20TIM1 DMA address for full transfer (TIMx_DMAR) . . . . .337
14.4.21TIM1 register map . . . . .338
15General-purpose timers (TIM5) . . . . .340
15.1TIM5 introduction . . . . .340
15.2TIM5 main features . . . . .340
15.3TIM5 functional description . . . . .341
15.3.1Time-base unit . . . . .341
15.3.2Counter modes . . . . .343
15.3.3Clock selection . . . . .351
15.3.4Capture/compare channels . . . . .353
15.3.5Input capture mode . . . . .355
15.3.6PWM input mode . . . . .356
15.3.7Forced output mode . . . . .357
15.3.8Output compare mode . . . . .358
15.3.9PWM mode . . . . .359
15.3.10One-pulse mode . . . . .362
15.3.11Encoder interface mode . . . . .363
15.3.12Timer input XOR function . . . . .366
15.3.13Timers and external trigger synchronization . . . . .366
15.3.14Debug mode . . . . .368
15.4TIM5 registers . . . . .369
15.4.1TIMx control register 1 (TIMx_CR1) . . . . .369
15.4.2TIMx control register 2 (TIMx_CR2) . . . . .371
15.4.3TIMx slave mode control register (TIMx_SMCR) . . . . .372
15.4.4TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . .373
15.4.5TIMx status register (TIMx_SR) . . . . .374
15.4.6TIMx event generation register (TIMx_EGR) . . . . .376
15.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . .377
15.4.8TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . .380
15.4.9TIMx capture/compare enable register (TIMx_CCER) . . . . .381
15.4.10TIMx counter (TIMx_CNT) . . . . .383
15.4.11TIMx prescaler (TIMx_PSC) . . . . .383
15.4.12TIMx auto-reload register (TIMx_ARR) . . . . .383
15.4.13TIMx capture/compare register 1 (TIMx_CCR1) . . . . .384
15.4.14TIMx capture/compare register 2 (TIMx_CCR2) . . . . .384
15.4.15TIMx capture/compare register 3 (TIMx_CCR3) . . . . .384
15.4.16TIMx capture/compare register 4 (TIMx_CCR4) . . . . .385
15.4.17TIMx DMA control register (TIMx_DCR) . . . . .385
15.4.18TIMx DMA address for full transfer (TIMx_DMAR) . . . . .386
15.4.19TIM5 option register (TIM5_OR) . . . . .387
15.4.20TIMx register map . . . . .388
16General-purpose timers (TIM9 and TIM11) . . . . .390
16.1TIM9 and TIM11 introduction . . . . .390
16.2TIM9 and TIM11 main features . . . . .390
16.2.1TIM9 main features . . . . .390
16.2.2TIM11 main features . . . . .391
16.3TIM9 and TIM11 functional description . . . . .393
16.3.1Time-base unit . . . . .393
16.3.2Counter modes . . . . .395
16.3.3Clock selection . . . . .398
16.3.4Capture/compare channels . . . . .400
16.3.5Input capture mode . . . . .401
17Basic timers (TIM6) . . . . .437
17.1Introduction . . . . .437
17.2TIM6 main features . . . . .437
17.3TIM6 functional description . . . . .438
17.3.1Time-base unit . . . . .438
17.3.2Counting mode . . . . .440
17.3.3Clock source . . . . .443
17.3.4Debug mode . . . . .444
17.4TIM6 registers . . . . .445
17.4.1TIM6 control register 1 (TIMx_CR1) . . . . .445
17.4.2TIM6 control register 2 (TIMx_CR2) . . . . .446
17.4.3TIM6 DMA/Interrupt enable register (TIMx_DIER) . . . . .446
17.4.4TIM6 status register (TIMx_SR) . . . . .447
17.4.5TIM6 event generation register (TIMx_EGR) . . . . .447
17.4.6TIM6 counter (TIMx_CNT) . . . . .447
17.4.7TIM6 prescaler (TIMx_PSC) . . . . .448
17.4.8TIM6 auto-reload register (TIMx_ARR) . . . . .448
17.4.9TIM6 register map . . . . .449
18Low-power timer (LPTIM) . . . . .450
18.1Introduction . . . . .450
18.2LPTIM main features . . . . .450
18.3LPTIM implementation . . . . .451
18.4LPTIM functional description . . . . .451
18.4.1LPTIM block diagram . . . . .451
18.4.2LPTIM trigger mapping . . . . .452
18.4.3LPTIM input1 multiplexing . . . . .452
18.4.4LPTIM reset and clocks . . . . .452
18.4.5Glitch filter . . . . .453
18.4.6Prescaler . . . . .454
18.4.7Trigger multiplexer . . . . .454
18.4.8Operating mode . . . . .455
18.4.9Timeout function . . . . .456
18.4.10Waveform generation . . . . .456
18.4.11Register update . . . . .458
18.4.12Counter mode . . . . .458
20.4IWDG registers . . . . .481
20.4.1Key register (IWDG_KR) . . . . .481
20.4.2Prescaler register (IWDG_PR) . . . . .482
20.4.3Reload register (IWDG_RLR) . . . . .483
20.4.4Status register (IWDG_SR) . . . . .483
20.4.5IWDG register map . . . . .484
21Real-time clock (RTC) . . . . .485
21.1Introduction . . . . .485
21.2RTC main features . . . . .485
21.3RTC functional description . . . . .487
21.3.1Clock and prescalers . . . . .487
21.3.2Real-time clock and calendar . . . . .487
21.3.3Programmable alarms . . . . .488
21.3.4Periodic auto-wakeup . . . . .488
21.3.5RTC initialization and configuration . . . . .489
21.3.6Reading the calendar . . . . .491
21.3.7Resetting the RTC . . . . .492
21.3.8RTC synchronization . . . . .492
21.3.9RTC reference clock detection . . . . .493
21.3.10RTC coarse digital calibration . . . . .493
21.3.11RTC smooth digital calibration . . . . .494
21.3.12Timestamp function . . . . .496
21.3.13Tamper detection . . . . .497
21.3.14Calibration clock output . . . . .498
21.3.15Alarm output . . . . .499
21.4RTC and low power modes . . . . .499
21.5RTC interrupts . . . . .500
21.6RTC registers . . . . .501
21.6.1RTC time register (RTC_TR) . . . . .501
21.6.2RTC date register (RTC_DR) . . . . .502
21.6.3RTC control register (RTC_CR) . . . . .503
21.6.4RTC initialization and status register (RTC_ISR) . . . . .505
21.6.5RTC prescaler register (RTC_PRER) . . . . .507
21.6.6RTC wakeup timer register (RTC_WUTR) . . . . .508
21.6.7RTC calibration register (RTC_CALIBR) . . . . .509
21.6.8RTC alarm A register (RTC_ALRMAR) . . . . .510
21.6.9RTC alarm B register (RTC_ALRMBR) . . . . .511
21.6.10RTC write protection register (RTC_WPR) . . . . .512
21.6.11RTC sub second register (RTC_SSR) . . . . .512
21.6.12RTC shift control register (RTC_SHIFTTR) . . . . .513
21.6.13RTC time stamp time register (RTC_TSTR) . . . . .514
21.6.14RTC time stamp date register (RTC_TSDR) . . . . .514
21.6.15RTC timestamp sub second register (RTC_TSSSR) . . . . .515
21.6.16RTC calibration register (RTC_CALR) . . . . .515
21.6.17RTC tamper and alternate function configuration register
(RTC_TAFCR) . . . . .		516
21.6.18RTC alarm A sub second register (RTC_ALRMASSR) . . . . .518
21.6.19RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .519
21.6.20RTC backup registers (RTC_BKPxR) . . . . .520
21.6.21RTC register map . . . . .521
22Fast-mode Plus Inter-integrated circuit interface (FMPI2C) . . . . .523
22.1Introduction . . . . .523
22.2FMPI2C main features . . . . .523
22.3FMPI2C implementation . . . . .524
22.4FMPI2C functional description . . . . .524
22.4.1FMPI2C block diagram . . . . .525
22.4.2FMPI2C pins and internal signals . . . . .525
22.4.3FMPI2C clock requirements . . . . .526
22.4.4FMPI2C mode selection . . . . .526
22.4.5FMPI2C initialization . . . . .527
22.4.6FMPI2C reset . . . . .531
22.4.7FMPI2C data transfer . . . . .532
22.4.8FMPI2C target mode . . . . .534
22.4.9FMPI2C controller mode . . . . .543
22.4.10FMPI2C_TIMINGR register configuration examples . . . . .554
22.4.11SMBus specific features . . . . .556
22.4.12SMBus initialization . . . . .558
22.4.13SMBus FMPI2C_TIMEOUTR register configuration examples . . . . .560
22.4.14SMBus target mode . . . . .561
22.4.15SMBus controller mode . . . . .564
22.4.16Error conditions . . . . .567
22.5FMPI2C in low-power modes . . . . .569
22.6FMPI2C interrupts . . . . .569
22.7FMPI2C DMA requests . . . . .570
22.7.1Transmission using DMA . . . . .570
22.7.2Reception using DMA . . . . .570
22.8FMPI2C debug modes . . . . .571
22.9FMPI2C registers . . . . .571
22.9.1FMPI2C control register 1 (FMPI2C_CR1) . . . . .571
22.9.2FMPI2C control register 2 (FMPI2C_CR2) . . . . .574
22.9.3FMPI2C own address 1 register (FMPI2C_OAR1) . . . . .576
22.9.4FMPI2C own address 2 register (FMPI2C_OAR2) . . . . .576
22.9.5FMPI2C timing register (FMPI2C_TIMINGR) . . . . .577
22.9.6FMPI2C timeout register (FMPI2C_TIMEOUTR) . . . . .578
22.9.7FMPI2C interrupt and status register (FMPI2C_ISR) . . . . .579
22.9.8FMPI2C interrupt clear register (FMPI2C_ICR) . . . . .582
22.9.9FMPI2C PEC register (FMPI2C_PECR) . . . . .583
22.9.10FMPI2C receive data register (FMPI2C_RXDR) . . . . .583
22.9.11FMPI2C transmit data register (FMPI2C_TXDR) . . . . .584
22.9.12FMPI2C register map . . . . .585
23Inter-integrated circuit (I 2 C) interface . . . . .586
23.1I 2 C introduction . . . . .586
23.2I 2 C main features . . . . .587
23.3I 2 C functional description . . . . .588
23.3.1Mode selection . . . . .588
23.3.2I2C target mode . . . . .589
23.3.3I2C controller mode . . . . .591
23.3.4Error conditions . . . . .596
23.3.5Programmable noise filter . . . . .597
23.3.6SDA/SCL line control . . . . .598
23.3.7SMBus . . . . .598
23.3.8DMA requests . . . . .600
23.3.9Packet error checking . . . . .602
23.4I 2 C interrupts . . . . .603
23.5I 2 C debug mode . . . . .604
23.6I 2 C registers . . . . .605

24 Universal synchronous receiver transmitter (USART)
/universal asynchronous receiver transmitter (UART) . . . . . 617

24.6.4Control register 1 (USART_CR1) . . . . .663
24.6.5Control register 2 (USART_CR2) . . . . .665
24.6.6Control register 3 (USART_CR3) . . . . .666
24.6.7Guard time and prescaler register (USART_GTPR) . . . . .668
24.6.8USART register map . . . . .669
25Serial peripheral interface/ inter-IC sound (SPI/I2S) . . . . .670
25.1Introduction . . . . .670
25.1.1SPI main features . . . . .671
25.1.2SPI extended features . . . . .672
25.1.3I2S features . . . . .672
25.2SPI/I2S implementation . . . . .672
25.3SPI functional description . . . . .673
25.3.1General description . . . . .673
25.3.2Communications between one master and one slave . . . . .674
25.3.3Standard multislave communication . . . . .677
25.3.4Multimaster communication . . . . .678
25.3.5Slave select (NSS) pin management . . . . .678
25.3.6Communication formats . . . . .680
25.3.7SPI configuration . . . . .682
25.3.8Procedure for enabling SPI . . . . .682
25.3.9Data transmission and reception procedures . . . . .683
25.3.10Procedure for disabling the SPI . . . . .685
25.3.11Communication using DMA (direct memory addressing) . . . . .686
25.3.12SPI status flags . . . . .688
25.3.13SPI error flags . . . . .689
25.4SPI special features . . . . .690
25.4.1TI mode . . . . .690
25.4.2CRC calculation . . . . .691
25.5SPI interrupts . . . . .693
25.6I 2 S functional description . . . . .694
25.6.1I 2 S general description . . . . .694
25.6.2I2S full-duplex . . . . .695
25.6.3Supported audio protocols . . . . .696
25.6.4Clock generator . . . . .703
25.6.5I 2 S master mode . . . . .705
25.6.6I 2 S slave mode . . . . .707
25.6.7I 2 S status flags . . . . .708
25.6.8I 2 S error flags . . . . .709
25.6.9I 2 S interrupts . . . . .710
25.6.10DMA features . . . . .710
25.7SPI and I 2 S registers . . . . .711
25.7.1SPI control register 1 (SPI_CR1) (not used in I 2 S mode) . . . . .711
25.7.2SPI control register 2 (SPI_CR2) . . . . .713
25.7.3SPI status register (SPI_SR) . . . . .714
25.7.4SPI data register (SPI_DR) . . . . .716
25.7.5SPI CRC polynomial register (SPI_CRCPR) (not used in I 2 S mode) . . . . .716
25.7.6SPI RX CRC register (SPI_RXCRCR) (not used in I 2 S mode) . . . . .717
25.7.7SPI TX CRC register (SPI_TXCRCR) (not used in I 2 S mode) . . . . .717
25.7.8SPI_I 2 S configuration register (SPI_I2SCFGGR) . . . . .718
25.7.9SPI_I 2 S prescaler register (SPI_I2SPR) . . . . .719
25.7.10SPI register map . . . . .721
26Debug support (DBG) . . . . .722
26.1Overview . . . . .722
26.2Reference Arm® documentation . . . . .723
26.3SWJ debug port (serial wire and JTAG) . . . . .723
26.3.1Mechanism to select the JTAG-DP or the SW-DP . . . . .724
26.4Pinout and debug port pins . . . . .724
26.4.1SWJ debug port pins . . . . .725
26.4.2Flexible SWJ-DP pin assignment . . . . .725
26.4.3Internal pull-up and pull-down on JTAG pins . . . . .725
26.4.4Using serial wire and releasing the unused debug pins as GPIOs . . . . .727
26.5JTAG TAP connection . . . . .727
26.6ID codes and locking mechanism . . . . .729
26.6.1MCU device ID code . . . . .729
26.6.2Boundary scan TAP . . . . .729
26.6.3Cortex®-M4 with FPU TAP . . . . .729
26.6.4Cortex®-M4 with FPU JEDEC-106 ID code . . . . .730
26.7JTAG debug port . . . . .730
26.8SW debug port . . . . .732
26.8.1SW protocol introduction . . . . .732
26.8.2SW protocol sequence . . . . .732
26.8.3SW-DP state machine (reset, idle states, ID code) . . . . .733
26.8.4DP and AP read/write accesses . . . . .733
26.8.5SW-DP registers . . . . .734
26.8.6SW-AP registers . . . . .735
26.9AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP . . . . .		735
26.10Core debug . . . . .736
26.11Capability of the debugger host to connect under system reset . . . . .737
26.12FPB (flash patch breakpoint) . . . . .737
26.13DWT (data watchpoint trigger) . . . . .738
26.14ITM (instrumentation trace macrocell) . . . . .738
26.14.1General description . . . . .738
26.14.2Time stamp packets, synchronization and overflow packets . . . . .738
26.15ETM (Embedded trace macrocell) . . . . .740
26.15.1General description . . . . .740
26.15.2Signal protocol, packet types . . . . .740
26.15.3Main ETM registers . . . . .740
26.15.4Configuration example . . . . .741
26.16MCU debug component (DBGMCU) . . . . .741
26.16.1Debug support for low-power modes . . . . .741
26.16.2Debug support for timers, watchdog, and I 2 C . . . . .742
26.16.3Debug MCU configuration register . . . . .742
26.16.4Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . .743
26.16.5Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . .745
26.17TPIU (trace port interface unit) . . . . .746
26.17.1Introduction . . . . .746
26.17.2TRACE pin assignment . . . . .747
26.17.3TPUI formatter . . . . .748
26.17.4TPUI frame synchronization packets . . . . .749
26.17.5Transmission of the synchronization frame packet . . . . .749
26.17.6Synchronous mode . . . . .749
26.17.7Asynchronous mode . . . . .750
26.17.8TRACECLKIN connection . . . . .750
26.17.9TPIU registers . . . . .750

List of tables

Table 1.Register boundary addresses . . . . .41
Table 2.Boot modes . . . . .45
Table 3.Embedded bootloader interfaces . . . . .45
Table 4.Memory mapping vs. Boot mode/physical remap in STM32F410 . . . . .46
Table 5.Flash module organization . . . . .48
Table 6.Number of wait states according to CPU clock (HCLK) frequency . . . . .49
Table 7.Maximum program/erase parallelism . . . . .53
Table 8.Flash interrupt request . . . . .55
Table 9.Option byte organization . . . . .55
Table 10.Description of the option bytes . . . . .56
Table 11.Access versus read protection level . . . . .59
Table 12.OTP area organization . . . . .62
Table 13.Flash register map and reset values . . . . .70
Table 14.Low-power mode summary . . . . .78
Table 15.Sleep-now entry and exit . . . . .79
Table 16.Sleep-on-exit entry and exit . . . . .80
Table 17.BAM-now entry and exit . . . . .81
Table 18.BAM-on-exit entry and exit . . . . .81
Table 19.Stop operating modes . . . . .82
Table 20.Stop mode entry and exit . . . . .84
Table 21.Standby mode entry and exit . . . . .85
Table 22.PWR - register map and reset values . . . . .93
Table 23.RCC register map and reset values . . . . .136
Table 24.Port bit configuration table . . . . .139
Table 25.Flexible SWJ-DP pin assignment . . . . .142
Table 26.RTC additional functions . . . . .148
Table 27.GPIO register map and reset values . . . . .155
Table 28.SYSCFG register map and reset values . . . . .164
Table 29.DMA1 request mapping . . . . .169
Table 30.DMA2 request mapping . . . . .170
Table 31.Source and destination address . . . . .171
Table 32.Source and destination address registers in double-buffer mode (DBM = 1) . . . . .176
Table 33.Packing/unpacking and endian behavior (bit PINC = MINC = 1) . . . . .177
Table 34.Restriction on NDT versus PSIZE and MSIZE . . . . .177
Table 35.FIFO threshold configurations . . . . .180
Table 36.Possible DMA configurations . . . . .184
Table 37.DMA interrupt requests . . . . .186
Table 38.DMA register map and reset values . . . . .196
Table 39.Vector table . . . . .200
Table 40.External interrupt/event controller register map and reset values . . . . .212
Table 41.CRC calculation unit register map and reset values . . . . .216
Table 42.ADC pins . . . . .219
Table 43.Analog watchdog channel selection . . . . .222
Table 44.Configuring the trigger polarity . . . . .226
Table 45.External trigger for regular channels . . . . .226
Table 46.External trigger for injected channels . . . . .227
Table 47.ADC interrupts . . . . .230
Table 48.ADC global register map . . . . .243
Table 49.ADC register map and reset values . . . . .243
Table 50.ADC register map and reset values (common ADC registers) . . . . .244
Table 51.DAC pins. . . . .246
Table 52.External triggers . . . . .249
Table 53.DAC register map and reset values . . . . .258
Table 54.RNG internal input/output signals . . . . .260
Table 55.RNG interrupt requests. . . . .265
Table 56.RNG configurations . . . . .266
Table 57.RNG register map and reset map. . . . .269
Table 58.Counting direction versus encoder signals. . . . .306
Table 59.TIMx Internal trigger connection . . . . .319
Table 60.Output control bits for complementary OCx and OCxN channels
with break feature . . . . .		331
Table 61.TIM1 register map and reset values . . . . .338
Table 62.Counting direction versus encoder signals. . . . .364
Table 63.TIMx internal trigger connection . . . . .373
Table 64.Output control bit for standard OCx channels. . . . .382
Table 65.TIM5 register map and reset values . . . . .388
Table 66.TIMx internal trigger connections . . . . .414
Table 67.Output control bit for standard OCx channels. . . . .422
Table 68.TIM9 register map and reset values . . . . .424
Table 69.Output control bit for standard OCx channels. . . . .432
Table 70.TIM11 register map and reset values . . . . .435
Table 71.TIM6 register map and reset values . . . . .449
Table 72.STM32F410 LPTIM features . . . . .451
Table 73.LPTIM1 external trigger connection . . . . .452
Table 74.Prescaler division ratios . . . . .454
Table 75.Encoder counting scenarios . . . . .460
Table 76.Effect of low-power modes on the LPTIM. . . . .461
Table 77.Interrupt events. . . . .461
Table 78.LPTIM register map and reset values. . . . .471
Table 79.WWDG register map and reset values . . . . .478
Table 80.Min/max IWDG timeout periods (ms) at 32 kHz (LSI). . . . .480
Table 81.IWDG register map and reset values . . . . .484
Table 82.Effect of low power modes on RTC . . . . .499
Table 83.Interrupt control bits . . . . .500
Table 84.RTC register map and reset values . . . . .521
Table 85.FMPI2C implementation . . . . .524
Table 86.FMPI2C input/output pins . . . . .525
Table 87.FMPI2C internal input/output signals . . . . .525
Table 88.Comparison of analog and digital filters . . . . .528
Table 89.I 2 C-bus and SMBus specification data setup and hold times . . . . .530
Table 90.FMPI2C configuration . . . . .534
Table 91.I 2 C-bus and SMBus specification clock timings . . . . .545
Table 92.Timing settings for f I2CCLK of 8 MHz. . . . .555
Table 93.Timing settings for f I2CCLK of 16 MHz. . . . .555
Table 94.SMBus timeout specifications. . . . .557
Table 95.SMBus with PEC configuration. . . . .559
Table 96.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms. . . . .560
Table 97.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .560
Table 98.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .560
Table 99.Effect of low-power modes to FMPI2C. . . . .569
Table 100.FMPI2C interrupt requests . . . . .569
Table 101.FMPI2C register map and reset values . . . . .585
Table 102.Maximum DNF[3:0] value to be compliant with Thd:dat(max) . . . . .597
Table 103.SMBus vs. I2C . . . . .598
Table 104.I2C interrupt requests . . . . .603
Table 105.I2C register map and reset values . . . . .616
Table 106.USART features . . . . .619
Table 107.Noise detection from sampled data . . . . .630
Table 108.Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 12 \) MHz, oversampling by 16. . . . .633
Table 109.Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 12 \) MHz, oversampling by 8. . . . .633
Table 110.Error calculation for programmed baud rates at \( f_{PCLK} = 16 \) MHz or \( f_{PCLK} = 24 \) MHz, oversampling by 16. . . . .634
Table 111.Error calculation for programmed baud rates at \( f_{PCLK} = 16 \) MHz or \( f_{PCLK} = 24 \) MHz, oversampling by 8. . . . .635
Table 112.Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 16 \) MHz, oversampling by 16. . . . .635
Table 113.Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 16 \) MHz, oversampling by 8. . . . .636
Table 114.Error calculation for programmed baud rates at \( f_{PCLK} = 30 \) MHz or \( f_{PCLK} = 60 \) MHz, oversampling by 16. . . . .637
Table 115.Error calculation for programmed baud rates at \( f_{PCLK} = 30 \) MHz or \( f_{PCLK} = 60 \) MHz, oversampling by 8 . . . . .637
Table 116.Error calculation for programmed baud rates at \( f_{PCLK} = 42 \) MHz or \( f_{PCLK} = 84 \) MHz, oversampling by 16. . . . .638
Table 117.Error calculation for programmed baud rates at \( f_{PCLK} = 42 \) MHz or \( f_{PCLK} = 84 \) MHz, oversampling by 8. . . . .639
Table 118.Error calculation for programmed baud rates at \( f_{PCLK} = 100 \) MHz or \( f_{PCLK} = 50 \) MHz, oversampling by 16. . . . .640
Table 119.Error calculation for programmed baud rates at \( f_{PCLK} = 100 \) MHz or \( f_{PCLK} = 50 \) MHz, oversampling by 8. . . . .641
Table 120.USART receiver tolerance when DIV fraction is 0 . . . . .642
Table 121.USART receiver tolerance when DIV_Fraction is different from 0 . . . . .642
Table 122.Frame formats . . . . .644
Table 123.USART interrupt requests. . . . .658
Table 124.USART register map and reset values . . . . .669
Table 125.STM32F410 SPI implementation . . . . .672
Table 126.SPI interrupt requests . . . . .693
Table 127.Audio-frequency precision using standard 8 MHz HSE . . . . .704
Table 128.I 2 S interrupt requests . . . . .710
Table 129.SPI register map and reset values . . . . .721
Table 130.SWJ debug port pins . . . . .725
Table 131.Flexible SWJ-DP pin assignment . . . . .725
Table 132.JTAG debug port data registers . . . . .730
Table 133.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .731
Table 134.Packet request (8-bits) . . . . .732
Table 135.ACK response (3 bits). . . . .733
Table 136.DATA transfer (33 bits). . . . .733
Table 137.SW-DP registers . . . . .734
Table 138.Cortex ® -M4 with FPU AHB-AP registers . . . . .735
Table 139.Core debug registers . . . . .736
Table 140.Main ITM registers . . . . .739
Table 141.Main ETM registers. . . . .741
Table 142.Asynchronous TRACE pin assignment. . . . .747
Table 143.Synchronous TRACE pin assignment . . . . .747
Table 144.Flexible TRACE pin assignment. . . . .748
Table 145.Important TPIU registers. . . . .750
Table 146.DBG register map and reset values . . . . .752
Table 147.Document revision history . . . . .756

List of figures

Figure 1.System architecture . . . . .37
Figure 2.Memory map . . . . .40
Figure 3.Flash memory interface connection inside system architecture . . . . .47
Figure 4.Sequential 32-bit instruction execution . . . . .51
Figure 5.RDP levels . . . . .59
Figure 6.PCROP levels . . . . .61
Figure 7.Power supply overview . . . . .71
Figure 8.Power-on reset/power-down reset waveform . . . . .74
Figure 9.BOR thresholds . . . . .75
Figure 10.PVD thresholds . . . . .76
Figure 11.Simplified diagram of the reset circuit . . . . .95
Figure 12.Clock tree . . . . .97
Figure 13.HSE/ LSE clock sources . . . . .99
Figure 14.Frequency measurement with TIM5 in Input capture mode . . . . .104
Figure 15.Frequency measurement with TIM11 in Input capture mode . . . . .104
Figure 16.Basic structure of a five-volt tolerant I/O port bit . . . . .139
Figure 17.Selecting an alternate function . . . . .143
Figure 18.Input floating/pull up/pull down configurations . . . . .145
Figure 19.Output configuration . . . . .146
Figure 20.Alternate function configuration . . . . .147
Figure 21.High impedance-analog configuration . . . . .147
Figure 22.DMA block diagram . . . . .167
Figure 23.System implementation of the two DMA controllers . . . . .168
Figure 24.Channel selection . . . . .169
Figure 25.Peripheral-to-memory mode . . . . .172
Figure 26.Memory-to-peripheral mode . . . . .173
Figure 27.Memory-to-memory mode . . . . .174
Figure 28.FIFO structure . . . . .179
Figure 29.External interrupt/event controller block diagram . . . . .205
Figure 30.External interrupt/event GPIO mapping . . . . .207
Figure 31.CRC calculation unit block diagram . . . . .213
Figure 32.Single ADC block diagram . . . . .218
Figure 33.Timing diagram . . . . .221
Figure 34.Analog watchdog's guarded area . . . . .221
Figure 35.Injected conversion latency . . . . .223
Figure 36.Right alignment of 12-bit data . . . . .225
Figure 37.Left alignment of 12-bit data . . . . .225
Figure 38.Left alignment of 6-bit data . . . . .225
Figure 39.Temperature sensor and VREFINT channel block diagram . . . . .229
Figure 40.DAC channel block diagram . . . . .246
Figure 41.Data registers in single DAC channel mode . . . . .247
Figure 42.Timing diagram for conversion with trigger disabled TEN = 0 . . . . .248
Figure 43.DAC LFSR register calculation algorithm . . . . .250
Figure 44.DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .250
Figure 45.DAC triangle wave generation . . . . .251
Figure 46.DAC conversion (SW trigger enabled) with triangle wave generation . . . . .251
Figure 47.RNG block diagram . . . . .260
Figure 48.Entropy source model . . . . .261
Figure 49.Advanced-control timer block diagram . . . . .271
Figure 50.Counter timing diagram with prescaler division change from 1 to 2 . . . . .273
Figure 51.Counter timing diagram with prescaler division change from 1 to 4 . . . . .273
Figure 52.Counter timing diagram, internal clock divided by 1 . . . . .274
Figure 53.Counter timing diagram, internal clock divided by 2 . . . . .275
Figure 54.Counter timing diagram, internal clock divided by 4 . . . . .275
Figure 55.Counter timing diagram, internal clock divided by N . . . . .275
Figure 56.Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded). . . . .		276
Figure 57.Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded). . . . .		276
Figure 58.Counter timing diagram, internal clock divided by 1 . . . . .278
Figure 59.Counter timing diagram, internal clock divided by 2 . . . . .278
Figure 60.Counter timing diagram, internal clock divided by 4 . . . . .279
Figure 61.Counter timing diagram, internal clock divided by N . . . . .279
Figure 62.Counter timing diagram, update event when repetition counter is not used. . . . .280
Figure 63.Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .281
Figure 64.Counter timing diagram, internal clock divided by 2 . . . . .281
Figure 65.Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .282
Figure 66.Counter timing diagram, internal clock divided by N . . . . .282
Figure 67.Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .283
Figure 68.Counter timing diagram, update event with ARPE=1 (counter overflow) . . . . .283
Figure 69.Update rate examples depending on mode and TIMx_RCR register settings . . . . .284
Figure 70.Control circuit in normal mode, internal clock divided by 1 . . . . .285
Figure 71.TI2 external clock connection example. . . . .286
Figure 72.Control circuit in external clock mode 1 . . . . .287
Figure 73.External trigger input block . . . . .287
Figure 74.Control circuit in external clock mode 2 . . . . .288
Figure 75.Capture/compare channel (example: channel 1 input stage) . . . . .289
Figure 76.Capture/compare channel 1 main circuit . . . . .289
Figure 77.Output stage of capture/compare channel (channels 1 to 3) . . . . .290
Figure 78.Output stage of capture/compare channel (channel 4). . . . .290
Figure 79.PWM input mode timing . . . . .292
Figure 80.Output compare mode, toggle on OC1. . . . .294
Figure 81.Edge-aligned PWM waveforms (ARR=8). . . . .295
Figure 82.Center-aligned PWM waveforms (ARR=8). . . . .296
Figure 83.Complementary output with dead-time insertion . . . . .298
Figure 84.Dead-time waveforms with delay greater than the negative pulse . . . . .298
Figure 85.Dead-time waveforms with delay greater than the positive pulse. . . . .298
Figure 86.Output behavior in response to a break . . . . .301
Figure 87.Clearing TIMx_OCxREF . . . . .302
Figure 88.6-step generation, COM example (OSSR=1) . . . . .303
Figure 89.Example of one pulse mode . . . . .304
Figure 90.Example of counter operation in encoder interface mode . . . . .307
Figure 91.Example of encoder interface mode with TI1FP1 polarity inverted. . . . .307
Figure 92.Example of Hall sensor interface . . . . .309
Figure 93.Control circuit in reset mode . . . . .310
Figure 94.Control circuit in gated mode . . . . .311
Figure 95.Control circuit in trigger mode . . . . .312
Figure 96.Control circuit in external clock mode 2 + trigger mode . . . . .313
Figure 97.General-purpose timer block diagram . . . . .341
Figure 98.Counter timing diagram with prescaler division change from 1 to 2 . . . . .342
Figure 99.Counter timing diagram with prescaler division change from 1 to 4 . . . . .343
Figure 100.Counter timing diagram, internal clock divided by 1 . . . . .344
Figure 101.Counter timing diagram, internal clock divided by 2 . . . . .344
Figure 102.Counter timing diagram, internal clock divided by 4 . . . . .344
Figure 103.Counter timing diagram, internal clock divided by N . . . . .345
Figure 104.Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .345
Figure 105.Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .346
Figure 106.Counter timing diagram, internal clock divided by 1 . . . . .347
Figure 107.Counter timing diagram, internal clock divided by 2 . . . . .347
Figure 108.Counter timing diagram, internal clock divided by 4 . . . . .347
Figure 109.Counter timing diagram, internal clock divided by N . . . . .348
Figure 110.Counter timing diagram, Update event . . . . .348
Figure 111.Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .349
Figure 112.Counter timing diagram, internal clock divided by 2 . . . . .350
Figure 113.Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .350
Figure 114.Counter timing diagram, internal clock divided by N . . . . .350
Figure 115.Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .351
Figure 116.Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .351
Figure 117.Control circuit in normal mode, internal clock divided by 1 . . . . .352
Figure 118.TI2 external clock connection example. . . . .352
Figure 119.Control circuit in external clock mode 1 . . . . .353
Figure 120.Capture/compare channel (example: channel 1 input stage). . . . .354
Figure 121.Capture/compare channel 1 main circuit . . . . .354
Figure 122.Output stage of capture/compare channel (channel 1). . . . .355
Figure 123.PWM input mode timing . . . . .357
Figure 124.Output compare mode, toggle on OC1 . . . . .359
Figure 125.Edge-aligned PWM waveforms (ARR=8). . . . .360
Figure 126.Center-aligned PWM waveforms (ARR=8). . . . .361
Figure 127.Example of one-pulse mode . . . . .362
Figure 128.Example of counter operation in encoder interface mode . . . . .365
Figure 129.Example of encoder interface mode with TI1FP1 polarity inverted . . . . .365
Figure 130.Control circuit in reset mode . . . . .366
Figure 131.Control circuit in gated mode . . . . .367
Figure 132.Control circuit in trigger mode . . . . .368
Figure 133.General-purpose timer block diagram (TIM9) . . . . .391
Figure 134.General-purpose timer block diagram (TIM11) . . . . .392
Figure 135.Counter timing diagram with prescaler division change from 1 to 2 . . . . .394
Figure 136.Counter timing diagram with prescaler division change from 1 to 4 . . . . .394
Figure 137.Counter timing diagram, internal clock divided by 1 . . . . .395
Figure 138.Counter timing diagram, internal clock divided by 2 . . . . .396
Figure 139.Counter timing diagram, internal clock divided by 4 . . . . .396
Figure 140.Counter timing diagram, internal clock divided by N . . . . .396
Figure 141.Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded) . . . . .		397
Figure 142.Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded) . . . . .		397
Figure 143.Control circuit in normal mode, internal clock divided by 1 . . . . .398
Figure 144.TI2 external clock connection example. . . . .399
Figure 145.Control circuit in external clock mode 1 . . . . .399
Figure 146.Capture/compare channel (example: channel 1 input stage). . . . .400
Figure 147.Capture/compare channel 1 main circuit . . . . .401
Figure 148.Output stage of capture/compare channel (channel 1). . . . .401
Figure 149. PWM input mode timing . . . . .403
Figure 150. Output compare mode, toggle on OC1. . . . .405
Figure 151. Edge-aligned PWM waveforms (ARR=8) . . . . .406
Figure 152. Example of One-pulse mode . . . . .407
Figure 153. Control circuit in reset mode . . . . .409
Figure 154. Control circuit in gated mode . . . . .410
Figure 155. Control circuit in trigger mode . . . . .410
Figure 156. Basic timer block diagram. . . . .437
Figure 157. Counter timing diagram with prescaler division change from 1 to 2 . . . . .439
Figure 158. Counter timing diagram with prescaler division change from 1 to 4 . . . . .439
Figure 159. Counter timing diagram, internal clock divided by 1 . . . . .440
Figure 160. Counter timing diagram, internal clock divided by 2 . . . . .441
Figure 161. Counter timing diagram, internal clock divided by 4 . . . . .441
Figure 162. Counter timing diagram, internal clock divided by N . . . . .442
Figure 163. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .442
Figure 164. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .443
Figure 165. Control circuit in normal mode, internal clock divided by 1 . . . . .444
Figure 166. Low-power timer block diagram . . . . .451
Figure 167. Glitch filter timing diagram . . . . .453
Figure 168. LPTIM output waveform, single counting mode configuration . . . . .455
Figure 169. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set). . . . .455
Figure 170. LPTIM output waveform, Continuous counting mode configuration . . . . .456
Figure 171. Waveform generation . . . . .457
Figure 172. Encoder mode counting sequence . . . . .460
Figure 173. Watchdog block diagram . . . . .473
Figure 174. Window watchdog timing diagram . . . . .474
Figure 175. Independent watchdog block diagram . . . . .480
Figure 176. RTC block diagram . . . . .486
Figure 177. Block diagram . . . . .525
Figure 178. I 2 C-bus protocol . . . . .527
Figure 179. Setup and hold timings . . . . .528
Figure 180. FMPI2C initialization flow . . . . .531
Figure 181. Data reception . . . . .532
Figure 182. Data transmission . . . . .533
Figure 183. Target initialization flow . . . . .536
Figure 184. Transfer sequence flow for FMPI2C target transmitter, NOSTRETCH = 0 . . . . .538
Figure 185. Transfer sequence flow for FMPI2C target transmitter, NOSTRETCH = 1 . . . . .539
Figure 186. Transfer bus diagrams for FMPI2C target transmitter (mandatory events only). . . . .540
Figure 187. Transfer sequence flow for FMPI2C target receiver, NOSTRETCH = 0 . . . . .541
Figure 188. Transfer sequence flow for FMPI2C target receiver, NOSTRETCH = 1 . . . . .542
Figure 189. Transfer bus diagrams for FMPI2C target receiver (mandatory events only) . . . . .542
Figure 190. Controller clock generation . . . . .544
Figure 191. Controller initialization flow . . . . .546
Figure 192. 10-bit address read access with HEAD10R = 0 . . . . .546
Figure 193. 10-bit address read access with HEAD10R = 1 . . . . .547
Figure 194. Transfer sequence flow for FMPI2C controller transmitter, N ≤ 255 bytes . . . . .548
Figure 195. Transfer sequence flow for FMPI2C controller transmitter, N > 255 bytes . . . . .549
Figure 196. Transfer bus diagrams for FMPI2C controller transmitter . . . . .549
(mandatory events only) . . . . .550
Figure 197. Transfer sequence flow for FMPI2C controller receiver, \( N \leq 255 \) bytes . . . . .552
Figure 198. Transfer sequence flow for FMPI2C controller receiver, \( N > 255 \) bytes . . . . .553
Figure 199. Transfer bus diagrams for FMPI2C controller receiver
(mandatory events only) . . . . .		554
Figure 200. Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .558
Figure 201. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .561
Figure 202. Transfer bus diagram for SMBus target transmitter (SBC = 1) . . . . .562
Figure 203. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .563
Figure 204. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .564
Figure 205. Bus transfer diagrams for SMBus controller transmitter . . . . .565
Figure 206. Bus transfer diagrams for SMBus controller receiver . . . . .567
Figure 207. I2C bus protocol . . . . .588
Figure 208. I2C block diagram . . . . .589
Figure 209. Transfer sequence diagram for target transmitter . . . . .590
Figure 210. Transfer sequence diagram for target receiver . . . . .591
Figure 211. Transfer sequence diagram for controller transmitter . . . . .594
Figure 212. Transfer sequence diagram for controller receiver . . . . .595
Figure 213. I2C interrupt mapping diagram . . . . .604
Figure 214. USART block diagram . . . . .621
Figure 215. Word length programming . . . . .622
Figure 216. Configurable stop bits . . . . .624
Figure 217. TC/TXE behavior when transmitting . . . . .625
Figure 218. Start bit detection when oversampling by 16 or 8 . . . . .626
Figure 219. Data sampling when oversampling by 16 . . . . .629
Figure 220. Data sampling when oversampling by 8 . . . . .630
Figure 221. Mute mode using Idle line detection . . . . .643
Figure 222. Mute mode using address mark detection . . . . .644
Figure 223. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .646
Figure 224. Break detection in LIN mode vs. Framing error detection. . . . .647
Figure 225. USART example of synchronous transmission. . . . .648
Figure 226. USART data clock timing diagram (M=0) . . . . .648
Figure 227. USART data clock timing diagram (M=1) . . . . .649
Figure 228. RX data setup/hold time . . . . .649
Figure 229. ISO 7816-3 asynchronous protocol . . . . .650
Figure 230. Parity error detection using the 1.5 stop bits . . . . .651
Figure 231. IrDA SIR ENDEC- block diagram . . . . .653
Figure 232. IrDA data modulation (3/16) -Normal mode . . . . .653
Figure 233. Transmission using DMA . . . . .655
Figure 234. Reception using DMA . . . . .656
Figure 235. Hardware flow control between 2 USARTs . . . . .656
Figure 236. RTS flow control . . . . .657
Figure 237. CTS flow control . . . . .657
Figure 238. USART interrupt mapping diagram . . . . .659
Figure 239. SPI block diagram. . . . .673
Figure 240. Full-duplex single master/ single slave application. . . . .674
Figure 241. Half-duplex single master/ single slave application . . . . .675
Figure 242. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		676
Figure 243. Master and three independent slaves. . . . .677
Figure 244. Multimaster application . . . . .678
Figure 245. Hardware/software slave select management . . . . .679
Figure 246. Data clock timing diagram . . . . .681
Figure 247. TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers . . . . .684
Figure 248. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers . . . . .685
Figure 249. Transmission using DMA . . . . .687
Figure 250. Reception using DMA . . . . .688
Figure 251. TI mode transfer . . . . .691
Figure 252. I 2 S block diagram . . . . .694
Figure 253. Full-duplex communication . . . . .696
Figure 254. I 2 S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0) . . . . .697
Figure 255. I 2 S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . .697
Figure 256. Transmitting 0x8EAA33 . . . . .698
Figure 257. Receiving 0x8EAA33 . . . . .698
Figure 258. I 2 S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . .698
Figure 259. Example of 16-bit data frame extended to 32-bit channel frame . . . . .699
Figure 260. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . .699
Figure 261. MSB justified 24-bit frame length with CPOL = 0 . . . . .699
Figure 262. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .700
Figure 263. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . .700
Figure 264. LSB justified 24-bit frame length with CPOL = 0 . . . . .700
Figure 265. Operations required to transmit 0x3478AE . . . . .701
Figure 266. Operations required to receive 0x3478AE . . . . .701
Figure 267. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .701
Figure 268. Example of 16-bit data frame extended to 32-bit channel frame . . . . .702
Figure 269. PCM standard waveforms (16-bit) . . . . .702
Figure 270. PCM standard waveforms (16-bit extended to 32-bit packet frame) . . . . .702
Figure 271. Audio sampling frequency definition . . . . .703
Figure 272. I 2 S clock generator architecture . . . . .703
Figure 273. Block diagram of STM32 MCU and Cortex ® -M4 with FPU-level debug support. . . . .722
Figure 274. SWJ debug port . . . . .724
Figure 275. JTAG TAP connections . . . . .728
Figure 276. TPIU block diagram . . . . .746

Chapters