66. Revision history

Added case of reset during half word write in Section : Error code correction (ECC).

Section 4: Embedded Flash memory (FLASH)
Updated Figure 8: Embedded Flash memory usage.
Section : Adjusting programming timing constraints: added note related to WRHIGHFREQ modification during Flash memory programming/erasing.
Section : Adjusting programming parallelism: added note related to PSIZE1/2 modification during Flash memory programming/erasing.
Secure DTCM size (ST_RAM_SIZE):
Removed Secure DTCM size (ST_RAM_SIZE) from Section : Changing security option bytes.
Updated ST_RAM_SIZE description and added ST_RAM_SIZE to the values programmed in the data protection option bytes in Section 4.4.6: Description of data protection option bytes.
Section : Definitions of RDP global protection level: updated description of RDP level 1 to 0 regression and RDP level 2.
Section : RDP protection transitions: user Flash memory can be partially or mass erased when doing a level regression from RDP level 1 to 0.

Section 5: Secure internal Flash memory (SIFM) (former Secure memory management section)
Removed Section Flash protections.
Updated Section 5.3.1: Associated features and Section 5.3.2: Boot state machine.
Added and added Note 2. below Figure 15: Flash memory areas and services in Standard and Secure access modes.
Updated Figure 16: Bootloader state machine in Secure access mode.
Updated Section 5.3.3: Secure access mode configuration.
Restructured Section 5.4: Root secure services (RSS):
Added Section 5.4.1: Secure area setting service and Section 5.4.2: Secure area exiting service
Renamed RSS services (removed RSS_ prefix).
Removed RSS_resetAndDestroyPCROPArea
Updated Section 5.5.1: Access rules and Section 5.5.2: Setting secure user memory areas. Remove sections Removing secure memory areas and Selecting secure user software.
Updated Figure 17: Core access to Flash memory areas

Section 7: Power control (PWR)
Renamed SD converter into SMPS step-down converter in the whole section.
Added case of device startup with VCORE supplied in Bypass mode in Section 7.4.1: System supply startup.
Added VOS0 in Section 7.4.2: Core domain, Section 7.4.3: PWR external supply and Section 7.6.2: Voltage scaling. Added Section : VOS0 activation/deactivation sequence.
Updated Section 7.5.5: Battery voltage thresholds.
Updated Section 7.5.6: Temperature thresholds to indicate that the thresholds are available only when the backup regulator is enabled.
Added note related to VOS0 activation in Section : Entering Stop mode and Section : Entering Standby mode.

Section 9: Reset and Clock Control (RCC)
Updated Section : HSE oscillator, Section : LSE oscillator and Figure 52: HSE/LSE clock source.
Changed maximum frequency to 480 MHz in Figure 55: Core and bus clock generation.
Updated Table 60: Kernel clock distribution overview.
Updated DIVP1[6:0] in Section 9.7.12: RCC PLL1 dividers configuration register (RCC_PLL1DIVR).
Renamed BKPSRAMAMEN into BKPRAMAMEN in Section 9.7.37: RCC D3 Autonomous mode register (RCC_D3AMR) register.
Added USB2OTGHSULPIEN in Section 9.7.40: RCC AHB1 clock register (RCC_AHB1ENR), and USB2OTGHSULPILPEN in Section 9.7.49: RCC AHB1 Sleep clock register (RCC_AHB1LPENR).
Renamed HDMICECRST into CECRST in Section 9.7.32: RCC APB1 peripheral reset register (RCC_APB1LRSTR), and HDMICECEN to CECEN in Section 7.7.45: RCC APB1 Clock Register (RCC_APB1LENR).

Section 9: General-purpose I/Os (GPIO)
Updated Figure 82: Analog inputs connected to ADC inputs to specify that the analog switch status depends on PxySO reset value in SYSCFG_PMCR.
MODER reset state changed to analog mode in Section 9.4.1: GPIO port mode register (GPIOx_MODER) (x =A to C and E, H).

Section 13: System configuration controller (SYSCFG)
Added note related to CSI clock required for setting READY bit in SYSCFG configuration register (SYSCFG_CFGR).
Added SYSCFG power control register (SYSCFG_PWRCR).

Section 17: Basic direct memory access controller (BDMA)
Updated Section : Channel state and disabling a channel.

Section 12: DMA request multiplexer (DMAMUX)
Removed references to security and privileged/unprivileged access control in Section 18.6.4: DMAMUX2 request line multiplexer interrupt channel status register (DMAMUX2_CSR), Section 18.6.6: DMAMUX2 request line multiplexer interrupt clear flag register (DMAMUX2_CFR) and Section 18.6.8: DMAMUX2 request generator channel x configuration register (DMAMUX2_RGxCR).

Section 19: Chrom-Art Accelerator™ controller (DMA2D)
Replaced DMA2D_FGPFCR by DMA2D_FGPFCCR in Section : Memory-to-memory with PFC, blending and fixed color FG.
Replaced DMA2D_BGPFCR by DMA2D_BGPFCCR in Section : Memory-to-memory with PFC, blending and fixed color BG.
Updated Section 19.6.9: DMA2D foreground color register (DMA2D_FGCOLR).
Added Section 19.6.21: DMA2D foreground CLUT (DMA2D_FGCLUT[y]) and Section 19.6.22: DMA2D background CLUT (DMA2D_BGCLUT[y]).
Table 145: DMA2D register map and reset values:
Changed APLHA[7:0] to reserved for DMA2D_FGCOLR
Changed APLHA[7:0] to reserved for DMA2D_BGCOLR

Section 23: Flexible memory controller (FMC)
Replaced BCH8 by Hamming in Section 23.8.6: Computation of the error correction code (ECC) in NAND Flash memory.
Updated Figure 115: Mode D write access waveforms.

Section 25: Delay block (DLYB)
Updated Section 25.1: Introduction to specify that the DLYB output clock can be used to clock the data received by Quad-SPI interface.

Section 26: Analog-to-digital converters (ADC)
Renamed OVSR into OVR, OSR into OSVR[9:0] and AUTODLY into AUTODLY.
Added Section 26.3: ADC implementation.
For all ADC internal channels connected to VBAT, VSENSE, VREFINT, and DAC internal channels, changed ADC channel name from ADCx_INPy/INMy to ADCx_VINP[y]/VINM[y].
Updated Table 213: Offset computation versus data resolution, Section : 16-bit and 8-bit signed format management: RSHIFTx,SSATE and Table 217: Analog watchdog 1,2,3 comparison.
Removed reference to ALIGN bit in the note related to data alignment in Section : Single ADC operating modes support when oversampling.
Updated Section 26.6.4: ADC configuration register (ADC_CFGR) to change RES[2:0] value corresponding to 8-bit format.

Section 30: Operational amplifiers (OPAMP)
Removed references to OPAMODE in Section 30.6.1: OPAMP1 control/status register (OPAMP1_CSR). Changed OPAMODE bitfield to reserved in Section 30.6.1: OPAMP1 control/status register (OPAMP1_CSR).

Section 35: JPEG codec (JPEG)
Table 290: JPEG codec register map and reset values:
JPEG_CR: added HPDIE (bit 6)
Renamed JPEG_HWCFR1/2 into JPEG_HWCFGR1/2

Section 33: LCD-TFT display controller (LTDC)
Section 33.4.1: LTDC global configuration parameters / Synchronous timing updated.

Section 19: True random number generator (RNG)
Updated Section 19.2: RNG main features.
Updated Section 19.4: RNG interrupts.
Updated Section 19.6: RNG entropy source validation.
Updated Table 97: RNG internal input/output signals.

Section 37: Cryptographic processor (CRYP)
Section 37.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR): renamed CRYP_CSGCMCCMxR[31:0] bitfield into CSGCMCCMx[31:0] and updated bitfield description.
Section 37.6.22: CRYP context swap GCM registers (CRYP_CSGCMxR): renamed CRYP_CSGCMx[31:0] bitfield into CSGCMx[31:0] and updated bitfield description.
Table 308: CRYP register map and reset values:
Added bitfield ranges for CRYP_K0LR/RR to CRYP_K3LR/RR.
Updated CRYP_IV0LR/RR to CRYP_IV1LR/RR.
Renamed CRYP_KxLR bitfields into Kx.

Section 38: Hash processor (HASH)
Changed CSRn into CSn for all HASH_CRSx registers in Table 313: HASH1 register map and reset values.

Section 22: Advanced-control timers (TIM1)
Replaced BKEx, BKPx by BKE, BK2E, BKP, BK2P.
Updated Figure 134: Advanced-control timer block diagram.
Updated Figure 177: Break and Break2 circuitry overview.
Updated Figure 164: Output stage of capture/compare channel (channel 1, idem ch. 2 and 3), Figure 165: Output stage of capture/compare channel (channel 4) and Figure 420: Output stage of capture/compare channel (channel 5, idem ch. 6).
Updated TIM1_CCMR1, TIM1_CCMR2, TIM1_CCMR3, TIM1_CCR2, TIM1_CCR4.
Added 00010 configuration for TS[4:0] in TIMx_SMCR register.
Table 347: TIM8 register map and reset values: extended DMAB bitfield to 32 bits for TIM8_DMAR.

Section 23: General-purpose timer (TIM2)
Updated Figure 194: General-purpose timer block diagram.
Updated Section 23.3.3: Clock selection.
Removed all information related to BDTR register and MOE and OSSSI bits.

Section 42: General-purpose timers (TIM12/TIM13/TIM14)
Updated Figure 497: General-purpose timer block diagram (TIM12).

Section 24: General-purpose timers (TIM16/TIM17)
Updated Figure 523: TIM15 block diagram.
Updated Figure 256: Capture/compare channel 1 main circuit? Figure 257: Output stage of capture/compare channel (channel 1) and Figure 540: Output stage of capture/compare channel (channel 2 for TIM15).
Updated Section 24.3.11: Using the break function.
Removed bit COMDE for TIM16/17.
Table 156: TIM16/TIM17 register map and reset values: changed TISEL[3:0] into TI1SEL[3:0] for TIM16_TISEL and TIM17_TISEL registers.

Section 29: Inter-integrated circuit (I2C) interface
Updated Section 29.3: I2C implementation.
Updated Section 29.7.2: I2C control register 2 (I2C_CR2), Section 29.7.3: I2C own address 1 register (I2C_OAR1), and Section 29.7.8: I2C interrupt clear register (I2C_ICR).

Section 25: Low-power timer (LPTIM)
Updated Section 25.4.8: Timeout function.
Updated WAVE bit description in Section 25.7.4: LPTIM configuration register (LPTIM_CFGR).

Section 30: Universal synchronous/asynchronous receiver transmitter (USART/UART)
Replaced DSI_NSS by DIS_NSS in USART_CR1.
Changed USART_TDR into USART_RDR in Figure 328: Reception using DMA.
Updated Section 30.5.4: USART FIFOs and thresholds.
Updated RTO bitfield description in Section 30.7.7: USART receiver timeout register (USART_RTOR).
Section 30.7.9: USART interrupt and status register [alternate] (USART_ISR):
Updated ABRF, IDLE bit descriptions
For FIFO disabled only: updated RXNE and ORE bit descriptions
Changed NFCF to NECF in Section 30.7.11: USART interrupt flag clear register (USART_ICR).
Table 193: USART register map and reset values:
USART_CR1: bit 12 changed to M0, bit 7 changed to TXEIE/TXFNIE, bit 5 changed to RXNEIE/RXFNEIE.
USART_ISR: changed TXE bit to TXE/TXNF and RXNE into RXNE/RXFNE
Corrected USART_ISR/TCGBT reset value for FIFO disabled.

Section 31: Low-power universal asynchronous receiver transmitter (LPUART)
Changed LPUART_TDR into LPUART_RDR in Figure 342: Reception using DMA.
Updated Section 30.5.4: USART FIFOs and thresholds.
Updated Section 31.5.1: LPUART control register 1 [alternate] (LPUART_CR1).
Corrected WUS bitfield length and changed RXFTCFG to TXFTCFG (bit 31 to 29) in Section 31.5.4: LPUART control register 3 (LPUART_CR3).
Section 31.5.8: LPUART interrupt and status register [alternate] (LPUART_ISR):
Updated IDLE bit descriptions
FIFO enabled only: updated reset value
Changed NFCF to NECF in Section 31.5.9: LPUART interrupt flag clear register (LPUART_ICR).
Table 199: LPUART register map and reset values
LPUART_CR1: bit 12 changed to M0, bit 5 changed to RXNEIE/RXFNEIE.
LPUART_ISR: changed TXE bit to TXE/TXFNF
Corrected LPUART_ISR reset value and bits 7 and 5 names.

Section 53: Serial peripheral interface (SPI)
Table 438: SPI register map and reset values:
SPI2S_SR: Changed bit 7 to CRCE.
SPI2S_I2SCFGR: added DATFMT (bit 14)

Section 57: Management data input/output (MDIOS)
In Table 459: MDIOS register map and reset values, for MDIOS_CR register, changed bit 3 to EIE and added DPC (bit 7).

Section 58: Secure digital input/output MultiMediaCard interface (SDMMC)
Replaced HOLD by DHOLD in the whole document.
Updated Figure 746: SDMMC block diagram and Table 464: SDMMC pins.
Updated Figure 755: CLKMUX unit.
Updated Wait_S in Section : Data path and Table 474: Data path status flags and clear bits.
Updated Section 58.5.3: General description.
Updated Section : Stream operation and CMD12.
Added Section 58.8: SDMMC interrupts.
Updated Section 58.9.10: SDMMC data counter register (SDMMC_DCNTR),
Section 58.9.11: SDMMC status register (SDMMC_STAR) and Section 58.9.15: SDMMC data FIFO registers x (SDMMC_FIFORx).
Updated Table 486: SDMMC register map.

Section 59: Controller area network with flexible data rate (FDCAN)
Updated Section 59.4.7: FDCAN nominal bit timing and prescaler register (FDCAN_NBTP), Section 59.4.12: FDCAN error counter register (FDCAN_ECR), Section 59.4.15: FDCAN interrupt register (FDCAN_IR), Section 59.4.37: FDCAN Tx buffer request pending register (FDCAN_TXBRP) and Section 59.4.64: FDCAN TT trigger select register (FDCAN_TTTS).
Updated Section Table 513.: FDCAN register map and reset values.
Updated FCCAN_CCU_CCFG in Section Table 514.: CCU register map and reset values.

Section 61: Ethernet (ETH): media access control (MAC) with DMA controller
Added Figure 833: Supported PHY interfaces.
Removed reference to AV standard in Section 61.1: Ethernet introduction.

Section 63: Debug infrastructure
Changed ETF RAM size to 4 Kbytes in Section 63.5.5: Embedded trace FIFO (ETF) and Section : ETF RAM size register (ETF_RSZ).
Added revision V and updated reset value in Section : DBGMCU identity code register (DBGMCU_IDC).
Renamed WDGLSD1/2 into DBG_IWDG1/2 in Section : DBGMCU APB4 peripheral freeze register CPU1 (DBGMCU_APB4FZ1) and Section : DBGMCU APB4 peripheral freeze register CPU2 (DBGMCU_APB4FZ2)
Prefixed all bits names in Section : DBGMCU APB1L peripheral freeze register CPU1 (DBGMCU_APB1LFZ1), Section : DBGMCU APB1L peripheral freeze register CPU2 (DBGMCU_APB1LFZ2), Section : DBGMCU APB2 peripheral freeze register CPU1 (DBGMCU_APB2FZ1), Section : DBGMCU APB2 peripheral freeze register CPU2 (DBGMCU_APB2FZ2), Section : DBGMCU APB4 peripheral freeze register CPU1 (DBGMCU_APB4FZ1) and Section : DBGMCU APB4 peripheral freeze register CPU2 (DBGMCU_APB4FZ2) by 'DBG_'.

Updated Section : Error code correction (ECC) and Section : Embedded bootloader .

Section 3: RAM ECC monitoring (RAMECC)
Changed ECCEN bit of RAMECC_MxCR to reserved.
Table 12: RAMECC register map and reset values : updated RAMECC_MxCR, RAMECC_MxSR. replaced by RAMECC_MxFAR at address offset 0x28+0x20*(x-1) and RAMECC_MxFDLH replaced by RAMECC_MxFDRH.

Section 4: Embedded flash memory (FLASH)
Restricted Table 15 to STM32H745xl/747xl/755xl/757xl and added Table 15 .
Added VOS0 range to Table 17 .

Section 5: Secure memory management (SMM) (former Secure internal Flash memory)
Updated exitSecureArea in Section 5.4.2: Secure area exiting service .

Section 7: Power control (PWR)
Moved LSI from backup to VDD domain in Figure 21: Power supply overview .
Added Figure 36: Switching VCORE from VOS1 to VOS0 in Section : VOS0 activation/deactivation sequence .
Updated list of GPIOs which use is restricted in Section 7.4.4: Backup domain .
Updated Section 7.4.8: DSI regulator .
Updated CStop mode exit in Section Table 42.: CStop mode .
Updated ACTVOSRDY bit definition in Section 7.8.2: PWR control status register 1 (PWR_CSR1) .
Updated VOSRDY bit definition in Section 7.8.7: PWR D3 domain control register (PWR_D3CR) .

Section 8: Low-power D3 domain application example
Replaced LINUART1 by LPUART1.
Updated Figure 45: Timing diagram of SRAM4-to-LPUART1 transfer with BDMA and D3 domain in Autonomous mode .
Updated section Section : EXTI programming .
Updated DMAMUX2_C0CR value for DMAMUX2_SYNC0 in Table 51: BDMA and DMAMUX2 initialization sequence (DMAMUX2_INIT) .
Renamed Table 52 into “LPUART1 start programming.

Section 9: Reset and Clock Control (RCC)
Renamed adc_ker_ck into adc_ker_ck_inputs.
Added note on RTC/AWU and updated USB1ULPI and ADC1/2/3 maximum allowed frequency for VOS0/1/2/3 in Table 66: Kernel clock distribution overview .
Updated introductory sentence of Section 9.4.2: System reset .

Section 10: Clock recovery system (CRS)
Added Section 10.3: CRS implementation . Updated Section 10.8.1: CRS control register (CRS_CR) . Updated Table 93: CRS register map and reset values .

Section 12: General-purpose I/Os (GPIO)
Changed to analog the mode in which most of the I/O ports are configured during and just after reset.

Section 16: Direct memory access controller (DMA)
Change Bit 20 to TRBUFF instead of reserved in Section 16.5.5: DMA stream x configuration register (DMA_SxCR) .

Section 21: Extended interrupt and event controller (EXTI)
Added note to event 80 in Table 152: EXTI Event input mapping .

Section 23: Flexible memory controller (FMC)
Updated Section : General transaction rules to clarify the behavior of the FMC when AXI transaction data size is different from the device data width and add the case of unaligned addresses.
Replaced FMC_CLK by fmc_ker_ck in the formulas of Section : WAIT management in asynchronous accesses .

Section 24: Quad-SPI interface (QUADSPI)
Updated Section 24.3.4: QUADSPI signal interface protocol modes .
Updated Section 24.3.11: QUADSPI configuration and Section 24.5.1: QUADSPI control register (QUADSPI_CR) adding 'when setting QUADSPI interface in DDR mode, the prescaler must be set with a division ratio of 2 or more' paragraph.
Updated FTHRES[4:0] bits description of Section 24.5.1: QUADSPI control register (QUADSPI_CR) for IP_XACT compliance.
Added note in Section 24.5.6: QUADSPI communication configuration register (QUADSPI_CCR) . Updated Section 24.5.7: QUADSPI address register (QUADSPI_AR) . Changed FLEVEL[6:0] by FLEVEL[5:0] in Section 24.5.14: QUADSPI register map .

Section 26: Analog-to-digital converters (ADC)
Removed note related to connection to DFSDM limited to ADC1 and ADC2, and added adc_sclk in Figure 141: ADC block diagram . Removed VREF+ and VREF- ranges and added adc_sclk in Table 209: ADC input/output pins .
Added reference to LDORDY bit in the whole section.
Updated Section 26.4.3: ADC clocks and renamed adc_ker_ck into adc_ker_ck_inputs. Updated Section : BOOST control .
Replaced SMPPLUS control by Extended sample time option (SMPPLUS control) and added LDO voltage regulator in Section 26.3: ADC implementation .
Updated Section 26.4.11: Channel selection (SQRx, JSQRx)
Removed RES[2:0] configuration in Table 217: Offset computation versus data resolution and Table 221: Analog watchdog 1,2,3 comparison .
Updated Section : ADC overrun (OVR, OVRMOD) . Added case of FIFO overflow in Section : Managing a sequence of conversion without using the DMA .
Updated Section : Single ADC operating modes support when oversampling to remove the mention that the offset correction is not supported in oversampling mode.

Section 26: Analog-to-digital converters (ADC)(continued)

Renamed VSENSEEN into TSEN, and replaced adc_hclk by adc_hclk in CKMODE[1:0] bitfield definition of in Section 26.7.2: ADC x common control register (ADCx_CCR) (x=1/2 or 3).

Updated RES[2:0] bitfield in Section 26.6.4: ADC configuration register (ADC_CFGR) . Updated LSHIFT[3:0] corresponding to the “Shift left 14-bits” configuration in Section 26.6.5: ADC configuration register 2 (ADC_CFGR2) .

Reworded JEXTEN[1:0] to remove duplicate 00 configuration for JEXTEN[1:0] in Section 26.6.16: ADC injected sequence register (ADC_JSQR) register. Updated Section 26.6.26: ADC calibration factors register (ADC_CALFACT) .

Removed ADC_CALCLKR register.

Section 27: Digital-to-analog converter (DAC)

Replaced sample and hold clock (lsi_ck and lse_ck when available) by dac_hold_ck.

Updated Section 27.3: DAC implementation and Figure 212: Dual-channel DAC block diagram . Section 27.4.2: DAC pins and internal signals : added DAC interconnection table, changed dac_chx_trg[0:15] into dac_chx_trg[1:15] (trigger 0 corresponds to the SW trigger) in block diagram and Table 230: DAC internal input/output signals .

Updated Figure 215: Timing diagram for conversion with trigger disabled TEN = 0 to make it independent from the bus (AHB or APB).

Removed Tables Trigger selection from Section 27.4.7: DAC trigger selection .

Updated Section : Sample and hold mode to indicate that the lsi_ck/lse_ck (when available) must not be stopped when Sample and hold mode enabled.

Updated supply voltages in Section 27.4.12: DAC channel buffer calibration .

Updated CStop mode description for DAC1 in Section 27.5: DAC in low-power modes .

Updated Section 27.6: DAC interrupts .

Updated TSELx bitfield description in Section 27.7.1: DAC control register (DAC_CR) register to add the correspondence between TSELx configurations and dac_chx_trgy.

Section 29: Comparator (COMP)

Removed condition on OR_CFG and changed OR bits to reserved in Section 29.7.3: Comparator option register (COMP_OR) .

Section 31: Digital filter for sigma delta modulators (DFSDM)

Updated Table 255: DFSDM break connection .

Removed all “ADC1 and ADC2 only” notes and footnotes.

Updated Section 31.7: DFSDM channel y registers (y=0..7) . Updated Section 31.7.5: DFSDM channel y data input register (DFSDM_CHyDATINR) .

Updated Section 31.8: DFSDM filter x module registers (x=0..3) .

Section 35: JPEG codec (JPEG)
Updated Section 35.5.5: JPEG codec configuration register 4-7 (JPEG_CONF4-7). bit 1 and bit 0 description.

Section 36: True random number generator (RNG)
Updated Section 36.1: Introduction and Section 36.2: RNG main features.
Updated Section 36.3.3: Random number generation and Figure 295: RNG initialization overview.
Updated note in Section 36.3.5: RNG operation.
Updated Section 36.5: RNG processing time and Section 36.6: RNG entropy source validation.
Updated Section 36.7.3: RNG data register (RNG_DR).

Section 37: Cryptographic processor (CRYP)
Updated number of clock cycles for TDES in Section 37.2: CRYP main features.
Removed flowcharts (Nonuser) in Section 37.4.5: CRYP procedure to perform a cipher operation.
Updated Section 37.4.17: CRYP key registers.
Updated Table 312: Cryptographic processor configuration for memory-to-peripheral DMA transfers and Table 313: Cryptographic processor configuration for peripheral-to-memory DMA transfers.
Section 37.5: CRYP interrupts: removed Figure CRYP interrupt mapping diagram and updated Table 314: CRYP interrupt requests.
Section 37.6: CRYP processing time: updated Table 315: Processing latency for ECB, CBC and CTR and Table 315: Processing latency for ECB, CBC and CTR.

Section 38: Hash processor (HASH)
Message size changed to \( 2^{64}-1 \) in Section 38.1: Introduction and Section 38.4.3: About secure hash algorithms.
Added Section 38.3: HASH implementation.
Updated Figure 320: HASH block diagram.
Updated Figure 321: Message data swapping feature.
Updated Section 38.4.8: HASH suspend/resume operations.
Renamed HASH_HRx registers located at address offset 0x0C into Section : HASH aliased digest register x (HASH_HRAx).
Updated ALGO description in Section 38.7.1: HASH control register (HASH_CR).
Specified value returned by reading Section 38.7.2: HASH data input register (HASH_DIN).

Section 40: Advanced-control timers (TIM1/TIM8)
Updated Figure 386: Advanced-control timer block diagram.
Updated Section 40.3.3: Repetition counter.
Updated Section 40.3.16: Using the break function.
Updated Section 40.4.2: TIMx control register 2 (TIMx_CR2)(x = 1, 8). Aligned TS[2:0] field in Section 40.4.3: TIMx slave mode control register (TIMx_SMCR)(x = 1, 8). Updated Section 40.4.5: TIMx status register (TIMx_SR)(x = 1, 8). Updated Section 40.4.6: TIMx event generation register (TIMx_EGR)(x = 1, 8). Updated Table 355: TIM1 register map and reset values, Table 356: TIM8 register map and reset values.
Updated Section 40.3.29: Debug mode.

Section 41: General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Updated Section 41.4.12: TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5).
Updated Table 360: TIM2/TIM3/TIM4/TIM5 register map and reset values.

Section 42: General-purpose timers (TIM12/TIM13/TIM14)
Updated Figure 496: General-purpose timer block diagram (TIM12).
Updated Figure 510: Capture/compare channel 1 main circuit.
Updated Figure 511: Output stage of capture/compare channel (channel 1).
Updated Section 42.4.1: TIM12 control register 1 (TIM12_CR1), Section 42.4.5: TIM12 status register (TIM12_SR) and Section 42.5.5: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 13 to 14).

Section 43: General-purpose timers (TIM15/TIM16/TIM17)
Updated Figure 522: TIM15 block diagram.
Updated Figure 537: Capture/compare channel 1 main circuit.
Updated: Section 43.5.2: TIM15 control register 2 (TIM15_CR2), Section 43.5.5: TIM15 status register (TIM15_SR), Section 43.5.9: TIM15 capture/compare enable register (TIM15_CCER), Section 43.6.2: TIMx control register 2 (TIMx_CR2)(x = 16 to 17), Section 43.6.4: TIMx status register (TIMx_SR)(x = 16 to 17), Section 43.6.7: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17) and Section 43.6.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17). Replaced DT[7:0] by DTG[7:0] in Table 368: TIM15 register map and reset values and Table 370: TIM16/TIM17 register map and reset values.

Section 45: Low-power timer (LPTIM)
Updated Section 45.4.5: Glitch filter.

Section 47: System window watchdog (WWDG)
Updated Section 47.5.1: WWDG control register (WWDG_CR).

Section 49: Real-time clock (RTC)
Updated Figure 580: Detailed RTC block diagram and Figure 581: Tamper detection. Updated Section 49.4: RTC low-power modes.
Updated Section 49.5: RTC interrupts.

Section 51: Universal synchronous/asynchronous receiver transmitter (USART/UART)

Section 51.8.10: USART interrupt and status register [alternate] (USART_ISR):

• – FIFO enabled: changed reset value to 0x0X80 00C0 in and Table 426: USART register map and reset values .
• – FIFO disabled: changed reset value to 0x0000 00C0 in Table 426: USART register map and reset values

Changed reset value to 0x0000 0000 in Section 51.8.12: USART receive data register (USART_RDR) and Section 51.8.13: USART transmit data register (USART_TDR) .

Updated Section 51.8: USART registers to indicate that USART and LPUART registers are accessed by words.

Section 52: Low-power universal asynchronous receiver transmitter (LPUART)

Added Section 51.4: USART implementation .

Section 52.7.7: LPUART interrupt and status register (LPUART_ISR):

• – FIFO enabled: changed reset value to 0x0080 00C0 in Table 434: LPUART register map and reset values .
• – FIFO disabled: changed reset value to 0x0000 00C0 in Table 434: LPUART register map and reset values .

Updated Section 52.7: LPUART registers to indicate that USART and LPUART registers are accessed by words.

Section 54: Serial audio interface (SAI)

Figure 689: SAI functional block diagram : number of Dn and CKn lines made generic, added note to indicate that all Dn and CKn might not be available on all SAI instances.

Added Section 54.3: SAI implementation .

Updated Table 445: SAI input/output pins to indicate the number of Dn/CKn available on each SAI instance.

Updated Figure 698: Start-up sequence .

Updated Section 54.6: SAI registers to indicate that SAI registers are accessed by words.

Section 56: Single wire protocol master interface (SWPMI)

Updated Section 56: Single wire protocol master interface (SWPMI) .

Section 59: Controller area network with flexible data rate (FDCAN)

Updated Section 59.1: Introduction and Section 59.2: FDCAN main features . Added Section 59.3: FDCAN implementation .

Section 59.4.1: Operating modes : updated Section : Software initialization , Section : CAN FD operation , and Section : Transceiver delay compensation .

Section 59.4.2: Message RAM : updated Acceptance filter , Figure 781: Standard message ID filter path and Figure 782: Extended message ID filter path .

Updated Section 59.4.4: Bit timing and Section 59.4.5: Clock calibration on CAN .

Section 59.4.6: Application : updated Section : Software calibration , Section : Clock calibration active and Section : Timing of interface signals .

Section 59: Controller area network with flexible data rate (FDCAN) (continued)

Section 59.4.8: TTCAN configuration : updated Section : Timing of interface signals . Updated Table 521: Standard message ID filter element field description , Table 523: Extended message ID filter element field description , Table 525: Trigger memory element description . Updated Table 525: Trigger memory element description and Table 780: Extended message ID filter path .

Updated Section 59.5.6: FDCAN CC control register (FDCAN_CCCR) , Section 59.5.15: FDCAN interrupt register (FDCAN_IR) , Section 59.5.18: FDCAN interrupt line enable register (FDCAN_ILE) , Section 59.5.21: FDCAN extended ID filter configuration register (FDCAN_XIDFC) , Section 59.5.31: FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) , Section 59.5.32: FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) and Section 59.7.2: Calibration configuration register (FDCAN_CCU_CCFG) . Updated Table 528: CCU register map and reset values .

Section 60: USB on-the-go high-speed (OTG_HS)

Updated Section 60.2: OTG_HS main features , Section 60.14.2: OTG interrupt register (OTG_GOTGINT) , Section 60.14.5: OTG reset register (OTG_GRSTCTL) , Section 60.14.6: OTG core interrupt register (OTG_GINTSTS) , Section 60.14.18: OTG host periodic transmit FIFO size register (OTG_HPTXFSIZ) , Section 60.14.22: OTG host frame interval register (OTG_HFIR) , Section 60.14.33: OTG host channel x transfer size register (OTG_HCTSIZx) , Section 60.14.39: OTG device configuration register (OTG_DCFG) , Section 60.14.40: OTG device control register (OTG_DCTL) , Section 60.14.41: OTG device status register (OTG_DSTS) , Section 60.14.42: OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) , Section 60.14.43: OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) , Section 60.14.54: OTG device IN endpoint x control register (OTG_DIEPCTLx) and Section 60.14.61: OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) .

Updated Section 60.10: OTG_HS Dynamic update of the OTG_HFIR register . Updated Section 60.15.3: Device initialization . Updated Section 60.15.5: Host programming model .

Section 61: Ethernet (ETH): media access control (MAC) with DMA controller

Replaced ptp_pps_o internal signal by eth_ptp_pps_out , and ptp_aux_ts_trig_i by eth_ptp_trgx (where x = 0 to 3) and ptp_aux_trig_i[x] by eth_ptp_trgx . Update ARPEN bit description in Section : Operating mode configuration register (ETH_MACCR) . Reintroduced EIPG enumerated values in Section : Extended operating mode configuration register (ETH_MACECR) . Removed sentence “This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input” from Section : System time nanoseconds register (ETH_MACSTNR) , and Section : System time nanoseconds update register (ETH_MACSTNUR) register descriptions.

Section 63: Debug infrastructure

Updated Figure 870: Block diagram of debug infrastructure , Figure 871: Power domains of debug infrastructure and Figure 872: Clock domains of debug infrastructure .

Updated Section : Clock domains .

Changed ID code for Instruction register = 1110 in Table 622: JTAG-DP data registers .

Updated notes in Table 623: Debug port registers .

Modified Section : Debug port target identification register (DP_TARGETID) reset value as well as bit descriptions.

Modified Section : Access port identification register (AP_IDR) reset value as well as description of REVISION bitfield.

Updated Table 625: System ROM table 1 .

Modified Section : SYSROM CoreSight peripheral identity register 0 (SYSROM_PIDR0) , Section : SYSROM CoreSight peripheral identity register 1 (SYSROM_PIDR1) and Section : SYSROM CoreSight peripheral identity register 2 (SYSROM_PIDR2) .

Added Table 626: System ROM table 2 .

Modified Section : CTI CoreSight peripheral identity register 0 (CTI_PIDR0) and Section : CTI CoreSight peripheral identity register 2 (CTI_PIDR2) . Updated bitfield description for Section : CTI application trigger set register (CTI_APPSET) , Section : CTI application trigger clear register (CTI_APPCLEAR) , Section : CTI application pulse register (CTI_APPPULSE) , Section : CTI trigger IN x enable register (CTI_INENx) , Section : CTI trigger OUT x enable register (CTI_OUTENx) and Section : CTI channel gate register (CTI_GATE) .

Updated Section : ETF CoreSight peripheral identity register 2 (ETF_PIDR2) reset value.

Modified Section : TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) , and Section : SWTF CoreSight peripheral identity register 2 (SWTF_PIDR2) .

Changed DBGSTBY_D3 and DBGSTOP_D3 to reserved in Section : SWTF CoreSight peripheral identity register 2 (SWTF_PIDR2) .

Updated Table 641: Cortex-M7 processor ROM table and Table 656: Cortex-M4 ROM table . Updated Table 651: Cortex-M4 ROM table .

Updated Section : Processor ROM CoreSight peripheral identity register 0 (M7_CPUROM_PIDR0) , Section : Processor ROM CoreSight peripheral identity register 1 (M7_CPUROM_PIDR1) and Section : Processor ROM CoreSight peripheral identity register 2 (M7_CPUROM_PIDR2) .

Updated Section : DWT CoreSight peripheral identity register 0 (M7_DWT_PIDR0) , Section : DWT CoreSight peripheral identity register 1 (M7_DWT_PIDR1) , Section : DWT CoreSight peripheral identity register 2 (M7_DWT_PIDR2) reset value.

Updated Section : ITM CoreSight peripheral identity register 0 (M7_ITM_PIDR0) , Section : ITM CoreSight peripheral identity register 1 (M7_ITM_PIDR1) , Section : ITM CoreSight peripheral identity register 2 (M7_ITM_PIDR2) .

Updated Table 648: Cortex-M7 ETM register map and reset values .

Updated Section : ITM CoreSight peripheral identity register 0 (M7_ITM_PIDR0) , Section : ITM CoreSight peripheral identity register 1 (M7_ITM_PIDR1) and Section : ITM CoreSight peripheral identity register 2 (M7_ITM_PIDR2) .

Updated Section : Introduction . Added errata sheet in the list of reference documents in Section : Related documents .

Section 2: Memory and bus architecture
Updated Table 2: Bus-master-to-bus-slave interconnect .
Updated Figure 1: System architecture for STM32H745/55/47/57xx devices .

Section 3: RAM ECC monitoring (RAMECC)
Added note to Section 3.1: Introduction .

Section 4: Embedded flash memory (FLASH)
Removed bootloader extension from Figure 8: Embedded flash memory usage .
Added option byte area (bank 1) in Table 14: Flash memory organization on STM32H745xl/747xl/755xl/757xl devices .
Section : Erase operation overview : added note related to the case where data cache is enabled after erase operations, removed the mention that Bank 2 can be erased with ST secure firmware.
Updated FLASH registers:
– Modified number of wait states in description of LATENCY bits in FLASH access control register (FLASH_ACR) .
– Updated FLASH option status register (FLASH_OPTSR_CUR) and FLASH option status register (FLASH_OPTSR_PRG) .
– Added note providing non-secure Flash area start address in SEC_AREA_END1 of FLASH secure address for bank 1 (FLASH_SCAR_CUR1) .
– Added formula to FAIL_ECC_ADDR1/2 in FLASH ECC fail address for bank 1 (FLASH_ECC_FA1R) and FLASH ECC fail address for bank 2 (FLASH_ECC_FA2R) , respectively.

Section 5: Secure memory management (SMM)
Added note below Figure 16: Bootloader state machine in Secure access mode .
Section 5.4: Root secure services (RSS) : added introduction and RSS API addresses.
Section 5.5.2: Setting secure user memory areas : modified name of the service used to initialize the option bytes.

Section 6: ART accelerator
Added note to PCACHEADDR[11:0] in ART accelerator - control register (ART_CTR) .

Section 7: Power control (PWR)
Modified Section 7.4: Power supplies , Section : VCORE supplied in Bypass mode (LDO and SMPS OFF) and Section 7.4.4: Backup domain .
Updated Section 7.4.8: DSI regulator .
Replaced WKUPn+1 with WKUPn, WKUPCn+1 with WKUPCn and WKUPFn+1 with WKUPFn in PWR wakeup clear register (PWR_WKUPCR) , PWR wakeup flag register (PWR_WKUPFR) and PWR wakeup enable and polarity register (PWR_WKUPEPR) .

Section 8: Low-power D3 domain application example
Changed section title.

Section 9: Reset and Clock Control (RCC)
Updated Figure 48: RCC Block diagram and Figure 53: PLL block diagram .
Updated step 4 of PLL initialization phase .
Table 62: Kernel clock distribution overview : changed TIM[8:1][17:12] and ADC1,2, 3 maximum allowed frequencies.
Updated RCC registers:

• – Updated DIVM3[5:0] in RCC PLLs clock source selection register (RCC_PLLCKSELR) register to remove the indication that the value 000000 corresponds to the default value after reset.
• – Updated maximum VCO frequency in PLLxVCOSEL of RCC PLL configuration register (RCC_PLLCFGGR) , DIVNx[8:0] of RCC_PLLxDIVR registers, FRACNx[12:0] of RCC_PLLxFRACR registers.
• – Updated RCC PLL1 dividers configuration register (RCC_PLL1DIVR) .
• – Updated description of FRACN1[12:0] bits in RCC PLL1 fractional divider register (RCC_PLL1FRACR) .
• – Added note to ARTRST bit description in RCC AHB1 peripheral reset register(RCC_AHB1RSTR) .
• – Replaced VREF with VREFBUF in description of bit 15 in RCC APB4 peripheral reset register (RCC_APB4RSTR) and RCC APB4 clock register (RCC_APB4ENR) .
• – Updated RCC AHB1 clock register (RCC_AHB1ENR) : modified position of USB2OTGHSULPIEN bit (bit 28 instead of bit 18)
• – Added note to USB2OTGHSULPILPEN in RCC AHB1 Sleep clock register (RCC_AHB1LPENR) .

Section 10: Clock recovery system (CRS)
Updated Section : FELIM value and CRS control register (CRS_CR) .

Section 11: Hardware semaphore (HSEM)
Updated Section 11.1: Introduction .
Section 11.3: Functional description deeply reworked.
Updated HSEM registers: HSEM register semaphore x (HSEM_Rx) , HSEM read lock register semaphore x (HSEM_RLRx) , HSEM interrupt enable register (HSEM_CnIER) , HSEM interrupt clear register (HSEM_CnICR) , HSEM interrupt status register (HSEM_CnISR) and HSEM interrupt status register (HSEM_CnMISR) .

Section 12: General-purpose I/Os (GPIO)
Updated additional functions in Section 12.3.2: I/O pin alternate function multiplexer and mapping . Modified port configuration required to use external interrupt lines in Section 12.3.8: External interrupt/wake-up lines .

Section 13: System configuration controller (SYSCFG)
SYSCFG peripheral mode configuration register (SYSCFG_PMCR) : updated reset value, added note indicating that it depends on the package, modified BOOSTVDDSEL bit description in ( \( V_{DDA} \) instead of \( V_{DD} \) ).
Added PI[x] pin in SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) .
Added SYSCFG system register (SYSCFG_SR0) .

Section 16: Direct memory access controller (DMA)
Updated number of DMA streams in Section 16.1: DMA introduction

Section 18: DMA request multiplexer (DMAMUX)
Updated caution note in Section 18.4.3: DMAMUX channels .

Section 19: Chrom-ART Accelerator controller (DMA2D)
Updated Section 19.3.1: General description , Figure 93: DMA2D block diagram, and Section 19.3.2: DMA2D internal signals .
Updated Section 19.3.9: DMA2D output FIFO , Section 19.3.12: DMA2D transactions , and Section 19.3.13: DMA2D configuration .
Updated DMA2D registers: DMA2D output color register (DMA2D_OCOLR) , DMA2D foreground CLUT (DMA2D_FGCLUTx) and DMA2D background CLUT (DMA2D_BGCLUTx) .

Section 22: Cyclic redundancy check calculation unit (CRC)
Added CRC register access granularity in Section 22.2: CRC main features and Section 22.4: CRC registers .
Updated Figure 102: CRC calculation unit block diagram.
Added note in Section : Polynomial programmability to clarify what are even and odd polynomials.

Section 23: Flexible memory controller (FMC)
Updated SRAM/NOR-flash chip-select control registers for bank x (FMC_BCRx) reset value.

Section 24: Quad-SPI interface (QUADSPI)
Changed status polling mode to Automatic status-polling.
Updated Section : Triggering the start of a command .

Section 25: Delay block (DLYB)
Updated Section 25.3.4: Delay line length configuration procedure and Section 25.3.5: Output clock phase configuration procedure .

Section 26: Analog-to-digital converters (ADC)
Added Section : Constraints between ADC clocks .
Updated Section : I/O analog switch voltage booster .
Updated Figure 175: Example of overrun (OVRMOD = 0) , Figure 181: AUTDLY=1 in auto- injected mode (JAUTO=1) , Figure 190: Regular and injected oversampling modes used simultaneously , and Figure 191: Triggered regular oversampling with injection .
Updated Section : DMA one shot mode (DMNGT=01) to change the DMA interrupt name to transfer complete interrupt.
Removed note on high shifting values in Section : Single ADC operating modes support when oversampling .
Replaced ADCx_CCR by ADCx_CDR in Section : Regular simultaneous mode with independent injected .
Updated temperature calculation formula in Section : Reading the temperature .

Section 27: Digital-to-analog converter (DAC)
Updated Section 27.2: DAC main features and changed OTRIMx[5:0] into OTRIMx[4:0] in In Figure 212: Dual-channel DAC block diagram .
In TSEL1/2 of DAC control register (DAC_CR) , changed internal trigger signal names from dac_ch1_trigx/dac_ch2_trigx to dac_ch1_trgx/dac_ch2_trgx.

Section 28: Voltage reference buffer (VREFBUF)
Updated Section 28.2: VREFBUF functional description .
Updated VRS[2:0] of VREFBUF control and status register (VREFBUF_CSR) .
Updated TRIM[5:0] of VREFBUF calibration control register (VREFBUF_CCR) .

Section 29: Comparator (COMP)
Comparator interrupt clear flag register (COMP_ICFR) : changed CC2IF/CC1IF access type to rc_w1 and updated address offset to 0x04.

Section 30: Operational amplifiers (OPAMP)
Updated rail-to-rail feature in Section 30.2: OPAMP main features .

Section 31: Digital filter for sigma delta modulators (DFSDM)
Removed indication of ID registers support in Section 31.3: DFSDM implementation .

Section 33: LCD-TFT display controller (LTDC)
Updated:
– Figure 250: LTDC block diagram
– Section 33.3.2: LTDC pins and internal signals
– Figure 252: Layer window programmable parameters
– Example of synchronous timings configuration

Section 34: DSI Host (DSI)
Updated Figure 255: DSI block diagram ; added Section 34.4.2: DSI Host pins and internal signals .
Updated Synchronization with the LTDC , Section 34.10: Functional description: virtual channels .
Added Section 34.12.2: D-PHY HS2LP and LP2HS durations .
Added Section 34.14.1: Programing procedure overview , and Section 34.14.2: Configuring the D-PHY parameters .
Updated DSI Host generic VCID register (DSI_GVCIDR) access type.

Section 35: JPEG codec (JPEG)
Updated JPEG_CONF Rx registers, JPEG quantization memory x (JPEG_QMEMx_y) , JPEG Huffman min (JPEG_HUFFMINx_y) , and JPEG Huffman min x (JPEG_HUFFMINx_y) .

Section 36: True random number generator (RNG)
Updated RNG data register (RNG_DR) .

Section 37: Cryptographic processor (CRYP)
Updated Section 37.2: CRYP main features , Section 37.1: Introduction , and added Section 37.3: CRYP implementation .
Updated Figure 297: AES-ECB mode overview and Figure 302: AES-CCM mode overview .
Updated Section 37.4.5: CRYP procedure to perform a cipher operation , Section 37.4.7: Preparing the CRYP AES key for decryption . Modified Section : AES CTR processing , Section : AES GCM processing , and Section : AES CCM processing . Updated Section 37.4.16: CRYP data registers and data swapping , Section 37.4.17: CRYP key registers and Section 37.4.18: CRYP initialization vector registers , Section 37.4.19: CRYP DMA interface and Section 37.6: CRYP processing time introduction .
Section 37.7: CRYP registers:

• – Updated CRYP control register (CRYP_CR) .
• – Updated CRYP data input register (CRYP_DIN) .
• – Updated CRYP DMA control register (CRYP_DMA CR) , CRYP masked interrupt status register (CRYP_MISR)
• – Updated all CRYP_KxLR/RR and CRYP_IVxLR/RR register descriptions.
• – Renamed IV bitfields of CRYP_IV0LR/RR and CRYP_IV1LR/RR to IVI . In the whole document, renamed CRPY_IVxR and CRPY_IVxL into CRPY_IVxRR and CRPY_IVxLR , respectively.

Section 38: Hash processor (HASH)
Changed SH-224/256 into SHA2-224/256 in the whole document.
Updated hash computation sequence and updated sequence to initialize the hash processor. in Section 38.4.5: Message digest computing .
Updated Section 38.4.7: HMAC operation .
Section 38.7: HASH registers:

• – Updated HASH control register (HASH_CR) .
• – Grouped together all HASH_CSRx ( HASH context swap register x (HASH_CSRx) )
• – Updated Table 322: HASH register map and reset values :

Section 40: Advanced-control timers (TIM1/TIM8)

Updated Figure 409: Control circuit in normal mode, internal clock divided by 1 , Figure 413: Control circuit in external clock mode 2 , Figure 415: Capture/compare channel 1 main circuit .

Updated Section 40.3.16: Using the break function , Section 40.3.18: Clearing the OCxREF signal on an external event , and Section 40.3.22: Encoder interface mode .

Section 40.4: TIM1/TIM8 registers :

• – Updated TIMx control register 1 (TIMx_CR1)(x = 1, 8) and TIMx control register 2 (TIMx_CR2)(x = 1, 8) .
• – Updated TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 1, 8) .
• – Updated Table 354: Output control bits for complementary OCx and OCxN channels with break feature .
• – Updated TIM1 alternate function option register 1 (TIM1_AF1) , TIM1 Alternate function register 2 (TIM1_AF2) , TIM8 Alternate function option register 1 (TIM8_AF1) and TIM8 Alternate function option register 2 (TIM8_AF2) .

Section 41: General-purpose timers (TIM2/TIM3/TIM4/TIM5)

Updated Figure 470: Control circuit in external clock mode 2 , Figure 472: Capture/Compare channel 1 main circuit , and Figure 473: Output stage of Capture/Compare channel (channel 1) .

Updated Section 41.3.12: Clearing the OCxREF signal on an external event .

Update note below Figure 490: Master/slave connection example with 1 channel only timers .

Section 41.4: TIM2/TIM3/TIM4/TIM5 registers : updated TIMx control register 2 (TIMx_CR2)(x = 2 to 5) , and TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 5) .

Section 42: General-purpose timers (TIM12/TIM13/TIM14)

Updated Figure 497: General-purpose timer block diagram (TIM13/TIM14) , Figure 510: Capture/compare channel 1 main circuit , and Figure 511: Output stage of capture/compare channel (channel 1) .

Updated Section 42.3.6: PWM input mode (only for TIM12) .

Added Section 42.3.18: Using timer output as trigger for other timers (TIM13/TIM14) .

Section 42.4: TIM12 registers : updated TIM12 control register 2 (TIM12_CR2) , TIM12 capture/compare mode register 1 [alternate] (TIM12_CCMR1) , TIM12 capture/compare enable register (TIM12_CCER) .

Section 42.5: TIM13/TIM14 registers : updated TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 13 to 14) , TIMx capture/compare enable register (TIMx_CCER)(x = 13 to 14)

Section 43: General-purpose timers (TIM15/TIM16/TIM17)

Updated Figure 523: TIM16/TIM17 block diagram , Figure 537: Capture/compare channel 1 main circuit , and Figure 538: Output stage of capture/compare channel (channel 1) .

Added Section 43.4.14: 6-step PWM generation

Added Section 43.4.23: Using timer output as trigger for other timers (TIM16/TIM17) .

Section 43.5: TIM15 registers:

• – Updated TIM15 control register 2 (TIM15_CR2) , TIM15 capture/compare mode register 1 (TIM15_CCMR1) .
• – Added CC2DE bit in TIM15 DMA/interrupt enable register (TIM15_DIER) .
• – Updated TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) on page 1958.
• – Updated Table 367: Output control bits for complementary OCx and OCxN channels with break feature (TIM15)

Section 43.6: TIM16/TIM17 registers:

• – Updated TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17) .
• – Updated Table 369: Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17)

Section 45: Low-power timer (LPTIM)

Updated Section 45.2: LPTIM main features , Section 45.4.4: LPTIM reset and clocks .

Added note to Section 45.4.7: Trigger multiplexer .

Updated Section 45.4.15: Encoder mode .

Updated CMPM bit description in LPTIM interrupt and status register (LPTIM_ISR) .

Updated LPTIM configuration register (LPTIM_CFGR) and LPTIM interrupt clear register (LPTIM_ICR) .

Section 47: System window watchdog (WWDG)

Updated Section 47.3: WWDG functional description introduction, Section Figure 576.: Watchdog block diagram , and Section 47.3.4: Controlling the down-counter .

Updated Section 47.4: WWDG interrupts , and Section 47.5.2: WWDG configuration register (WWDG_CFR) .

Section 49: Real-time clock (RTC)

Updated Section : Alarm output , and Section 29.7.4: RTC initialization and status register (RTC_ISR) .

Section 50: Inter-integrated circuit (I2C) interface

Updated Section 50.4: I2C functional description introduction.

Updated Section 50.4.3: I2C clock requirements and Section : I2C timings .

Updated I2C control register 2 (I2C_CR2) , I2C timing register (I2C_TIMINGR) , I2C timeout register (I2C_TIMEOUTR) , I2C interrupt and status register (I2C_ISR) , I2C interrupt clear register (I2C_ICR) , I2C PEC register (I2C_PECR) .

Section 51: Universal synchronous/asynchronous receiver transmitter (USART/UART)

Renamed SCLK pin to CK in the whole section.

Added wakeup from Stop in Section 51.2: USART main features .

Updated Figure 636: RS232 RTS flow control and Figure 637: RS232 CTS flow control to replace RTS and CTS by nRTS and nCTS respectively.

Added Section 51.6: USART in low-power modes . Updated Section 51.7: USART interrupts .

Section 51.8: USART registers

• – Updated ADD[7:0] bitfield descriptions in USART control register 2 (USART_CR2)
• – Updated PSC bitfield description in USART guard time and prescaler register (USART_GTPR)
• – Updated ABRREQ bit description in USART request register (USART_RQR) register.
• – Updated SBKF bit description in USART interrupt and status register [alternate] (USART_ISR) .

Section 52: Low-power universal asynchronous receiver transmitter (LPUART)

Renamed SCLK pin to CK in the whole section.

Updated Table 428: Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz .

Replaced 88.36 Kaud by 88.36 kbaud in the example provided in Section : Determining the maximum LPUART baud rate that enables to correctly wake up the MCU from low-power mode .

Added Section 52.5: LPUART in low-power modes and updated Section 52.6: LPUART interrupts .

Section 52.7: LPUART registers: updated LPUART control register 2 (LPUART_CR2) , and LPUART interrupt and status register [alternate] (LPUART_ISR) .

Section 53: Serial peripheral interface (SPI)

Updated Section 53.2: SPI main features , Figure 654: SPI2S block diagram , Section 53.4.2: SPI signals , Section 53.4.3: SPI communication general aspects , note below Figure 655: Full-duplex single master/ single slave application , Figure 656: Half-duplex single master/ single slave application , notes below Figure 657: Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) , Figure 658: Master and three independent slaves at star topology , Section 53.4.7: Slave select (SS) pin management , Section 53.4.8: Communication formats , Section 53.4.9: Configuration of SPI , Section 53.4.10: Procedure for enabling SPI , Section 53.4.11: SPI data transmission and reception procedures , Section 53.4.12: Procedure for disabling the SPI , and Section 53.4.14: Communication using DMA (direct memory addressing) .

Updated Section 53.5.1: TI mode , Section 53.5.2: SPI error flags and Section 53.5.3: CRC computation .

Updated Section 53.6: Low-power mode management and Section 53.7: SPI wakeup and interrupts .

Updated Section 53.8: I2S main features and Section 53.9.2: Pin sharing with SPI function .

Section 53: Serial peripheral interface (SPI) (continued)

Added note on 24- and 32-bit data width availability in Section 53.9.5: Supported audio protocols , below Figure 671: Master I2S Philips protocol waveforms (16/32-bit full accuracy) to Figure 679: Slave PCM waveforms , and Section 53.9.10: Internal FIFOs . Updated note below Table 438: WS and CK level before SPI/I2S is enabled when AFCNTR = 1 , Section 53.9.7: Startup sequence , Section 53.9.9: Clock generator , Section 53.9.12: Handling of underrun situation , and Section 53.9.13: Handling of overrun situation . Suppressed section Master I2S MSB Aligned, full-duplex . Updated Section : Slave I2S Philips standard, receive procedure.

Section 53.11: SPI/I2S registers:

• – Updated SPI/I2S control register 1 (SPI_CR1) .
• – Updated SPI configuration register 1 (SPI_CFG1) and SPI configuration register 2 (SPI_CFG2) .
• – Updated SPI/I2S status register (SPI_SR) .
• – Updated SPI/I2S transmit data register (SPI_TXDR) and SPI/I2S receive data register (SPI_RXDR) .
• – Updated SPI polynomial register (SPI_CRCPOLY) .
• – Updated SPI transmitter CRC register (SPI_TXCRC) and SPI receiver CRC register (SPI_RXCRC) .
• – Updated SPI underrun data register (SPI_UDRDR) .
• – Updated WSINV, CHLEN and DATLEN[1:0] of SPI/I2S configuration register (SPI_I2SCFGR)

Section 54: Serial audio interface (SAI)

Section 54.4.10: PDM interface : added reference to implementation section and note 2 in Table 450: TDM frame configuration examples .
In Section 54.4.12: SPDIF output , replaced \( F_{\text{SAI\_CK\_x}} \) by \( F_{\text{sai\_x\_ker\_ck}} \) in the formula enabling to compute the bit rate.
Added note related to bitfield usage depending on Dx line availability in SAI PDM delay register (SAI_PDMPLY) .

Section 55: SPDIF receiver interface (SPDIFRX)

Added note in about RCC capabilities in Section 55.2: SPDIFRX main features and Table 459: Minimum spdifrx_ker_ck frequency versus audio sampling rate .
Updated Section 55.3: SPDIFRX functional description , Figure 711: SPDIFRX block diagram , Figure 716: SPDIFRX decoder , Figure 717: Noise filtering and edge detection and Section 55.5.1: SPDIFRX control register (SPDIFRX_CR) .

Section 58: Secure digital input/output MultiMediaCard interface (SDMMC).

Updated Section : Data path , Section : Data FIFO , Section : Stream operation and CMD12 , Section : Block operation and CMD12 , Section : Normal boot operation , and Section : Alternative boot operation .

Section 58.10: SDMMC registers : updated DBLOCKSIZE[3:0] in SDMMC data control register (SDMMC_DCTRL) , SDMMC IDMA buffer 0 base address register (SDMMC_IDMABASE0R) and SDMMC IDMA buffer 1 base address register (SDMMC_IDMABASE1R) .

Section 59: Controller area network with flexible data rate (FDCAN)
Updated Section 59.4.6: Application . Modified Section Figure 777.: Transceiver delay measurement .

Updated FDCAN data bit timing and prescaler register (FDCAN_DBTP) , and FDCAN CC control register (FDCAN_CCCR) .
Added Section 59.5.47: FDCAN register map and Section 59.5: FDCAN registers .

Section 60: USB on-the-go high-speed (OTG_HS)
Updated Section 60.4.3: OTG_HS core , Section 60.4.4: Embedded full-speed OTG PHY connected to OTG_HS .
Added Section 60.4.5: OTG detections .
Updated Section 60.4.6: High-speed OTG PHY connected to OTG_HS and Section 60.5: OTG_HS dual role device (DRD) .
Added Figure 795: OTG_HS peripheral-only connection and Figure 796: OTG_HS host-only connection .
Section 60.14: OTG_HS registers :
– Updated Table 540: TRDT values .
– Added ODDFRM bit in OTG host channel x characteristics register (OTG_HCCHARx) .

Section 61: Ethernet (ETH): media access control (MAC) with DMA controller
Updated Section 61.1: Ethernet introduction , Section 61.2: Ethernet main features , Section 61.3: Ethernet pins and internal signals , Figure 824: Ethernet high-level block diagram .
Updated step 9 of DMA reception sequence in Section : DMA reception . Added Section : Priority scheme for Tx DMA and Rx DMA .
Updated Section 61.5.1: Double VLAN processing , Section 61.5.2: Source address and VLAN insertion, replacement, or deletion , Section 61.5.3: Packet filtering , Section 61.5.4: IEEE 1588 timestamp support , Section 61.5.5: Checksum offload engine , Section 61.5.6: TCP segmentation offload , Section 61.5.7: IPv4 ARP offload , Section 61.5.8: Loopback , Section 61.5.9: Flow control and Section 61.5.10: MAC management counters .
Updated Section : SMA functional overview , Section : MII management write operations , Section : MII management read operation , and Section : Preamble suppression .
Updated Section 61.6.2: Media independent interface (MII) and Section 61.6.3: Reduced media independent interface (RMII) .
Updated Section 61.7: Ethernet low-power modes .
Updated Section 61.9.1: DMA initialization , Section 61.9.3: MAC initialization , Section 61.9.5: Stopping and starting transmission . Added Section 61.9.6: Programming guidelines for switching to new descriptor list in RxDMA , Section 61.9.7: Programming guidelines for switching the AHB clock frequency , and Section 61.9.10: Programming guidelines for PTP offload feature . Updated Section 61.9.11: Programming guidelines for Energy Efficient Ethernet (EEE) , Section 61.9.12: Programming guidelines for flexible pulse-per-second (PPS) output , Section 61.9.13: Programming guidelines for TSO and Section 61.9.14: Programming guidelines to perform VLAN filtering on the receive .

Section 61: Ethernet (ETH): media access control (MAC) with DMA controller (continued)

Section 61.10: Descriptors:

• – Section 61.10.3: Transmit descriptor: updated TDES2 normal descriptor (read format), TDES3 normal descriptor (read format), TDES3 normal descriptor (write-back format), TDES3 context descriptor (read format).
• – Section 61.10.4: Receive descriptor: RDES0 normal descriptor (read format), RDES0 normal descriptor (write-back format), RDES3 normal descriptor (read format), RDES3 normal descriptor (write-back format).

Section 61.11.2: Ethernet DMA registers:

• – DMA mode register (ETH_DMAMR): changed DA bit access type to rw.
• – Updated System bus mode register (ETH_DMASBMR) reset value.
• – Updated Channel transmit control register (ETH_DMACCTXCR) and Channel receive control register (ETH_DMACRXCR) .
• – Updated TDESLA and RDESLA bitfield descriptions of Channel Tx descriptor list address register (ETH_DMACTXDLAR) and Channel Rx descriptor list address register (ETH_DMACRXDLAR) , respectively.
• – Updated TDT and RDT bitfield descriptions in Channel Tx descriptor tail pointer register (ETH_DMACTXDTPR) and Channel Rx descriptor tail pointer register (ETH_DMACRXDTPR) , respectively.
• – Updated TDRL bitfield descriptions in Channel Tx descriptor ring length register (ETH_DMACTXRLR) . Updated Channel Rx descriptor ring length register (ETH_DMACRXRLR) .
• – Channel interrupt enable register (ETH_DMACIER): removed MMCIE/MMCRSIPIS and GPIIS/GPIIE from Figure 859: Generation of ETH_DMAISR flags ; updated AIE bit description.
• – Added RWU bitfield in Channel Rx interrupt watchdog timer register (ETH_DMACRXIWTR) .
• – Channel status register (ETH_DMACSR): changed bit 15:10, 8:6 and 2: 0 access type to rc_w1; updated REB, TEB, AIS, CDE and TBU bit descriptions
• – Channel missed frame count register (ETH_DMACMFCR): changed all bit access type to rc_r.

Section 61.11.3: Ethernet MTL registers

• – Operating mode Register (ETH_MTLOMR): updated CNTPRST and RAA and DTXSTS bit descriptions.
• – Updated Tx queue operating mode Register (ETH_MTLTXQOMR) .
• – Updated Tx queue underflow register (ETH_MTLTXQUR) bit access type.
• – Updated Tx queue debug register (ETH_MTLTXQDR) .
• – Updated Rx queue operating mode register (ETH_MTLRXQOMR) .
• – Updated Rx queue missed packet and overflow counter register (ETH_MTLRXQMPOCR) access type.

Section 61: Ethernet (ETH): media access control (MAC) with DMA controller (continued)

Section 61.11.4: Ethernet MAC and MMC registers

• – Updated Operating mode configuration register (ETH_MACCR) , Extended operating mode configuration register (ETH_MACECR) , Packet filtering control register (ETH_MACPFR) , and Watchdog timeout register (ETH_MACWTR) .
• – Updated Hash Table 0 register (ETH_MACHT0R) and Hash Table 1 register (ETH_MACHT1R) .
• – Updated VLAN tag register (ETH_MACVTR) , VLAN Hash table register (ETH_MACVHTR) , VLAN inclusion register (ETH_MACVIR) and VLAN inclusion register (ETH_MACVIR) .
• – Updated Tx Queue flow control register (ETH_MACQTXFCR) and Rx flow control register (ETH_MACRXFCR) , Interrupt status register (ETH_MACISR) , Rx Tx status register (ETH_MACRXTXSR) and PMT control status register (ETH_MACPCSR) .
• – Remote wakeup packet filter register (ETH_MACRWKPFR) : moved Table: Remote wakeup packet filter register to Section : Description of remote wakeup packet mode
• – Updated LPI control and status register (ETH_MACLCSR)
• – Updated Version register (ETH_MACVR) reset value.
• – Added HW feature 0 register (ETH_MACHWF0R) , updated HW feature 1 register (ETH_MACHWF1R) , and HW feature 2 register (ETH_MACHWF2R) .
• – Updated MAC Address x high register (ETH_MACAxHR) .
• – Updated MMC Rx interrupt register (ETH_MMC_RX_INTERRUPT) , MMC Tx interrupt register (ETH_MMC_TX_INTERRUPT) , MMC Rx interrupt mask register (ETH_MMC_RX_INTERRUPT_MASK) and MMC Tx interrupt mask register (ETH_MMC_TX_INTERRUPT_MASK) .
• – Updated L3 and L4 control 0 register (ETH_MACL3L4C0R) to Layer3 address 3 filter 1 register (ETH_MACL3A31R) .
• – Timestamp control Register (ETH_MACTSCR) : moved Table Timestamp snapshot dependency on register bits to Section : Clock types , updated TSUPDT and TSINIT bit descriptions.
• – Updated Subsecond increment register (ETH_MACSSIR) , System time nanoseconds register (ETH_MACSTNR) , System time seconds update register (ETH_MACSTSUR) , System time nanoseconds update register (ETH_MACSTNUR) , Timestamp addend register (ETH_MACTSAR) , and Timestamp status register (ETH_MACTSSR) .
• – Modified Tx timestamp status nanoseconds register (ETH_MACTXTSSNR) bit access type.
• – Updated Auxiliary control register (ETH_MACACR) .

Section 63: Debug infrastructure

Replaced Cortex-M7 with Cortex-M4 in DBGMCU_APB4 peripheral freeze register CPU2 (DBGMCU_APB4FZ2) . Updated bit 20 description in Section : DBGMCU configuration register (DBGMCU_CR) . Replaced PRESCALER - 1 with PRESCALER +1 in the description of PRESCALER[12:0] bits ( SWO current output divisor register (SWO_CODR) )

Section 64: Device electronic signature

Updated Section 64.1: Unique device ID register (96 bits) ; added Section 64.3: Line identifier .

Added Section 65: Important security notice.