20. Nested vectored interrupt controllers (NVIC1 and NVIC2)

20.1 NVIC features

Both CPU1 (Cortex ^® -M7) and CPU2 (Cortex ^® -M4) cores have their own nested vector interrupt controller (respectively NVIC1 and NVIC2). The NVIC includes the following features:

• • up to 150 maskable interrupt channels for STM32H7xxx (not including the 16 interrupt lines of Cortex ^® -M7 / Cortex ^® -M4 with FPU)
• • 16 programmable priority levels (4 bits of interrupt priority are used)
• • low-latency exception and interrupt handling
• • power management control
• • implementation of system control registers

The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts.

All interrupts, including the core exceptions, are managed by the NVIC.

For more information on exceptions and NVIC programming, refer to PM0253 and PM0214 programming manuals for Cortex ^® -M7 and for Cortex ^® -M4, respectively.

20.1.1 SysTick calibration value register

The SysTick calibration value (SYST_CALIB) is fixed to 0x3E8. It provides a reference timebase of 1 ms based when the SysTick clock frequency is 1 MHz. To match the 1 ms timebase whatever the application frequency, the SysTick reload value must be programmed as follows in the SYST_RVR register:

• • The SysTick clock source is the 100 MHz CPU clock (HCLK):

• • or the SysTick clock source is an external clock:

where \( F_{\text{HCLK}} \) refers to the AHB frequency expressed in MHz.

For example, to achieve a timebase of 1 ms when the SysTick clock source is the 100 MHz HCLK:

20.1.2 Interrupt and exception vectors

Each CPU has its own exceptions connected to its Nested vectored interrupt controller (NVIC): reset, NMI, HardFault, MemManage, Bus Fault, UsageFault, SVCall, DebugMonitor, PendSV, SysTick.

Each CPU also has its own Floating Point Unit (FPU) interrupt connected to its Nested Vectored Interrupt Controller (NVIC), in position 81.

The Window Watchdog 1 (WWDG1) interrupt is connected to the CPU1 NVIC (NVIC1) position 0, while Window Watchdog 2 (WWDG2) interrupt is connected to the CPU2 NVIC (NVIC2) position 0.

The Window Watchdog 1 (WWDG1) reset output signal is connected to the CPU2 NVIC (NVIC2) position 143 via the Extended Interrupt and Event Controller (EXTI). Similarly, the Window Watchdog 2 (WWDG2) reset output signal is connected to the CPU1 NVIC (NVIC1) position 143 via the Extended Interrupt and Event Controller (EXTI).

Refer to Section 47: System window watchdog (WWDG) and Section 48: Independent watchdog (IWDG) for the description of watchdog interrupts and reset.

Hardware Semaphore (HSEM) interrupt line 0 is connected to the CPU1 NVIC (NVIC1) position 125, while Hardware Semaphore (HSEM) interrupt line 1 is connected to the CPU2 NVIC (NVIC2) position 126.

The CPU2 hold interrupt is connected to the CPU1 NVIC (NVIC1) position 148. Similarly, the CPU1 hold interrupt is connected to the CPU2 NVIC (NVIC2) position 148. Refer to Power control (PWR) for the description of the CPU hold mechanism.

All other interrupt lines coming from peripherals are connected in a symmetrical way on both NVIC1 and NVIC2.

Table 149. NVIC1 (CPU1) and NVIC2 (CPU2) ⁽¹⁾

1. When different signals are connected to the same NVIC interrupt line, they are OR-ed.